diff --git a/software/main.c b/software/main.c
index 49e249ee3c78b476b713f14e7457851dff02effe..b7f1f761975d7c8304f95fd572e180a27f411d80 100644
--- a/software/main.c
+++ b/software/main.c
@@ -37,7 +37,7 @@
#include "at86rf2xx.h"
#include "at86rf2xx_params.h"
-#define ENABLE_DEBUG (1)
+#define ENABLE_DEBUG (0)
#include "debug.h"
#define SEND_INTERVAL (1)
@@ -53,11 +53,11 @@
/// 512 required for samr21-xpro, 256 sufficient for INGA and telosb
#ifdef BOARD_SAMR21_XPRO
-char dump_thread_stack[1024+256];
-char send_thread_stack[1024+256];
+ char dump_thread_stack[1024+256];
+ char send_thread_stack[1024+256];
#else
-char dump_thread_stack[512+256];
-char send_thread_stack[512+256];
+ char dump_thread_stack[512+256];
+ char send_thread_stack[512+256];
#endif
#ifdef BOARD_TELOSB
@@ -78,7 +78,7 @@ char send_thread_stack[512+256];
//#define CLOCK_CALIB_WAIT() _delay_us(1)
#define CLOCK_CALIB_FRQ_XTAL 32768UL
- #define CLOCK_CALIB_FRQ_REF_CNT (uint16_t)((CLOCK_CORECLOCK / CLOCK_CALIB_FRQ_XTAL) * 100)
+ #define CLOCK_CALIB_FRQ_REF_CNT (uint16_t)(( (CLOCK_CORECLOCK) / CLOCK_CALIB_FRQ_XTAL) * 100)
#define CALIBRATION_SLEEP_TIME 1
char calib_thread_stack[512+256];
@@ -700,7 +700,7 @@ void *send_thread(void *arg)
cli();
at86rf233_disable_irq(&at86rf2xx_dev);
- uint8_t tries = 50;
+ uint8_t tries = 10;
uint8_t bak_timsk2, bak_tccr2b, bak_tccr2a, bak_tccr1b, bak_assr, bak_ddrd, bak_portd;
//uint16_t min = 0xFFFF;
//uint8_t min_osccal = 0;
@@ -709,7 +709,11 @@ void *send_thread(void *arg)
/* backup timer register */
bak_timsk2 = TIMSK2;
TIMSK2 = 0x00;
+
/* backup timer register */
+ bak_tccr2b = TCCR2B;
+ bak_tccr2a = TCCR2A;
+ bak_tccr1b = TCCR1B;
bak_assr = ASSR;
ASSR = 0x00;
ASSR |= (1 << AS2); //CLK_SRC für TIMER2 ist externer Quarz
@@ -717,112 +721,84 @@ void *send_thread(void *arg)
while (ASSR & ((1 << TCN2UB)|(1 << OCR2AUB)|(1 << TCR2AUB)|(1<< TCR2BUB))){
;
}
- /* backup timer register */
- bak_tccr2b = TCCR2B;
- TCCR2B = 0x00;
- bak_tccr2a = TCCR2A;
+
+ TCCR2B = 0x00;
TCCR2A = 0x00; //set OC2B off
- bak_tccr1b = TCCR1B;
TCCR1B = 0x00;
TCCR1B |= 1 << ICES1; //Activate Input Capture on positive/rising edge
TCCR1B |= 1 << ICNC1; //Activate Noise Canceler
- OCR2B = 100;
- //set D6 to output and set on 0. Save D6
+ OCR2B = 100; /*Trigger Compare Match at 100 Ticks*/
+
+ /* set D6 to output and set on 0. Save D6 */
bak_ddrd = DDRD;
bak_portd = PORTD;
+
DDRD |= 1 << PD6;
PORTD &= ~(1 << PD6);
- TCCR1B |= 1 << CS10; //No Prescaler
-
- DEBUG("PIND init: %d\n", PIND);
do {
- //clear Flag for ICF1
+ /* clear Flag for ICF1 */
if(TIFR1 & (1 << ICF1)) {
- TIFR1 |= 1 << ICF1;
+ TIFR1 |= (1 << ICF1 | 1 << OCF1B | 1 << OCF1A | 1 << TOV1);
}
- //clear Flag for OCR2B
+ /* clear Flag for OCR2B */
if(TIFR2 & (1 << OCF2B)){
- TIFR2 |= 1 << OCF2B;
+ TIFR2 |= (1 << OCF2B | 1 << OCF2B | 1 << TOV2);
}
PORTD &= (~(1 << PD6)); /*Set pin D6 back to 0 */
- //DEBUG("Entering while, %d %d\n", TIFR2, TIFR1);
- //DEBUG("PIND before: %d\n", PIND);
-
- TCCR2A = 0x30; //set OC2B on Compare Match
-
- TCNT2 = 0;
- //DEBUG("PIND before while: %d\n", PIND);
- //Turn on Timer
- //TCCR1B |= 1 << CS10; //No Prescaler
+ /* Turn on Timer and reset Counter Regs */
TCNT1 = 0;
- TCCR2B |= 1 << CS20; //No Prescaler
-
- while ((!(TIFR2 & (1 << OCF2B))) || (!(TIFR1 & (1 << ICF1)))); /* Check for both flags */
- /**
- DEBUG("Reg T2 Val: %d\n", TIFR2);
- DEBUG("Reg T1 Val: %d\n", TIFR1);
- DEBUG("DDRD: %d\n", DDRD);
- DEBUG("PIND: %d\n", PIND);
- DEBUG("TCCR1A: %d\n", TCCR1A);
- DEBUG("TCCR1B: %d\n", TCCR1B);
- DEBUG("TCCR2A: %d\n", TCCR2A);
- DEBUG("TCCR2B: %d\n", TCCR2B);
- DEBUG("-------->\n");
- **/
- ticks = ICR1;
- TCCR2B &= 0b11111000; //Off
- //TCCR1B &= 0b11111000; //Off
- //DEBUG("Count: %d\n", TCNT2);
- //DEBUG("PIND before: %d\n", PIND);
- TCCR2A = 0x00; //set OC2B into Port-Mode
- //DEBUG("Reg T2 Val after flag2: %d\n", TIFR2);
- //DEBUG("Reg T1 Val after flag2: %d\n", TIFR1);
- //DEBUG("PIND after: %d\n", PIND);
+ TCNT2 = 0;
+ TCCR2B |= 1 << CS20; /* No Prescaler */
+ while (ASSR & ((1 << TCN2UB)|(1 << OCR2AUB)|(1 << TCR2AUB)|(1<< TCR2BUB))){ /*Wait until new Settings have been transferred*/
+ ;
+ }
+ TCCR1B |= 1 << CS10; /* No Prescaler */
+
+ while ( (!(TIFR2 & (1 << OCF2B))) ); /*wait for Compare Match */
+ PORTD |= (1 << PD6); //set OC2B and trigger input capture
+
+ while((!(TIFR1 & (1 << ICF1)))); /*wait for input capture*/
+
+ ticks = ICR1; /* Transfer captured ticks */
+ TCCR2B &= 0b11111000; /*Turn Timer 2 off */
+ TCCR1B &= 0b11111000; /*Turn Timer 1 off */
+
+ while (ASSR & ((1 << TCN2UB)|(1 << OCR2AUB)|(1 << TCR2AUB)|(1<< TCR2BUB))){ /*Wait until new Settings have been transferred*/
+ ;
+ }
+
+ DEBUG("Count: %d\n", TCNT2);
+ DEBUG("PIND before: %d\n", PIND);
+ DEBUG("Reg T1 Val after flag2: %d\n", TIFR1);
+ DEBUG("Reg T2 Val after flag2: %d\n", TIFR2);
+ DEBUG("PIND after: %d\n", PIND);
DEBUG("Counted Ticks: %ul\n", ticks);
DEBUG("----->\n");
/*CLOCK_CALIB_FRQ_REF_CNT = 24400*/
if (ticks > CLOCK_CALIB_FRQ_REF_CNT) {
- /**
- if((ticks - CLOCK_CALIB_FRQ_REF_CNT) < min){
- min_osccal = OSCCAL;
+ if(OSCCAL != 0)
+ {
+ OSCCAL--;
}
- **/
- //OSCCAL--;
+
} else if (ticks < CLOCK_CALIB_FRQ_REF_CNT) {
- /**
- if((CLOCK_CALIB_FRQ_REF_CNT - ticks) < min){
- min_osccal = OSCCAL;
+ if(OSCCAL != 255)
+ {
+ OSCCAL++;
}
- **/
- //OSCCAL++;
} else if (ticks == CLOCK_CALIB_FRQ_REF_CNT) {
tries = 1;
- //min_osccal = OSCCAL;
- }
- /**
- for (unsigned int i = 0xFFFF; i > 0; i--) {
- __asm__("nop");
- }
- for (unsigned int i = 0xFFFF; i > 0; i--) {
- __asm__("nop");
}
- **/
}while (--tries);
+ DEBUG("Final OSCCAl Value %d\n", OSCCAL);
+ DEBUG("====================\n");
- //OSCCAL = min_osccal;
- DEBUG("Setting OSCCAl to Value %d\n", OSCCAL);
-
- for (unsigned int i = 0xFF; i > 0; i--) {
- __asm__("nop");
- }
- DEBUG("Counted Ticks: %ul\n", ticks);
-
/* restore registers */
ASSR = bak_assr;
TIMSK2 = bak_timsk2;
@@ -832,9 +808,6 @@ void *send_thread(void *arg)
DDRD = bak_ddrd;
PORTD = bak_portd;
- for (unsigned int i = 0xFFFF; i > 0; i--) { /* Delay for XTAL to settle */
- __asm__("nop");
- }
sei();
at86rf233_enable_irq(&at86rf2xx_dev);
}