diff --git a/boards/f4vi1/include/periph_conf.h b/boards/f4vi1/include/periph_conf.h
index c4ea0359a78866ae9cf5a88e13cd4ca9a334c5ce..40628145751d4fad33c86ad7bc8639c0981b01d7 100644
--- a/boards/f4vi1/include/periph_conf.h
+++ b/boards/f4vi1/include/periph_conf.h
@@ -51,31 +51,30 @@ extern "C" {
 /** @} */
 
 /**
- * @name Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (2U)
-#define TIMER_0_EN          1
-#define TIMER_1_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK / 2)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    },
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
-
-/* Timer 1 configuration */
-#define TIMER_1_DEV         TIM5
-#define TIMER_1_CHANNELS    4
-#define TIMER_1_FREQ        (CLOCK_CORECLOCK / 2)
-#define TIMER_1_MAX_VALUE   (0xffffffff)
-#define TIMER_1_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
 #define TIMER_1_ISR         isr_tim5
-#define TIMER_1_IRQ_CHAN    TIM5_IRQn
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/fox/include/periph_conf.h b/boards/fox/include/periph_conf.h
index 1796c5fc17f5efa35785992849792f9131db5b2e..e3198aab35a8546a2b11799e30df1b86122e2395 100644
--- a/boards/fox/include/periph_conf.h
+++ b/boards/fox/include/periph_conf.h
@@ -67,12 +67,14 @@ extern "C" {
 static const timer_conf_t timer_config[] = {
     {
         .dev      = TIM2,
+        .max      = 0x0000ffff,
         .rcc_mask = RCC_APB1ENR_TIM2EN,
         .bus      = APB1,
         .irqn     = TIM2_IRQn
     },
     {
         .dev      = TIM3,
+        .max      = 0x0000ffff,
         .rcc_mask = RCC_APB1ENR_TIM3EN,
         .bus      = APB1,
         .irqn     = TIM3_IRQn
diff --git a/boards/iotlab-common/include/periph_conf_common.h b/boards/iotlab-common/include/periph_conf_common.h
index 0a24e4b39c7b1258d339fc7cf736ab5c654b6976..5ce6492258f55b0640edb5099ec3aa4ae81f9adf 100644
--- a/boards/iotlab-common/include/periph_conf_common.h
+++ b/boards/iotlab-common/include/periph_conf_common.h
@@ -40,11 +40,13 @@ extern "C" {
 #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1      /* AHB clock -> 72MHz */
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1     /* APB2 clock -> 72MHz */
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2     /* APB1 clock -> 36MHz */
-/* resulting bus clocks */
-#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2          (CLOCK_CORECLOCK)
 /* configuration of flash access cycles */
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
 /** @} */
 
 /**
@@ -66,12 +68,14 @@ extern "C" {
 static const timer_conf_t timer_config[] = {
     {
         .dev      = TIM2,
+        .max      = 0x0000ffff,
         .rcc_mask = RCC_APB1ENR_TIM2EN,
         .bus      = APB1,
         .irqn     = TIM2_IRQn
     },
     {
         .dev      = TIM3,
+        .max      = 0x0000ffff,
         .rcc_mask = RCC_APB1ENR_TIM3EN,
         .bus      = APB1,
         .irqn     = TIM3_IRQn
diff --git a/boards/limifrog-v1/include/periph_conf.h b/boards/limifrog-v1/include/periph_conf.h
index d283e9b3fb50edcb3da9539771c81ce60425f486..5007a0cdb946d1f9fcd4fea049944d4c2f4db414 100644
--- a/boards/limifrog-v1/include/periph_conf.h
+++ b/boards/limifrog-v1/include/periph_conf.h
@@ -42,6 +42,11 @@ extern "C" {
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV1     /* APB1 clock -> 32MHz */
 /* configuration of flash access cycles */
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
diff --git a/boards/msbiot/include/periph_conf.h b/boards/msbiot/include/periph_conf.h
index cc7f5596a255c74b9d8602d1fbe40a802213c29e..e6eadc1364c37787851f6fbcdfe00cb604785e9d 100644
--- a/boards/msbiot/include/periph_conf.h
+++ b/boards/msbiot/include/periph_conf.h
@@ -48,33 +48,31 @@ extern "C" {
 #define CLOCK_APB1          (CLOCK_CORECLOCK / 4)
 /** @} */
 
-
 /**
- * @name Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (2U)
-#define TIMER_0_EN          1
-#define TIMER_1_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (84000000U)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    },
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
-
-/* Timer 1 configuration */
-#define TIMER_1_DEV         TIM5
-#define TIMER_1_CHANNELS    4
-#define TIMER_1_FREQ        (84000000U)
-#define TIMER_1_MAX_VALUE   (0xffffffff)
-#define TIMER_1_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
 #define TIMER_1_ISR         isr_tim5
-#define TIMER_1_IRQ_CHAN    TIM5_IRQn
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f030/include/periph_conf.h b/boards/nucleo-f030/include/periph_conf.h
index 5d21bdd0bf9d1f1af042e3f03a5b1e90161424d0..a2df78bd1a7f67371738e4cefee9a251b1eea029 100644
--- a/boards/nucleo-f030/include/periph_conf.h
+++ b/boards/nucleo-f030/include/periph_conf.h
@@ -21,6 +21,8 @@
 #ifndef PERIPH_CONF_H_
 #define PERIPH_CONF_H_
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -34,24 +36,30 @@ extern "C" {
 
 /* the actual PLL values are automatically generated */
 #define CLOCK_PLL_MUL       (CLOCK_CORECLOCK / CLOCK_HSE)
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
- * @brief Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM3
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0x0000ffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
-#define TIMER_0_IRQ_CHAN    TIM3_IRQn
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM3,
+        .max      = 0x0000ffff,
+        .rcc_mask = RCC_APB1ENR_TIM3EN,
+        .bus      = APB1,
+        .irqn     = TIM3_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim3
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f070/include/periph_conf.h b/boards/nucleo-f070/include/periph_conf.h
index afcdd00e352f3f79d057cfce04e122a4ed0a0f0e..0a077edbcaa9dbe78e6365ba35ccac0da3f38af5 100644
--- a/boards/nucleo-f070/include/periph_conf.h
+++ b/boards/nucleo-f070/include/periph_conf.h
@@ -21,6 +21,8 @@
 #ifndef PERIPH_CONF_H_
 #define PERIPH_CONF_H_
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -34,24 +36,30 @@ extern "C" {
 
 /* the actual PLL values are automatically generated */
 #define CLOCK_PLL_MUL       (CLOCK_CORECLOCK / CLOCK_HSE)
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
- * @brief Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM3
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM3EN)
-#define TIMER_0_IRQ_CHAN    TIM3_IRQn
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM3,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM3EN,
+        .bus      = APB1,
+        .irqn     = TIM3_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim3
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f072/include/periph_conf.h b/boards/nucleo-f072/include/periph_conf.h
index 46bd5826670a5910b84e369e22befc26fd8daf6d..28e77ab738d4d3b95c5c1b218e23e81b8b57fec3 100644
--- a/boards/nucleo-f072/include/periph_conf.h
+++ b/boards/nucleo-f072/include/periph_conf.h
@@ -20,6 +20,8 @@
 #ifndef PERIPH_CONF_H_
 #define PERIPH_CONF_H_
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -33,24 +35,30 @@ extern "C" {
 
 /* the actual PLL values are automatically generated */
 #define CLOCK_PLL_MUL       (CLOCK_CORECLOCK / CLOCK_HSE)
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
- * @brief Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f091/include/periph_conf.h b/boards/nucleo-f091/include/periph_conf.h
index 27a21eb2dfbcd938a82c96b5a49427bbab604e7c..01bfb369ad7dc00923baea4459859d3033b7d397 100644
--- a/boards/nucleo-f091/include/periph_conf.h
+++ b/boards/nucleo-f091/include/periph_conf.h
@@ -34,24 +34,30 @@ extern "C" {
 
 /* the actual PLL values are automatically generated */
 #define CLOCK_PLL_MUL       (CLOCK_CORECLOCK / CLOCK_HSE)
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
- * @brief Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f103/include/periph_conf.h b/boards/nucleo-f103/include/periph_conf.h
index cc55dd2a08bf7ff50c8f75232bedf94f8a02fef7..feb31718a4fb23e3d241d4e43b408cc2e65b0c5f 100644
--- a/boards/nucleo-f103/include/periph_conf.h
+++ b/boards/nucleo-f103/include/periph_conf.h
@@ -31,22 +31,20 @@ extern "C" {
  */
 #define CLOCK_HSE           (8000000U)              /* external oscillator */
 #define CLOCK_CORECLOCK     (72000000U)             /* desired core clock frequency */
-
 /* the actual PLL values are automatically generated */
 #define CLOCK_PLL_DIV       (1)
 #define CLOCK_PLL_MUL       (9)
-
 /* AHB, APB1, APB2 dividers */
 #define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2    /* max 36 MHz (!) */
-
-/* resulting bus clocks */
-#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2          (CLOCK_CORECLOCK)
-
 /* Flash latency */
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2    /* for >= 72 MHz */
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
 /** @} */
 
 /**
@@ -70,12 +68,15 @@ extern "C" {
 static const timer_conf_t timer_config[] = {
     {
         .dev      = TIM2,
+        .max      = 0x0000ffff,
         .rcc_mask = RCC_APB1ENR_TIM2EN,
         .bus      = APB1,
         .irqn     = TIM2_IRQn
     },
     {
         .dev      = TIM3,
+        .max      = 0x0000ffff,
+
         .rcc_mask = RCC_APB1ENR_TIM3EN,
         .bus      = APB1,
         .irqn     = TIM3_IRQn
diff --git a/boards/nucleo-f207/Makefile.features b/boards/nucleo-f207/Makefile.features
index 0458cbfedff69b355ec9b8414d556138184c9675..b53a6d772ec5452622ef0561309111b4ae0fb819 100644
--- a/boards/nucleo-f207/Makefile.features
+++ b/boards/nucleo-f207/Makefile.features
@@ -2,7 +2,6 @@
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_gpio
 FEATURES_PROVIDED += periph_i2c
-FEATURES_PROVIDED += periph_pwm
 FEATURES_PROVIDED += periph_rtc
 FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += periph_timer
diff --git a/boards/nucleo-f207/include/periph_conf.h b/boards/nucleo-f207/include/periph_conf.h
index 6a2d118aa80da20d0e705258051b9df9ea9288e1..a8679b0c6aee1aac19926e79c314ce2a41003b7a 100644
--- a/boards/nucleo-f207/include/periph_conf.h
+++ b/boards/nucleo-f207/include/periph_conf.h
@@ -73,52 +73,37 @@ static const pwm_conf_t pwm_config[PWM_NUMOF] = {
 /** @} */
 
 /**
- * @name Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (4U)
-#define TIMER_0_EN          1
-#define TIMER_1_EN          1
-#define TIMER_2_EN          1
-#define TIMER_3_EN          1
-#define TIMER_IRQ_PRIO      1
-
-static const timer_conf_t timer_config[TIMER_NUMOF] = {
+static const timer_conf_t timer_config[] = {
     {
         .dev      = TIM2,
-        .channels = 4,
-        .freq     = (CLOCK_APB1 * 2),
+        .max      = 0xffffffff,
         .rcc_mask = RCC_APB1ENR_TIM2EN,
         .bus      = APB1,
-        .irqn     = TIM2_IRQn,
-        .priority = TIMER_IRQ_PRIO
+        .irqn     = TIM2_IRQn
     },
     {
         .dev      = TIM5,
-        .channels = 4,
-        .freq     = (CLOCK_APB1 * 2),
+        .max      = 0xffffffff,
         .rcc_mask = RCC_APB1ENR_TIM5EN,
         .bus      = APB1,
-        .irqn     = TIM5_IRQn,
-        .priority = TIMER_IRQ_PRIO
+        .irqn     = TIM5_IRQn
     },
     {
         .dev      = TIM3,
-        .channels = 4,
-        .freq     = (CLOCK_APB1 * 2),
+        .max      = 0xffffffff,
         .rcc_mask = RCC_APB1ENR_TIM3EN,
         .bus      = APB1,
-        .irqn     = TIM3_IRQn,
-        .priority = TIMER_IRQ_PRIO
+        .irqn     = TIM3_IRQn
     },
     {
         .dev      = TIM4,
-        .channels = 4,
-        .freq     = (CLOCK_APB1 * 2),
+        .max      = 0xffffffff,
         .rcc_mask = RCC_APB1ENR_TIM4EN,
         .bus      = APB1,
-        .irqn     = TIM4_IRQn,
-        .priority = TIMER_IRQ_PRIO
+        .irqn     = TIM4_IRQn
     }
 };
 
@@ -126,6 +111,8 @@ static const timer_conf_t timer_config[TIMER_NUMOF] = {
 #define TIMER_1_ISR         isr_tim5
 #define TIMER_2_ISR         isr_tim3
 #define TIMER_3_ISR         isr_tim4
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f303/include/periph_conf.h b/boards/nucleo-f303/include/periph_conf.h
index 6d0316cfa59644ce5581ed9c720a9d0124137ff0..249df3fc459ee94a5870e0e5b158dd5d1c52ad03 100755
--- a/boards/nucleo-f303/include/periph_conf.h
+++ b/boards/nucleo-f303/include/periph_conf.h
@@ -21,6 +21,8 @@
 #ifndef PERIPH_CONF_H_
 #define PERIPH_CONF_H_
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -38,6 +40,11 @@ extern "C" {
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
 /** @} */
 
 /**
@@ -48,21 +55,22 @@ extern "C" {
 /** @} */
 
 /**
- * @brief Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f334/include/periph_conf.h b/boards/nucleo-f334/include/periph_conf.h
index 3aca8fac9772593aa580986477aa3e5f452ec9b0..5167710ce0a5d1f2c8a756beb3eb15bc405d037f 100644
--- a/boards/nucleo-f334/include/periph_conf.h
+++ b/boards/nucleo-f334/include/periph_conf.h
@@ -20,6 +20,8 @@
 #ifndef PERIPH_CONF_H_
 #define PERIPH_CONF_H_
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -37,6 +39,18 @@ extern "C" {
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
+/** @} */
+
+/**
+ * @brief   DAC configuration
+ * @{
+ */
+#define DAC_NUMOF           (0)
 /** @} */
 
 /**
@@ -50,18 +64,19 @@ extern "C" {
  * @brief Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
-#define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    }
+};
+
+#define TIMER_0_ISR         (isr_tim2)
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f401/include/board.h b/boards/nucleo-f401/include/board.h
index 9df74ec0efc5b6dc6611d3dc925330641502ae6b..6e2be0642aac5785de2db2d57cca8db460b04d30 100644
--- a/boards/nucleo-f401/include/board.h
+++ b/boards/nucleo-f401/include/board.h
@@ -31,7 +31,7 @@ extern "C" {
  * @name xtimer configuration
  * @{
  */
-#define XTIMER_DEV          TIMER_0
+#define XTIMER_DEV          TIMER_DEV(0)
 #define XTIMER_CHAN         (0)
 #define XTIMER_OVERHEAD     (6)
 #define XTIMER_BACKOFF      (5)
diff --git a/boards/nucleo-f401/include/periph_conf.h b/boards/nucleo-f401/include/periph_conf.h
index 49915b525735926437aaa07636ef73defbc02fb2..a8e2115ec362eff05f499cdd0d811d96bb2811a5 100644
--- a/boards/nucleo-f401/include/periph_conf.h
+++ b/boards/nucleo-f401/include/periph_conf.h
@@ -49,31 +49,30 @@ extern "C" {
 /** @} */
 
 /**
- * @name Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (2U)
-#define TIMER_0_EN          1
-#define TIMER_1_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    },
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
-
-/* Timer 1 configuration */
-#define TIMER_1_DEV         TIM5
-#define TIMER_1_CHANNELS    4
-#define TIMER_1_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_1_MAX_VALUE   (0xffffffff)
-#define TIMER_1_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
 #define TIMER_1_ISR         isr_tim5
-#define TIMER_1_IRQ_CHAN    TIM5_IRQn
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-f446/include/board.h b/boards/nucleo-f446/include/board.h
index ebe8b92a08951f842a6c8021141abc6d4c8d403e..1c9143a094e3207f13d48a8ef0f66439a2153024 100644
--- a/boards/nucleo-f446/include/board.h
+++ b/boards/nucleo-f446/include/board.h
@@ -31,7 +31,7 @@ extern "C" {
  * @name xtimer configuration
  * @{
  */
-#define XTIMER_DEV          TIMER_0
+#define XTIMER_DEV          TIMER_DEV(0)
 #define XTIMER_CHAN         (0)
 #define XTIMER_OVERHEAD     (6)
 #define XTIMER_BACKOFF      (5)
diff --git a/boards/nucleo-f446/include/periph_conf.h b/boards/nucleo-f446/include/periph_conf.h
index d4a2d093bec93ebbe329ff7197a4c7a2165e818b..fa2703181bb24d7370aba718ac034645efa3fb2a 100644
--- a/boards/nucleo-f446/include/periph_conf.h
+++ b/boards/nucleo-f446/include/periph_conf.h
@@ -49,31 +49,30 @@ extern "C" {
 /** @} */
 
 /**
- * @name Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (2U)
-#define TIMER_0_EN          1
-#define TIMER_1_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    },
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
-
-/* Timer 1 configuration */
-#define TIMER_1_DEV         TIM5
-#define TIMER_1_CHANNELS    4
-#define TIMER_1_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_1_MAX_VALUE   (0xffffffff)
-#define TIMER_1_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
 #define TIMER_1_ISR         isr_tim5
-#define TIMER_1_IRQ_CHAN    TIM5_IRQn
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/nucleo-l1/include/periph_conf.h b/boards/nucleo-l1/include/periph_conf.h
index 39e5460b5ef2746624bf58cf9e427804b145e70f..52d27d3c8d50fa280c6bf288b7523a325163bc28 100644
--- a/boards/nucleo-l1/include/periph_conf.h
+++ b/boards/nucleo-l1/include/periph_conf.h
@@ -41,6 +41,11 @@ extern "C" {
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV1     /* APB1 clock -> 32MHz */
 /* configuration of flash access cycles */
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
@@ -55,12 +60,17 @@ extern "C" {
  * @{
  */
 static const timer_conf_t timer_config[] = {
-    /* device, RCC bit, IRQ bit */
-    {TIM5, 3, TIM5_IRQn},
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
 };
-/* interrupt routines */
+
 #define TIMER_0_ISR         (isr_tim5)
-/* number of defined timers */
+
 #define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
diff --git a/boards/spark-core/include/periph_conf.h b/boards/spark-core/include/periph_conf.h
index a495db8f03383ae381677a8583b10e32026dc016..80ff806d041852a110ccea097639b318ba4d04a3 100644
--- a/boards/spark-core/include/periph_conf.h
+++ b/boards/spark-core/include/periph_conf.h
@@ -67,12 +67,14 @@
 static const timer_conf_t timer_config[] = {
     {
         .dev      = TIM2,
+        .max      = 0x0000ffff,
         .rcc_mask = RCC_APB1ENR_TIM2EN,
         .bus      = APB1,
         .irqn     = TIM2_IRQn
     },
     {
         .dev      = TIM3,
+        .max      = 0x0000ffff,
         .rcc_mask = RCC_APB1ENR_TIM3EN,
         .bus      = APB1,
         .irqn     = TIM3_IRQn
diff --git a/boards/stm32f0discovery/include/periph_conf.h b/boards/stm32f0discovery/include/periph_conf.h
index a686ff1fd129f34e153638621a81ae032b030eb8..4c2027c0d78f00dfcbdae10f72fe0e9afa8ed92a 100644
--- a/boards/stm32f0discovery/include/periph_conf.h
+++ b/boards/stm32f0discovery/include/periph_conf.h
@@ -34,24 +34,30 @@ extern "C" {
 
 /* the actual PLL values are automatically generated */
 #define CLOCK_PLL_MUL       (CLOCK_CORECLOCK / CLOCK_HSE)
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 1)
 /** @} */
 
 /**
- * @name Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
-
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    }
+};
+
 #define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/stm32f3discovery/include/periph_conf.h b/boards/stm32f3discovery/include/periph_conf.h
index b5593aa02b273b433db9bd6a7e0f9f82d0d84e2f..22e3bdf5f0146a506040c8411727cbe845aa7738 100644
--- a/boards/stm32f3discovery/include/periph_conf.h
+++ b/boards/stm32f3discovery/include/periph_conf.h
@@ -19,6 +19,8 @@
 #ifndef PERIPH_CONF_H_
 #define PERIPH_CONF_H_
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -36,6 +38,11 @@ extern "C" {
 #define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
 #define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2
 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
 /** @} */
 
 /**
@@ -50,21 +57,22 @@ extern "C" {
 /** @} */
 
 /**
- * @brief Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (1U)
-#define TIMER_0_EN          1
-#define TIMER_IRQ_PRIO      1
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    }
+};
 
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
 #define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
diff --git a/boards/stm32f4discovery/include/board.h b/boards/stm32f4discovery/include/board.h
index 41925c1409a32b1de92b3bab6c01ab9330ba9b7f..98c95f1148d37c712f5919115f13b74907bb95e6 100644
--- a/boards/stm32f4discovery/include/board.h
+++ b/boards/stm32f4discovery/include/board.h
@@ -32,7 +32,7 @@ extern "C" {
  * @name xtimer configuration
  * @{
  */
-#define XTIMER_DEV          TIMER_0
+#define XTIMER_DEV          TIMER_DEV(0)
 #define XTIMER_CHAN         (0)
 #define XTIMER_OVERHEAD     (6)
 #define XTIMER_BACKOFF      (10)
diff --git a/boards/stm32f4discovery/include/periph_conf.h b/boards/stm32f4discovery/include/periph_conf.h
index 264742e349a243c850c706d163278eaa0a7ea4b8..c25a03b31778bd9822d0e78ecd266a366cb2a68e 100644
--- a/boards/stm32f4discovery/include/periph_conf.h
+++ b/boards/stm32f4discovery/include/periph_conf.h
@@ -50,31 +50,30 @@ extern "C" {
 /** @} */
 
 /**
- * @name Timer configuration
+ * @brief   Timer configuration
  * @{
  */
-#define TIMER_NUMOF         (2U)
-#define TIMER_0_EN          1
-#define TIMER_1_EN          1
-#define TIMER_IRQ_PRIO      1
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM2,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM2EN,
+        .bus      = APB1,
+        .irqn     = TIM2_IRQn
+    },
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
+};
 
-/* Timer 0 configuration */
-#define TIMER_0_DEV         TIM2
-#define TIMER_0_CHANNELS    4
-#define TIMER_0_FREQ        (CLOCK_CORECLOCK / 2)
-#define TIMER_0_MAX_VALUE   (0xffffffff)
-#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
 #define TIMER_0_ISR         isr_tim2
-#define TIMER_0_IRQ_CHAN    TIM2_IRQn
-
-/* Timer 1 configuration */
-#define TIMER_1_DEV         TIM5
-#define TIMER_1_CHANNELS    4
-#define TIMER_1_FREQ        (CLOCK_CORECLOCK / 2)
-#define TIMER_1_MAX_VALUE   (0xffffffff)
-#define TIMER_1_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
 #define TIMER_1_ISR         isr_tim5
-#define TIMER_1_IRQ_CHAN    TIM5_IRQn
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
 /** @} */
 
 /**
@@ -103,7 +102,7 @@ static const uart_conf_t uart_config[] = {
         .irqn       = USART3_IRQn,
         .dma_stream = 3,
         .dma_chan   = 4
-    },
+    }
 };
 
 /* assign ISR vector names */
diff --git a/cpu/stm32_common/cpu_common.c b/cpu/stm32_common/cpu_common.c
index 7f6b0320a79c8c48711ad9a9dee0e246060f282e..12dac29d8d7838f0bf449e1fff0b7d84657a84dd 100644
--- a/cpu/stm32_common/cpu_common.c
+++ b/cpu/stm32_common/cpu_common.c
@@ -18,8 +18,19 @@
  * @}
  */
 
+#include "periph_conf.h"
 #include "periph_cpu_common.h"
 
+uint32_t periph_apb_clk(uint8_t bus)
+{
+    if (bus == APB1) {
+        return CLOCK_APB1;
+    }
+    else {
+        return CLOCK_APB2;
+    }
+}
+
 void periph_clk_en(uint8_t bus, uint32_t mask)
 {
     if (bus == APB1) {
diff --git a/cpu/stm32_common/include/periph_cpu_common.h b/cpu/stm32_common/include/periph_cpu_common.h
index e9abc3a0a50842addd5ac8ae978436b3bd48d296..1e3bae20df55c3898ee43409f58032ea32eaf5a7 100644
--- a/cpu/stm32_common/include/periph_cpu_common.h
+++ b/cpu/stm32_common/include/periph_cpu_common.h
@@ -30,6 +30,11 @@ extern "C" {
  */
 #define CPUID_LEN           (12U)
 
+/**
+ * @brief   All STM timers have 4 capture-compare channels
+ */
+#define TIMER_CHAN          (4U)
+
 /**
  * @brief   Use the shared SPI functions
  * @{
@@ -65,6 +70,26 @@ typedef uint32_t gpio_t;
  */
 #define GPIO_PIN(x, y)      ((GPIOA_BASE + (x << 10)) | y)
 
+/**
+ * @brief   Timer configuration
+ */
+typedef struct {
+    TIM_TypeDef *dev;       /**< timer device */
+    uint32_t max;           /**< maximum value to count to (16/32 bit) */
+    uint32_t rcc_mask;      /**< corresponding bit in the RCC register */
+    uint8_t bus;            /**< APBx bus the timer is clock from */
+    uint8_t irqn;           /**< global IRQ channel */
+} timer_conf_t;
+
+/**
+ * @brief   Get the actual bus clock frequency for the APB buses
+ *
+ * @param[in] bus       target APBx bus
+ *
+ * @return              bus clock frequency in Hz
+ */
+uint32_t periph_apb_clk(uint8_t bus);
+
 /**
  * @brief   Enable the given peripheral clock
  *
diff --git a/cpu/stm32f1/periph/timer.c b/cpu/stm32_common/periph/timer.c
similarity index 90%
rename from cpu/stm32f1/periph/timer.c
rename to cpu/stm32_common/periph/timer.c
index e57d9b53cb96f33ff9aff904ff8cfb1f6ce82f80..8d51c4a09293db433431f029927dc9ae6995f097 100644
--- a/cpu/stm32f1/periph/timer.c
+++ b/cpu/stm32_common/periph/timer.c
@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_stm32f1
+ * @ingroup     cpu_stm32_common
  * @{
  *
  * @file
@@ -54,9 +54,9 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
     /* configure the timer as upcounter in continuous mode */
     dev(tim)->CR1  = 0;
     dev(tim)->CR2  = 0;
-    dev(tim)->ARR  = TIMER_MAXVAL;
+    dev(tim)->ARR  = timer_config[tim].max;
     /* set prescaler */
-    dev(tim)->PSC = ((CLOCK_CORECLOCK / freq) - 1);
+    dev(tim)->PSC = ((periph_apb_clk(timer_config[tim].bus) / freq) - 1);
     /* generate an update event to apply our configuration */
     dev(tim)->EGR = TIM_EGR_UG;
 
@@ -76,11 +76,11 @@ int timer_set(tim_t tim, int channel, unsigned int timeout)
 
 int timer_set_absolute(tim_t tim, int channel, unsigned int value)
 {
-    if (channel >= TIMER_CHANNELS) {
+    if (channel >= TIMER_CHAN) {
         return -1;
     }
 
-    dev(tim)->CCR[channel] = (value & TIMER_MAXVAL);
+    dev(tim)->CCR[channel] = (value & timer_config[tim].max);
     dev(tim)->SR &= ~(TIM_SR_CC1IF << channel);
     dev(tim)->DIER |= (TIM_DIER_CC1IE << channel);
 
@@ -89,7 +89,7 @@ int timer_set_absolute(tim_t tim, int channel, unsigned int value)
 
 int timer_clear(tim_t tim, int channel)
 {
-    if (channel >= TIMER_CHANNELS) {
+    if (channel >= TIMER_CHAN) {
         return -1;
     }
 
@@ -126,7 +126,7 @@ static inline void irq_handler(tim_t tim)
 {
     uint32_t status = (dev(tim)->SR & dev(tim)->DIER);
 
-    for (unsigned int i = 0; i < TIMER_CHANNELS; i++) {
+    for (uint8_t i = 0; i < TIMER_CHAN; i++) {
         if (status & (TIM_SR_CC1IF << i)) {
             dev(tim)->DIER &= ~(TIM_DIER_CC1IE << i);
             isr_ctx[tim].cb(isr_ctx[tim].arg, i);
diff --git a/cpu/stm32f0/include/stm32f030x8.h b/cpu/stm32f0/include/stm32f030x8.h
index 72197c54ff25a79f19432db539f07f851970d589..a65d267d65ec66d7e924f2ea6d186aaa7262b0a5 100644
--- a/cpu/stm32f0/include/stm32f030x8.h
+++ b/cpu/stm32f0/include/stm32f030x8.h
@@ -399,10 +399,7 @@ typedef struct
   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];       /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
diff --git a/cpu/stm32f0/include/stm32f051x8.h b/cpu/stm32f0/include/stm32f051x8.h
index 0091344c012b6d8a361ecc50e7c808213ef6d37d..14b0167dda41ae1cc8edb182a1f6fc9fd03c679c 100644
--- a/cpu/stm32f0/include/stm32f051x8.h
+++ b/cpu/stm32f0/include/stm32f051x8.h
@@ -451,10 +451,7 @@ typedef struct
   __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
   __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
-  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
-  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
-  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint32_t CCR[4];          /*!< TIM capture/compare register 1 - 4,          Address offset: 0x34 */
   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
   __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
diff --git a/cpu/stm32f0/include/stm32f070xb.h b/cpu/stm32f0/include/stm32f070xb.h
index 89556ca5fa37c2635d7807531e0a403af5a77e69..6a8350b04b5d33c868a125d37d18ff4aa29400d1 100644
--- a/cpu/stm32f0/include/stm32f070xb.h
+++ b/cpu/stm32f0/include/stm32f070xb.h
@@ -404,10 +404,7 @@ typedef struct
   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];       /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
diff --git a/cpu/stm32f0/include/stm32f072xb.h b/cpu/stm32f0/include/stm32f072xb.h
index e46190fecfd90c0c8ddf0cad4b63be15c1f2a650..0a69e112d4c16cd3f5aeb3fb2f77cd843f31a5f0 100755
--- a/cpu/stm32f0/include/stm32f072xb.h
+++ b/cpu/stm32f0/include/stm32f072xb.h
@@ -543,10 +543,7 @@ typedef struct
   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];       /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
diff --git a/cpu/stm32f0/include/stm32f091xc.h b/cpu/stm32f0/include/stm32f091xc.h
index 0478ded96da20e797c8117e773a89fd854ea7f24..f787161884635048db662be2a5c63d32c18df6bf 100644
--- a/cpu/stm32f0/include/stm32f091xc.h
+++ b/cpu/stm32f0/include/stm32f091xc.h
@@ -537,10 +537,7 @@ typedef struct
   __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
   __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
-  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
-  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
-  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint32_t CCR[4];          /*!< TIM capture/compare register 1-4,            Address offset: 0x34 */
   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
   __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
diff --git a/cpu/stm32f0/periph/timer.c b/cpu/stm32f0/periph/timer.c
deleted file mode 100644
index 4e6896e4597dba95dbdfa80fdcdee2583cfda781..0000000000000000000000000000000000000000
--- a/cpu/stm32f0/periph/timer.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * Copyright (C) 2014 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup     cpu_stm32f0
- * @{
- *
- * @file
- * @brief       Low-level timer driver implementation
- *
- * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
- *
- * @}
- */
-
-#include <stdlib.h>
-
-#include "cpu.h"
-#include "board.h"
-#include "sched.h"
-#include "thread.h"
-#include "periph_conf.h"
-#include "periph/timer.h"
-
-/* guard file in case no TIMER devices are defined */
-#if TIMER_0_EN || TIMER_1_EN
-
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev);
-
-/**
- * Timer state memory
- */
-static timer_isr_ctx_t config[TIMER_NUMOF];
-
-
-int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
-{
-    TIM_TypeDef *timer;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            /* enable timer peripheral clock */
-            TIMER_0_CLKEN();
-            /* set timer's IRQ priority */
-            NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
-            /* select timer */
-            timer = TIMER_0_DEV;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            /* enable timer peripheral clock */
-            TIMER_1_CLKEN();
-            /* set timer's IRQ priority */
-            NVIC_SetPriority(TIMER_1_IRQ_CHAN, TIMER_IRQ_PRIO);
-            /* select timer */
-            timer = TIMER_1_DEV;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-
-    /* set callback function */
-    config[dev].cb = cb;
-    config[dev].arg = arg;
-
-    /* set timer to run in counter mode */
-    timer->CR1 |= TIM_CR1_URS;
-
-    /* set auto-reload and prescaler values and load new values */
-    timer->ARR = TIMER_0_MAX_VALUE;
-    timer->PSC = (TIMER_0_FREQ / freq) - 1;
-    timer->EGR |= TIM_EGR_UG;
-
-    /* enable the timer's interrupt */
-    timer_irq_enable(dev);
-
-    /* start the timer */
-    timer_start(dev);
-
-    return 0;
-}
-
-int timer_set(tim_t dev, int channel, unsigned int timeout)
-{
-    int now = timer_read(dev);
-    return timer_set_absolute(dev, channel, now + timeout - 1);
-}
-
-int timer_set_absolute(tim_t dev, int channel, unsigned int value)
-{
-    TIM_TypeDef *timer = NULL;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            timer = TIMER_0_DEV;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            timer = TIMER_1_DEV;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-
-    switch (channel) {
-        case 0:
-            timer->CCR1 = value;
-            timer->SR &= ~TIM_SR_CC1IF;
-            timer->DIER |= TIM_DIER_CC1IE;
-            break;
-        case 1:
-            timer->CCR2 = value;
-            timer->SR &= ~TIM_SR_CC2IF;
-            timer->DIER |= TIM_DIER_CC2IE;
-            break;
-        case 2:
-            timer->CCR3 = value;
-            timer->SR &= ~TIM_SR_CC3IF;
-            timer->DIER |= TIM_DIER_CC3IE;
-            break;
-        case 3:
-            timer->CCR4 = value;
-            timer->SR &= ~TIM_SR_CC4IF;
-            timer->DIER |= TIM_DIER_CC4IE;
-            break;
-        default:
-            return -1;
-    }
-    return 0;
-}
-
-int timer_clear(tim_t dev, int channel)
-{
-    TIM_TypeDef *timer;
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            timer = TIMER_0_DEV;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            timer = TIMER_1_DEV;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-    switch (channel) {
-        case 0:
-            timer->DIER &= ~TIM_DIER_CC1IE;
-            break;
-        case 1:
-            timer->DIER &= ~TIM_DIER_CC2IE;
-            break;
-        case 2:
-            timer->DIER &= ~TIM_DIER_CC3IE;
-            break;
-        case 3:
-            timer->DIER &= ~TIM_DIER_CC4IE;
-            break;
-        default:
-            return -1;
-    }
-    return 0;
-}
-
-unsigned int timer_read(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            return TIMER_0_DEV->CNT;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            return TIMER_1_DEV->CNT;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return 0;
-    }
-}
-
-void timer_start(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            TIMER_0_DEV->CR1 |= TIM_CR1_CEN;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            TIMER_1_DEV->CR1 |= TIM_CR1_CEN;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_stop(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            TIMER_0_DEV->CR1 &= ~TIM_CR1_CEN;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            TIMER_1_DEV->CR1 &= ~TIM_CR1_CEN;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_irq_enable(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            NVIC_EnableIRQ(TIMER_0_IRQ_CHAN);
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            NVIC_EnableIRQ(TIMER_1_IRQ_CHAN);
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_irq_disable(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            NVIC_DisableIRQ(TIMER_0_IRQ_CHAN);
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            NVIC_DisableIRQ(TIMER_1_IRQ_CHAN);
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-#if TIMER_0_EN
-void TIMER_0_ISR(void)
-{
-    irq_handler(TIMER_0, TIMER_0_DEV);
-}
-#endif
-
-#if TIMER_1_EN
-void TIMER_1_ISR(void)
-{
-    irq_handler(TIMER_1, TIMER_1_DEV);
-}
-#endif
-
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev)
-{
-    if (dev->SR & TIM_SR_CC1IF) {
-        dev->DIER &= ~TIM_DIER_CC1IE;
-        dev->SR &= ~TIM_SR_CC1IF;
-        config[timer].cb(config[timer].arg, 0);
-    }
-    else if (dev->SR & TIM_SR_CC2IF) {
-        dev->DIER &= ~TIM_DIER_CC2IE;
-        dev->SR &= ~TIM_SR_CC2IF;
-        config[timer].cb(config[timer].arg, 1);
-    }
-    else if (dev->SR & TIM_SR_CC3IF) {
-        dev->DIER &= ~TIM_DIER_CC3IE;
-        dev->SR &= ~TIM_SR_CC3IF;
-        config[timer].cb(config[timer].arg, 2);
-    }
-    else if (dev->SR & TIM_SR_CC4IF) {
-        dev->DIER &= ~TIM_DIER_CC4IE;
-        dev->SR &= ~TIM_SR_CC4IF;
-        config[timer].cb(config[timer].arg, 3);
-    }
-    if (sched_context_switch_request) {
-        thread_yield();
-    }
-}
-#endif /* TIMER_0_EN || TIMER_1_EN */
diff --git a/cpu/stm32f1/include/periph_cpu.h b/cpu/stm32f1/include/periph_cpu.h
index 66b4c5c806096ff29c33ad37bb97a7e6e7cb860e..4ebe15fd983a0d8557d32eb897b2022ca591b086 100644
--- a/cpu/stm32f1/include/periph_cpu.h
+++ b/cpu/stm32f1/include/periph_cpu.h
@@ -30,16 +30,6 @@ extern "C" {
  */
 #define ADC_DEVS            (2U)
 
-/**
- * @brief   All timers for the STM32F1 have 4 CC channels
- */
-#define TIMER_CHANNELS      (4U)
-
-/**
- * @brief   All timers have a width of 16-bit
- */
-#define TIMER_MAXVAL        (0xffff)
-
 /**
  * @brief declare needed generic SPI functions
  * @{
@@ -136,16 +126,6 @@ typedef struct {
     uint8_t chan;           /**< CPU ADC channel connected to the pin */
 } adc_conf_t;
 
-/**
- * @brief   Timer configuration
- */
-typedef struct {
-    TIM_TypeDef *dev;       /**< timer device */
-    uint32_t rcc_mask;      /**< corresponding bit in the RCC register */
-    uint8_t bus;            /**< APBx bus the timer is clock from */
-    uint8_t irqn;           /**< global IRQ channel */
-} timer_conf_t;
-
 /**
  * @brief   UART configuration options
  */
diff --git a/cpu/stm32f2/include/periph_cpu.h b/cpu/stm32f2/include/periph_cpu.h
index 7be5c1a5572e7762ced7093bc2f6d92538c09e54..730f84ee1471968b9c0a48c1daa864a563efab99 100644
--- a/cpu/stm32f2/include/periph_cpu.h
+++ b/cpu/stm32f2/include/periph_cpu.h
@@ -113,22 +113,6 @@ typedef struct {
     uint8_t AF;             /**< alternate function */
 } pwm_conf_t;
 
-
-/**
- * @brief   Timer configuration
- * @{
- */
-typedef struct {
-    TIM_TypeDef *dev;       /**< timer device */
-    uint8_t channels;       /**< number of channel */
-    uint32_t freq;          /**< frequency */
-    uint32_t rcc_mask;      /**< corresponding bit in the RCC register */
-    uint8_t bus;            /**< APBx bus the timer is clock from */
-    uint8_t irqn;           /**< global IRQ channel */
-    uint8_t priority;       /**< priority */
-} timer_conf_t;
-/** @} */
-
 /**
  * @brief   Structure for UART configuration data
  * @{
diff --git a/cpu/stm32f2/include/stm32f205xx.h b/cpu/stm32f2/include/stm32f205xx.h
index 2df392001f4d5bc8c7f9ff938a637009e37fa5aa..7bd97235cbc50ceffe9eac7a7bf0f19d31385369 100644
--- a/cpu/stm32f2/include/stm32f205xx.h
+++ b/cpu/stm32f2/include/stm32f205xx.h
@@ -659,10 +659,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f2/include/stm32f207xx.h b/cpu/stm32f2/include/stm32f207xx.h
index 19184e8c0afeda4f72e1f79a24926b6bb2c7197a..7dce3752c6e3f3f5033fda844cb9d0c255b3d40c 100644
--- a/cpu/stm32f2/include/stm32f207xx.h
+++ b/cpu/stm32f2/include/stm32f207xx.h
@@ -754,10 +754,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f2/include/stm32f215xx.h b/cpu/stm32f2/include/stm32f215xx.h
index df6f857a3d791bd44ba3662d50ef3256099dd7d5..3101e8684979e8d70a47157af4b06602f3f04fe4 100644
--- a/cpu/stm32f2/include/stm32f215xx.h
+++ b/cpu/stm32f2/include/stm32f215xx.h
@@ -660,10 +660,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f2/include/stm32f217xx.h b/cpu/stm32f2/include/stm32f217xx.h
index 40730b681b5d93c79fd1c1ce356cfed593084cd7..65b6b0d348818a9ecc98cad2f0b16f506538c546 100644
--- a/cpu/stm32f2/include/stm32f217xx.h
+++ b/cpu/stm32f2/include/stm32f217xx.h
@@ -755,10 +755,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f2/periph/pwm.c b/cpu/stm32f2/periph/pwm.c
deleted file mode 100644
index 699d00dba415124eabc0ba8f8050d6a4fee226b4..0000000000000000000000000000000000000000
--- a/cpu/stm32f2/periph/pwm.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright (C) 2015 Engineering-Spirit
- * Copyright (C) 2016 OTA keys S.A.
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup     cpu_stm32f2
- * @{
- *
- * @file
- * @brief       Low-level PWM driver implementation
- *
- * @author      Hauke Petersen <mail@haukepetersen.de>
- * @author      Fabian Nack <nack@inf.fu-berlin.de>
- * @author      Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
- * @author      Aurelien Gonce <aurelien.gonce@altran.fr>
- *
- * @}
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include "cpu.h"
-#include "periph/pwm.h"
-#include "periph_conf.h"
-#include "periph/timer.h"
-
-/* ignore file in case no PWM devices are defined */
-#if (PWM_NUMOF > 0)
-
-/**
- * @brief   Get the timer device
- */
-static inline TIM_TypeDef *get_tim_dev(pwm_t tim)
-{
-    return timer_config[tim].dev;
-}
-
-/**
- * @brief   Get the pwm device
- */
-static inline GPIO_TypeDef *get_pwm_port(pwm_t pwm)
-{
-    return pwm_config[pwm].port;
-}
-
-uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
-{
-    GPIO_TypeDef *port = get_pwm_port(dev);
-    tim_t tim = pwm_config[dev].tim;
-    TIM_TypeDef *timer_dev = get_tim_dev(tim);
-    uint8_t channels = pwm_channels(tim);
-    uint32_t pins[channels];
-
-    /* enable timer peripheral clock */
-    pwm_poweron(tim);
-
-    /* pins configuration */
-    pins[0] = pwm_config[dev].CH0;
-    if (channels > 1) {
-        pins[1] = pwm_config[dev].CH1;
-    }
-    if (channels > 2) {
-        pins[2] = pwm_config[dev].CH2;
-    }
-    if (channels > 3) {
-        pins[3] = pwm_config[dev].CH3;
-    }
-
-    /* enable pwm peripheral */
-    if (pwm_config[dev].bus == AHB1) {
-        RCC->AHB1ENR |= pwm_config[dev].rcc_mask;
-    } else if (pwm_config[dev].bus == AHB2) {
-        RCC->AHB2ENR |= pwm_config[dev].rcc_mask;
-    } else {
-        RCC->AHB3ENR |= pwm_config[dev].rcc_mask;
-    }
-
-    /* setup pins: alternate function */
-    for (int i = 0; i < channels; i++) {
-        port->MODER &= ~(3 << (pins[i] * 2));
-        port->MODER |= (2 << (pins[i] * 2));
-        if (pins[i] < 8) {
-            port->AFR[0] &= ~(0xf << (pins[i] * 4));
-            port->AFR[0] |= (pwm_config[dev].AF << (pins[i] * 4));
-        } else {
-            port->AFR[1] &= ~(0xf << ((pins[i] - 8) * 4));
-            port->AFR[1] |= (pwm_config[dev].AF << ((pins[i] - 8) * 4));
-        }
-    }
-
-    /* Reset C/C and timer configuration register */
-    switch (channels) {
-        case 4:
-            timer_dev->CCR4 = 0;
-            /* Fall through */
-        case 3:
-            timer_dev->CCR3 = 0;
-            timer_dev->CR2 = 0;
-            /* Fall through */
-        case 2:
-            timer_dev->CCR2 = 0;
-            /* Fall through */
-        case 1:
-            timer_dev->CCR1 = 0;
-            timer_dev->CR1 = 0;
-            break;
-    }
-
-    /* set prescale and auto-reload registers to matching values for resolution and frequency */
-    if (res > 0xffff || (res * freq) > timer_config[tim].freq) {
-        return 0;
-    }
-    timer_dev->PSC = (timer_config[tim].freq / (res * freq)) - 1;
-    timer_dev->ARR = res - 1;
-    /* calculate the actual PWM frequency */
-    freq = (timer_config[tim].freq / (res * (timer_dev->PSC + 1)));
-
-    /* set PWM mode */
-    switch (mode) {
-        case PWM_LEFT:
-            timer_dev->CCMR1 = (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
-                                TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
-            if (channels > 2) {
-                timer_dev->CCMR2 = (TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
-                                    TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
-            }
-            break;
-        case PWM_RIGHT:
-            timer_dev->CCMR1 = (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
-                                TIM_CCMR1_OC2M_0 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2);
-            if (channels > 2) {
-                timer_dev->CCMR2 = (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
-                                    TIM_CCMR2_OC4M_0 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2);
-            }
-            break;
-        case PWM_CENTER:
-            timer_dev->CCMR1 = 0;
-            if (channels > 2) {
-                timer_dev->CCMR2 = 0;
-            }
-            timer_dev->CR1 |= (TIM_CR1_CMS_0 | TIM_CR1_CMS_1);
-            break;
-    }
-
-    /* enable output on PWM pins */
-    timer_dev->CCER = (TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E);
-
-    /* enable PWM outputs */
-    timer_dev->BDTR = TIM_BDTR_MOE;
-
-    /* enable timer ergo the PWM generation */
-    pwm_start(tim);
-
-    return freq;
-}
-
-uint8_t pwm_channels(pwm_t dev) {
-    return (timer_config[dev].channels);
-}
-
-void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
-{
-    tim_t tim = pwm_config[dev].tim;
-    TIM_TypeDef *timer_dev = get_tim_dev(tim);
-
-    if (channel >= pwm_channels(tim)) {
-        return;
-    }
-
-    /* norm value to maximum possible value */
-    if (value > timer_dev->ARR) {
-        value = (uint16_t) timer_dev->ARR;
-    }
-
-    switch (channel) {
-        case 0:
-            timer_dev->CCR1 = value;
-            break;
-        case 1:
-            timer_dev->CCR2 = value;
-            break;
-        case 2:
-            timer_dev->CCR3 = value;
-            break;
-        case 3:
-            timer_dev->CCR4 = value;
-            break;
-        default:
-            break;
-    }
-}
-
-void pwm_start(pwm_t dev)
-{
-    get_tim_dev(dev)->CR1 |= TIM_CR1_CEN;
-}
-
-void pwm_stop(pwm_t dev)
-{
-    get_tim_dev(dev)->CR1 &= ~(TIM_CR1_CEN);
-}
-
-void pwm_poweron(pwm_t dev)
-{
-    periph_clk_en(timer_config[dev].bus, timer_config[dev].rcc_mask);
-}
-
-void pwm_poweroff(pwm_t dev)
-{
-    periph_clk_dis(timer_config[dev].bus, timer_config[dev].rcc_mask);
-}
-
-#endif /* PWM_NUMOF > 0*/
diff --git a/cpu/stm32f2/periph/timer.c b/cpu/stm32f2/periph/timer.c
deleted file mode 100644
index a09a2e833c104fcfff1e4274be4c2f48256e2c8b..0000000000000000000000000000000000000000
--- a/cpu/stm32f2/periph/timer.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright (C) 2014 Freie Universität Berlin
- * Copyright (C) 2016  OTA keys S.A.
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup     cpu_stm32f2
- * @{
- *
- * @file
- * @brief       Low-level timer driver implementation
- *
- * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
- * @author      Aurelien Gonce <aurelien.gonce@altran.fr>
- *
- * @}
- */
-
-#include <stdlib.h>
-
-#include "cpu.h"
-#include "board.h"
-#include "sched.h"
-#include "thread.h"
-#include "periph_conf.h"
-#include "periph/timer.h"
-
-/** Unified IRQ handler for all timers */
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev);
-
-/** Timer state memory */
-static timer_isr_ctx_t config[TIMER_NUMOF];
-
-/**
- * @brief   Get the timer device
- */
-static inline TIM_TypeDef *get_dev(tim_t tim)
-{
-    return timer_config[tim].dev;
-}
-
-int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
-{
-    /* check if device is valid */
-    if (dev >= TIMER_NUMOF) {
-        return -1;
-    }
-
-    /* enable timer peripheral clock */
-    periph_clk_en(timer_config[dev].bus, timer_config[dev].rcc_mask);
-
-    /* set timer's IRQ priority */
-    NVIC_SetPriority(timer_config[dev].irqn, timer_config[dev].priority);
-
-    /* set prescaler */
-    get_dev(dev)->PSC = (timer_config[dev].freq / freq) - 1;
-
-    /* set callback function */
-    config[dev].cb = cb;
-    config[dev].arg = arg;
-
-    /* set timer to run in counter mode */
-    get_dev(dev)->CR1 = 0;
-    get_dev(dev)->CR2 = 0;
-
-    /* set auto-reload and prescaler values and load new values */
-    get_dev(dev)->EGR |= TIM_EGR_UG;
-
-    /* enable the timer's interrupt */
-    timer_irq_enable(dev);
-
-    /* start the timer */
-    timer_start(dev);
-
-    return 0;
-}
-
-int timer_set(tim_t dev, int channel, unsigned int timeout)
-{
-    int now = timer_read(dev);
-    return timer_set_absolute(dev, channel, now + timeout);
-}
-
-int timer_set_absolute(tim_t dev, int channel, unsigned int value)
-{
-    if (channel >= timer_config[dev].channels || dev >= TIMER_NUMOF) {
-        return -1;
-    }
-
-    switch (channel) {
-        case 0:
-            get_dev(dev)->CCR1 = value;
-            get_dev(dev)->SR &= ~TIM_SR_CC1IF;
-            get_dev(dev)->DIER |= TIM_DIER_CC1IE;
-            break;
-        case 1:
-            get_dev(dev)->CCR2 = value;
-            get_dev(dev)->SR &= ~TIM_SR_CC2IF;
-            get_dev(dev)->DIER |= TIM_DIER_CC2IE;
-            break;
-        case 2:
-            get_dev(dev)->CCR3 = value;
-            get_dev(dev)->SR &= ~TIM_SR_CC3IF;
-            get_dev(dev)->DIER |= TIM_DIER_CC3IE;
-            break;
-        case 3:
-            get_dev(dev)->CCR4 = value;
-            get_dev(dev)->SR &= ~TIM_SR_CC4IF;
-            get_dev(dev)->DIER |= TIM_DIER_CC4IE;
-            break;
-        default:
-            return -1;
-    }
-
-    return 0;
-}
-
-int timer_clear(tim_t dev, int channel)
-{
-    if (channel >= timer_config[dev].channels || dev >= TIMER_NUMOF) {
-        return -1;
-    }
-
-    get_dev(dev)->DIER &= ~(TIM_DIER_CC1IE << channel);
-
-    return 0;
-}
-
-unsigned int timer_read(tim_t dev)
-{
-    return (unsigned int)get_dev(dev)->CNT;
-}
-
-void timer_start(tim_t dev)
-{
-    get_dev(dev)->CR1 |= TIM_CR1_CEN;
-}
-
-void timer_stop(tim_t dev)
-{
-    get_dev(dev)->CR1 &= ~TIM_CR1_CEN;
-}
-
-void timer_irq_enable(tim_t dev)
-{
-    NVIC_EnableIRQ(timer_config[dev].irqn);
-}
-
-void timer_irq_disable(tim_t dev)
-{
-    NVIC_DisableIRQ(timer_config[dev].irqn);
-}
-
-void TIMER_0_ISR(void)
-{
-    irq_handler(TIMER_0, get_dev(TIMER_0));
-}
-
-void TIMER_1_ISR(void)
-{
-    irq_handler(TIMER_1, get_dev(TIMER_1));
-}
-
-void TIMER_2_ISR(void)
-{
-    irq_handler(TIMER_2, get_dev(TIMER_2));
-}
-
-void TIMER_3_ISR(void)
-{
-    irq_handler(TIMER_3, get_dev(TIMER_3));
-}
-
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev)
-{
-    if (dev->SR & TIM_SR_CC1IF) {
-        dev->DIER &= ~TIM_DIER_CC1IE;
-        dev->SR &= ~TIM_SR_CC1IF;
-        config[timer].cb(config[timer].arg, 0);
-    }
-    else if (dev->SR & TIM_SR_CC2IF) {
-        dev->DIER &= ~TIM_DIER_CC2IE;
-        dev->SR &= ~TIM_SR_CC2IF;
-        config[timer].cb(config[timer].arg, 1);
-    }
-    else if (dev->SR & TIM_SR_CC3IF) {
-        dev->DIER &= ~TIM_DIER_CC3IE;
-        dev->SR &= ~TIM_SR_CC3IF;
-        config[timer].cb(config[timer].arg, 2);
-    }
-    else if (dev->SR & TIM_SR_CC4IF) {
-        dev->DIER &= ~TIM_DIER_CC4IE;
-        dev->SR &= ~TIM_SR_CC4IF;
-        config[timer].cb(config[timer].arg, 3);
-    }
-    if (sched_context_switch_request) {
-        thread_yield();
-    }
-}
diff --git a/cpu/stm32f3/include/stm32f303xc.h b/cpu/stm32f3/include/stm32f303xc.h
index 2a63eec22f66bf4425e738843855afe1383fd05c..8092514f8ca5652f1bd18383b2157b71b5604439 100644
--- a/cpu/stm32f3/include/stm32f303xc.h
+++ b/cpu/stm32f3/include/stm32f303xc.h
@@ -601,10 +601,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f3/include/stm32f303xe.h b/cpu/stm32f3/include/stm32f303xe.h
index 8ca99f50fa77221332513b9c3a8787163b1ef61a..95c7dfaf347ae81ad1da9e7c3a5645064c157a12 100644
--- a/cpu/stm32f3/include/stm32f303xe.h
+++ b/cpu/stm32f3/include/stm32f303xe.h
@@ -676,10 +676,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f3/include/stm32f334x8.h b/cpu/stm32f3/include/stm32f334x8.h
index 26348529f1639fe6f44a439011673080d391618d..61e576cf18b1b358b3661ea9c615762a4b0184f8 100644
--- a/cpu/stm32f3/include/stm32f334x8.h
+++ b/cpu/stm32f3/include/stm32f334x8.h
@@ -693,10 +693,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f3/periph/pwm.c b/cpu/stm32f3/periph/pwm.c
index 21d727bba31401a3f2d6ad8cf46da5c468206e7f..b906251c5f90190c517c9a62c228537f43f36b9c 100644
--- a/cpu/stm32f3/periph/pwm.c
+++ b/cpu/stm32f3/periph/pwm.c
@@ -167,22 +167,7 @@ void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
             return;
     }
 
-    switch (channel) {
-        case 0:
-            tim->CCR1 = value;
-            break;
-        case 1:
-            tim->CCR2 = value;
-            break;
-        case 2:
-            tim->CCR3 = value;
-            break;
-        case 3:
-            tim->CCR4 = value;
-            break;
-        default:
-            return;
-    }
+    tim->CCR[channel] = value;
 }
 
 void pwm_start(pwm_t dev)
diff --git a/cpu/stm32f3/periph/timer.c b/cpu/stm32f3/periph/timer.c
deleted file mode 100644
index d6a25a26ff52926623bbefc6042bdce4701be342..0000000000000000000000000000000000000000
--- a/cpu/stm32f3/periph/timer.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * Copyright (C) 2014 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup     cpu_stm32f3
- * @{
- *
- * @file
- * @brief       Low-level timer driver implementation
- *
- * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
- *
- * @}
- */
-
-#include <stdlib.h>
-
-#include "cpu.h"
-#include "board.h"
-#include "sched.h"
-#include "thread.h"
-#include "periph_conf.h"
-#include "periph/timer.h"
-
-/** Unified IRQ handler for all timers */
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev);
-
-/** Timer state memory */
-static timer_isr_ctx_t config[TIMER_NUMOF];
-
-
-int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
-{
-    TIM_TypeDef *timer;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            /* enable timer peripheral clock */
-            TIMER_0_CLKEN();
-            /* set timer's IRQ priority */
-            NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
-            /* select timer */
-            timer = TIMER_0_DEV;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-
-    /* set callback function */
-    config[dev].cb = cb;
-    config[dev].arg = arg;
-
-    /* set timer to run in counter mode */
-    timer->CR1 = 0;
-    timer->CR2 = 0;
-
-    /* set auto-reload and prescaler values and load new values */
-    timer->PSC = (TIMER_0_FREQ / freq) - 1;
-    timer->EGR |= TIM_EGR_UG;
-
-    /* enable the timer's interrupt */
-    timer_irq_enable(dev);
-
-    /* start the timer */
-    timer_start(dev);
-
-    return 0;
-}
-
-int timer_set(tim_t dev, int channel, unsigned int timeout)
-{
-    int now = timer_read(dev);
-    return timer_set_absolute(dev, channel, now + timeout - 1);
-}
-
-int timer_set_absolute(tim_t dev, int channel, unsigned int value)
-{
-    TIM_TypeDef *timer;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            timer = TIMER_0_DEV;
-            break;
-#endif
-        default:
-            return -1;
-    }
-
-    switch (channel) {
-        case 0:
-            timer->CCR1 = value;
-            timer->SR &= ~TIM_SR_CC1IF;
-            timer->DIER |= TIM_DIER_CC1IE;
-            break;
-        case 1:
-            timer->CCR2 = value;
-            timer->SR &= ~TIM_SR_CC2IF;
-            timer->DIER |= TIM_DIER_CC2IE;
-            break;
-        case 2:
-            timer->CCR3 = value;
-            timer->SR &= ~TIM_SR_CC3IF;
-            timer->DIER |= TIM_DIER_CC3IE;
-            break;
-        case 3:
-            timer->CCR4 = value;
-            timer->SR &= ~TIM_SR_CC4IF;
-            timer->DIER |= TIM_DIER_CC4IE;
-            break;
-        default:
-            return -1;
-    }
-
-    return 0;
-}
-
-int timer_clear(tim_t dev, int channel)
-{
-    TIM_TypeDef *timer;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            timer = TIMER_0_DEV;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-
-    switch (channel) {
-        case 0:
-            timer->DIER &= ~TIM_DIER_CC1IE;
-            break;
-        case 1:
-            timer->DIER &= ~TIM_DIER_CC2IE;
-            break;
-        case 2:
-            timer->DIER &= ~TIM_DIER_CC3IE;
-            break;
-        case 3:
-            timer->DIER &= ~TIM_DIER_CC4IE;
-            break;
-        default:
-            return -1;
-    }
-
-    return 0;
-}
-
-unsigned int timer_read(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            return TIMER_0_DEV->CNT;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return 0;
-    }
-}
-
-void timer_start(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            TIMER_0_DEV->CR1 |= TIM_CR1_CEN;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_stop(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            TIMER_0_DEV->CR1 &= ~TIM_CR1_CEN;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_irq_enable(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            NVIC_EnableIRQ(TIMER_0_IRQ_CHAN);
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_irq_disable(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            NVIC_DisableIRQ(TIMER_0_IRQ_CHAN);
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-#if TIMER_0_EN
-void TIMER_0_ISR(void)
-{
-    irq_handler(TIMER_0, TIMER_0_DEV);
-}
-#endif
-
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev)
-{
-    if (dev->SR & TIM_SR_CC1IF) {
-        dev->DIER &= ~TIM_DIER_CC1IE;
-        dev->SR &= ~TIM_SR_CC1IF;
-        config[timer].cb(config[timer].arg, 0);
-    }
-    else if (dev->SR & TIM_SR_CC2IF) {
-        dev->DIER &= ~TIM_DIER_CC2IE;
-        dev->SR &= ~TIM_SR_CC2IF;
-        config[timer].cb(config[timer].arg, 1);
-    }
-    else if (dev->SR & TIM_SR_CC3IF) {
-        dev->DIER &= ~TIM_DIER_CC3IE;
-        dev->SR &= ~TIM_SR_CC3IF;
-        config[timer].cb(config[timer].arg, 2);
-    }
-    else if (dev->SR & TIM_SR_CC4IF) {
-        dev->DIER &= ~TIM_DIER_CC4IE;
-        dev->SR &= ~TIM_SR_CC4IF;
-        config[timer].cb(config[timer].arg, 3);
-    }
-    if (sched_context_switch_request) {
-        thread_yield();
-    }
-}
diff --git a/cpu/stm32f4/include/stm32f401xe.h b/cpu/stm32f4/include/stm32f401xe.h
index 37285418ab79f5a4d41b639bd0180cd132c662b0..661505f490af6f92e9542c6a2a56e3eb99c9f3d4 100644
--- a/cpu/stm32f4/include/stm32f401xe.h
+++ b/cpu/stm32f4/include/stm32f401xe.h
@@ -498,10 +498,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f4/include/stm32f407xx.h b/cpu/stm32f4/include/stm32f407xx.h
index af53f573b8f9c0cf6f272bb400f77c018ed5edb2..62f43dce813f9fc44944ce09f90ba45419a6de40 100644
--- a/cpu/stm32f4/include/stm32f407xx.h
+++ b/cpu/stm32f4/include/stm32f407xx.h
@@ -757,10 +757,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f4/include/stm32f415xx.h b/cpu/stm32f4/include/stm32f415xx.h
index c5b2bf4ca60930026fae4656002137d77b94a4ec..6675e8ecfd223bb23900be1ec5109c19dc3f1441 100644
--- a/cpu/stm32f4/include/stm32f415xx.h
+++ b/cpu/stm32f4/include/stm32f415xx.h
@@ -663,10 +663,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f4/include/stm32f446xx.h b/cpu/stm32f4/include/stm32f446xx.h
index e9c5dffaa0067530aa8f655f10f02d92d04a73c2..18f1665c153f43e4f15652368d93069327ddbc73 100644
--- a/cpu/stm32f4/include/stm32f446xx.h
+++ b/cpu/stm32f4/include/stm32f446xx.h
@@ -774,10 +774,7 @@ typedef struct
   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t CCR[4];      /*!< TIM capture/compare register 1-4,    Address offset: 0x34 */
   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
diff --git a/cpu/stm32f4/periph/pwm.c b/cpu/stm32f4/periph/pwm.c
index 6febecfcfebf46cedfa42a71d2f3c401b7b8eb69..2c02680cbdd8667dbeb067725da770a7dd32c58e 100644
--- a/cpu/stm32f4/periph/pwm.c
+++ b/cpu/stm32f4/periph/pwm.c
@@ -102,17 +102,17 @@ uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
     /* Reset C/C and timer configuration register */
     switch (channels) {
         case 4:
-            tim->CCR4 = 0;
+            tim->CCR[3] = 0;
             /* Fall through */
         case 3:
-            tim->CCR3 = 0;
+            tim->CCR[2] = 0;
             tim->CR2 = 0;
             /* Fall through */
         case 2:
-            tim->CCR2 = 0;
+            tim->CCR[1] = 0;
             /* Fall through */
         case 1:
-            tim->CCR1 = 0;
+            tim->CCR[0] = 0;
             tim->CR1 = 0;
             break;
     }
@@ -211,22 +211,7 @@ void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
         value = (uint32_t)tim->ARR;
     }
 
-    switch (channel) {
-        case 0:
-            tim->CCR1 = value;
-            break;
-        case 1:
-            tim->CCR2 = value;
-            break;
-        case 2:
-            tim->CCR3 = value;
-            break;
-        case 3:
-            tim->CCR4 = value;
-            break;
-        default:
-            return;
-    }
+    tim->CCR[channel] = value;
 }
 
 void pwm_start(pwm_t dev)
diff --git a/cpu/stm32f4/periph/timer.c b/cpu/stm32f4/periph/timer.c
deleted file mode 100644
index 6b2db5892d4305d9d5f608ad5907f24dba5e7040..0000000000000000000000000000000000000000
--- a/cpu/stm32f4/periph/timer.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Copyright (C) 2014 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup     cpu_stm32f4
- * @{
- *
- * @file
- * @brief       Low-level timer driver implementation
- *
- * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
- *
- * @}
- */
-
-#include <stdlib.h>
-
-#include "cpu.h"
-#include "board.h"
-#include "sched.h"
-#include "thread.h"
-#include "periph_conf.h"
-#include "periph/timer.h"
-
-/** Unified IRQ handler for all timers */
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev);
-
-/** Timer state memory */
-static timer_isr_ctx_t config[TIMER_NUMOF];
-
-
-int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
-{
-    TIM_TypeDef *timer;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            /* enable timer peripheral clock */
-            TIMER_0_CLKEN();
-            /* set timer's IRQ priority */
-            NVIC_SetPriority(TIMER_0_IRQ_CHAN, TIMER_IRQ_PRIO);
-            /* select timer */
-            timer = TIMER_0_DEV;
-            timer->PSC = (TIMER_0_FREQ / freq) - 1;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            /* enable timer peripheral clock */
-            TIMER_1_CLKEN();
-            /* set timer's IRQ priority */
-            NVIC_SetPriority(TIMER_1_IRQ_CHAN, TIMER_IRQ_PRIO);
-            /* select timer */
-            timer = TIMER_1_DEV;
-            timer->PSC = (TIMER_1_FREQ / freq) - 1;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-
-    /* set callback function */
-    config[dev].cb = cb;
-    config[dev].arg = arg;
-
-    /* set timer to run in counter mode */
-    timer->CR1 = 0;
-    timer->CR2 = 0;
-
-    /* set auto-reload and prescaler values and load new values */
-    timer->EGR |= TIM_EGR_UG;
-
-    /* enable the timer's interrupt */
-    timer_irq_enable(dev);
-
-    /* start the timer */
-    timer_start(dev);
-
-    return 0;
-}
-
-int timer_set(tim_t dev, int channel, unsigned int timeout)
-{
-    int now = timer_read(dev);
-    return timer_set_absolute(dev, channel, now + timeout - 1);
-}
-
-int timer_set_absolute(tim_t dev, int channel, unsigned int value)
-{
-    TIM_TypeDef *timer;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            timer = TIMER_0_DEV;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            timer = TIMER_1_DEV;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-
-    switch (channel) {
-        case 0:
-            timer->CCR1 = value;
-            timer->SR &= ~TIM_SR_CC1IF;
-            timer->DIER |= TIM_DIER_CC1IE;
-            break;
-        case 1:
-            timer->CCR2 = value;
-            timer->SR &= ~TIM_SR_CC2IF;
-            timer->DIER |= TIM_DIER_CC2IE;
-            break;
-        case 2:
-            timer->CCR3 = value;
-            timer->SR &= ~TIM_SR_CC3IF;
-            timer->DIER |= TIM_DIER_CC3IE;
-            break;
-        case 3:
-            timer->CCR4 = value;
-            timer->SR &= ~TIM_SR_CC4IF;
-            timer->DIER |= TIM_DIER_CC4IE;
-            break;
-        default:
-            return -1;
-    }
-
-    return 0;
-}
-
-int timer_clear(tim_t dev, int channel)
-{
-    TIM_TypeDef *timer;
-
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            timer = TIMER_0_DEV;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            timer = TIMER_1_DEV;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return -1;
-    }
-
-    switch (channel) {
-        case 0:
-            timer->DIER &= ~TIM_DIER_CC1IE;
-            break;
-        case 1:
-            timer->DIER &= ~TIM_DIER_CC2IE;
-            break;
-        case 2:
-            timer->DIER &= ~TIM_DIER_CC3IE;
-            break;
-        case 3:
-            timer->DIER &= ~TIM_DIER_CC4IE;
-            break;
-        default:
-            return -1;
-    }
-
-    return 0;
-}
-
-unsigned int timer_read(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            return TIMER_0_DEV->CNT;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            return TIMER_1_DEV->CNT;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-        default:
-            return 0;
-    }
-}
-
-void timer_start(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            TIMER_0_DEV->CR1 |= TIM_CR1_CEN;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            TIMER_1_DEV->CR1 |= TIM_CR1_CEN;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_stop(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            TIMER_0_DEV->CR1 &= ~TIM_CR1_CEN;
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            TIMER_1_DEV->CR1 &= ~TIM_CR1_CEN;
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_irq_enable(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            NVIC_EnableIRQ(TIMER_0_IRQ_CHAN);
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            NVIC_EnableIRQ(TIMER_1_IRQ_CHAN);
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void timer_irq_disable(tim_t dev)
-{
-    switch (dev) {
-#if TIMER_0_EN
-        case TIMER_0:
-            NVIC_DisableIRQ(TIMER_0_IRQ_CHAN);
-            break;
-#endif
-#if TIMER_1_EN
-        case TIMER_1:
-            NVIC_DisableIRQ(TIMER_1_IRQ_CHAN);
-            break;
-#endif
-        case TIMER_UNDEFINED:
-            break;
-    }
-}
-
-void TIMER_0_ISR(void)
-{
-    irq_handler(TIMER_0, TIMER_0_DEV);
-}
-
-void TIMER_1_ISR(void)
-{
-    irq_handler(TIMER_1, TIMER_1_DEV);
-}
-
-static inline void irq_handler(tim_t timer, TIM_TypeDef *dev)
-{
-    if (dev->SR & TIM_SR_CC1IF) {
-        dev->DIER &= ~TIM_DIER_CC1IE;
-        dev->SR &= ~TIM_SR_CC1IF;
-        config[timer].cb(config[timer].arg, 0);
-    }
-    else if (dev->SR & TIM_SR_CC2IF) {
-        dev->DIER &= ~TIM_DIER_CC2IE;
-        dev->SR &= ~TIM_SR_CC2IF;
-        config[timer].cb(config[timer].arg, 1);
-    }
-    else if (dev->SR & TIM_SR_CC3IF) {
-        dev->DIER &= ~TIM_DIER_CC3IE;
-        dev->SR &= ~TIM_SR_CC3IF;
-        config[timer].cb(config[timer].arg, 2);
-    }
-    else if (dev->SR & TIM_SR_CC4IF) {
-        dev->DIER &= ~TIM_DIER_CC4IE;
-        dev->SR &= ~TIM_SR_CC4IF;
-        config[timer].cb(config[timer].arg, 3);
-    }
-    if (sched_context_switch_request) {
-        thread_yield();
-    }
-}
diff --git a/cpu/stm32l1/include/periph_cpu.h b/cpu/stm32l1/include/periph_cpu.h
index 00856683ca995ca2131e461ad7154e6477fa948d..a8be489f2a6fc1b892c5011cfdb90d80142cb222 100644
--- a/cpu/stm32l1/include/periph_cpu.h
+++ b/cpu/stm32l1/include/periph_cpu.h
@@ -107,15 +107,6 @@ typedef struct {
  */
 void gpio_init_af(gpio_t pin, gpio_af_t af);
 
-/**
- * @brief   Timer configuration data structure
- */
-typedef struct {
-    TIM_TypeDef *dev;       /**< timer device */
-    uint8_t rcc;            /**< bit in the RCC register */
-    uint8_t irqn;           /**< IRQ vector entry number */
-} timer_conf_t;
-
 /**
  * @brief   I2C configuration data structure
  */
diff --git a/cpu/stm32l1/include/stm32l1xx.h b/cpu/stm32l1/include/stm32l1xx.h
index 9e168897481f942f4bf254d7e9b9bd60e9e99cd3..84117731ecf30a90a16116ffcb65c8fffb85b220 100644
--- a/cpu/stm32l1/include/stm32l1xx.h
+++ b/cpu/stm32l1/include/stm32l1xx.h
@@ -852,7 +852,7 @@ typedef struct
   uint16_t      RESERVED10;   /*!< Reserved, 0x2A                                            */
   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
   uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */
-  __IO uint32_t CCR[4];       /*!< TIM capture/compare registers 1-4,      Address offset: 0x34 ++ */
+  __IO uint32_t CCR[4];       /*!< TIM capture/compare registers 1-4,   Address offset: 0x34 ++ */
   uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */
   __IO uint16_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
   uint16_t      RESERVED18;   /*!< Reserved, 0x4A                                            */
diff --git a/cpu/stm32l1/periph/timer.c b/cpu/stm32l1/periph/timer.c
deleted file mode 100644
index 03c074b9b83f881f1bb7ad1d4124b766fdbe61c9..0000000000000000000000000000000000000000
--- a/cpu/stm32l1/periph/timer.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @addtogroup  driver_periph
- * @{
- *
- * @file
- * @brief       Low-level timer driver implementation
- *
- * @author      Thomas Eichinger <thomas.eichinger@fu-berlin.de>
- * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
- *
- * @}
- */
-
-#include "cpu.h"
-#include "sched.h"
-#include "thread.h"
-#include "periph_conf.h"
-#include "periph/timer.h"
-
-/**
- * @brief   All timers on this CPU have 4 channels
- */
-#define CHANNEL_NUMOF       (4U)
-
-/**
- * @brief   Interrupt state
- */
-static timer_isr_ctx_t isr_ctx[TIMER_NUMOF];
-
-/**
- * @brief   Get the timers base register
- */
-static inline TIM_TypeDef *_tim(tim_t dev)
-{
-    return timer_config[dev].dev;
-}
-
-int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
-{
-    TIM_TypeDef *tim;
-
-    /* check if given timer exists */
-    if (dev >= TIMER_NUMOF) {
-        return -1;
-    }
-
-    /* get base register */
-    tim = _tim(dev);
-    /* save callback */
-    isr_ctx[dev].cb = cb;
-    isr_ctx[dev].arg = arg;
-    /* enable peripheral clock */
-    RCC->APB1ENR |= (1 << timer_config[dev].rcc);
-    /* reset timer and configure to up-counting mode */
-    tim->CR1 = 0;
-    tim->CR2 = 0;
-    tim->SR = 0;
-    /* configure reload and pre-scaler values */
-    tim->ARR = 0xffffffff;
-    tim->PSC = (CLOCK_CORECLOCK / freq) - 1;
-    /* trigger update event to make pre-scaler value effective */
-    tim->EGR = TIM_EGR_UG;
-    /* enable interrupts and start the timer */
-    timer_irq_enable(dev);
-    timer_start(dev);
-    return 0;
-}
-
-int timer_set(tim_t dev, int channel, unsigned int timeout)
-{
-    int now = timer_read(dev);
-    return timer_set_absolute(dev, channel, now + timeout - 1);
-}
-
-int timer_set_absolute(tim_t dev, int channel, unsigned int value)
-{
-    TIM_TypeDef *tim;
-
-    if (dev >= TIMER_NUMOF || channel >= CHANNEL_NUMOF || channel < 0) {
-        return -1;
-    }
-
-    tim = _tim(dev);
-    tim->CCR[channel] = value;
-    tim->SR &= ~(1 << (channel + 1));
-    tim->DIER |= (1 << (channel + 1));
-    return 0;
-}
-
-int timer_clear(tim_t dev, int channel)
-{
-    TIM_TypeDef *tim;
-
-    if (dev >= TIMER_NUMOF || channel >= CHANNEL_NUMOF || channel < 0) {
-        return -1;
-    }
-
-    tim = _tim(dev);
-    tim->DIER &= ~(1 << (channel + 1));
-    return 0;
-}
-
-unsigned int timer_read(tim_t dev)
-{
-    return (unsigned int)_tim(dev)->CNT;
-}
-
-void timer_start(tim_t dev)
-{
-    _tim(dev)->CR1 |= TIM_CR1_CEN;
-}
-
-void timer_stop(tim_t dev)
-{
-    _tim(dev)->CR1 &= ~(TIM_CR1_CEN);
-}
-
-void timer_irq_enable(tim_t dev)
-{
-    NVIC_EnableIRQ(timer_config[dev].irqn);
-}
-
-void timer_irq_disable(tim_t dev)
-{
-    NVIC_DisableIRQ(timer_config[dev].irqn);
-}
-
-static inline void irq_handler(tim_t num, TIM_TypeDef *tim)
-{
-    for (int i = 0; i < CHANNEL_NUMOF; i++) {
-        uint16_t bit = (1 << (i + 1));
-        if ((tim->SR & bit) && (tim->DIER & bit)) {
-            tim->SR &= ~(bit);
-            tim->DIER &= ~(bit);
-            isr_ctx[num].cb(isr_ctx[num].arg, i);
-        }
-    }
-    if (sched_context_switch_request) {
-        thread_yield();
-    }
-}
-
-#ifdef TIMER_0_ISR
-void TIMER_0_ISR(void)
-{
-    irq_handler(0, timer_config[0].dev);
-}
-#endif
-
-#ifdef TIMER_1_ISR
-void TIMER_1_ISR(void)
-{
-    irq_handler(0, timer_config[0].dev);
-}
-#endif