diff --git a/boards/nucleo-l073/Makefile b/boards/nucleo-l073/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f8fcbb53a06595771dae356338a7bf2c0673734d
--- /dev/null
+++ b/boards/nucleo-l073/Makefile
@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/nucleo-l073/Makefile.dep b/boards/nucleo-l073/Makefile.dep
new file mode 100644
index 0000000000000000000000000000000000000000..76e2dc17b45c22bfb5b499e63647610ca247b349
--- /dev/null
+++ b/boards/nucleo-l073/Makefile.dep
@@ -0,0 +1 @@
+include $(RIOTBOARD)/nucleo-common/Makefile.dep
diff --git a/boards/nucleo-l073/Makefile.features b/boards/nucleo-l073/Makefile.features
new file mode 100644
index 0000000000000000000000000000000000000000..ae8430d7d88f442094464a3060f8ba600e6e73de
--- /dev/null
+++ b/boards/nucleo-l073/Makefile.features
@@ -0,0 +1,13 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# load the common Makefile.features for Nucleo boards
+include $(RIOTBOARD)/nucleo-common/Makefile.features
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m0_1
diff --git a/boards/nucleo-l073/Makefile.include b/boards/nucleo-l073/Makefile.include
new file mode 100644
index 0000000000000000000000000000000000000000..71759157dcff838d750a0ff7c2c49b7b29a80c0c
--- /dev/null
+++ b/boards/nucleo-l073/Makefile.include
@@ -0,0 +1,6 @@
+## the cpu to build for
+export CPU = stm32l0
+export CPU_MODEL = stm32l073rz
+
+# load the common Makefile.include for Nucleo boards
+include $(RIOTBOARD)/nucleo-common/Makefile.include
diff --git a/boards/nucleo-l073/board.c b/boards/nucleo-l073/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..03eb7f4caec71c439f83e809d8da1a0b230e5e5f
--- /dev/null
+++ b/boards/nucleo-l073/board.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Freie Universität Berlin
+ * 2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo-l073
+ * @{
+ *
+ * @file
+ * @brief Board specific implementations for the nucleo-l073 board
+ *
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+
+
+void board_init(void)
+{
+ /* initialize the boards LED */
+ gpio_init(LED0_PIN, GPIO_OUT);
+
+ /* initialize the CPU */
+ cpu_init();
+}
diff --git a/boards/nucleo-l073/dist/openocd.cfg b/boards/nucleo-l073/dist/openocd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..b4c77067577c9921998ea962edb9368452143d36
--- /dev/null
+++ b/boards/nucleo-l073/dist/openocd.cfg
@@ -0,0 +1,7 @@
+source [find interface/stlink-v2-1.cfg]
+
+transport select hla_swd
+
+source [find target/stm32l0.cfg]
+
+reset_config srst_only
diff --git a/boards/nucleo-l073/include/board.h b/boards/nucleo-l073/include/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..d410d7e1d5d22451b216d96d16fb735a4e2a82c3
--- /dev/null
+++ b/boards/nucleo-l073/include/board.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2017 Freie Universität Berlin
+ * 2017 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup boards_nucleo-l073 Nucleo-L073
+ * @ingroup boards
+ * @brief Board specific files for the nucleo-l073 board
+ * @{
+ *
+ * @file
+ * @brief Board specific definitions for the nucleo-l073 board
+ *
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author Alexandre Aabdie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include <stdint.h>
+#include "board_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name xtimer configuration
+ * @{
+ */
+#define XTIMER_DEV TIMER_DEV(0)
+#define XTIMER_CHAN (0)
+#define XTIMER_WIDTH (16)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */
diff --git a/boards/nucleo-l073/include/periph_conf.h b/boards/nucleo-l073/include/periph_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..5778149f7eea5a666ec61f645408e51258630449
--- /dev/null
+++ b/boards/nucleo-l073/include/periph_conf.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2017 Freie Universität Berlin
+ * 2017 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo-l073
+ * @{
+ *
+ * @file
+ * @brief Peripheral MCU configuration for the nucleo-l073 board
+ *
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author Alexandre Aabdie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+#define CLOCK_HSI (16000000U) /* internal oscillator */
+#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
+
+/* configuration of PLL prescaler and multiply values */
+/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
+#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
+#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
+/* configuration of peripheral bus clock prescalers */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
+/* configuration of flash access cycles */
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
+/** @} */
+
+/**
+ * @brief Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+ {
+ .dev = TIM2,
+ .max = 0x0000ffff,
+ .rcc_mask = RCC_APB1ENR_TIM2EN,
+ .bus = APB1,
+ .irqn = TIM2_IRQn
+ }
+};
+
+#define TIMER_0_ISR isr_tim2
+
+#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @brief UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+ {
+ .dev = USART2,
+ .rcc_mask = RCC_APB1ENR_USART2EN,
+ .rx_pin = GPIO_PIN(PORT_A, 3),
+ .tx_pin = GPIO_PIN(PORT_A, 2),
+ .rx_af = GPIO_AF4,
+ .tx_af = GPIO_AF4,
+ .bus = APB1,
+ .irqn = USART2_IRQn
+ },
+ {
+ .dev = USART4,
+ .rcc_mask = RCC_APB1ENR_USART4EN,
+ .rx_pin = GPIO_PIN(PORT_C, 11),
+ .tx_pin = GPIO_PIN(PORT_C, 10),
+ .rx_af = GPIO_AF6,
+ .tx_af = GPIO_AF6,
+ .bus = APB1,
+ .irqn = USART4_5_IRQn
+ },
+};
+
+#define UART_0_ISR (isr_usart2)
+#define UART_1_ISR (isr_usart4_5)
+
+#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @brief PWM configuration
+ * @{
+ */
+static const pwm_conf_t pwm_config[] = {
+ {
+ .dev = TIM3,
+ .rcc_mask = RCC_APB1ENR_TIM3EN,
+ .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
+ { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
+ { .pin = GPIO_PIN(PORT_C, 8) , .cc_chan = 2 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 } },
+ .af = GPIO_AF2,
+ .bus = APB1
+ }
+};
+
+#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
+/** @} */
+
+/**
+ * @name SPI configuration
+ *
+ * @note The spi_divtable is auto-generated from
+ * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+ { /* for APB1 @ 32000000Hz */
+ 7, /* -> 125000Hz */
+ 5, /* -> 500000Hz */
+ 4, /* -> 1000000Hz */
+ 2, /* -> 4000000Hz */
+ 1 /* -> 8000000Hz */
+ },
+ { /* for APB2 @ 32000000Hz */
+ 7, /* -> 125000Hz */
+ 5, /* -> 500000Hz */
+ 4, /* -> 1000000Hz */
+ 2, /* -> 4000000Hz */
+ 1 /* -> 8000000Hz */
+ }
+};
+
+static const spi_conf_t spi_config[] = {
+ {
+ .dev = SPI1,
+ .mosi_pin = GPIO_PIN(PORT_A, 7),
+ .miso_pin = GPIO_PIN(PORT_A, 6),
+ .sclk_pin = GPIO_PIN(PORT_A, 5),
+ .cs_pin = GPIO_UNDEF,
+ .af = GPIO_AF0,
+ .rccmask = RCC_APB2ENR_SPI1EN,
+ .apbbus = APB2
+ }
+};
+
+#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+/**
+ * @brief ADC configuration
+ * @{
+ */
+#define ADC_NUMOF (0)
+/** @} */
+
+
+/**
+ * @brief DAC configuration
+ * @{
+ */
+#define DAC_NUMOF (0)
+/** @} */
+
+/**
+ * @name RTC configuration
+ * @{
+ */
+#define RTC_NUMOF (0U)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */