From 1b307b3802c497853e302d7bc427eaacf61cfabd Mon Sep 17 00:00:00 2001
From: Kees Bakker <kees@sodaq.com>
Date: Thu, 11 Aug 2016 21:42:58 +0200
Subject: [PATCH] cpu/sam21_common: eliminate trailing white space in CMSIS
include files
---
.../include/cmsis/samr21/README.md | 8 ++++
.../cmsis/samr21/include/instance/ac.h | 2 +-
.../cmsis/samr21/include/instance/gclk.h | 20 ++++----
.../cmsis/samr21/include/instance/nvmctrl.h | 18 ++++----
.../cmsis/samr21/include/instance/pm.h | 10 ++--
.../cmsis/samr21/include/instance/rfctrl.h | 2 +-
.../cmsis/samr21/include/instance/sbmatrix.h | 2 +-
.../cmsis/samr21/include/instance/sercom0.h | 2 +-
.../cmsis/samr21/include/instance/sercom1.h | 2 +-
.../cmsis/samr21/include/instance/sercom2.h | 2 +-
.../cmsis/samr21/include/instance/sercom3.h | 2 +-
.../cmsis/samr21/include/instance/sercom4.h | 2 +-
.../cmsis/samr21/include/instance/sercom5.h | 2 +-
.../cmsis/samr21/include/instance/sysctrl.h | 46 +++++++++----------
.../cmsis/samr21/include/instance/tc3.h | 2 +-
.../cmsis/samr21/include/instance/tc4.h | 2 +-
.../cmsis/samr21/include/instance/tc5.h | 2 +-
.../cmsis/samr21/include/instance/tcc0.h | 2 +-
.../cmsis/samr21/include/instance/tcc1.h | 2 +-
.../cmsis/samr21/include/instance/tcc2.h | 2 +-
.../include/cmsis/samr21/include/samr21e16a.h | 2 +-
.../include/cmsis/samr21/include/samr21e17a.h | 2 +-
.../include/cmsis/samr21/include/samr21e18a.h | 2 +-
.../include/cmsis/samr21/include/samr21g16a.h | 2 +-
.../include/cmsis/samr21/include/samr21g17a.h | 2 +-
.../include/cmsis/samr21/include/samr21g18a.h | 2 +-
26 files changed, 76 insertions(+), 68 deletions(-)
diff --git a/cpu/sam21_common/include/cmsis/samr21/README.md b/cpu/sam21_common/include/cmsis/samr21/README.md
index 3d961976a8..9c9ff143b8 100644
--- a/cpu/sam21_common/include/cmsis/samr21/README.md
+++ b/cpu/sam21_common/include/cmsis/samr21/README.md
@@ -5,3 +5,11 @@ of samr21 (it was called samd21).
Since then the files has been updated using a distribution from Atmel
Currently we're using sam0/utils/cmsis/samr21 from asf-3.21.0.7z.
+
+## Trailing White Space
+
+Because of the whitespace check (dist/tools/whitespacecheck/check.sh) all
+the trailing white space had to be removed. Please take this into account
+when comparing to the original ASF distribution.
+
+ find include/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/ac.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/ac.h
index 00e9e3536c..5b247e625e 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/ac.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/ac.h
@@ -84,7 +84,7 @@
#define AC_CMP_NUM 2 // Number of comparators
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
-#define AC_NUM_CMP 2
+#define AC_NUM_CMP 2
#define AC_PAIRS 1 // Number of pairs of comparators
#endif /* _SAMR21_AC_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/gclk.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/gclk.h
index ef05884dbb..87fcbbda82 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/gclk.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/gclk.h
@@ -63,20 +63,20 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
-#define GCLK_GENDIV_BITS 16
+#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
#define GCLK_NUM 37 // Number of Generic Clock Users
-#define GCLK_SOURCE_DFLL48M 7
-#define GCLK_SOURCE_FDPLL 8
-#define GCLK_SOURCE_GCLKGEN1 2
-#define GCLK_SOURCE_GCLKIN 1
+#define GCLK_SOURCE_DFLL48M 7
+#define GCLK_SOURCE_FDPLL 8
+#define GCLK_SOURCE_GCLKGEN1 2
+#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
-#define GCLK_SOURCE_OSCULP32K 3
-#define GCLK_SOURCE_OSC8M 6
-#define GCLK_SOURCE_OSC32K 4
-#define GCLK_SOURCE_XOSC 0
-#define GCLK_SOURCE_XOSC32K 5
+#define GCLK_SOURCE_OSCULP32K 3
+#define GCLK_SOURCE_OSC8M 6
+#define GCLK_SOURCE_OSC32K 4
+#define GCLK_SOURCE_XOSC 0
+#define GCLK_SOURCE_XOSC32K 5
#endif /* _SAMR21_GCLK_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/nvmctrl.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/nvmctrl.h
index aac27672a0..df11f3ebf8 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/nvmctrl.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/nvmctrl.h
@@ -77,16 +77,16 @@
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
-#define NVMCTRL_FLASH_SIZE 262144
+#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
-#define NVMCTRL_PAGES 4096
-#define NVMCTRL_PAGE_HW 32
-#define NVMCTRL_PAGE_SIZE 64
-#define NVMCTRL_PAGE_W 16
-#define NVMCTRL_PMSB 3
-#define NVMCTRL_PSZ_BITS 6
-#define NVMCTRL_ROW_PAGES 4
-#define NVMCTRL_ROW_SIZE 256
+#define NVMCTRL_PAGES 4096
+#define NVMCTRL_PAGE_HW 32
+#define NVMCTRL_PAGE_SIZE 64
+#define NVMCTRL_PAGE_W 16
+#define NVMCTRL_PMSB 3
+#define NVMCTRL_PSZ_BITS 6
+#define NVMCTRL_ROW_PAGES 4
+#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/pm.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/pm.h
index 2fa68d927b..2e89325818 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/pm.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/pm.h
@@ -81,10 +81,10 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
-#define PM_CTRL_MCSEL_DFLL48M 3
-#define PM_CTRL_MCSEL_GCLK 0
-#define PM_CTRL_MCSEL_OSC8M 1
-#define PM_CTRL_MCSEL_XOSC 2
-#define PM_PM_CLK_APB_NUM 2
+#define PM_CTRL_MCSEL_DFLL48M 3
+#define PM_CTRL_MCSEL_GCLK 0
+#define PM_CTRL_MCSEL_OSC8M 1
+#define PM_CTRL_MCSEL_XOSC 2
+#define PM_PM_CLK_APB_NUM 2
#endif /* _SAMR21_PM_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/rfctrl.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/rfctrl.h
index 0a61a92e23..434e28e28f 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/rfctrl.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/rfctrl.h
@@ -55,6 +55,6 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RFCTRL peripheral ========== */
-#define RFCTRL_FBUSMSB 5
+#define RFCTRL_FBUSMSB 5
#endif /* _SAMR21_RFCTRL_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sbmatrix.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sbmatrix.h
index 1f9e6ecd00..1bbbca4b4a 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sbmatrix.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sbmatrix.h
@@ -149,7 +149,7 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SBMATRIX peripheral ========== */
-#define SBMATRIX_DEFINED
+#define SBMATRIX_DEFINED
/* ========== Instance parameters for SBMATRIX ========== */
#define SBMATRIX_SLAVE_FLASH 0
#define SBMATRIX_SLAVE_HPB0 1
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom0.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom0.h
index 897db351d7..08bf01d26e 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom0.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom0.h
@@ -141,6 +141,6 @@
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM0_INT_MSB 6
+#define SERCOM0_INT_MSB 6
#endif /* _SAMR21_SERCOM0_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom1.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom1.h
index 726e576d98..00759e2773 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom1.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom1.h
@@ -141,6 +141,6 @@
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM1_INT_MSB 6
+#define SERCOM1_INT_MSB 6
#endif /* _SAMR21_SERCOM1_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom2.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom2.h
index 73d870c172..a258ea12b5 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom2.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom2.h
@@ -141,6 +141,6 @@
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM2_INT_MSB 6
+#define SERCOM2_INT_MSB 6
#endif /* _SAMR21_SERCOM2_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom3.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom3.h
index 22162ed9bd..37a0fd36b6 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom3.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom3.h
@@ -141,6 +141,6 @@
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM3_INT_MSB 6
+#define SERCOM3_INT_MSB 6
#endif /* _SAMR21_SERCOM3_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom4.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom4.h
index cbdb2faa6c..19cfb2ed51 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom4.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom4.h
@@ -141,6 +141,6 @@
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM4_INT_MSB 6
+#define SERCOM4_INT_MSB 6
#endif /* _SAMR21_SERCOM4_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom5.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom5.h
index a26d9ebaeb..ff31909412 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom5.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sercom5.h
@@ -141,6 +141,6 @@
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
-#define SERCOM5_INT_MSB 6
+#define SERCOM5_INT_MSB 6
#endif /* _SAMR21_SERCOM5_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/sysctrl.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/sysctrl.h
index 646fed35d2..20751d0e5d 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/sysctrl.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/sysctrl.h
@@ -93,31 +93,31 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SYSCTRL peripheral ========== */
-#define SYSCTRL_BGAP_CALIB_MSB 11
-#define SYSCTRL_BOD33_CALIB_MSB 5
-#define SYSCTRL_DFLL48M_COARSE_MSB 5
-#define SYSCTRL_DFLL48M_FINE_MSB 9
+#define SYSCTRL_BGAP_CALIB_MSB 11
+#define SYSCTRL_BOD33_CALIB_MSB 5
+#define SYSCTRL_DFLL48M_COARSE_MSB 5
+#define SYSCTRL_DFLL48M_FINE_MSB 9
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
-#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
-#define SYSCTRL_POR33_ENTEST_MSB 1
-#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
-#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
-#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
-#define SYSCTRL_VREF_CONTROL_MSB 48
-#define SYSCTRL_VREF_STATUS_MSB 7
-#define SYSCTRL_VREG_LEVEL_MSB 2
-#define SYSCTRL_BOD12_VERSION 0x111
-#define SYSCTRL_BOD33_VERSION 0x111
-#define SYSCTRL_DFLL48M_VERSION 0x301
-#define SYSCTRL_FDPLL_VERSION 0x111
-#define SYSCTRL_OSCULP32K_VERSION 0x111
-#define SYSCTRL_OSC8M_VERSION 0x120
-#define SYSCTRL_OSC32K_VERSION 0x1101
-#define SYSCTRL_VREF_VERSION 0x200
-#define SYSCTRL_VREG_VERSION 0x201
-#define SYSCTRL_XOSC_VERSION 0x1111
-#define SYSCTRL_XOSC32K_VERSION 0x1111
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
+#define SYSCTRL_POR33_ENTEST_MSB 1
+#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
+#define SYSCTRL_VREF_CONTROL_MSB 48
+#define SYSCTRL_VREF_STATUS_MSB 7
+#define SYSCTRL_VREG_LEVEL_MSB 2
+#define SYSCTRL_BOD12_VERSION 0x111
+#define SYSCTRL_BOD33_VERSION 0x111
+#define SYSCTRL_DFLL48M_VERSION 0x301
+#define SYSCTRL_FDPLL_VERSION 0x111
+#define SYSCTRL_OSCULP32K_VERSION 0x111
+#define SYSCTRL_OSC8M_VERSION 0x120
+#define SYSCTRL_OSC32K_VERSION 0x1101
+#define SYSCTRL_VREF_VERSION 0x200
+#define SYSCTRL_VREG_VERSION 0x201
+#define SYSCTRL_XOSC_VERSION 0x1111
+#define SYSCTRL_XOSC32K_VERSION 0x1111
#endif /* _SAMR21_SYSCTRL_INSTANCE_ */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/tc3.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/tc3.h
index 20b6a6da9d..f5108e0f63 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/tc3.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/tc3.h
@@ -106,7 +106,7 @@
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
#define TC3_GCLK_ID 27 // Index of Generic Clock
-#define TC3_MASTER 0
+#define TC3_MASTER 0
#define TC3_OW_NUM 2 // Number of Output Waveforms
#define TC3_PERIOD_EXT 0 // Period feature implemented
#define TC3_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/tc4.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/tc4.h
index 64466cc06a..3d0e2503c3 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/tc4.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/tc4.h
@@ -106,7 +106,7 @@
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
#define TC4_GCLK_ID 28 // Index of Generic Clock
-#define TC4_MASTER 1
+#define TC4_MASTER 1
#define TC4_OW_NUM 2 // Number of Output Waveforms
#define TC4_PERIOD_EXT 0 // Period feature implemented
#define TC4_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/tc5.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/tc5.h
index b09e078fa1..902687bda6 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/tc5.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/tc5.h
@@ -106,7 +106,7 @@
#define TC5_DMAC_ID_MC_SIZE 2
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
#define TC5_GCLK_ID 28 // Index of Generic Clock
-#define TC5_MASTER 0
+#define TC5_MASTER 0
#define TC5_OW_NUM 2 // Number of Output Waveforms
#define TC5_PERIOD_EXT 0 // Period feature implemented
#define TC5_SHADOW_EXT 0 // Shadow feature implemented
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc0.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc0.h
index d8821574e6..05e0a21cd7 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc0.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc0.h
@@ -127,7 +127,7 @@
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
-#define TCC0_SIZE 24
+#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc1.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc1.h
index 6e9b9527ed..0fe6aa7b99 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc1.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc1.h
@@ -115,7 +115,7 @@
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
-#define TCC1_SIZE 24
+#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc2.h b/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc2.h
index 51f3e699fc..c121cf33dc 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc2.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/instance/tcc2.h
@@ -111,7 +111,7 @@
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
-#define TCC2_SIZE 16
+#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/samr21e16a.h b/cpu/sam21_common/include/cmsis/samr21/include/samr21e16a.h
index e9d86d9805..931bafca9c 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/samr21e16a.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/samr21e16a.h
@@ -229,7 +229,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/samr21e17a.h b/cpu/sam21_common/include/cmsis/samr21/include/samr21e17a.h
index 75abceb2ae..38d7a98c75 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/samr21e17a.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/samr21e17a.h
@@ -229,7 +229,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/samr21e18a.h b/cpu/sam21_common/include/cmsis/samr21/include/samr21e18a.h
index cd8957b975..6bae1e0e0a 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/samr21e18a.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/samr21e18a.h
@@ -229,7 +229,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/samr21g16a.h b/cpu/sam21_common/include/cmsis/samr21/include/samr21g16a.h
index 12a26d2cb7..5a51cc15ab 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/samr21g16a.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/samr21g16a.h
@@ -229,7 +229,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/samr21g17a.h b/cpu/sam21_common/include/cmsis/samr21/include/samr21g17a.h
index bab27fdfe9..1f7ed0341c 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/samr21g17a.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/samr21g17a.h
@@ -229,7 +229,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
diff --git a/cpu/sam21_common/include/cmsis/samr21/include/samr21g18a.h b/cpu/sam21_common/include/cmsis/samr21/include/samr21g18a.h
index 3436f2b452..00ac5f292e 100644
--- a/cpu/sam21_common/include/cmsis/samr21/include/samr21g18a.h
+++ b/cpu/sam21_common/include/cmsis/samr21/include/samr21g18a.h
@@ -229,7 +229,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
-#define LITTLE_ENDIAN 1
+#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
--
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