From 2945532c3bc88fe009eaa8112d04746d05e34c5a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= <joakim.nohlgard@eistec.se>
Date: Fri, 4 Aug 2017 13:49:54 +0200
Subject: [PATCH] k22f: Update to latest vendor headers
---
cpu/k22f/include/vendor/MK22F12810.h | 14918 +++++++----------
cpu/k22f/include/vendor/MK22F25612.h | 16229 +++++++-----------
cpu/k22f/include/vendor/MK22FA12.h | 21947 ++++++++++---------------
3 files changed, 20014 insertions(+), 33080 deletions(-)
diff --git a/cpu/k22f/include/vendor/MK22F12810.h b/cpu/k22f/include/vendor/MK22F12810.h
index 60a54873e9..13159c2a60 100644
--- a/cpu/k22f/include/vendor/MK22F12810.h
+++ b/cpu/k22f/include/vendor/MK22F12810.h
@@ -1,21 +1,25 @@
/*
** ###################################################################
+** Processors: MK22FN128VDC10
+** MK22FN128VLH10
+** MK22FN128VLL10
+** MK22FN128VMP10
+**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
**
** Reference manual: K22P121M100SF9RM, Rev. 1, April 25, 2014
** Version: rev. 1.6, 2015-02-19
-** Build: b150225
+** Build: b170112
**
** Abstract:
** CMSIS Peripheral Access Layer for MK22F12810
**
-** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
+** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
@@ -26,7 +30,7 @@
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
@@ -41,8 +45,8 @@
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
-** http: www.freescale.com
-** mail: support@freescale.com
+** http: www.nxp.com
+** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2013-11-01)
@@ -75,29 +79,14 @@
* CMSIS Peripheral Access Layer for MK22F12810
*/
-
-/* ----------------------------------------------------------------------------
- -- MCU activation
- ---------------------------------------------------------------------------- */
-
-/* Prevention from multiple including the same memory map */
-#if !defined(MK22F12810_H_) /* Check if memory map has not been already included */
-#define MK22F12810_H_
-#define MCU_MK22F12810
-
-/* Check if another memory map has not been also included */
-#if (defined(MCU_ACTIVE))
- #error MK22F12810 memory map: There is already included another memory map. Only one memory map can be included.
-#endif /* (defined(MCU_ACTIVE)) */
-#define MCU_ACTIVE
-
-#include <stdint.h>
+#ifndef _MK22F12810_H_
+#define _MK22F12810_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
+#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0006u
+#define MCU_MEM_MAP_VERSION_MINOR 0x0006U
/**
* @brief Macro to calculate address of an aliased word in the peripheral
@@ -116,8 +105,8 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -126,7 +115,7 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -135,7 +124,7 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
@@ -279,6 +268,108 @@ typedef enum IRQn {
*/ /* end of group Cortex_Core_Configuration */
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
+ kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
+ kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
+ kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
+ kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
+ kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
+ kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
+ kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
+ kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
+ kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
+ kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
+ kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
+ kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
+ kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
+ kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
+ kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
+ kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
+ kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */
+ kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
+ kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1. */
+ kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
+ kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
+ kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
+ kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
+ kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
+ kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
+ kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
+ kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
+ kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
+ kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
+ kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
+ kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
+ kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */
+ kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */
+ kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */
+ kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */
+ kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
+ kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
+ kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
+ kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
+ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
+ kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
+ kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
+ kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
+ kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
+ kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
+ kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
+ kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
+ kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
+ kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
+ kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
+ kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
+ kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
+ kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
+ kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
+ kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
+ kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
+ kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
+ kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
+ kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
+ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -344,51 +435,7 @@ typedef struct {
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type, *ADC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register accessors */
-#define ADC_SC1_REG(base,index) ((base)->SC1[index])
-#define ADC_SC1_COUNT 2
-#define ADC_CFG1_REG(base) ((base)->CFG1)
-#define ADC_CFG2_REG(base) ((base)->CFG2)
-#define ADC_R_REG(base,index) ((base)->R[index])
-#define ADC_R_COUNT 2
-#define ADC_CV1_REG(base) ((base)->CV1)
-#define ADC_CV2_REG(base) ((base)->CV2)
-#define ADC_SC2_REG(base) ((base)->SC2)
-#define ADC_SC3_REG(base) ((base)->SC3)
-#define ADC_OFS_REG(base) ((base)->OFS)
-#define ADC_PG_REG(base) ((base)->PG)
-#define ADC_MG_REG(base) ((base)->MG)
-#define ADC_CLPD_REG(base) ((base)->CLPD)
-#define ADC_CLPS_REG(base) ((base)->CLPS)
-#define ADC_CLP4_REG(base) ((base)->CLP4)
-#define ADC_CLP3_REG(base) ((base)->CLP3)
-#define ADC_CLP2_REG(base) ((base)->CLP2)
-#define ADC_CLP1_REG(base) ((base)->CLP1)
-#define ADC_CLP0_REG(base) ((base)->CLP0)
-#define ADC_CLMD_REG(base) ((base)->CLMD)
-#define ADC_CLMS_REG(base) ((base)->CLMS)
-#define ADC_CLM4_REG(base) ((base)->CLM4)
-#define ADC_CLM3_REG(base) ((base)->CLM3)
-#define ADC_CLM2_REG(base) ((base)->CLM2)
-#define ADC_CLM1_REG(base) ((base)->CLM1)
-#define ADC_CLM0_REG(base) ((base)->CLM0)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
+} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
@@ -399,211 +446,197 @@ typedef struct {
* @{
*/
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH_WIDTH 5
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_DIFF_WIDTH 1
-#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_AIEN_WIDTH 1
-#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-#define ADC_SC1_COCO_WIDTH 1
-#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK_WIDTH 2
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE_WIDTH 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADLSMP_WIDTH 1
-#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV_WIDTH 2
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-#define ADC_CFG1_ADLPC_WIDTH 1
-#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS_WIDTH 2
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADHSC_WIDTH 1
-#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_ADACKEN_WIDTH 1
-#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-#define ADC_CFG2_MUXSEL_WIDTH 1
-#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D_WIDTH 16
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV_WIDTH 16
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV_WIDTH 16
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL_WIDTH 2
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_DMAEN_WIDTH 1
-#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACREN_WIDTH 1
-#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFGT_WIDTH 1
-#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ACFE_WIDTH 1
-#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADTRG_WIDTH 1
-#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-#define ADC_SC2_ADACT_WIDTH 1
-#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS_WIDTH 2
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_AVGE_WIDTH 1
-#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_ADCO_WIDTH 1
-#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CALF_WIDTH 1
-#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-#define ADC_SC3_CAL_WIDTH 1
-#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS_WIDTH 16
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG_WIDTH 16
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG_WIDTH 16
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD_WIDTH 6
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS_WIDTH 6
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4_WIDTH 10
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3_WIDTH 9
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2_WIDTH 8
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1_WIDTH 7
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0_WIDTH 6
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD_WIDTH 6
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS_WIDTH 6
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4_WIDTH 10
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3_WIDTH 9
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2_WIDTH 8
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1_WIDTH 7
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0_WIDTH 6
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK (0x1FU)
+#define ADC_SC1_ADCH_SHIFT (0U)
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK (0x20U)
+#define ADC_SC1_DIFF_SHIFT (5U)
+#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK (0x40U)
+#define ADC_SC1_AIEN_SHIFT (6U)
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK (0x80U)
+#define ADC_SC1_COCO_SHIFT (7U)
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT (0U)
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK (0xCU)
+#define ADC_CFG1_MODE_SHIFT (2U)
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT (4U)
+#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK (0x60U)
+#define ADC_CFG1_ADIV_SHIFT (5U)
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT (7U)
+#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT (0U)
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT (2U)
+#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT (3U)
+#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT (4U)
+#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK (0xFFFFU)
+#define ADC_R_D_SHIFT (0U)
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK (0xFFFFU)
+#define ADC_CV1_CV_SHIFT (0U)
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK (0xFFFFU)
+#define ADC_CV2_CV_SHIFT (0U)
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK (0x3U)
+#define ADC_SC2_REFSEL_SHIFT (0U)
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK (0x4U)
+#define ADC_SC2_DMAEN_SHIFT (2U)
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK (0x8U)
+#define ADC_SC2_ACREN_SHIFT (3U)
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK (0x10U)
+#define ADC_SC2_ACFGT_SHIFT (4U)
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK (0x20U)
+#define ADC_SC2_ACFE_SHIFT (5U)
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK (0x40U)
+#define ADC_SC2_ADTRG_SHIFT (6U)
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK (0x80U)
+#define ADC_SC2_ADACT_SHIFT (7U)
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK (0x3U)
+#define ADC_SC3_AVGS_SHIFT (0U)
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK (0x4U)
+#define ADC_SC3_AVGE_SHIFT (2U)
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK (0x8U)
+#define ADC_SC3_ADCO_SHIFT (3U)
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK (0x40U)
+#define ADC_SC3_CALF_SHIFT (6U)
+#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK (0x80U)
+#define ADC_SC3_CAL_SHIFT (7U)
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK (0xFFFFU)
+#define ADC_PG_PG_SHIFT (0U)
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK (0xFFFFU)
+#define ADC_MG_MG_SHIFT (0U)
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT (0U)
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT (0U)
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT (0U)
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT (0U)
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT (0U)
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT (0U)
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT (0U)
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT (0U)
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT (0U)
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT (0U)
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT (0U)
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT (0U)
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT (0U)
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT (0U)
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
/*!
* @}
@@ -615,12 +648,10 @@ typedef struct {
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
-#define ADC0_BASE_PTR (ADC0)
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x40027000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
-#define ADC1_BASE_PTR (ADC1)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
/** Array initializer of ADC peripheral base pointers */
@@ -628,85 +659,6 @@ typedef struct {
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register instance definitions */
-/* ADC0 */
-#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
-#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
-#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
-#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
-#define ADC0_RA ADC_R_REG(ADC0,0)
-#define ADC0_RB ADC_R_REG(ADC0,1)
-#define ADC0_CV1 ADC_CV1_REG(ADC0)
-#define ADC0_CV2 ADC_CV2_REG(ADC0)
-#define ADC0_SC2 ADC_SC2_REG(ADC0)
-#define ADC0_SC3 ADC_SC3_REG(ADC0)
-#define ADC0_OFS ADC_OFS_REG(ADC0)
-#define ADC0_PG ADC_PG_REG(ADC0)
-#define ADC0_MG ADC_MG_REG(ADC0)
-#define ADC0_CLPD ADC_CLPD_REG(ADC0)
-#define ADC0_CLPS ADC_CLPS_REG(ADC0)
-#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
-#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
-#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
-#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
-#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
-#define ADC0_CLMD ADC_CLMD_REG(ADC0)
-#define ADC0_CLMS ADC_CLMS_REG(ADC0)
-#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
-#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
-#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
-#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
-#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
-/* ADC1 */
-#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
-#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
-#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
-#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
-#define ADC1_RA ADC_R_REG(ADC1,0)
-#define ADC1_RB ADC_R_REG(ADC1,1)
-#define ADC1_CV1 ADC_CV1_REG(ADC1)
-#define ADC1_CV2 ADC_CV2_REG(ADC1)
-#define ADC1_SC2 ADC_SC2_REG(ADC1)
-#define ADC1_SC3 ADC_SC3_REG(ADC1)
-#define ADC1_OFS ADC_OFS_REG(ADC1)
-#define ADC1_PG ADC_PG_REG(ADC1)
-#define ADC1_MG ADC_MG_REG(ADC1)
-#define ADC1_CLPD ADC_CLPD_REG(ADC1)
-#define ADC1_CLPS ADC_CLPS_REG(ADC1)
-#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
-#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
-#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
-#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
-#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
-#define ADC1_CLMD ADC_CLMD_REG(ADC1)
-#define ADC1_CLMS ADC_CLMS_REG(ADC1)
-#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
-#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
-#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
-#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
-#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
-
-/* ADC - Register array accessors */
-#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
-#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
-#define ADC0_R(index) ADC_R_REG(ADC0,index)
-#define ADC1_R(index) ADC_R_REG(ADC1,index)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
@@ -729,30 +681,7 @@ typedef struct {
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type, *CMP_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register accessors */
-#define CMP_CR0_REG(base) ((base)->CR0)
-#define CMP_CR1_REG(base) ((base)->CR1)
-#define CMP_FPR_REG(base) ((base)->FPR)
-#define CMP_SCR_REG(base) ((base)->SCR)
-#define CMP_DACCR_REG(base) ((base)->DACCR)
-#define CMP_MUXCR_REG(base) ((base)->MUXCR)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
+} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
@@ -763,100 +692,84 @@ typedef struct {
* @{
*/
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR_WIDTH 2
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT_WIDTH 3
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_EN_WIDTH 1
-#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_OPE_WIDTH 1
-#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_COS_WIDTH 1
-#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_INV_WIDTH 1
-#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_PMODE_WIDTH 1
-#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
-#define CMP_CR1_TRIGM_MASK 0x20u
-#define CMP_CR1_TRIGM_SHIFT 5
-#define CMP_CR1_TRIGM_WIDTH 1
-#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_TRIGM_SHIFT))&CMP_CR1_TRIGM_MASK)
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_WE_WIDTH 1
-#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-#define CMP_CR1_SE_WIDTH 1
-#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER_WIDTH 8
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_COUT_WIDTH 1
-#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFF_WIDTH 1
-#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_CFR_WIDTH 1
-#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IEF_WIDTH 1
-#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_IER_WIDTH 1
-#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-#define CMP_SCR_DMAEN_WIDTH 1
-#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL_WIDTH 6
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_VRSEL_WIDTH 1
-#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-#define CMP_DACCR_DACEN_WIDTH 1
-#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL_WIDTH 3
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL_WIDTH 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK (0x20U)
+#define CMP_CR1_TRIGM_SHIFT (5U)
+#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+
/*!
* @}
@@ -868,12 +781,10 @@ typedef struct {
#define CMP0_BASE (0x40073000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
-#define CMP0_BASE_PTR (CMP0)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x40073008u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
-#define CMP1_BASE_PTR (CMP1)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
/** Array initializer of CMP peripheral base pointers */
@@ -881,37 +792,6 @@ typedef struct {
/** Interrupt vectors for the CMP peripheral type */
#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register instance definitions */
-/* CMP0 */
-#define CMP0_CR0 CMP_CR0_REG(CMP0)
-#define CMP0_CR1 CMP_CR1_REG(CMP0)
-#define CMP0_FPR CMP_FPR_REG(CMP0)
-#define CMP0_SCR CMP_SCR_REG(CMP0)
-#define CMP0_DACCR CMP_DACCR_REG(CMP0)
-#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
-/* CMP1 */
-#define CMP1_CR0 CMP_CR0_REG(CMP1)
-#define CMP1_CR1 CMP_CR1_REG(CMP1)
-#define CMP1_FPR CMP_FPR_REG(CMP1)
-#define CMP1_SCR CMP_SCR_REG(CMP1)
-#define CMP1_DACCR CMP_DACCR_REG(CMP1)
-#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
@@ -961,40 +841,7 @@ typedef struct {
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
-} CRC_Type, *CRC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register accessors */
-#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
-#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
-#define CRC_DATA_REG(base) ((base)->DATA)
-#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
-#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
-#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
-#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
-#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
-#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
-#define CRC_GPOLY_REG(base) ((base)->GPOLY)
-#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
-#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
-#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
-#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
-#define CRC_CTRL_REG(base) ((base)->CTRL)
-#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
+} CRC_Type;
/* ----------------------------------------------------------------------------
-- CRC Register Masks
@@ -1005,134 +852,122 @@ typedef struct {
* @{
*/
-/* DATAL Bit Fields */
-#define CRC_DATAL_DATAL_MASK 0xFFFFu
-#define CRC_DATAL_DATAL_SHIFT 0
-#define CRC_DATAL_DATAL_WIDTH 16
-#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
-/* DATAH Bit Fields */
-#define CRC_DATAH_DATAH_MASK 0xFFFFu
-#define CRC_DATAH_DATAH_SHIFT 0
-#define CRC_DATAH_DATAH_WIDTH 16
-#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
-/* DATA Bit Fields */
-#define CRC_DATA_LL_MASK 0xFFu
-#define CRC_DATA_LL_SHIFT 0
-#define CRC_DATA_LL_WIDTH 8
-#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
-#define CRC_DATA_LU_MASK 0xFF00u
-#define CRC_DATA_LU_SHIFT 8
-#define CRC_DATA_LU_WIDTH 8
-#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
-#define CRC_DATA_HL_MASK 0xFF0000u
-#define CRC_DATA_HL_SHIFT 16
-#define CRC_DATA_HL_WIDTH 8
-#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
-#define CRC_DATA_HU_MASK 0xFF000000u
-#define CRC_DATA_HU_SHIFT 24
-#define CRC_DATA_HU_WIDTH 8
-#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
-/* DATALL Bit Fields */
-#define CRC_DATALL_DATALL_MASK 0xFFu
-#define CRC_DATALL_DATALL_SHIFT 0
-#define CRC_DATALL_DATALL_WIDTH 8
-#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
-/* DATALU Bit Fields */
-#define CRC_DATALU_DATALU_MASK 0xFFu
-#define CRC_DATALU_DATALU_SHIFT 0
-#define CRC_DATALU_DATALU_WIDTH 8
-#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
-/* DATAHL Bit Fields */
-#define CRC_DATAHL_DATAHL_MASK 0xFFu
-#define CRC_DATAHL_DATAHL_SHIFT 0
-#define CRC_DATAHL_DATAHL_WIDTH 8
-#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
-/* DATAHU Bit Fields */
-#define CRC_DATAHU_DATAHU_MASK 0xFFu
-#define CRC_DATAHU_DATAHU_SHIFT 0
-#define CRC_DATAHU_DATAHU_WIDTH 8
-#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT 0
-#define CRC_GPOLYL_GPOLYL_WIDTH 16
-#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT 0
-#define CRC_GPOLYH_GPOLYH_WIDTH 16
-#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK 0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT 0
-#define CRC_GPOLY_LOW_WIDTH 16
-#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT 16
-#define CRC_GPOLY_HIGH_WIDTH 16
-#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
-#define CRC_GPOLYLL_GPOLYLL_WIDTH 8
-#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
-#define CRC_GPOLYLU_GPOLYLU_WIDTH 8
-#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
-#define CRC_GPOLYHL_GPOLYHL_WIDTH 8
-#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
-#define CRC_GPOLYHU_GPOLYHU_WIDTH 8
-#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK 0x1000000u
-#define CRC_CTRL_TCRC_SHIFT 24
-#define CRC_CTRL_TCRC_WIDTH 1
-#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
-#define CRC_CTRL_WAS_MASK 0x2000000u
-#define CRC_CTRL_WAS_SHIFT 25
-#define CRC_CTRL_WAS_WIDTH 1
-#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
-#define CRC_CTRL_FXOR_MASK 0x4000000u
-#define CRC_CTRL_FXOR_SHIFT 26
-#define CRC_CTRL_FXOR_WIDTH 1
-#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
-#define CRC_CTRL_TOTR_MASK 0x30000000u
-#define CRC_CTRL_TOTR_SHIFT 28
-#define CRC_CTRL_TOTR_WIDTH 2
-#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK 0xC0000000u
-#define CRC_CTRL_TOT_SHIFT 30
-#define CRC_CTRL_TOT_WIDTH 2
-#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK 0x1u
-#define CRC_CTRLHU_TCRC_SHIFT 0
-#define CRC_CTRLHU_TCRC_WIDTH 1
-#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
-#define CRC_CTRLHU_WAS_MASK 0x2u
-#define CRC_CTRLHU_WAS_SHIFT 1
-#define CRC_CTRLHU_WAS_WIDTH 1
-#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
-#define CRC_CTRLHU_FXOR_MASK 0x4u
-#define CRC_CTRLHU_FXOR_SHIFT 2
-#define CRC_CTRLHU_FXOR_WIDTH 1
-#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
-#define CRC_CTRLHU_TOTR_MASK 0x30u
-#define CRC_CTRLHU_TOTR_SHIFT 4
-#define CRC_CTRLHU_TOTR_WIDTH 2
-#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK 0xC0u
-#define CRC_CTRLHU_TOT_SHIFT 6
-#define CRC_CTRLHU_TOT_WIDTH 2
-#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+/*! @name DATAL - CRC_DATAL register. */
+#define CRC_DATAL_DATAL_MASK (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT (0U)
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+
+/*! @name DATAH - CRC_DATAH register. */
+#define CRC_DATAH_DATAH_MASK (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT (0U)
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+
+/*! @name DATA - CRC Data register */
+#define CRC_DATA_LL_MASK (0xFFU)
+#define CRC_DATA_LL_SHIFT (0U)
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK (0xFF00U)
+#define CRC_DATA_LU_SHIFT (8U)
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK (0xFF0000U)
+#define CRC_DATA_HL_SHIFT (16U)
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK (0xFF000000U)
+#define CRC_DATA_HU_SHIFT (24U)
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+
+/*! @name DATALL - CRC_DATALL register. */
+#define CRC_DATALL_DATALL_MASK (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT (0U)
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+
+/*! @name DATALU - CRC_DATALU register. */
+#define CRC_DATALU_DATALU_MASK (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT (0U)
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+
+/*! @name DATAHL - CRC_DATAHL register. */
+#define CRC_DATAHL_DATAHL_MASK (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT (0U)
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+
+/*! @name DATAHU - CRC_DATAHU register. */
+#define CRC_DATAHU_DATAHU_MASK (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT (0U)
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial register */
+#define CRC_GPOLY_LOW_MASK (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT (0U)
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT (16U)
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control register */
+#define CRC_CTRL_TCRC_MASK (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT (24U)
+#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT (25U)
+#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT (26U)
+#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT (28U)
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT (30U)
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC_MASK (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT (0U)
+#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT (1U)
+#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT (2U)
+#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT (4U)
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT (6U)
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
/*!
* @}
@@ -1144,46 +979,11 @@ typedef struct {
#define CRC_BASE (0x40032000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
-#define CRC_BASE_PTR (CRC0)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS { CRC_BASE }
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS { CRC0 }
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register instance definitions */
-/* CRC */
-#define CRC_DATA CRC_DATA_REG(CRC0)
-#define CRC_DATAL CRC_DATAL_REG(CRC0)
-#define CRC_DATALL CRC_DATALL_REG(CRC0)
-#define CRC_DATALU CRC_DATALU_REG(CRC0)
-#define CRC_DATAH CRC_DATAH_REG(CRC0)
-#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
-#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
-#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
-#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
-#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
-#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
-#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
-#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
-#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
-#define CRC_CTRL CRC_CTRL_REG(CRC0)
-#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
@@ -1208,32 +1008,7 @@ typedef struct {
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type, *DAC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register accessors */
-#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
-#define DAC_DATL_COUNT 16
-#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
-#define DAC_DATH_COUNT 16
-#define DAC_SR_REG(base) ((base)->SR)
-#define DAC_C0_REG(base) ((base)->C0)
-#define DAC_C1_REG(base) ((base)->C1)
-#define DAC_C2_REG(base) ((base)->C2)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
+} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
@@ -1244,88 +1019,81 @@ typedef struct {
* @{
*/
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0_WIDTH 8
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1_WIDTH 4
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPBF_WIDTH 1
-#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-#define DAC_SR_DACBFRPTF_WIDTH 1
-#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
-#define DAC_SR_DACBFWMF_MASK 0x4u
-#define DAC_SR_DACBFWMF_SHIFT 2
-#define DAC_SR_DACBFWMF_WIDTH 1
-#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBBIEN_WIDTH 1
-#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_DACBTIEN_WIDTH 1
-#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
-#define DAC_C0_DACBWIEN_MASK 0x4u
-#define DAC_C0_DACBWIEN_SHIFT 2
-#define DAC_C0_DACBWIEN_WIDTH 1
-#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_LPEN_WIDTH 1
-#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACSWTRG_WIDTH 1
-#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACTRGSEL_WIDTH 1
-#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACRFS_WIDTH 1
-#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-#define DAC_C0_DACEN_WIDTH 1
-#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFEN_WIDTH 1
-#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
-#define DAC_C1_DACBFMD_MASK 0x6u
-#define DAC_C1_DACBFMD_SHIFT 1
-#define DAC_C1_DACBFMD_WIDTH 2
-#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
-#define DAC_C1_DACBFWM_MASK 0x18u
-#define DAC_C1_DACBFWM_SHIFT 3
-#define DAC_C1_DACBFWM_WIDTH 2
-#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-#define DAC_C1_DMAEN_WIDTH 1
-#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0xFu
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFUP_WIDTH 4
-#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
-#define DAC_C2_DACBFRP_MASK 0xF0u
-#define DAC_C2_DACBFRP_SHIFT 4
-#define DAC_C2_DACBFRP_WIDTH 4
-#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK (0xFFU)
+#define DAC_DATL_DATA0_SHIFT (0U)
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT (16U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK (0xFU)
+#define DAC_DATH_DATA1_SHIFT (0U)
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT (16U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT (0U)
+#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT (1U)
+#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK (0x4U)
+#define DAC_SR_DACBFWMF_SHIFT (2U)
+#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT (0U)
+#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT (1U)
+#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK (0x4U)
+#define DAC_C0_DACBWIEN_SHIFT (2U)
+#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK (0x8U)
+#define DAC_C0_LPEN_SHIFT (3U)
+#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT (4U)
+#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT (5U)
+#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK (0x40U)
+#define DAC_C0_DACRFS_SHIFT (6U)
+#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK (0x80U)
+#define DAC_C0_DACEN_SHIFT (7U)
+#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK (0x1U)
+#define DAC_C1_DACBFEN_SHIFT (0U)
+#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK (0x6U)
+#define DAC_C1_DACBFMD_SHIFT (1U)
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK (0x18U)
+#define DAC_C1_DACBFWM_SHIFT (3U)
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK (0x80U)
+#define DAC_C1_DMAEN_SHIFT (7U)
+#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK (0xFU)
+#define DAC_C2_DACBFUP_SHIFT (0U)
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT (4U)
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
/*!
* @}
@@ -1337,7 +1105,6 @@ typedef struct {
#define DAC0_BASE (0x4003F000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
-#define DAC0_BASE_PTR (DAC0)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS { DAC0_BASE }
/** Array initializer of DAC peripheral base pointers */
@@ -1345,64 +1112,6 @@ typedef struct {
/** Interrupt vectors for the DAC peripheral type */
#define DAC_IRQS { DAC0_IRQn }
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register instance definitions */
-/* DAC0 */
-#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
-#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
-#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
-#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
-#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
-#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
-#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
-#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
-#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
-#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
-#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
-#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
-#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
-#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
-#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
-#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
-#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
-#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
-#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
-#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
-#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
-#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
-#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
-#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
-#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
-#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
-#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
-#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
-#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
-#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
-#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
-#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
-#define DAC0_SR DAC_SR_REG(DAC0)
-#define DAC0_C0 DAC_C0_REG(DAC0)
-#define DAC0_C1 DAC_C1_REG(DAC0)
-#define DAC0_C2 DAC_C2_REG(DAC0)
-
-/* DAC - Register array accessors */
-#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
-#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
@@ -1470,74 +1179,7 @@ typedef struct {
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[4];
-} DMA_Type, *DMA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register accessors */
-#define DMA_CR_REG(base) ((base)->CR)
-#define DMA_ES_REG(base) ((base)->ES)
-#define DMA_ERQ_REG(base) ((base)->ERQ)
-#define DMA_EEI_REG(base) ((base)->EEI)
-#define DMA_CEEI_REG(base) ((base)->CEEI)
-#define DMA_SEEI_REG(base) ((base)->SEEI)
-#define DMA_CERQ_REG(base) ((base)->CERQ)
-#define DMA_SERQ_REG(base) ((base)->SERQ)
-#define DMA_CDNE_REG(base) ((base)->CDNE)
-#define DMA_SSRT_REG(base) ((base)->SSRT)
-#define DMA_CERR_REG(base) ((base)->CERR)
-#define DMA_CINT_REG(base) ((base)->CINT)
-#define DMA_INT_REG(base) ((base)->INT)
-#define DMA_ERR_REG(base) ((base)->ERR)
-#define DMA_HRS_REG(base) ((base)->HRS)
-#define DMA_EARS_REG(base) ((base)->EARS)
-#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
-#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
-#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
-#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
-#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
-#define DMA_SADDR_COUNT 4
-#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
-#define DMA_SOFF_COUNT 4
-#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
-#define DMA_ATTR_COUNT 4
-#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
-#define DMA_NBYTES_MLNO_COUNT 4
-#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
-#define DMA_NBYTES_MLOFFNO_COUNT 4
-#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
-#define DMA_NBYTES_MLOFFYES_COUNT 4
-#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
-#define DMA_SLAST_COUNT 4
-#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
-#define DMA_DADDR_COUNT 4
-#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
-#define DMA_DOFF_COUNT 4
-#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
-#define DMA_CITER_ELINKNO_COUNT 4
-#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
-#define DMA_CITER_ELINKYES_COUNT 4
-#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
-#define DMA_DLAST_SGA_COUNT 4
-#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
-#define DMA_CSR_COUNT 4
-#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
-#define DMA_BITER_ELINKNO_COUNT 4
-#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
-#define DMA_BITER_ELINKYES_COUNT 4
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
+} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
@@ -1548,517 +1190,478 @@ typedef struct {
* @{
*/
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK 0x2u
-#define DMA_CR_EDBG_SHIFT 1
-#define DMA_CR_EDBG_WIDTH 1
-#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
-#define DMA_CR_ERCA_MASK 0x4u
-#define DMA_CR_ERCA_SHIFT 2
-#define DMA_CR_ERCA_WIDTH 1
-#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
-#define DMA_CR_HOE_MASK 0x10u
-#define DMA_CR_HOE_SHIFT 4
-#define DMA_CR_HOE_WIDTH 1
-#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
-#define DMA_CR_HALT_MASK 0x20u
-#define DMA_CR_HALT_SHIFT 5
-#define DMA_CR_HALT_WIDTH 1
-#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
-#define DMA_CR_CLM_MASK 0x40u
-#define DMA_CR_CLM_SHIFT 6
-#define DMA_CR_CLM_WIDTH 1
-#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
-#define DMA_CR_EMLM_MASK 0x80u
-#define DMA_CR_EMLM_SHIFT 7
-#define DMA_CR_EMLM_WIDTH 1
-#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
-#define DMA_CR_ECX_MASK 0x10000u
-#define DMA_CR_ECX_SHIFT 16
-#define DMA_CR_ECX_WIDTH 1
-#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
-#define DMA_CR_CX_MASK 0x20000u
-#define DMA_CR_CX_SHIFT 17
-#define DMA_CR_CX_WIDTH 1
-#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
-#define DMA_CR_ACTIVE_MASK 0x80000000u
-#define DMA_CR_ACTIVE_SHIFT 31
-#define DMA_CR_ACTIVE_WIDTH 1
-#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ACTIVE_SHIFT))&DMA_CR_ACTIVE_MASK)
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK 0x1u
-#define DMA_ES_DBE_SHIFT 0
-#define DMA_ES_DBE_WIDTH 1
-#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
-#define DMA_ES_SBE_MASK 0x2u
-#define DMA_ES_SBE_SHIFT 1
-#define DMA_ES_SBE_WIDTH 1
-#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
-#define DMA_ES_SGE_MASK 0x4u
-#define DMA_ES_SGE_SHIFT 2
-#define DMA_ES_SGE_WIDTH 1
-#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
-#define DMA_ES_NCE_MASK 0x8u
-#define DMA_ES_NCE_SHIFT 3
-#define DMA_ES_NCE_WIDTH 1
-#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
-#define DMA_ES_DOE_MASK 0x10u
-#define DMA_ES_DOE_SHIFT 4
-#define DMA_ES_DOE_WIDTH 1
-#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
-#define DMA_ES_DAE_MASK 0x20u
-#define DMA_ES_DAE_SHIFT 5
-#define DMA_ES_DAE_WIDTH 1
-#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
-#define DMA_ES_SOE_MASK 0x40u
-#define DMA_ES_SOE_SHIFT 6
-#define DMA_ES_SOE_WIDTH 1
-#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
-#define DMA_ES_SAE_MASK 0x80u
-#define DMA_ES_SAE_SHIFT 7
-#define DMA_ES_SAE_WIDTH 1
-#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
-#define DMA_ES_ERRCHN_MASK 0x300u
-#define DMA_ES_ERRCHN_SHIFT 8
-#define DMA_ES_ERRCHN_WIDTH 2
-#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK 0x4000u
-#define DMA_ES_CPE_SHIFT 14
-#define DMA_ES_CPE_WIDTH 1
-#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
-#define DMA_ES_ECX_MASK 0x10000u
-#define DMA_ES_ECX_SHIFT 16
-#define DMA_ES_ECX_WIDTH 1
-#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
-#define DMA_ES_VLD_MASK 0x80000000u
-#define DMA_ES_VLD_SHIFT 31
-#define DMA_ES_VLD_WIDTH 1
-#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK 0x1u
-#define DMA_ERQ_ERQ0_SHIFT 0
-#define DMA_ERQ_ERQ0_WIDTH 1
-#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
-#define DMA_ERQ_ERQ1_MASK 0x2u
-#define DMA_ERQ_ERQ1_SHIFT 1
-#define DMA_ERQ_ERQ1_WIDTH 1
-#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
-#define DMA_ERQ_ERQ2_MASK 0x4u
-#define DMA_ERQ_ERQ2_SHIFT 2
-#define DMA_ERQ_ERQ2_WIDTH 1
-#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
-#define DMA_ERQ_ERQ3_MASK 0x8u
-#define DMA_ERQ_ERQ3_SHIFT 3
-#define DMA_ERQ_ERQ3_WIDTH 1
-#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK 0x1u
-#define DMA_EEI_EEI0_SHIFT 0
-#define DMA_EEI_EEI0_WIDTH 1
-#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
-#define DMA_EEI_EEI1_MASK 0x2u
-#define DMA_EEI_EEI1_SHIFT 1
-#define DMA_EEI_EEI1_WIDTH 1
-#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
-#define DMA_EEI_EEI2_MASK 0x4u
-#define DMA_EEI_EEI2_SHIFT 2
-#define DMA_EEI_EEI2_WIDTH 1
-#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
-#define DMA_EEI_EEI3_MASK 0x8u
-#define DMA_EEI_EEI3_SHIFT 3
-#define DMA_EEI_EEI3_WIDTH 1
-#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK 0x3u
-#define DMA_CEEI_CEEI_SHIFT 0
-#define DMA_CEEI_CEEI_WIDTH 2
-#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK 0x40u
-#define DMA_CEEI_CAEE_SHIFT 6
-#define DMA_CEEI_CAEE_WIDTH 1
-#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
-#define DMA_CEEI_NOP_MASK 0x80u
-#define DMA_CEEI_NOP_SHIFT 7
-#define DMA_CEEI_NOP_WIDTH 1
-#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK 0x3u
-#define DMA_SEEI_SEEI_SHIFT 0
-#define DMA_SEEI_SEEI_WIDTH 2
-#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK 0x40u
-#define DMA_SEEI_SAEE_SHIFT 6
-#define DMA_SEEI_SAEE_WIDTH 1
-#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
-#define DMA_SEEI_NOP_MASK 0x80u
-#define DMA_SEEI_NOP_SHIFT 7
-#define DMA_SEEI_NOP_WIDTH 1
-#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK 0x3u
-#define DMA_CERQ_CERQ_SHIFT 0
-#define DMA_CERQ_CERQ_WIDTH 2
-#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK 0x40u
-#define DMA_CERQ_CAER_SHIFT 6
-#define DMA_CERQ_CAER_WIDTH 1
-#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
-#define DMA_CERQ_NOP_MASK 0x80u
-#define DMA_CERQ_NOP_SHIFT 7
-#define DMA_CERQ_NOP_WIDTH 1
-#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK 0x3u
-#define DMA_SERQ_SERQ_SHIFT 0
-#define DMA_SERQ_SERQ_WIDTH 2
-#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK 0x40u
-#define DMA_SERQ_SAER_SHIFT 6
-#define DMA_SERQ_SAER_WIDTH 1
-#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
-#define DMA_SERQ_NOP_MASK 0x80u
-#define DMA_SERQ_NOP_SHIFT 7
-#define DMA_SERQ_NOP_WIDTH 1
-#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK 0x3u
-#define DMA_CDNE_CDNE_SHIFT 0
-#define DMA_CDNE_CDNE_WIDTH 2
-#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK 0x40u
-#define DMA_CDNE_CADN_SHIFT 6
-#define DMA_CDNE_CADN_WIDTH 1
-#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
-#define DMA_CDNE_NOP_MASK 0x80u
-#define DMA_CDNE_NOP_SHIFT 7
-#define DMA_CDNE_NOP_WIDTH 1
-#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK 0x3u
-#define DMA_SSRT_SSRT_SHIFT 0
-#define DMA_SSRT_SSRT_WIDTH 2
-#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK 0x40u
-#define DMA_SSRT_SAST_SHIFT 6
-#define DMA_SSRT_SAST_WIDTH 1
-#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
-#define DMA_SSRT_NOP_MASK 0x80u
-#define DMA_SSRT_NOP_SHIFT 7
-#define DMA_SSRT_NOP_WIDTH 1
-#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK 0x3u
-#define DMA_CERR_CERR_SHIFT 0
-#define DMA_CERR_CERR_WIDTH 2
-#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK 0x40u
-#define DMA_CERR_CAEI_SHIFT 6
-#define DMA_CERR_CAEI_WIDTH 1
-#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
-#define DMA_CERR_NOP_MASK 0x80u
-#define DMA_CERR_NOP_SHIFT 7
-#define DMA_CERR_NOP_WIDTH 1
-#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK 0x3u
-#define DMA_CINT_CINT_SHIFT 0
-#define DMA_CINT_CINT_WIDTH 2
-#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK 0x40u
-#define DMA_CINT_CAIR_SHIFT 6
-#define DMA_CINT_CAIR_WIDTH 1
-#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
-#define DMA_CINT_NOP_MASK 0x80u
-#define DMA_CINT_NOP_SHIFT 7
-#define DMA_CINT_NOP_WIDTH 1
-#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK 0x1u
-#define DMA_INT_INT0_SHIFT 0
-#define DMA_INT_INT0_WIDTH 1
-#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
-#define DMA_INT_INT1_MASK 0x2u
-#define DMA_INT_INT1_SHIFT 1
-#define DMA_INT_INT1_WIDTH 1
-#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
-#define DMA_INT_INT2_MASK 0x4u
-#define DMA_INT_INT2_SHIFT 2
-#define DMA_INT_INT2_WIDTH 1
-#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
-#define DMA_INT_INT3_MASK 0x8u
-#define DMA_INT_INT3_SHIFT 3
-#define DMA_INT_INT3_WIDTH 1
-#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK 0x1u
-#define DMA_ERR_ERR0_SHIFT 0
-#define DMA_ERR_ERR0_WIDTH 1
-#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
-#define DMA_ERR_ERR1_MASK 0x2u
-#define DMA_ERR_ERR1_SHIFT 1
-#define DMA_ERR_ERR1_WIDTH 1
-#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
-#define DMA_ERR_ERR2_MASK 0x4u
-#define DMA_ERR_ERR2_SHIFT 2
-#define DMA_ERR_ERR2_WIDTH 1
-#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
-#define DMA_ERR_ERR3_MASK 0x8u
-#define DMA_ERR_ERR3_SHIFT 3
-#define DMA_ERR_ERR3_WIDTH 1
-#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK 0x1u
-#define DMA_HRS_HRS0_SHIFT 0
-#define DMA_HRS_HRS0_WIDTH 1
-#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
-#define DMA_HRS_HRS1_MASK 0x2u
-#define DMA_HRS_HRS1_SHIFT 1
-#define DMA_HRS_HRS1_WIDTH 1
-#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
-#define DMA_HRS_HRS2_MASK 0x4u
-#define DMA_HRS_HRS2_SHIFT 2
-#define DMA_HRS_HRS2_WIDTH 1
-#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
-#define DMA_HRS_HRS3_MASK 0x8u
-#define DMA_HRS_HRS3_SHIFT 3
-#define DMA_HRS_HRS3_WIDTH 1
-#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
-/* EARS Bit Fields */
-#define DMA_EARS_EDREQ_0_MASK 0x1u
-#define DMA_EARS_EDREQ_0_SHIFT 0
-#define DMA_EARS_EDREQ_0_WIDTH 1
-#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
-#define DMA_EARS_EDREQ_1_MASK 0x2u
-#define DMA_EARS_EDREQ_1_SHIFT 1
-#define DMA_EARS_EDREQ_1_WIDTH 1
-#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
-#define DMA_EARS_EDREQ_2_MASK 0x4u
-#define DMA_EARS_EDREQ_2_SHIFT 2
-#define DMA_EARS_EDREQ_2_WIDTH 1
-#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
-#define DMA_EARS_EDREQ_3_MASK 0x8u
-#define DMA_EARS_EDREQ_3_SHIFT 3
-#define DMA_EARS_EDREQ_3_WIDTH 1
-#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK 0x3u
-#define DMA_DCHPRI3_CHPRI_SHIFT 0
-#define DMA_DCHPRI3_CHPRI_WIDTH 2
-#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK 0x40u
-#define DMA_DCHPRI3_DPA_SHIFT 6
-#define DMA_DCHPRI3_DPA_WIDTH 1
-#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
-#define DMA_DCHPRI3_ECP_MASK 0x80u
-#define DMA_DCHPRI3_ECP_SHIFT 7
-#define DMA_DCHPRI3_ECP_WIDTH 1
-#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK 0x3u
-#define DMA_DCHPRI2_CHPRI_SHIFT 0
-#define DMA_DCHPRI2_CHPRI_WIDTH 2
-#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK 0x40u
-#define DMA_DCHPRI2_DPA_SHIFT 6
-#define DMA_DCHPRI2_DPA_WIDTH 1
-#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
-#define DMA_DCHPRI2_ECP_MASK 0x80u
-#define DMA_DCHPRI2_ECP_SHIFT 7
-#define DMA_DCHPRI2_ECP_WIDTH 1
-#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK 0x3u
-#define DMA_DCHPRI1_CHPRI_SHIFT 0
-#define DMA_DCHPRI1_CHPRI_WIDTH 2
-#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK 0x40u
-#define DMA_DCHPRI1_DPA_SHIFT 6
-#define DMA_DCHPRI1_DPA_WIDTH 1
-#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
-#define DMA_DCHPRI1_ECP_MASK 0x80u
-#define DMA_DCHPRI1_ECP_SHIFT 7
-#define DMA_DCHPRI1_ECP_WIDTH 1
-#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK 0x3u
-#define DMA_DCHPRI0_CHPRI_SHIFT 0
-#define DMA_DCHPRI0_CHPRI_WIDTH 2
-#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK 0x40u
-#define DMA_DCHPRI0_DPA_SHIFT 6
-#define DMA_DCHPRI0_DPA_WIDTH 1
-#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
-#define DMA_DCHPRI0_ECP_MASK 0x80u
-#define DMA_DCHPRI0_ECP_SHIFT 7
-#define DMA_DCHPRI0_ECP_WIDTH 1
-#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT 0
-#define DMA_SADDR_SADDR_WIDTH 32
-#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK 0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT 0
-#define DMA_SOFF_SOFF_WIDTH 16
-#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK 0x7u
-#define DMA_ATTR_DSIZE_SHIFT 0
-#define DMA_ATTR_DSIZE_WIDTH 3
-#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK 0xF8u
-#define DMA_ATTR_DMOD_SHIFT 3
-#define DMA_ATTR_DMOD_WIDTH 5
-#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK 0x700u
-#define DMA_ATTR_SSIZE_SHIFT 8
-#define DMA_ATTR_SSIZE_WIDTH 3
-#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK 0xF800u
-#define DMA_ATTR_SMOD_SHIFT 11
-#define DMA_ATTR_SMOD_WIDTH 5
-#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLNO_NBYTES_WIDTH 32
-#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH 30
-#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
-#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH 10
-#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
-#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH 20
-#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
-#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT 0
-#define DMA_SLAST_SLAST_WIDTH 32
-#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT 0
-#define DMA_DADDR_DADDR_WIDTH 32
-#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK 0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT 0
-#define DMA_DOFF_DOFF_WIDTH 16
-#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT 0
-#define DMA_CITER_ELINKNO_CITER_WIDTH 15
-#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
-#define DMA_CITER_ELINKNO_ELINK_WIDTH 1
-#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT 0
-#define DMA_CITER_ELINKYES_CITER_WIDTH 9
-#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK 0x600u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_CITER_ELINKYES_LINKCH_WIDTH 2
-#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
-#define DMA_CITER_ELINKYES_ELINK_WIDTH 1
-#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
-#define DMA_DLAST_SGA_DLASTSGA_WIDTH 32
-#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK 0x1u
-#define DMA_CSR_START_SHIFT 0
-#define DMA_CSR_START_WIDTH 1
-#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
-#define DMA_CSR_INTMAJOR_MASK 0x2u
-#define DMA_CSR_INTMAJOR_SHIFT 1
-#define DMA_CSR_INTMAJOR_WIDTH 1
-#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
-#define DMA_CSR_INTHALF_MASK 0x4u
-#define DMA_CSR_INTHALF_SHIFT 2
-#define DMA_CSR_INTHALF_WIDTH 1
-#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
-#define DMA_CSR_DREQ_MASK 0x8u
-#define DMA_CSR_DREQ_SHIFT 3
-#define DMA_CSR_DREQ_WIDTH 1
-#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
-#define DMA_CSR_ESG_MASK 0x10u
-#define DMA_CSR_ESG_SHIFT 4
-#define DMA_CSR_ESG_WIDTH 1
-#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
-#define DMA_CSR_MAJORELINK_MASK 0x20u
-#define DMA_CSR_MAJORELINK_SHIFT 5
-#define DMA_CSR_MAJORELINK_WIDTH 1
-#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
-#define DMA_CSR_ACTIVE_MASK 0x40u
-#define DMA_CSR_ACTIVE_SHIFT 6
-#define DMA_CSR_ACTIVE_WIDTH 1
-#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
-#define DMA_CSR_DONE_MASK 0x80u
-#define DMA_CSR_DONE_SHIFT 7
-#define DMA_CSR_DONE_WIDTH 1
-#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
-#define DMA_CSR_MAJORLINKCH_MASK 0x300u
-#define DMA_CSR_MAJORLINKCH_SHIFT 8
-#define DMA_CSR_MAJORLINKCH_WIDTH 2
-#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK 0xC000u
-#define DMA_CSR_BWC_SHIFT 14
-#define DMA_CSR_BWC_WIDTH 2
-#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT 0
-#define DMA_BITER_ELINKNO_BITER_WIDTH 15
-#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
-#define DMA_BITER_ELINKNO_ELINK_WIDTH 1
-#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT 0
-#define DMA_BITER_ELINKYES_BITER_WIDTH 9
-#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK 0x600u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_BITER_ELINKYES_LINKCH_WIDTH 2
-#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
-#define DMA_BITER_ELINKYES_ELINK_WIDTH 1
-#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG_MASK (0x2U)
+#define DMA_CR_EDBG_SHIFT (1U)
+#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK (0x4U)
+#define DMA_CR_ERCA_SHIFT (2U)
+#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK (0x10U)
+#define DMA_CR_HOE_SHIFT (4U)
+#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK (0x20U)
+#define DMA_CR_HALT_SHIFT (5U)
+#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK (0x40U)
+#define DMA_CR_CLM_SHIFT (6U)
+#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK (0x80U)
+#define DMA_CR_EMLM_SHIFT (7U)
+#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK (0x10000U)
+#define DMA_CR_ECX_SHIFT (16U)
+#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK (0x20000U)
+#define DMA_CR_CX_SHIFT (17U)
+#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+#define DMA_CR_ACTIVE_MASK (0x80000000U)
+#define DMA_CR_ACTIVE_SHIFT (31U)
+#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE_MASK (0x1U)
+#define DMA_ES_DBE_SHIFT (0U)
+#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK (0x2U)
+#define DMA_ES_SBE_SHIFT (1U)
+#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK (0x4U)
+#define DMA_ES_SGE_SHIFT (2U)
+#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK (0x8U)
+#define DMA_ES_NCE_SHIFT (3U)
+#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK (0x10U)
+#define DMA_ES_DOE_SHIFT (4U)
+#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK (0x20U)
+#define DMA_ES_DAE_SHIFT (5U)
+#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK (0x40U)
+#define DMA_ES_SOE_SHIFT (6U)
+#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK (0x80U)
+#define DMA_ES_SAE_SHIFT (7U)
+#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK (0x300U)
+#define DMA_ES_ERRCHN_SHIFT (8U)
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK (0x4000U)
+#define DMA_ES_CPE_SHIFT (14U)
+#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK (0x10000U)
+#define DMA_ES_ECX_SHIFT (16U)
+#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK (0x80000000U)
+#define DMA_ES_VLD_SHIFT (31U)
+#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+
+/*! @name ERQ - Enable Request Register */
+#define DMA_ERQ_ERQ0_MASK (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT (0U)
+#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT (1U)
+#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT (2U)
+#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT (3U)
+#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+
+/*! @name EEI - Enable Error Interrupt Register */
+#define DMA_EEI_EEI0_MASK (0x1U)
+#define DMA_EEI_EEI0_SHIFT (0U)
+#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK (0x2U)
+#define DMA_EEI_EEI1_SHIFT (1U)
+#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK (0x4U)
+#define DMA_EEI_EEI2_SHIFT (2U)
+#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK (0x8U)
+#define DMA_EEI_EEI3_SHIFT (3U)
+#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK (0x3U)
+#define DMA_CEEI_CEEI_SHIFT (0U)
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK (0x40U)
+#define DMA_CEEI_CAEE_SHIFT (6U)
+#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK (0x80U)
+#define DMA_CEEI_NOP_SHIFT (7U)
+#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK (0x3U)
+#define DMA_SEEI_SEEI_SHIFT (0U)
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK (0x40U)
+#define DMA_SEEI_SAEE_SHIFT (6U)
+#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK (0x80U)
+#define DMA_SEEI_NOP_SHIFT (7U)
+#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK (0x3U)
+#define DMA_CERQ_CERQ_SHIFT (0U)
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK (0x40U)
+#define DMA_CERQ_CAER_SHIFT (6U)
+#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK (0x80U)
+#define DMA_CERQ_NOP_SHIFT (7U)
+#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK (0x3U)
+#define DMA_SERQ_SERQ_SHIFT (0U)
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK (0x40U)
+#define DMA_SERQ_SAER_SHIFT (6U)
+#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK (0x80U)
+#define DMA_SERQ_NOP_SHIFT (7U)
+#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK (0x3U)
+#define DMA_CDNE_CDNE_SHIFT (0U)
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK (0x40U)
+#define DMA_CDNE_CADN_SHIFT (6U)
+#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK (0x80U)
+#define DMA_CDNE_NOP_SHIFT (7U)
+#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK (0x3U)
+#define DMA_SSRT_SSRT_SHIFT (0U)
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK (0x40U)
+#define DMA_SSRT_SAST_SHIFT (6U)
+#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK (0x80U)
+#define DMA_SSRT_NOP_SHIFT (7U)
+#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK (0x3U)
+#define DMA_CERR_CERR_SHIFT (0U)
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK (0x40U)
+#define DMA_CERR_CAEI_SHIFT (6U)
+#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK (0x80U)
+#define DMA_CERR_NOP_SHIFT (7U)
+#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK (0x3U)
+#define DMA_CINT_CINT_SHIFT (0U)
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK (0x40U)
+#define DMA_CINT_CAIR_SHIFT (6U)
+#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK (0x80U)
+#define DMA_CINT_NOP_SHIFT (7U)
+#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+
+/*! @name INT - Interrupt Request Register */
+#define DMA_INT_INT0_MASK (0x1U)
+#define DMA_INT_INT0_SHIFT (0U)
+#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK (0x2U)
+#define DMA_INT_INT1_SHIFT (1U)
+#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK (0x4U)
+#define DMA_INT_INT2_SHIFT (2U)
+#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK (0x8U)
+#define DMA_INT_INT3_SHIFT (3U)
+#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+
+/*! @name ERR - Error Register */
+#define DMA_ERR_ERR0_MASK (0x1U)
+#define DMA_ERR_ERR0_SHIFT (0U)
+#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK (0x2U)
+#define DMA_ERR_ERR1_SHIFT (1U)
+#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK (0x4U)
+#define DMA_ERR_ERR2_SHIFT (2U)
+#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK (0x8U)
+#define DMA_ERR_ERR3_SHIFT (3U)
+#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+
+/*! @name HRS - Hardware Request Status Register */
+#define DMA_HRS_HRS0_MASK (0x1U)
+#define DMA_HRS_HRS0_SHIFT (0U)
+#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK (0x2U)
+#define DMA_HRS_HRS1_SHIFT (1U)
+#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK (0x4U)
+#define DMA_HRS_HRS2_SHIFT (2U)
+#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK (0x8U)
+#define DMA_HRS_HRS3_SHIFT (3U)
+#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+
+/*! @name EARS - Enable Asynchronous Request in Stop Register */
+#define DMA_EARS_EDREQ_0_MASK (0x1U)
+#define DMA_EARS_EDREQ_0_SHIFT (0U)
+#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK (0x2U)
+#define DMA_EARS_EDREQ_1_SHIFT (1U)
+#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK (0x4U)
+#define DMA_EARS_EDREQ_2_SHIFT (2U)
+#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK (0x8U)
+#define DMA_EARS_EDREQ_3_SHIFT (3U)
+#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+#define DMA_DCHPRI3_CHPRI_MASK (0x3U)
+#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT (6U)
+#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT (7U)
+#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+#define DMA_DCHPRI2_CHPRI_MASK (0x3U)
+#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT (6U)
+#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT (7U)
+#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+#define DMA_DCHPRI1_CHPRI_MASK (0x3U)
+#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT (6U)
+#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT (7U)
+#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+#define DMA_DCHPRI0_CHPRI_MASK (0x3U)
+#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT (6U)
+#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT (7U)
+#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+
+/*! @name SADDR - TCD Source Address */
+#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT (0U)
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT (4U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT (0U)
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT (4U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT (0U)
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT (3U)
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT (8U)
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT (11U)
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT (4U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
+#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT (4U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT (4U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT (4U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT (0U)
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT (4U)
+
+/*! @name DADDR - TCD Destination Address */
+#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT (0U)
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT (4U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT (0U)
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT (4U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT (4U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK (0x600U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT (4U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT (4U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START_MASK (0x1U)
+#define DMA_CSR_START_SHIFT (0U)
+#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT (1U)
+#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK (0x4U)
+#define DMA_CSR_INTHALF_SHIFT (2U)
+#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK (0x8U)
+#define DMA_CSR_DREQ_SHIFT (3U)
+#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK (0x10U)
+#define DMA_CSR_ESG_SHIFT (4U)
+#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT (5U)
+#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT (6U)
+#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK (0x80U)
+#define DMA_CSR_DONE_SHIFT (7U)
+#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK (0x300U)
+#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK (0xC000U)
+#define DMA_CSR_BWC_SHIFT (14U)
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT (4U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT (4U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK (0x600U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT (4U)
+
/*!
* @}
@@ -2070,130 +1673,14 @@ typedef struct {
#define DMA_BASE (0x40008000u)
/** Peripheral DMA base pointer */
#define DMA0 ((DMA_Type *)DMA_BASE)
-#define DMA_BASE_PTR (DMA0)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0 }
/** Interrupt vectors for the DMA peripheral type */
-#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
+#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
#define DMA_ERROR_IRQS { DMA_Error_IRQn }
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register instance definitions */
-/* DMA */
-#define DMA_CR DMA_CR_REG(DMA0)
-#define DMA_ES DMA_ES_REG(DMA0)
-#define DMA_ERQ DMA_ERQ_REG(DMA0)
-#define DMA_EEI DMA_EEI_REG(DMA0)
-#define DMA_CEEI DMA_CEEI_REG(DMA0)
-#define DMA_SEEI DMA_SEEI_REG(DMA0)
-#define DMA_CERQ DMA_CERQ_REG(DMA0)
-#define DMA_SERQ DMA_SERQ_REG(DMA0)
-#define DMA_CDNE DMA_CDNE_REG(DMA0)
-#define DMA_SSRT DMA_SSRT_REG(DMA0)
-#define DMA_CERR DMA_CERR_REG(DMA0)
-#define DMA_CINT DMA_CINT_REG(DMA0)
-#define DMA_INT DMA_INT_REG(DMA0)
-#define DMA_ERR DMA_ERR_REG(DMA0)
-#define DMA_HRS DMA_HRS_REG(DMA0)
-#define DMA_EARS DMA_EARS_REG(DMA0)
-#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
-#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
-#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
-#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
-#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
-#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
-#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
-#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
-#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
-#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
-#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
-#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
-#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
-#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
-#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
-#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
-#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
-#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
-#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
-#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
-#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
-#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
-#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
-#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
-#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
-#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
-#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
-#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
-#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
-
-/* DMA - Register array accessors */
-#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
-#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
-#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
-#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
-#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
-#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
-#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
-#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
-#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
-#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
-#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
-#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
-#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
@@ -2211,26 +1698,7 @@ typedef struct {
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type, *DMAMUX_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register accessors */
-#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
-#define DMAMUX_CHCFG_COUNT 4
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
+} DMAMUX_Type;
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
@@ -2241,19 +1709,20 @@ typedef struct {
* @{
*/
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE_WIDTH 6
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_TRIG_WIDTH 1
-#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-#define DMAMUX_CHCFG_ENBL_WIDTH 1
-#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT (4U)
+
/*!
* @}
@@ -2265,37 +1734,11 @@ typedef struct {
#define DMAMUX_BASE (0x40021000u)
/** Peripheral DMAMUX base pointer */
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
-#define DMAMUX_BASE_PTR (DMAMUX)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX }
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register instance definitions */
-/* DMAMUX */
-#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
-#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
-#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
-#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
-
-/* DMAMUX - Register array accessors */
-#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
@@ -2318,76 +1761,51 @@ typedef struct {
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
uint8_t RESERVED_0[1];
__IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
-} EWM_Type, *EWM_MemMapPtr;
+} EWM_Type;
/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
+ -- EWM Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN_MASK (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT (0U)
+#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT (1U)
+#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK (0x4U)
+#define EWM_CTRL_INEN_SHIFT (2U)
+#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK (0x8U)
+#define EWM_CTRL_INTEN_SHIFT (3U)
+#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
-/* EWM - Register accessors */
-#define EWM_CTRL_REG(base) ((base)->CTRL)
-#define EWM_SERV_REG(base) ((base)->SERV)
-#define EWM_CMPL_REG(base) ((base)->CMPL)
-#define EWM_CMPH_REG(base) ((base)->CMPH)
-#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT (0U)
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT (0U)
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
-/* ----------------------------------------------------------------------------
- -- EWM Register Masks
- ---------------------------------------------------------------------------- */
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT (0U)
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
-/*!
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
+/*! @name CLKPRESCALER - Clock Prescaler Register */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
+#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK 0x1u
-#define EWM_CTRL_EWMEN_SHIFT 0
-#define EWM_CTRL_EWMEN_WIDTH 1
-#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
-#define EWM_CTRL_ASSIN_MASK 0x2u
-#define EWM_CTRL_ASSIN_SHIFT 1
-#define EWM_CTRL_ASSIN_WIDTH 1
-#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
-#define EWM_CTRL_INEN_MASK 0x4u
-#define EWM_CTRL_INEN_SHIFT 2
-#define EWM_CTRL_INEN_WIDTH 1
-#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
-#define EWM_CTRL_INTEN_MASK 0x8u
-#define EWM_CTRL_INTEN_SHIFT 3
-#define EWM_CTRL_INTEN_WIDTH 1
-#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK 0xFFu
-#define EWM_SERV_SERVICE_SHIFT 0
-#define EWM_SERV_SERVICE_WIDTH 8
-#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK 0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT 0
-#define EWM_CMPL_COMPAREL_WIDTH 8
-#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK 0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT 0
-#define EWM_CMPH_COMPAREH_WIDTH 8
-#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
-/* CLKPRESCALER Bit Fields */
-#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
-#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
-#define EWM_CLKPRESCALER_CLK_DIV_WIDTH 8
-#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
/*!
* @}
@@ -2399,7 +1817,6 @@ typedef struct {
#define EWM_BASE (0x40061000u)
/** Peripheral EWM base pointer */
#define EWM ((EWM_Type *)EWM_BASE)
-#define EWM_BASE_PTR (EWM)
/** Array initializer of EWM peripheral base addresses */
#define EWM_BASE_ADDRS { EWM_BASE }
/** Array initializer of EWM peripheral base pointers */
@@ -2407,29 +1824,6 @@ typedef struct {
/** Interrupt vectors for the EWM peripheral type */
#define EWM_IRQS { WDOG_EWM_IRQn }
-/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register instance definitions */
-/* EWM */
-#define EWM_CTRL EWM_CTRL_REG(EWM)
-#define EWM_SERV EWM_SERV_REG(EWM)
-#define EWM_CMPL EWM_CMPL_REG(EWM)
-#define EWM_CMPH EWM_CMPH_REG(EWM)
-#define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group EWM_Peripheral_Access_Layer */
@@ -2459,41 +1853,7 @@ typedef struct {
__IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
__IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
} SET[4][8];
-} FMC_Type, *FMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register accessors */
-#define FMC_PFAPR_REG(base) ((base)->PFAPR)
-#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
-#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
-#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
-#define FMC_TAGVDW0S_COUNT 8
-#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
-#define FMC_TAGVDW1S_COUNT 8
-#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
-#define FMC_TAGVDW2S_COUNT 8
-#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
-#define FMC_TAGVDW3S_COUNT 8
-#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
-#define FMC_DATA_U_COUNT 4
-#define FMC_DATA_U_COUNT2 8
-#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
-#define FMC_DATA_L_COUNT 4
-#define FMC_DATA_L_COUNT2 8
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
+} FMC_Type;
/* ----------------------------------------------------------------------------
-- FMC Register Masks
@@ -2504,191 +1864,180 @@ typedef struct {
* @{
*/
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK 0x3u
-#define FMC_PFAPR_M0AP_SHIFT 0
-#define FMC_PFAPR_M0AP_WIDTH 2
-#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK 0xCu
-#define FMC_PFAPR_M1AP_SHIFT 2
-#define FMC_PFAPR_M1AP_WIDTH 2
-#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK 0x30u
-#define FMC_PFAPR_M2AP_SHIFT 4
-#define FMC_PFAPR_M2AP_WIDTH 2
-#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK 0xC0u
-#define FMC_PFAPR_M3AP_SHIFT 6
-#define FMC_PFAPR_M3AP_WIDTH 2
-#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M4AP_MASK 0x300u
-#define FMC_PFAPR_M4AP_SHIFT 8
-#define FMC_PFAPR_M4AP_WIDTH 2
-#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
-#define FMC_PFAPR_M5AP_MASK 0xC00u
-#define FMC_PFAPR_M5AP_SHIFT 10
-#define FMC_PFAPR_M5AP_WIDTH 2
-#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
-#define FMC_PFAPR_M6AP_MASK 0x3000u
-#define FMC_PFAPR_M6AP_SHIFT 12
-#define FMC_PFAPR_M6AP_WIDTH 2
-#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
-#define FMC_PFAPR_M7AP_MASK 0xC000u
-#define FMC_PFAPR_M7AP_SHIFT 14
-#define FMC_PFAPR_M7AP_WIDTH 2
-#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK 0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT 16
-#define FMC_PFAPR_M0PFD_WIDTH 1
-#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
-#define FMC_PFAPR_M1PFD_MASK 0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT 17
-#define FMC_PFAPR_M1PFD_WIDTH 1
-#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
-#define FMC_PFAPR_M2PFD_MASK 0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT 18
-#define FMC_PFAPR_M2PFD_WIDTH 1
-#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
-#define FMC_PFAPR_M3PFD_MASK 0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT 19
-#define FMC_PFAPR_M3PFD_WIDTH 1
-#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
-#define FMC_PFAPR_M4PFD_MASK 0x100000u
-#define FMC_PFAPR_M4PFD_SHIFT 20
-#define FMC_PFAPR_M4PFD_WIDTH 1
-#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
-#define FMC_PFAPR_M5PFD_MASK 0x200000u
-#define FMC_PFAPR_M5PFD_SHIFT 21
-#define FMC_PFAPR_M5PFD_WIDTH 1
-#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
-#define FMC_PFAPR_M6PFD_MASK 0x400000u
-#define FMC_PFAPR_M6PFD_SHIFT 22
-#define FMC_PFAPR_M6PFD_WIDTH 1
-#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
-#define FMC_PFAPR_M7PFD_MASK 0x800000u
-#define FMC_PFAPR_M7PFD_SHIFT 23
-#define FMC_PFAPR_M7PFD_WIDTH 1
-#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK 0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT 0
-#define FMC_PFB0CR_B0SEBE_WIDTH 1
-#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
-#define FMC_PFB0CR_B0IPE_MASK 0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT 1
-#define FMC_PFB0CR_B0IPE_WIDTH 1
-#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
-#define FMC_PFB0CR_B0DPE_MASK 0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT 2
-#define FMC_PFB0CR_B0DPE_WIDTH 1
-#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
-#define FMC_PFB0CR_B0ICE_MASK 0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT 3
-#define FMC_PFB0CR_B0ICE_WIDTH 1
-#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
-#define FMC_PFB0CR_B0DCE_MASK 0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT 4
-#define FMC_PFB0CR_B0DCE_WIDTH 1
-#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
-#define FMC_PFB0CR_CRC_MASK 0xE0u
-#define FMC_PFB0CR_CRC_SHIFT 5
-#define FMC_PFB0CR_CRC_WIDTH 3
-#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK 0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT 17
-#define FMC_PFB0CR_B0MW_WIDTH 2
-#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT 19
-#define FMC_PFB0CR_S_B_INV_WIDTH 1
-#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
-#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT 20
-#define FMC_PFB0CR_CINV_WAY_WIDTH 4
-#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
-#define FMC_PFB0CR_CLCK_WAY_WIDTH 4
-#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT 28
-#define FMC_PFB0CR_B0RWSC_WIDTH 4
-#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* PFB1CR Bit Fields */
-#define FMC_PFB1CR_B1SEBE_MASK 0x1u
-#define FMC_PFB1CR_B1SEBE_SHIFT 0
-#define FMC_PFB1CR_B1SEBE_WIDTH 1
-#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
-#define FMC_PFB1CR_B1IPE_MASK 0x2u
-#define FMC_PFB1CR_B1IPE_SHIFT 1
-#define FMC_PFB1CR_B1IPE_WIDTH 1
-#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
-#define FMC_PFB1CR_B1DPE_MASK 0x4u
-#define FMC_PFB1CR_B1DPE_SHIFT 2
-#define FMC_PFB1CR_B1DPE_WIDTH 1
-#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
-#define FMC_PFB1CR_B1ICE_MASK 0x8u
-#define FMC_PFB1CR_B1ICE_SHIFT 3
-#define FMC_PFB1CR_B1ICE_WIDTH 1
-#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
-#define FMC_PFB1CR_B1DCE_MASK 0x10u
-#define FMC_PFB1CR_B1DCE_SHIFT 4
-#define FMC_PFB1CR_B1DCE_WIDTH 1
-#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
-#define FMC_PFB1CR_B1MW_MASK 0x60000u
-#define FMC_PFB1CR_B1MW_SHIFT 17
-#define FMC_PFB1CR_B1MW_WIDTH 2
-#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
-#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
-#define FMC_PFB1CR_B1RWSC_SHIFT 28
-#define FMC_PFB1CR_B1RWSC_WIDTH 4
-#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
-/* TAGVDW0S Bit Fields */
-#define FMC_TAGVDW0S_valid_MASK 0x1u
-#define FMC_TAGVDW0S_valid_SHIFT 0
-#define FMC_TAGVDW0S_valid_WIDTH 1
-#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
-#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW0S_tag_SHIFT 5
-#define FMC_TAGVDW0S_tag_WIDTH 14
-#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
-/* TAGVDW1S Bit Fields */
-#define FMC_TAGVDW1S_valid_MASK 0x1u
-#define FMC_TAGVDW1S_valid_SHIFT 0
-#define FMC_TAGVDW1S_valid_WIDTH 1
-#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
-#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW1S_tag_SHIFT 5
-#define FMC_TAGVDW1S_tag_WIDTH 14
-#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
-/* TAGVDW2S Bit Fields */
-#define FMC_TAGVDW2S_valid_MASK 0x1u
-#define FMC_TAGVDW2S_valid_SHIFT 0
-#define FMC_TAGVDW2S_valid_WIDTH 1
-#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
-#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW2S_tag_SHIFT 5
-#define FMC_TAGVDW2S_tag_WIDTH 14
-#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
-/* TAGVDW3S Bit Fields */
-#define FMC_TAGVDW3S_valid_MASK 0x1u
-#define FMC_TAGVDW3S_valid_SHIFT 0
-#define FMC_TAGVDW3S_valid_WIDTH 1
-#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
-#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW3S_tag_SHIFT 5
-#define FMC_TAGVDW3S_tag_WIDTH 14
-#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
-/* DATA_U Bit Fields */
-#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_U_data_SHIFT 0
-#define FMC_DATA_U_data_WIDTH 32
-#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
-/* DATA_L Bit Fields */
-#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_L_data_SHIFT 0
-#define FMC_DATA_L_data_WIDTH 32
-#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+/*! @name PFAPR - Flash Access Protection Register */
+#define FMC_PFAPR_M0AP_MASK (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT (0U)
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT (2U)
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT (4U)
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT (6U)
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK (0x300U)
+#define FMC_PFAPR_M4AP_SHIFT (8U)
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK (0xC00U)
+#define FMC_PFAPR_M5AP_SHIFT (10U)
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK (0x3000U)
+#define FMC_PFAPR_M6AP_SHIFT (12U)
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK (0xC000U)
+#define FMC_PFAPR_M7AP_SHIFT (14U)
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK (0x10000U)
+#define FMC_PFAPR_M0PFD_SHIFT (16U)
+#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK (0x20000U)
+#define FMC_PFAPR_M1PFD_SHIFT (17U)
+#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK (0x40000U)
+#define FMC_PFAPR_M2PFD_SHIFT (18U)
+#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK (0x80000U)
+#define FMC_PFAPR_M3PFD_SHIFT (19U)
+#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK (0x100000U)
+#define FMC_PFAPR_M4PFD_SHIFT (20U)
+#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK (0x200000U)
+#define FMC_PFAPR_M5PFD_SHIFT (21U)
+#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK (0x400000U)
+#define FMC_PFAPR_M6PFD_SHIFT (22U)
+#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK (0x800000U)
+#define FMC_PFAPR_M7PFD_SHIFT (23U)
+#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+
+/*! @name PFB0CR - Flash Bank 0 Control Register */
+#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
+#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
+#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK (0x2U)
+#define FMC_PFB0CR_B0IPE_SHIFT (1U)
+#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK (0x4U)
+#define FMC_PFB0CR_B0DPE_SHIFT (2U)
+#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK (0x8U)
+#define FMC_PFB0CR_B0ICE_SHIFT (3U)
+#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK (0x10U)
+#define FMC_PFB0CR_B0DCE_SHIFT (4U)
+#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK (0xE0U)
+#define FMC_PFB0CR_CRC_SHIFT (5U)
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK (0x60000U)
+#define FMC_PFB0CR_B0MW_SHIFT (17U)
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
+#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
+#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
+#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
+#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
+#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
+
+/*! @name PFB1CR - Flash Bank 1 Control Register */
+#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
+#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
+#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK (0x2U)
+#define FMC_PFB1CR_B1IPE_SHIFT (1U)
+#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK (0x4U)
+#define FMC_PFB1CR_B1DPE_SHIFT (2U)
+#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK (0x8U)
+#define FMC_PFB1CR_B1ICE_SHIFT (3U)
+#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK (0x10U)
+#define FMC_PFB1CR_B1DCE_SHIFT (4U)
+#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK (0x60000U)
+#define FMC_PFB1CR_B1MW_SHIFT (17U)
+#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
+#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
+#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
+
+/*! @name TAGVDW0S - Cache Tag Storage */
+#define FMC_TAGVDW0S_valid_MASK (0x1U)
+#define FMC_TAGVDW0S_valid_SHIFT (0U)
+#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW0S_tag_SHIFT (5U)
+#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
+
+/* The count of FMC_TAGVDW0S */
+#define FMC_TAGVDW0S_COUNT (8U)
+
+/*! @name TAGVDW1S - Cache Tag Storage */
+#define FMC_TAGVDW1S_valid_MASK (0x1U)
+#define FMC_TAGVDW1S_valid_SHIFT (0U)
+#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW1S_tag_SHIFT (5U)
+#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
+
+/* The count of FMC_TAGVDW1S */
+#define FMC_TAGVDW1S_COUNT (8U)
+
+/*! @name TAGVDW2S - Cache Tag Storage */
+#define FMC_TAGVDW2S_valid_MASK (0x1U)
+#define FMC_TAGVDW2S_valid_SHIFT (0U)
+#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW2S_tag_SHIFT (5U)
+#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
+
+/* The count of FMC_TAGVDW2S */
+#define FMC_TAGVDW2S_COUNT (8U)
+
+/*! @name TAGVDW3S - Cache Tag Storage */
+#define FMC_TAGVDW3S_valid_MASK (0x1U)
+#define FMC_TAGVDW3S_valid_SHIFT (0U)
+#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW3S_tag_SHIFT (5U)
+#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
+
+/* The count of FMC_TAGVDW3S */
+#define FMC_TAGVDW3S_COUNT (8U)
+
+/*! @name DATA_U - Cache Data Storage (upper word) */
+#define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_U_data_SHIFT (0U)
+#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT (4U)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT2 (8U)
+
+/*! @name DATA_L - Cache Data Storage (lower word) */
+#define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_L_data_SHIFT (0U)
+#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT (4U)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT2 (8U)
+
/*!
* @}
@@ -2700,137 +2049,11 @@ typedef struct {
#define FMC_BASE (0x4001F000u)
/** Peripheral FMC base pointer */
#define FMC ((FMC_Type *)FMC_BASE)
-#define FMC_BASE_PTR (FMC)
/** Array initializer of FMC peripheral base addresses */
#define FMC_BASE_ADDRS { FMC_BASE }
/** Array initializer of FMC peripheral base pointers */
#define FMC_BASE_PTRS { FMC }
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register instance definitions */
-/* FMC */
-#define FMC_PFAPR FMC_PFAPR_REG(FMC)
-#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
-#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
-#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
-#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
-#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
-#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
-#define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
-#define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
-#define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
-#define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
-#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
-#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
-#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
-#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
-#define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
-#define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
-#define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
-#define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
-#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
-#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
-#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
-#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
-#define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
-#define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
-#define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
-#define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
-#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
-#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
-#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
-#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
-#define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
-#define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
-#define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
-#define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
-#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
-#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
-#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
-#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
-#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
-#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
-#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
-#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
-#define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
-#define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
-#define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
-#define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
-#define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
-#define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
-#define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
-#define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
-#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
-#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
-#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
-#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
-#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
-#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
-#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
-#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
-#define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
-#define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
-#define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
-#define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
-#define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
-#define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
-#define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
-#define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
-#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
-#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
-#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
-#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
-#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
-#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
-#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
-#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
-#define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
-#define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
-#define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
-#define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
-#define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
-#define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
-#define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
-#define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
-#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
-#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
-#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
-#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
-#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
-#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
-#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
-#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
-#define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
-#define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
-#define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
-#define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
-#define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
-#define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
-#define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
-#define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
-
-/* FMC - Register array accessors */
-#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
-#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
-#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
-#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
-#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
-#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FMC_Peripheral_Access_Layer */
@@ -2887,62 +2110,7 @@ typedef struct {
__I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
uint8_t RESERVED_1[2];
__I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
-} FTFA_Type, *FTFA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTFA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
- * @{
- */
-
-
-/* FTFA - Register accessors */
-#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
-#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
-#define FTFA_FSEC_REG(base) ((base)->FSEC)
-#define FTFA_FOPT_REG(base) ((base)->FOPT)
-#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
-#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
-#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
-#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
-#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
-#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
-#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
-#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
-#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
-#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
-#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
-#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
-#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
-#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
-#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
-#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
-#define FTFA_XACCH3_REG(base) ((base)->XACCH3)
-#define FTFA_XACCH2_REG(base) ((base)->XACCH2)
-#define FTFA_XACCH1_REG(base) ((base)->XACCH1)
-#define FTFA_XACCH0_REG(base) ((base)->XACCH0)
-#define FTFA_XACCL3_REG(base) ((base)->XACCL3)
-#define FTFA_XACCL2_REG(base) ((base)->XACCL2)
-#define FTFA_XACCL1_REG(base) ((base)->XACCL1)
-#define FTFA_XACCL0_REG(base) ((base)->XACCL0)
-#define FTFA_SACCH3_REG(base) ((base)->SACCH3)
-#define FTFA_SACCH2_REG(base) ((base)->SACCH2)
-#define FTFA_SACCH1_REG(base) ((base)->SACCH1)
-#define FTFA_SACCH0_REG(base) ((base)->SACCH0)
-#define FTFA_SACCL3_REG(base) ((base)->SACCL3)
-#define FTFA_SACCL2_REG(base) ((base)->SACCL2)
-#define FTFA_SACCL1_REG(base) ((base)->SACCL1)
-#define FTFA_SACCL0_REG(base) ((base)->SACCL0)
-#define FTFA_FACSS_REG(base) ((base)->FACSS)
-#define FTFA_FACSN_REG(base) ((base)->FACSN)
-
-/*!
- * @}
- */ /* end of group FTFA_Register_Accessor_Macros */
-
+} FTFA_Type;
/* ----------------------------------------------------------------------------
-- FTFA Register Masks
@@ -2953,236 +2121,226 @@ typedef struct {
* @{
*/
-/* FSTAT Bit Fields */
-#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFA_FSTAT_MGSTAT0_SHIFT 0
-#define FTFA_FSTAT_MGSTAT0_WIDTH 1
-#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_MGSTAT0_SHIFT))&FTFA_FSTAT_MGSTAT0_MASK)
-#define FTFA_FSTAT_FPVIOL_MASK 0x10u
-#define FTFA_FSTAT_FPVIOL_SHIFT 4
-#define FTFA_FSTAT_FPVIOL_WIDTH 1
-#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_FPVIOL_SHIFT))&FTFA_FSTAT_FPVIOL_MASK)
-#define FTFA_FSTAT_ACCERR_MASK 0x20u
-#define FTFA_FSTAT_ACCERR_SHIFT 5
-#define FTFA_FSTAT_ACCERR_WIDTH 1
-#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_ACCERR_SHIFT))&FTFA_FSTAT_ACCERR_MASK)
-#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFA_FSTAT_RDCOLERR_SHIFT 6
-#define FTFA_FSTAT_RDCOLERR_WIDTH 1
-#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_RDCOLERR_SHIFT))&FTFA_FSTAT_RDCOLERR_MASK)
-#define FTFA_FSTAT_CCIF_MASK 0x80u
-#define FTFA_FSTAT_CCIF_SHIFT 7
-#define FTFA_FSTAT_CCIF_WIDTH 1
-#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_CCIF_SHIFT))&FTFA_FSTAT_CCIF_MASK)
-/* FCNFG Bit Fields */
-#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFA_FCNFG_ERSSUSP_SHIFT 4
-#define FTFA_FCNFG_ERSSUSP_WIDTH 1
-#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSSUSP_SHIFT))&FTFA_FCNFG_ERSSUSP_MASK)
-#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFA_FCNFG_ERSAREQ_SHIFT 5
-#define FTFA_FCNFG_ERSAREQ_WIDTH 1
-#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSAREQ_SHIFT))&FTFA_FCNFG_ERSAREQ_MASK)
-#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFA_FCNFG_RDCOLLIE_WIDTH 1
-#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_RDCOLLIE_SHIFT))&FTFA_FCNFG_RDCOLLIE_MASK)
-#define FTFA_FCNFG_CCIE_MASK 0x80u
-#define FTFA_FCNFG_CCIE_SHIFT 7
-#define FTFA_FCNFG_CCIE_WIDTH 1
-#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_CCIE_SHIFT))&FTFA_FCNFG_CCIE_MASK)
-/* FSEC Bit Fields */
-#define FTFA_FSEC_SEC_MASK 0x3u
-#define FTFA_FSEC_SEC_SHIFT 0
-#define FTFA_FSEC_SEC_WIDTH 2
-#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
-#define FTFA_FSEC_FSLACC_MASK 0xCu
-#define FTFA_FSEC_FSLACC_SHIFT 2
-#define FTFA_FSEC_FSLACC_WIDTH 2
-#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
-#define FTFA_FSEC_MEEN_MASK 0x30u
-#define FTFA_FSEC_MEEN_SHIFT 4
-#define FTFA_FSEC_MEEN_WIDTH 2
-#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
-#define FTFA_FSEC_KEYEN_MASK 0xC0u
-#define FTFA_FSEC_KEYEN_SHIFT 6
-#define FTFA_FSEC_KEYEN_WIDTH 2
-#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFA_FOPT_OPT_MASK 0xFFu
-#define FTFA_FOPT_OPT_SHIFT 0
-#define FTFA_FOPT_OPT_WIDTH 8
-#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB3_CCOBn_SHIFT 0
-#define FTFA_FCCOB3_CCOBn_WIDTH 8
-#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB2_CCOBn_SHIFT 0
-#define FTFA_FCCOB2_CCOBn_WIDTH 8
-#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB1_CCOBn_SHIFT 0
-#define FTFA_FCCOB1_CCOBn_WIDTH 8
-#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB0_CCOBn_SHIFT 0
-#define FTFA_FCCOB0_CCOBn_WIDTH 8
-#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB7_CCOBn_SHIFT 0
-#define FTFA_FCCOB7_CCOBn_WIDTH 8
-#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB6_CCOBn_SHIFT 0
-#define FTFA_FCCOB6_CCOBn_WIDTH 8
-#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB5_CCOBn_SHIFT 0
-#define FTFA_FCCOB5_CCOBn_WIDTH 8
-#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB4_CCOBn_SHIFT 0
-#define FTFA_FCCOB4_CCOBn_WIDTH 8
-#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBB_CCOBn_SHIFT 0
-#define FTFA_FCCOBB_CCOBn_WIDTH 8
-#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBA_CCOBn_SHIFT 0
-#define FTFA_FCCOBA_CCOBn_WIDTH 8
-#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB9_CCOBn_SHIFT 0
-#define FTFA_FCCOB9_CCOBn_WIDTH 8
-#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB8_CCOBn_SHIFT 0
-#define FTFA_FCCOB8_CCOBn_WIDTH 8
-#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFA_FPROT3_PROT_MASK 0xFFu
-#define FTFA_FPROT3_PROT_SHIFT 0
-#define FTFA_FPROT3_PROT_WIDTH 8
-#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFA_FPROT2_PROT_MASK 0xFFu
-#define FTFA_FPROT2_PROT_SHIFT 0
-#define FTFA_FPROT2_PROT_WIDTH 8
-#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFA_FPROT1_PROT_MASK 0xFFu
-#define FTFA_FPROT1_PROT_SHIFT 0
-#define FTFA_FPROT1_PROT_WIDTH 8
-#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFA_FPROT0_PROT_MASK 0xFFu
-#define FTFA_FPROT0_PROT_SHIFT 0
-#define FTFA_FPROT0_PROT_WIDTH 8
-#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
-/* XACCH3 Bit Fields */
-#define FTFA_XACCH3_XA_MASK 0xFFu
-#define FTFA_XACCH3_XA_SHIFT 0
-#define FTFA_XACCH3_XA_WIDTH 8
-#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
-/* XACCH2 Bit Fields */
-#define FTFA_XACCH2_XA_MASK 0xFFu
-#define FTFA_XACCH2_XA_SHIFT 0
-#define FTFA_XACCH2_XA_WIDTH 8
-#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
-/* XACCH1 Bit Fields */
-#define FTFA_XACCH1_XA_MASK 0xFFu
-#define FTFA_XACCH1_XA_SHIFT 0
-#define FTFA_XACCH1_XA_WIDTH 8
-#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
-/* XACCH0 Bit Fields */
-#define FTFA_XACCH0_XA_MASK 0xFFu
-#define FTFA_XACCH0_XA_SHIFT 0
-#define FTFA_XACCH0_XA_WIDTH 8
-#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
-/* XACCL3 Bit Fields */
-#define FTFA_XACCL3_XA_MASK 0xFFu
-#define FTFA_XACCL3_XA_SHIFT 0
-#define FTFA_XACCL3_XA_WIDTH 8
-#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
-/* XACCL2 Bit Fields */
-#define FTFA_XACCL2_XA_MASK 0xFFu
-#define FTFA_XACCL2_XA_SHIFT 0
-#define FTFA_XACCL2_XA_WIDTH 8
-#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
-/* XACCL1 Bit Fields */
-#define FTFA_XACCL1_XA_MASK 0xFFu
-#define FTFA_XACCL1_XA_SHIFT 0
-#define FTFA_XACCL1_XA_WIDTH 8
-#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
-/* XACCL0 Bit Fields */
-#define FTFA_XACCL0_XA_MASK 0xFFu
-#define FTFA_XACCL0_XA_SHIFT 0
-#define FTFA_XACCL0_XA_WIDTH 8
-#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
-/* SACCH3 Bit Fields */
-#define FTFA_SACCH3_SA_MASK 0xFFu
-#define FTFA_SACCH3_SA_SHIFT 0
-#define FTFA_SACCH3_SA_WIDTH 8
-#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
-/* SACCH2 Bit Fields */
-#define FTFA_SACCH2_SA_MASK 0xFFu
-#define FTFA_SACCH2_SA_SHIFT 0
-#define FTFA_SACCH2_SA_WIDTH 8
-#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
-/* SACCH1 Bit Fields */
-#define FTFA_SACCH1_SA_MASK 0xFFu
-#define FTFA_SACCH1_SA_SHIFT 0
-#define FTFA_SACCH1_SA_WIDTH 8
-#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
-/* SACCH0 Bit Fields */
-#define FTFA_SACCH0_SA_MASK 0xFFu
-#define FTFA_SACCH0_SA_SHIFT 0
-#define FTFA_SACCH0_SA_WIDTH 8
-#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
-/* SACCL3 Bit Fields */
-#define FTFA_SACCL3_SA_MASK 0xFFu
-#define FTFA_SACCL3_SA_SHIFT 0
-#define FTFA_SACCL3_SA_WIDTH 8
-#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
-/* SACCL2 Bit Fields */
-#define FTFA_SACCL2_SA_MASK 0xFFu
-#define FTFA_SACCL2_SA_SHIFT 0
-#define FTFA_SACCL2_SA_WIDTH 8
-#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
-/* SACCL1 Bit Fields */
-#define FTFA_SACCL1_SA_MASK 0xFFu
-#define FTFA_SACCL1_SA_SHIFT 0
-#define FTFA_SACCL1_SA_WIDTH 8
-#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
-/* SACCL0 Bit Fields */
-#define FTFA_SACCL0_SA_MASK 0xFFu
-#define FTFA_SACCL0_SA_SHIFT 0
-#define FTFA_SACCL0_SA_WIDTH 8
-#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
-/* FACSS Bit Fields */
-#define FTFA_FACSS_SGSIZE_MASK 0xFFu
-#define FTFA_FACSS_SGSIZE_SHIFT 0
-#define FTFA_FACSS_SGSIZE_WIDTH 8
-#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
-/* FACSN Bit Fields */
-#define FTFA_FACSN_NUMSG_MASK 0xFFu
-#define FTFA_FACSN_NUMSG_SHIFT 0
-#define FTFA_FACSN_NUMSG_WIDTH 8
-#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
+/*! @name FSTAT - Flash Status Register */
+#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
+#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
+#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
+#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
+#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
+#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
+#define FTFA_FSTAT_ACCERR_MASK (0x20U)
+#define FTFA_FSTAT_ACCERR_SHIFT (5U)
+#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
+#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
+#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
+#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
+#define FTFA_FSTAT_CCIF_MASK (0x80U)
+#define FTFA_FSTAT_CCIF_SHIFT (7U)
+#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
+#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
+#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
+#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
+#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
+#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
+#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
+#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
+#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
+#define FTFA_FCNFG_CCIE_MASK (0x80U)
+#define FTFA_FCNFG_CCIE_SHIFT (7U)
+#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFA_FSEC_SEC_MASK (0x3U)
+#define FTFA_FSEC_SEC_SHIFT (0U)
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK (0xCU)
+#define FTFA_FSEC_FSLACC_SHIFT (2U)
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK (0x30U)
+#define FTFA_FSEC_MEEN_SHIFT (4U)
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK (0xC0U)
+#define FTFA_FSEC_KEYEN_SHIFT (6U)
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFA_FOPT_OPT_MASK (0xFFU)
+#define FTFA_FOPT_OPT_SHIFT (0U)
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFA_FPROT3_PROT_MASK (0xFFU)
+#define FTFA_FPROT3_PROT_SHIFT (0U)
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFA_FPROT2_PROT_MASK (0xFFU)
+#define FTFA_FPROT2_PROT_SHIFT (0U)
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFA_FPROT1_PROT_MASK (0xFFU)
+#define FTFA_FPROT1_PROT_SHIFT (0U)
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFA_FPROT0_PROT_MASK (0xFFU)
+#define FTFA_FPROT0_PROT_SHIFT (0U)
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
+
+/*! @name XACCH3 - Execute-only Access Registers */
+#define FTFA_XACCH3_XA_MASK (0xFFU)
+#define FTFA_XACCH3_XA_SHIFT (0U)
+#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
+
+/*! @name XACCH2 - Execute-only Access Registers */
+#define FTFA_XACCH2_XA_MASK (0xFFU)
+#define FTFA_XACCH2_XA_SHIFT (0U)
+#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
+
+/*! @name XACCH1 - Execute-only Access Registers */
+#define FTFA_XACCH1_XA_MASK (0xFFU)
+#define FTFA_XACCH1_XA_SHIFT (0U)
+#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
+
+/*! @name XACCH0 - Execute-only Access Registers */
+#define FTFA_XACCH0_XA_MASK (0xFFU)
+#define FTFA_XACCH0_XA_SHIFT (0U)
+#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
+
+/*! @name XACCL3 - Execute-only Access Registers */
+#define FTFA_XACCL3_XA_MASK (0xFFU)
+#define FTFA_XACCL3_XA_SHIFT (0U)
+#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
+
+/*! @name XACCL2 - Execute-only Access Registers */
+#define FTFA_XACCL2_XA_MASK (0xFFU)
+#define FTFA_XACCL2_XA_SHIFT (0U)
+#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
+
+/*! @name XACCL1 - Execute-only Access Registers */
+#define FTFA_XACCL1_XA_MASK (0xFFU)
+#define FTFA_XACCL1_XA_SHIFT (0U)
+#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
+
+/*! @name XACCL0 - Execute-only Access Registers */
+#define FTFA_XACCL0_XA_MASK (0xFFU)
+#define FTFA_XACCL0_XA_SHIFT (0U)
+#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
+
+/*! @name SACCH3 - Supervisor-only Access Registers */
+#define FTFA_SACCH3_SA_MASK (0xFFU)
+#define FTFA_SACCH3_SA_SHIFT (0U)
+#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
+
+/*! @name SACCH2 - Supervisor-only Access Registers */
+#define FTFA_SACCH2_SA_MASK (0xFFU)
+#define FTFA_SACCH2_SA_SHIFT (0U)
+#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
+
+/*! @name SACCH1 - Supervisor-only Access Registers */
+#define FTFA_SACCH1_SA_MASK (0xFFU)
+#define FTFA_SACCH1_SA_SHIFT (0U)
+#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
+
+/*! @name SACCH0 - Supervisor-only Access Registers */
+#define FTFA_SACCH0_SA_MASK (0xFFU)
+#define FTFA_SACCH0_SA_SHIFT (0U)
+#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
+
+/*! @name SACCL3 - Supervisor-only Access Registers */
+#define FTFA_SACCL3_SA_MASK (0xFFU)
+#define FTFA_SACCL3_SA_SHIFT (0U)
+#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
+
+/*! @name SACCL2 - Supervisor-only Access Registers */
+#define FTFA_SACCL2_SA_MASK (0xFFU)
+#define FTFA_SACCL2_SA_SHIFT (0U)
+#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
+
+/*! @name SACCL1 - Supervisor-only Access Registers */
+#define FTFA_SACCL1_SA_MASK (0xFFU)
+#define FTFA_SACCL1_SA_SHIFT (0U)
+#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
+
+/*! @name SACCL0 - Supervisor-only Access Registers */
+#define FTFA_SACCL0_SA_MASK (0xFFU)
+#define FTFA_SACCL0_SA_SHIFT (0U)
+#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
+
+/*! @name FACSS - Flash Access Segment Size Register */
+#define FTFA_FACSS_SGSIZE_MASK (0xFFU)
+#define FTFA_FACSS_SGSIZE_SHIFT (0U)
+#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
+
+/*! @name FACSN - Flash Access Segment Number Register */
+#define FTFA_FACSN_NUMSG_MASK (0xFFU)
+#define FTFA_FACSN_NUMSG_SHIFT (0U)
+#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
+
/*!
* @}
@@ -3194,7 +2352,6 @@ typedef struct {
#define FTFA_BASE (0x40020000u)
/** Peripheral FTFA base pointer */
#define FTFA ((FTFA_Type *)FTFA_BASE)
-#define FTFA_BASE_PTR (FTFA)
/** Array initializer of FTFA peripheral base addresses */
#define FTFA_BASE_ADDRS { FTFA_BASE }
/** Array initializer of FTFA peripheral base pointers */
@@ -3203,62 +2360,6 @@ typedef struct {
#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
-/* ----------------------------------------------------------------------------
- -- FTFA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
- * @{
- */
-
-
-/* FTFA - Register instance definitions */
-/* FTFA */
-#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
-#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
-#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
-#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
-#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
-#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
-#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
-#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
-#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
-#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
-#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
-#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
-#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
-#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
-#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
-#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
-#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
-#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
-#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
-#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
-#define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
-#define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
-#define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
-#define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
-#define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
-#define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
-#define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
-#define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
-#define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
-#define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
-#define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
-#define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
-#define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
-#define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
-#define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
-#define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
-#define FTFA_FACSS FTFA_FACSS_REG(FTFA)
-#define FTFA_FACSN FTFA_FACSN_REG(FTFA)
-
-/*!
- * @}
- */ /* end of group FTFA_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
@@ -3302,51 +2403,7 @@ typedef struct {
__IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
__IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
__IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type, *FTM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register accessors */
-#define FTM_SC_REG(base) ((base)->SC)
-#define FTM_CNT_REG(base) ((base)->CNT)
-#define FTM_MOD_REG(base) ((base)->MOD)
-#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
-#define FTM_CnSC_COUNT 8
-#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
-#define FTM_CnV_COUNT 8
-#define FTM_CNTIN_REG(base) ((base)->CNTIN)
-#define FTM_STATUS_REG(base) ((base)->STATUS)
-#define FTM_MODE_REG(base) ((base)->MODE)
-#define FTM_SYNC_REG(base) ((base)->SYNC)
-#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
-#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
-#define FTM_COMBINE_REG(base) ((base)->COMBINE)
-#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
-#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
-#define FTM_POL_REG(base) ((base)->POL)
-#define FTM_FMS_REG(base) ((base)->FMS)
-#define FTM_FILTER_REG(base) ((base)->FILTER)
-#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
-#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
-#define FTM_CONF_REG(base) ((base)->CONF)
-#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
-#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
-#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
-#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
-#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
+} FTM_Type;
/* ----------------------------------------------------------------------------
-- FTM Register Masks
@@ -3357,759 +2414,608 @@ typedef struct {
* @{
*/
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK 0x7u
-#define FTM_SC_PS_SHIFT 0
-#define FTM_SC_PS_WIDTH 3
-#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK 0x18u
-#define FTM_SC_CLKS_SHIFT 3
-#define FTM_SC_CLKS_WIDTH 2
-#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK 0x20u
-#define FTM_SC_CPWMS_SHIFT 5
-#define FTM_SC_CPWMS_WIDTH 1
-#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
-#define FTM_SC_TOIE_MASK 0x40u
-#define FTM_SC_TOIE_SHIFT 6
-#define FTM_SC_TOIE_WIDTH 1
-#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
-#define FTM_SC_TOF_MASK 0x80u
-#define FTM_SC_TOF_SHIFT 7
-#define FTM_SC_TOF_WIDTH 1
-#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK 0xFFFFu
-#define FTM_CNT_COUNT_SHIFT 0
-#define FTM_CNT_COUNT_WIDTH 16
-#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK 0xFFFFu
-#define FTM_MOD_MOD_SHIFT 0
-#define FTM_MOD_MOD_WIDTH 16
-#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK 0x1u
-#define FTM_CnSC_DMA_SHIFT 0
-#define FTM_CnSC_DMA_WIDTH 1
-#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
-#define FTM_CnSC_ICRST_MASK 0x2u
-#define FTM_CnSC_ICRST_SHIFT 1
-#define FTM_CnSC_ICRST_WIDTH 1
-#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ICRST_SHIFT))&FTM_CnSC_ICRST_MASK)
-#define FTM_CnSC_ELSA_MASK 0x4u
-#define FTM_CnSC_ELSA_SHIFT 2
-#define FTM_CnSC_ELSA_WIDTH 1
-#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
-#define FTM_CnSC_ELSB_MASK 0x8u
-#define FTM_CnSC_ELSB_SHIFT 3
-#define FTM_CnSC_ELSB_WIDTH 1
-#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
-#define FTM_CnSC_MSA_MASK 0x10u
-#define FTM_CnSC_MSA_SHIFT 4
-#define FTM_CnSC_MSA_WIDTH 1
-#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
-#define FTM_CnSC_MSB_MASK 0x20u
-#define FTM_CnSC_MSB_SHIFT 5
-#define FTM_CnSC_MSB_WIDTH 1
-#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
-#define FTM_CnSC_CHIE_MASK 0x40u
-#define FTM_CnSC_CHIE_SHIFT 6
-#define FTM_CnSC_CHIE_WIDTH 1
-#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
-#define FTM_CnSC_CHF_MASK 0x80u
-#define FTM_CnSC_CHF_SHIFT 7
-#define FTM_CnSC_CHF_WIDTH 1
-#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK 0xFFFFu
-#define FTM_CnV_VAL_SHIFT 0
-#define FTM_CnV_VAL_WIDTH 16
-#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK 0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT 0
-#define FTM_CNTIN_INIT_WIDTH 16
-#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK 0x1u
-#define FTM_STATUS_CH0F_SHIFT 0
-#define FTM_STATUS_CH0F_WIDTH 1
-#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
-#define FTM_STATUS_CH1F_MASK 0x2u
-#define FTM_STATUS_CH1F_SHIFT 1
-#define FTM_STATUS_CH1F_WIDTH 1
-#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
-#define FTM_STATUS_CH2F_MASK 0x4u
-#define FTM_STATUS_CH2F_SHIFT 2
-#define FTM_STATUS_CH2F_WIDTH 1
-#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
-#define FTM_STATUS_CH3F_MASK 0x8u
-#define FTM_STATUS_CH3F_SHIFT 3
-#define FTM_STATUS_CH3F_WIDTH 1
-#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
-#define FTM_STATUS_CH4F_MASK 0x10u
-#define FTM_STATUS_CH4F_SHIFT 4
-#define FTM_STATUS_CH4F_WIDTH 1
-#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
-#define FTM_STATUS_CH5F_MASK 0x20u
-#define FTM_STATUS_CH5F_SHIFT 5
-#define FTM_STATUS_CH5F_WIDTH 1
-#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
-#define FTM_STATUS_CH6F_MASK 0x40u
-#define FTM_STATUS_CH6F_SHIFT 6
-#define FTM_STATUS_CH6F_WIDTH 1
-#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
-#define FTM_STATUS_CH7F_MASK 0x80u
-#define FTM_STATUS_CH7F_SHIFT 7
-#define FTM_STATUS_CH7F_WIDTH 1
-#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK 0x1u
-#define FTM_MODE_FTMEN_SHIFT 0
-#define FTM_MODE_FTMEN_WIDTH 1
-#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
-#define FTM_MODE_INIT_MASK 0x2u
-#define FTM_MODE_INIT_SHIFT 1
-#define FTM_MODE_INIT_WIDTH 1
-#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
-#define FTM_MODE_WPDIS_MASK 0x4u
-#define FTM_MODE_WPDIS_SHIFT 2
-#define FTM_MODE_WPDIS_WIDTH 1
-#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
-#define FTM_MODE_PWMSYNC_MASK 0x8u
-#define FTM_MODE_PWMSYNC_SHIFT 3
-#define FTM_MODE_PWMSYNC_WIDTH 1
-#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
-#define FTM_MODE_CAPTEST_MASK 0x10u
-#define FTM_MODE_CAPTEST_SHIFT 4
-#define FTM_MODE_CAPTEST_WIDTH 1
-#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
-#define FTM_MODE_FAULTM_MASK 0x60u
-#define FTM_MODE_FAULTM_SHIFT 5
-#define FTM_MODE_FAULTM_WIDTH 2
-#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK 0x80u
-#define FTM_MODE_FAULTIE_SHIFT 7
-#define FTM_MODE_FAULTIE_WIDTH 1
-#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK 0x1u
-#define FTM_SYNC_CNTMIN_SHIFT 0
-#define FTM_SYNC_CNTMIN_WIDTH 1
-#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
-#define FTM_SYNC_CNTMAX_MASK 0x2u
-#define FTM_SYNC_CNTMAX_SHIFT 1
-#define FTM_SYNC_CNTMAX_WIDTH 1
-#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
-#define FTM_SYNC_REINIT_MASK 0x4u
-#define FTM_SYNC_REINIT_SHIFT 2
-#define FTM_SYNC_REINIT_WIDTH 1
-#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
-#define FTM_SYNC_SYNCHOM_MASK 0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT 3
-#define FTM_SYNC_SYNCHOM_WIDTH 1
-#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
-#define FTM_SYNC_TRIG0_MASK 0x10u
-#define FTM_SYNC_TRIG0_SHIFT 4
-#define FTM_SYNC_TRIG0_WIDTH 1
-#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
-#define FTM_SYNC_TRIG1_MASK 0x20u
-#define FTM_SYNC_TRIG1_SHIFT 5
-#define FTM_SYNC_TRIG1_WIDTH 1
-#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
-#define FTM_SYNC_TRIG2_MASK 0x40u
-#define FTM_SYNC_TRIG2_SHIFT 6
-#define FTM_SYNC_TRIG2_WIDTH 1
-#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
-#define FTM_SYNC_SWSYNC_MASK 0x80u
-#define FTM_SYNC_SWSYNC_SHIFT 7
-#define FTM_SYNC_SWSYNC_WIDTH 1
-#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK 0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT 0
-#define FTM_OUTINIT_CH0OI_WIDTH 1
-#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
-#define FTM_OUTINIT_CH1OI_MASK 0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT 1
-#define FTM_OUTINIT_CH1OI_WIDTH 1
-#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
-#define FTM_OUTINIT_CH2OI_MASK 0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT 2
-#define FTM_OUTINIT_CH2OI_WIDTH 1
-#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
-#define FTM_OUTINIT_CH3OI_MASK 0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT 3
-#define FTM_OUTINIT_CH3OI_WIDTH 1
-#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
-#define FTM_OUTINIT_CH4OI_MASK 0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT 4
-#define FTM_OUTINIT_CH4OI_WIDTH 1
-#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
-#define FTM_OUTINIT_CH5OI_MASK 0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT 5
-#define FTM_OUTINIT_CH5OI_WIDTH 1
-#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
-#define FTM_OUTINIT_CH6OI_MASK 0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT 6
-#define FTM_OUTINIT_CH6OI_WIDTH 1
-#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
-#define FTM_OUTINIT_CH7OI_MASK 0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT 7
-#define FTM_OUTINIT_CH7OI_WIDTH 1
-#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK 0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT 0
-#define FTM_OUTMASK_CH0OM_WIDTH 1
-#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
-#define FTM_OUTMASK_CH1OM_MASK 0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT 1
-#define FTM_OUTMASK_CH1OM_WIDTH 1
-#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
-#define FTM_OUTMASK_CH2OM_MASK 0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT 2
-#define FTM_OUTMASK_CH2OM_WIDTH 1
-#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
-#define FTM_OUTMASK_CH3OM_MASK 0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT 3
-#define FTM_OUTMASK_CH3OM_WIDTH 1
-#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
-#define FTM_OUTMASK_CH4OM_MASK 0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT 4
-#define FTM_OUTMASK_CH4OM_WIDTH 1
-#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
-#define FTM_OUTMASK_CH5OM_MASK 0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT 5
-#define FTM_OUTMASK_CH5OM_WIDTH 1
-#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
-#define FTM_OUTMASK_CH6OM_MASK 0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT 6
-#define FTM_OUTMASK_CH6OM_WIDTH 1
-#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
-#define FTM_OUTMASK_CH7OM_MASK 0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT 7
-#define FTM_OUTMASK_CH7OM_WIDTH 1
-#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK 0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT 0
-#define FTM_COMBINE_COMBINE0_WIDTH 1
-#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
-#define FTM_COMBINE_COMP0_MASK 0x2u
-#define FTM_COMBINE_COMP0_SHIFT 1
-#define FTM_COMBINE_COMP0_WIDTH 1
-#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
-#define FTM_COMBINE_DECAPEN0_MASK 0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT 2
-#define FTM_COMBINE_DECAPEN0_WIDTH 1
-#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
-#define FTM_COMBINE_DECAP0_MASK 0x8u
-#define FTM_COMBINE_DECAP0_SHIFT 3
-#define FTM_COMBINE_DECAP0_WIDTH 1
-#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
-#define FTM_COMBINE_DTEN0_MASK 0x10u
-#define FTM_COMBINE_DTEN0_SHIFT 4
-#define FTM_COMBINE_DTEN0_WIDTH 1
-#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
-#define FTM_COMBINE_SYNCEN0_MASK 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT 5
-#define FTM_COMBINE_SYNCEN0_WIDTH 1
-#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
-#define FTM_COMBINE_FAULTEN0_MASK 0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT 6
-#define FTM_COMBINE_FAULTEN0_WIDTH 1
-#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
-#define FTM_COMBINE_COMBINE1_MASK 0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT 8
-#define FTM_COMBINE_COMBINE1_WIDTH 1
-#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
-#define FTM_COMBINE_COMP1_MASK 0x200u
-#define FTM_COMBINE_COMP1_SHIFT 9
-#define FTM_COMBINE_COMP1_WIDTH 1
-#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
-#define FTM_COMBINE_DECAPEN1_MASK 0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT 10
-#define FTM_COMBINE_DECAPEN1_WIDTH 1
-#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
-#define FTM_COMBINE_DECAP1_MASK 0x800u
-#define FTM_COMBINE_DECAP1_SHIFT 11
-#define FTM_COMBINE_DECAP1_WIDTH 1
-#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
-#define FTM_COMBINE_DTEN1_MASK 0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT 12
-#define FTM_COMBINE_DTEN1_WIDTH 1
-#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
-#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT 13
-#define FTM_COMBINE_SYNCEN1_WIDTH 1
-#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
-#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT 14
-#define FTM_COMBINE_FAULTEN1_WIDTH 1
-#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
-#define FTM_COMBINE_COMBINE2_MASK 0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT 16
-#define FTM_COMBINE_COMBINE2_WIDTH 1
-#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
-#define FTM_COMBINE_COMP2_MASK 0x20000u
-#define FTM_COMBINE_COMP2_SHIFT 17
-#define FTM_COMBINE_COMP2_WIDTH 1
-#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
-#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT 18
-#define FTM_COMBINE_DECAPEN2_WIDTH 1
-#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
-#define FTM_COMBINE_DECAP2_MASK 0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT 19
-#define FTM_COMBINE_DECAP2_WIDTH 1
-#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
-#define FTM_COMBINE_DTEN2_MASK 0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT 20
-#define FTM_COMBINE_DTEN2_WIDTH 1
-#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
-#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT 21
-#define FTM_COMBINE_SYNCEN2_WIDTH 1
-#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
-#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT 22
-#define FTM_COMBINE_FAULTEN2_WIDTH 1
-#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
-#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT 24
-#define FTM_COMBINE_COMBINE3_WIDTH 1
-#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
-#define FTM_COMBINE_COMP3_MASK 0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT 25
-#define FTM_COMBINE_COMP3_WIDTH 1
-#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
-#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT 26
-#define FTM_COMBINE_DECAPEN3_WIDTH 1
-#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
-#define FTM_COMBINE_DECAP3_MASK 0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT 27
-#define FTM_COMBINE_DECAP3_WIDTH 1
-#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
-#define FTM_COMBINE_DTEN3_MASK 0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT 28
-#define FTM_COMBINE_DTEN3_WIDTH 1
-#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
-#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT 29
-#define FTM_COMBINE_SYNCEN3_WIDTH 1
-#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
-#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT 30
-#define FTM_COMBINE_FAULTEN3_WIDTH 1
-#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT 0
-#define FTM_DEADTIME_DTVAL_WIDTH 6
-#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK 0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT 6
-#define FTM_DEADTIME_DTPS_WIDTH 2
-#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
-#define FTM_EXTTRIG_CH2TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
-#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
-#define FTM_EXTTRIG_CH3TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
-#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
-#define FTM_EXTTRIG_CH4TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
-#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
-#define FTM_EXTTRIG_CH5TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
-#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
-#define FTM_EXTTRIG_CH0TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
-#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
-#define FTM_EXTTRIG_CH1TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
-#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
-#define FTM_EXTTRIG_INITTRIGEN_WIDTH 1
-#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
-#define FTM_EXTTRIG_TRIGF_MASK 0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT 7
-#define FTM_EXTTRIG_TRIGF_WIDTH 1
-#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK 0x1u
-#define FTM_POL_POL0_SHIFT 0
-#define FTM_POL_POL0_WIDTH 1
-#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
-#define FTM_POL_POL1_MASK 0x2u
-#define FTM_POL_POL1_SHIFT 1
-#define FTM_POL_POL1_WIDTH 1
-#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
-#define FTM_POL_POL2_MASK 0x4u
-#define FTM_POL_POL2_SHIFT 2
-#define FTM_POL_POL2_WIDTH 1
-#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
-#define FTM_POL_POL3_MASK 0x8u
-#define FTM_POL_POL3_SHIFT 3
-#define FTM_POL_POL3_WIDTH 1
-#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
-#define FTM_POL_POL4_MASK 0x10u
-#define FTM_POL_POL4_SHIFT 4
-#define FTM_POL_POL4_WIDTH 1
-#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
-#define FTM_POL_POL5_MASK 0x20u
-#define FTM_POL_POL5_SHIFT 5
-#define FTM_POL_POL5_WIDTH 1
-#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
-#define FTM_POL_POL6_MASK 0x40u
-#define FTM_POL_POL6_SHIFT 6
-#define FTM_POL_POL6_WIDTH 1
-#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
-#define FTM_POL_POL7_MASK 0x80u
-#define FTM_POL_POL7_SHIFT 7
-#define FTM_POL_POL7_WIDTH 1
-#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK 0x1u
-#define FTM_FMS_FAULTF0_SHIFT 0
-#define FTM_FMS_FAULTF0_WIDTH 1
-#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
-#define FTM_FMS_FAULTF1_MASK 0x2u
-#define FTM_FMS_FAULTF1_SHIFT 1
-#define FTM_FMS_FAULTF1_WIDTH 1
-#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
-#define FTM_FMS_FAULTF2_MASK 0x4u
-#define FTM_FMS_FAULTF2_SHIFT 2
-#define FTM_FMS_FAULTF2_WIDTH 1
-#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
-#define FTM_FMS_FAULTF3_MASK 0x8u
-#define FTM_FMS_FAULTF3_SHIFT 3
-#define FTM_FMS_FAULTF3_WIDTH 1
-#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
-#define FTM_FMS_FAULTIN_MASK 0x20u
-#define FTM_FMS_FAULTIN_SHIFT 5
-#define FTM_FMS_FAULTIN_WIDTH 1
-#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
-#define FTM_FMS_WPEN_MASK 0x40u
-#define FTM_FMS_WPEN_SHIFT 6
-#define FTM_FMS_WPEN_WIDTH 1
-#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
-#define FTM_FMS_FAULTF_MASK 0x80u
-#define FTM_FMS_FAULTF_SHIFT 7
-#define FTM_FMS_FAULTF_WIDTH 1
-#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK 0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT 0
-#define FTM_FILTER_CH0FVAL_WIDTH 4
-#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK 0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT 4
-#define FTM_FILTER_CH1FVAL_WIDTH 4
-#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK 0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT 8
-#define FTM_FILTER_CH2FVAL_WIDTH 4
-#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK 0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT 12
-#define FTM_FILTER_CH3FVAL_WIDTH 4
-#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
-#define FTM_FLTCTRL_FAULT0EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
-#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
-#define FTM_FLTCTRL_FAULT1EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
-#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
-#define FTM_FLTCTRL_FAULT2EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
-#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
-#define FTM_FLTCTRL_FAULT3EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
-#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
-#define FTM_FLTCTRL_FFLTR0EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
-#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
-#define FTM_FLTCTRL_FFLTR1EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
-#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
-#define FTM_FLTCTRL_FFLTR2EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
-#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
-#define FTM_FLTCTRL_FFLTR3EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
-#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT 8
-#define FTM_FLTCTRL_FFVAL_WIDTH 4
-#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK 0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT 0
-#define FTM_QDCTRL_QUADEN_WIDTH 1
-#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
-#define FTM_QDCTRL_TOFDIR_MASK 0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT 1
-#define FTM_QDCTRL_TOFDIR_WIDTH 1
-#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
-#define FTM_QDCTRL_QUADIR_MASK 0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT 2
-#define FTM_QDCTRL_QUADIR_WIDTH 1
-#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
-#define FTM_QDCTRL_QUADMODE_MASK 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT 3
-#define FTM_QDCTRL_QUADMODE_WIDTH 1
-#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
-#define FTM_QDCTRL_PHBPOL_MASK 0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT 4
-#define FTM_QDCTRL_PHBPOL_WIDTH 1
-#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
-#define FTM_QDCTRL_PHAPOL_MASK 0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT 5
-#define FTM_QDCTRL_PHAPOL_WIDTH 1
-#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
-#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
-#define FTM_QDCTRL_PHBFLTREN_WIDTH 1
-#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
-#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
-#define FTM_QDCTRL_PHAFLTREN_WIDTH 1
-#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK 0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT 0
-#define FTM_CONF_NUMTOF_WIDTH 5
-#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK 0xC0u
-#define FTM_CONF_BDMMODE_SHIFT 6
-#define FTM_CONF_BDMMODE_WIDTH 2
-#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK 0x200u
-#define FTM_CONF_GTBEEN_SHIFT 9
-#define FTM_CONF_GTBEEN_WIDTH 1
-#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
-#define FTM_CONF_GTBEOUT_MASK 0x400u
-#define FTM_CONF_GTBEOUT_SHIFT 10
-#define FTM_CONF_GTBEOUT_WIDTH 1
-#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK 0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT 0
-#define FTM_FLTPOL_FLT0POL_WIDTH 1
-#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
-#define FTM_FLTPOL_FLT1POL_MASK 0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT 1
-#define FTM_FLTPOL_FLT1POL_WIDTH 1
-#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
-#define FTM_FLTPOL_FLT2POL_MASK 0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT 2
-#define FTM_FLTPOL_FLT2POL_WIDTH 1
-#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
-#define FTM_FLTPOL_FLT3POL_MASK 0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT 3
-#define FTM_FLTPOL_FLT3POL_WIDTH 1
-#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
-#define FTM_SYNCONF_HWTRIGMODE_WIDTH 1
-#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
-#define FTM_SYNCONF_CNTINC_MASK 0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT 2
-#define FTM_SYNCONF_CNTINC_WIDTH 1
-#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
-#define FTM_SYNCONF_INVC_MASK 0x10u
-#define FTM_SYNCONF_INVC_SHIFT 4
-#define FTM_SYNCONF_INVC_WIDTH 1
-#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
-#define FTM_SYNCONF_SWOC_MASK 0x20u
-#define FTM_SYNCONF_SWOC_SHIFT 5
-#define FTM_SYNCONF_SWOC_WIDTH 1
-#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
-#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT 7
-#define FTM_SYNCONF_SYNCMODE_WIDTH 1
-#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
-#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
-#define FTM_SYNCONF_SWRSTCNT_WIDTH 1
-#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
-#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT 9
-#define FTM_SYNCONF_SWWRBUF_WIDTH 1
-#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
-#define FTM_SYNCONF_SWOM_MASK 0x400u
-#define FTM_SYNCONF_SWOM_SHIFT 10
-#define FTM_SYNCONF_SWOM_WIDTH 1
-#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
-#define FTM_SYNCONF_SWINVC_MASK 0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT 11
-#define FTM_SYNCONF_SWINVC_WIDTH 1
-#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
-#define FTM_SYNCONF_SWSOC_MASK 0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT 12
-#define FTM_SYNCONF_SWSOC_WIDTH 1
-#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
-#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
-#define FTM_SYNCONF_HWRSTCNT_WIDTH 1
-#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
-#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT 17
-#define FTM_SYNCONF_HWWRBUF_WIDTH 1
-#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
-#define FTM_SYNCONF_HWOM_MASK 0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT 18
-#define FTM_SYNCONF_HWOM_WIDTH 1
-#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
-#define FTM_SYNCONF_HWINVC_MASK 0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT 19
-#define FTM_SYNCONF_HWINVC_WIDTH 1
-#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
-#define FTM_SYNCONF_HWSOC_MASK 0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT 20
-#define FTM_SYNCONF_HWSOC_WIDTH 1
-#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK 0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT 0
-#define FTM_INVCTRL_INV0EN_WIDTH 1
-#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
-#define FTM_INVCTRL_INV1EN_MASK 0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT 1
-#define FTM_INVCTRL_INV1EN_WIDTH 1
-#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
-#define FTM_INVCTRL_INV2EN_MASK 0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT 2
-#define FTM_INVCTRL_INV2EN_WIDTH 1
-#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
-#define FTM_INVCTRL_INV3EN_MASK 0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT 3
-#define FTM_INVCTRL_INV3EN_WIDTH 1
-#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK 0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT 0
-#define FTM_SWOCTRL_CH0OC_WIDTH 1
-#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
-#define FTM_SWOCTRL_CH1OC_MASK 0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT 1
-#define FTM_SWOCTRL_CH1OC_WIDTH 1
-#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
-#define FTM_SWOCTRL_CH2OC_MASK 0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT 2
-#define FTM_SWOCTRL_CH2OC_WIDTH 1
-#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
-#define FTM_SWOCTRL_CH3OC_MASK 0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT 3
-#define FTM_SWOCTRL_CH3OC_WIDTH 1
-#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
-#define FTM_SWOCTRL_CH4OC_MASK 0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT 4
-#define FTM_SWOCTRL_CH4OC_WIDTH 1
-#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
-#define FTM_SWOCTRL_CH5OC_MASK 0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT 5
-#define FTM_SWOCTRL_CH5OC_WIDTH 1
-#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
-#define FTM_SWOCTRL_CH6OC_MASK 0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT 6
-#define FTM_SWOCTRL_CH6OC_WIDTH 1
-#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
-#define FTM_SWOCTRL_CH7OC_MASK 0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT 7
-#define FTM_SWOCTRL_CH7OC_WIDTH 1
-#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
-#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT 8
-#define FTM_SWOCTRL_CH0OCV_WIDTH 1
-#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
-#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT 9
-#define FTM_SWOCTRL_CH1OCV_WIDTH 1
-#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
-#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT 10
-#define FTM_SWOCTRL_CH2OCV_WIDTH 1
-#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
-#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT 11
-#define FTM_SWOCTRL_CH3OCV_WIDTH 1
-#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
-#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT 12
-#define FTM_SWOCTRL_CH4OCV_WIDTH 1
-#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
-#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT 13
-#define FTM_SWOCTRL_CH5OCV_WIDTH 1
-#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
-#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT 14
-#define FTM_SWOCTRL_CH6OCV_WIDTH 1
-#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
-#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT 15
-#define FTM_SWOCTRL_CH7OCV_WIDTH 1
-#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT 0
-#define FTM_PWMLOAD_CH0SEL_WIDTH 1
-#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
-#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT 1
-#define FTM_PWMLOAD_CH1SEL_WIDTH 1
-#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
-#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT 2
-#define FTM_PWMLOAD_CH2SEL_WIDTH 1
-#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
-#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT 3
-#define FTM_PWMLOAD_CH3SEL_WIDTH 1
-#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
-#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT 4
-#define FTM_PWMLOAD_CH4SEL_WIDTH 1
-#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
-#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT 5
-#define FTM_PWMLOAD_CH5SEL_WIDTH 1
-#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
-#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT 6
-#define FTM_PWMLOAD_CH6SEL_WIDTH 1
-#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
-#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT 7
-#define FTM_PWMLOAD_CH7SEL_WIDTH 1
-#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
-#define FTM_PWMLOAD_LDOK_MASK 0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT 9
-#define FTM_PWMLOAD_LDOK_WIDTH 1
-#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+/*! @name SC - Status And Control */
+#define FTM_SC_PS_MASK (0x7U)
+#define FTM_SC_PS_SHIFT (0U)
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK (0x18U)
+#define FTM_SC_CLKS_SHIFT (3U)
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK (0x20U)
+#define FTM_SC_CPWMS_SHIFT (5U)
+#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK (0x40U)
+#define FTM_SC_TOIE_SHIFT (6U)
+#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK (0x80U)
+#define FTM_SC_TOF_SHIFT (7U)
+#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+
+/*! @name CNT - Counter */
+#define FTM_CNT_COUNT_MASK (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT (0U)
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define FTM_MOD_MOD_MASK (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT (0U)
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status And Control */
+#define FTM_CnSC_DMA_MASK (0x1U)
+#define FTM_CnSC_DMA_SHIFT (0U)
+#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ICRST_MASK (0x2U)
+#define FTM_CnSC_ICRST_SHIFT (1U)
+#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
+#define FTM_CnSC_ELSA_MASK (0x4U)
+#define FTM_CnSC_ELSA_SHIFT (2U)
+#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK (0x8U)
+#define FTM_CnSC_ELSB_SHIFT (3U)
+#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK (0x10U)
+#define FTM_CnSC_MSA_SHIFT (4U)
+#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK (0x20U)
+#define FTM_CnSC_MSB_SHIFT (5U)
+#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK (0x40U)
+#define FTM_CnSC_CHIE_SHIFT (6U)
+#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK (0x80U)
+#define FTM_CnSC_CHF_SHIFT (7U)
+#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT (8U)
+
+/*! @name CnV - Channel (n) Value */
+#define FTM_CnV_VAL_MASK (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT (0U)
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+#define FTM_CNTIN_INIT_MASK (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT (0U)
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+
+/*! @name STATUS - Capture And Compare Status */
+#define FTM_STATUS_CH0F_MASK (0x1U)
+#define FTM_STATUS_CH0F_SHIFT (0U)
+#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK (0x2U)
+#define FTM_STATUS_CH1F_SHIFT (1U)
+#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK (0x4U)
+#define FTM_STATUS_CH2F_SHIFT (2U)
+#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK (0x8U)
+#define FTM_STATUS_CH3F_SHIFT (3U)
+#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK (0x10U)
+#define FTM_STATUS_CH4F_SHIFT (4U)
+#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK (0x20U)
+#define FTM_STATUS_CH5F_SHIFT (5U)
+#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK (0x40U)
+#define FTM_STATUS_CH6F_SHIFT (6U)
+#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK (0x80U)
+#define FTM_STATUS_CH7F_SHIFT (7U)
+#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+
+/*! @name MODE - Features Mode Selection */
+#define FTM_MODE_FTMEN_MASK (0x1U)
+#define FTM_MODE_FTMEN_SHIFT (0U)
+#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK (0x2U)
+#define FTM_MODE_INIT_SHIFT (1U)
+#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK (0x4U)
+#define FTM_MODE_WPDIS_SHIFT (2U)
+#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK (0x8U)
+#define FTM_MODE_PWMSYNC_SHIFT (3U)
+#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK (0x10U)
+#define FTM_MODE_CAPTEST_SHIFT (4U)
+#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK (0x60U)
+#define FTM_MODE_FAULTM_SHIFT (5U)
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK (0x80U)
+#define FTM_MODE_FAULTIE_SHIFT (7U)
+#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+
+/*! @name SYNC - Synchronization */
+#define FTM_SYNC_CNTMIN_MASK (0x1U)
+#define FTM_SYNC_CNTMIN_SHIFT (0U)
+#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK (0x2U)
+#define FTM_SYNC_CNTMAX_SHIFT (1U)
+#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK (0x4U)
+#define FTM_SYNC_REINIT_SHIFT (2U)
+#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK (0x8U)
+#define FTM_SYNC_SYNCHOM_SHIFT (3U)
+#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK (0x10U)
+#define FTM_SYNC_TRIG0_SHIFT (4U)
+#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK (0x20U)
+#define FTM_SYNC_TRIG1_SHIFT (5U)
+#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK (0x40U)
+#define FTM_SYNC_TRIG2_SHIFT (6U)
+#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK (0x80U)
+#define FTM_SYNC_SWSYNC_SHIFT (7U)
+#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+
+/*! @name OUTINIT - Initial State For Channels Output */
+#define FTM_OUTINIT_CH0OI_MASK (0x1U)
+#define FTM_OUTINIT_CH0OI_SHIFT (0U)
+#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK (0x2U)
+#define FTM_OUTINIT_CH1OI_SHIFT (1U)
+#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK (0x4U)
+#define FTM_OUTINIT_CH2OI_SHIFT (2U)
+#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK (0x8U)
+#define FTM_OUTINIT_CH3OI_SHIFT (3U)
+#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK (0x10U)
+#define FTM_OUTINIT_CH4OI_SHIFT (4U)
+#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK (0x20U)
+#define FTM_OUTINIT_CH5OI_SHIFT (5U)
+#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK (0x40U)
+#define FTM_OUTINIT_CH6OI_SHIFT (6U)
+#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK (0x80U)
+#define FTM_OUTINIT_CH7OI_SHIFT (7U)
+#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+
+/*! @name OUTMASK - Output Mask */
+#define FTM_OUTMASK_CH0OM_MASK (0x1U)
+#define FTM_OUTMASK_CH0OM_SHIFT (0U)
+#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK (0x2U)
+#define FTM_OUTMASK_CH1OM_SHIFT (1U)
+#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK (0x4U)
+#define FTM_OUTMASK_CH2OM_SHIFT (2U)
+#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK (0x8U)
+#define FTM_OUTMASK_CH3OM_SHIFT (3U)
+#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK (0x10U)
+#define FTM_OUTMASK_CH4OM_SHIFT (4U)
+#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK (0x20U)
+#define FTM_OUTMASK_CH5OM_SHIFT (5U)
+#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK (0x40U)
+#define FTM_OUTMASK_CH6OM_SHIFT (6U)
+#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK (0x80U)
+#define FTM_OUTMASK_CH7OM_SHIFT (7U)
+#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+
+/*! @name COMBINE - Function For Linked Channels */
+#define FTM_COMBINE_COMBINE0_MASK (0x1U)
+#define FTM_COMBINE_COMBINE0_SHIFT (0U)
+#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK (0x2U)
+#define FTM_COMBINE_COMP0_SHIFT (1U)
+#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
+#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
+#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK (0x8U)
+#define FTM_COMBINE_DECAP0_SHIFT (3U)
+#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK (0x10U)
+#define FTM_COMBINE_DTEN0_SHIFT (4U)
+#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
+#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
+#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
+#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
+#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK (0x100U)
+#define FTM_COMBINE_COMBINE1_SHIFT (8U)
+#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK (0x200U)
+#define FTM_COMBINE_COMP1_SHIFT (9U)
+#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
+#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
+#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK (0x800U)
+#define FTM_COMBINE_DECAP1_SHIFT (11U)
+#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK (0x1000U)
+#define FTM_COMBINE_DTEN1_SHIFT (12U)
+#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
+#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
+#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
+#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
+#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
+#define FTM_COMBINE_COMBINE2_SHIFT (16U)
+#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK (0x20000U)
+#define FTM_COMBINE_COMP2_SHIFT (17U)
+#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
+#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
+#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK (0x80000U)
+#define FTM_COMBINE_DECAP2_SHIFT (19U)
+#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK (0x100000U)
+#define FTM_COMBINE_DTEN2_SHIFT (20U)
+#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
+#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
+#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
+#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
+#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
+#define FTM_COMBINE_COMBINE3_SHIFT (24U)
+#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK (0x2000000U)
+#define FTM_COMBINE_COMP3_SHIFT (25U)
+#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
+#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
+#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
+#define FTM_COMBINE_DECAP3_SHIFT (27U)
+#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
+#define FTM_COMBINE_DTEN3_SHIFT (28U)
+#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
+#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
+#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
+#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
+#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT (0U)
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT (6U)
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+
+/*! @name EXTTRIG - FTM External Trigger */
+#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
+#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
+#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
+#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
+#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
+#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
+#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
+#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
+#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
+#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
+#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
+#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
+#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
+#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
+#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
+#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+
+/*! @name POL - Channels Polarity */
+#define FTM_POL_POL0_MASK (0x1U)
+#define FTM_POL_POL0_SHIFT (0U)
+#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK (0x2U)
+#define FTM_POL_POL1_SHIFT (1U)
+#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK (0x4U)
+#define FTM_POL_POL2_SHIFT (2U)
+#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK (0x8U)
+#define FTM_POL_POL3_SHIFT (3U)
+#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK (0x10U)
+#define FTM_POL_POL4_SHIFT (4U)
+#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK (0x20U)
+#define FTM_POL_POL5_SHIFT (5U)
+#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK (0x40U)
+#define FTM_POL_POL6_SHIFT (6U)
+#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK (0x80U)
+#define FTM_POL_POL7_SHIFT (7U)
+#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+
+/*! @name FMS - Fault Mode Status */
+#define FTM_FMS_FAULTF0_MASK (0x1U)
+#define FTM_FMS_FAULTF0_SHIFT (0U)
+#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK (0x2U)
+#define FTM_FMS_FAULTF1_SHIFT (1U)
+#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK (0x4U)
+#define FTM_FMS_FAULTF2_SHIFT (2U)
+#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK (0x8U)
+#define FTM_FMS_FAULTF3_SHIFT (3U)
+#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK (0x20U)
+#define FTM_FMS_FAULTIN_SHIFT (5U)
+#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK (0x40U)
+#define FTM_FMS_WPEN_SHIFT (6U)
+#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK (0x80U)
+#define FTM_FMS_FAULTF_SHIFT (7U)
+#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+
+/*! @name FILTER - Input Capture Filter Control */
+#define FTM_FILTER_CH0FVAL_MASK (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT (0U)
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT (4U)
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT (8U)
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT (12U)
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+
+/*! @name FLTCTRL - Fault Control */
+#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
+#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
+#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
+#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
+#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
+#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
+#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
+#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
+#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
+#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
+#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
+#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
+#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control And Status */
+#define FTM_QDCTRL_QUADEN_MASK (0x1U)
+#define FTM_QDCTRL_QUADEN_SHIFT (0U)
+#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
+#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
+#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK (0x4U)
+#define FTM_QDCTRL_QUADIR_SHIFT (2U)
+#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
+#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
+#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
+#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
+#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
+#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
+#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
+#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
+#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
+#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
+#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+
+/*! @name CONF - Configuration */
+#define FTM_CONF_NUMTOF_MASK (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT (0U)
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT (6U)
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK (0x200U)
+#define FTM_CONF_GTBEEN_SHIFT (9U)
+#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK (0x400U)
+#define FTM_CONF_GTBEOUT_SHIFT (10U)
+#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
+#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
+#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
+#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
+#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
+#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
+#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
+#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
+#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+
+/*! @name SYNCONF - Synchronization Configuration */
+#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
+#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK (0x4U)
+#define FTM_SYNCONF_CNTINC_SHIFT (2U)
+#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK (0x10U)
+#define FTM_SYNCONF_INVC_SHIFT (4U)
+#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK (0x20U)
+#define FTM_SYNCONF_SWOC_SHIFT (5U)
+#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
+#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
+#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
+#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
+#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
+#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
+#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK (0x400U)
+#define FTM_SYNCONF_SWOM_SHIFT (10U)
+#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK (0x800U)
+#define FTM_SYNCONF_SWINVC_SHIFT (11U)
+#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
+#define FTM_SYNCONF_SWSOC_SHIFT (12U)
+#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
+#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
+#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
+#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
+#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK (0x40000U)
+#define FTM_SYNCONF_HWOM_SHIFT (18U)
+#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
+#define FTM_SYNCONF_HWINVC_SHIFT (19U)
+#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
+#define FTM_SYNCONF_HWSOC_SHIFT (20U)
+#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+
+/*! @name INVCTRL - FTM Inverting Control */
+#define FTM_INVCTRL_INV0EN_MASK (0x1U)
+#define FTM_INVCTRL_INV0EN_SHIFT (0U)
+#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK (0x2U)
+#define FTM_INVCTRL_INV1EN_SHIFT (1U)
+#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK (0x4U)
+#define FTM_INVCTRL_INV2EN_SHIFT (2U)
+#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK (0x8U)
+#define FTM_INVCTRL_INV3EN_SHIFT (3U)
+#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+
+/*! @name SWOCTRL - FTM Software Output Control */
+#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
+#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
+#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
+#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
+#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
+#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
+#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
+#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
+#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
+#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
+#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
+#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
+#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
+#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
+#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
+#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
+#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
+#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
+#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
+#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
+#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
+#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
+#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
+#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
+#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
+#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
+#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
+#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
+#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
+#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
+#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
+#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
+#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+
+/*! @name PWMLOAD - FTM PWM Load */
+#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
+#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
+#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
+#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
+#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
+#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
+#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
+#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
+#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
+#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
+#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
+#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
+#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
+#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
+#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
+#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
+#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK (0x200U)
+#define FTM_PWMLOAD_LDOK_SHIFT (9U)
+#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+
/*!
* @}
@@ -4121,17 +3027,14 @@ typedef struct {
#define FTM0_BASE (0x40038000u)
/** Peripheral FTM0 base pointer */
#define FTM0 ((FTM_Type *)FTM0_BASE)
-#define FTM0_BASE_PTR (FTM0)
/** Peripheral FTM1 base address */
#define FTM1_BASE (0x40039000u)
/** Peripheral FTM1 base pointer */
#define FTM1 ((FTM_Type *)FTM1_BASE)
-#define FTM1_BASE_PTR (FTM1)
/** Peripheral FTM2 base address */
#define FTM2_BASE (0x4003A000u)
/** Peripheral FTM2 base pointer */
#define FTM2 ((FTM_Type *)FTM2_BASE)
-#define FTM2_BASE_PTR (FTM2)
/** Array initializer of FTM peripheral base addresses */
#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE }
/** Array initializer of FTM peripheral base pointers */
@@ -4139,127 +3042,6 @@ typedef struct {
/** Interrupt vectors for the FTM peripheral type */
#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register instance definitions */
-/* FTM0 */
-#define FTM0_SC FTM_SC_REG(FTM0)
-#define FTM0_CNT FTM_CNT_REG(FTM0)
-#define FTM0_MOD FTM_MOD_REG(FTM0)
-#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
-#define FTM0_C0V FTM_CnV_REG(FTM0,0)
-#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
-#define FTM0_C1V FTM_CnV_REG(FTM0,1)
-#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
-#define FTM0_C2V FTM_CnV_REG(FTM0,2)
-#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
-#define FTM0_C3V FTM_CnV_REG(FTM0,3)
-#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
-#define FTM0_C4V FTM_CnV_REG(FTM0,4)
-#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
-#define FTM0_C5V FTM_CnV_REG(FTM0,5)
-#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
-#define FTM0_C6V FTM_CnV_REG(FTM0,6)
-#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
-#define FTM0_C7V FTM_CnV_REG(FTM0,7)
-#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
-#define FTM0_STATUS FTM_STATUS_REG(FTM0)
-#define FTM0_MODE FTM_MODE_REG(FTM0)
-#define FTM0_SYNC FTM_SYNC_REG(FTM0)
-#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
-#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
-#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
-#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
-#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
-#define FTM0_POL FTM_POL_REG(FTM0)
-#define FTM0_FMS FTM_FMS_REG(FTM0)
-#define FTM0_FILTER FTM_FILTER_REG(FTM0)
-#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
-#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
-#define FTM0_CONF FTM_CONF_REG(FTM0)
-#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
-#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
-#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
-#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
-#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
-/* FTM1 */
-#define FTM1_SC FTM_SC_REG(FTM1)
-#define FTM1_CNT FTM_CNT_REG(FTM1)
-#define FTM1_MOD FTM_MOD_REG(FTM1)
-#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
-#define FTM1_C0V FTM_CnV_REG(FTM1,0)
-#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
-#define FTM1_C1V FTM_CnV_REG(FTM1,1)
-#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
-#define FTM1_STATUS FTM_STATUS_REG(FTM1)
-#define FTM1_MODE FTM_MODE_REG(FTM1)
-#define FTM1_SYNC FTM_SYNC_REG(FTM1)
-#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
-#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
-#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
-#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
-#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
-#define FTM1_POL FTM_POL_REG(FTM1)
-#define FTM1_FMS FTM_FMS_REG(FTM1)
-#define FTM1_FILTER FTM_FILTER_REG(FTM1)
-#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
-#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
-#define FTM1_CONF FTM_CONF_REG(FTM1)
-#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
-#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
-#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
-#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
-#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
-/* FTM2 */
-#define FTM2_SC FTM_SC_REG(FTM2)
-#define FTM2_CNT FTM_CNT_REG(FTM2)
-#define FTM2_MOD FTM_MOD_REG(FTM2)
-#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
-#define FTM2_C0V FTM_CnV_REG(FTM2,0)
-#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
-#define FTM2_C1V FTM_CnV_REG(FTM2,1)
-#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
-#define FTM2_STATUS FTM_STATUS_REG(FTM2)
-#define FTM2_MODE FTM_MODE_REG(FTM2)
-#define FTM2_SYNC FTM_SYNC_REG(FTM2)
-#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
-#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
-#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
-#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
-#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
-#define FTM2_POL FTM_POL_REG(FTM2)
-#define FTM2_FMS FTM_FMS_REG(FTM2)
-#define FTM2_FILTER FTM_FILTER_REG(FTM2)
-#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
-#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
-#define FTM2_CONF FTM_CONF_REG(FTM2)
-#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
-#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
-#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
-#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
-#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
-
-/* FTM - Register array accessors */
-#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
-#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
-#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
-#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
-#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
-#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FTM_Peripheral_Access_Layer */
@@ -4282,70 +3064,47 @@ typedef struct {
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type, *GPIO_MemMapPtr;
+} GPIO_Type;
/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
+ -- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT (0U)
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
-/* GPIO - Register accessors */
-#define GPIO_PDOR_REG(base) ((base)->PDOR)
-#define GPIO_PSOR_REG(base) ((base)->PSOR)
-#define GPIO_PCOR_REG(base) ((base)->PCOR)
-#define GPIO_PTOR_REG(base) ((base)->PTOR)
-#define GPIO_PDIR_REG(base) ((base)->PDIR)
-#define GPIO_PDDR_REG(base) ((base)->PDDR)
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT (0U)
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT (0U)
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT (0U)
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT (0U)
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT (0U)
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO_WIDTH 32
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO_WIDTH 32
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO_WIDTH 32
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO_WIDTH 32
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI_WIDTH 32
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD_WIDTH 32
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/*!
* @}
@@ -4353,87 +3112,30 @@ typedef struct {
/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-#define PTA_BASE_PTR (PTA)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-#define PTB_BASE_PTR (PTB)
-/** Peripheral PTC base address */
-#define PTC_BASE (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC ((GPIO_Type *)PTC_BASE)
-#define PTC_BASE_PTR (PTC)
-/** Peripheral PTD base address */
-#define PTD_BASE (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD ((GPIO_Type *)PTD_BASE)
-#define PTD_BASE_PTR (PTD)
-/** Peripheral PTE base address */
-#define PTE_BASE (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE ((GPIO_Type *)PTE_BASE)
-#define PTE_BASE_PTR (PTE)
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE ((GPIO_Type *)GPIOE_BASE)
/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
-
-/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register instance definitions */
-/* PTA */
-#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
-#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
-#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
-#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
-#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
-#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
-/* PTB */
-#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
-#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
-#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
-#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
-#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
-#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
-/* PTC */
-#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
-#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
-#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
-#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
-#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
-#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
-/* PTD */
-#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
-#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
-#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
-#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
-#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
-#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
-/* PTE */
-#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
-#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
-#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
-#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
-#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
-#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
+#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
/*!
* @}
@@ -4463,36 +3165,7 @@ typedef struct {
__IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
__IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
__IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type, *I2C_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register accessors */
-#define I2C_A1_REG(base) ((base)->A1)
-#define I2C_F_REG(base) ((base)->F)
-#define I2C_C1_REG(base) ((base)->C1)
-#define I2C_S_REG(base) ((base)->S)
-#define I2C_D_REG(base) ((base)->D)
-#define I2C_C2_REG(base) ((base)->C2)
-#define I2C_FLT_REG(base) ((base)->FLT)
-#define I2C_RA_REG(base) ((base)->RA)
-#define I2C_SMB_REG(base) ((base)->SMB)
-#define I2C_A2_REG(base) ((base)->A2)
-#define I2C_SLTH_REG(base) ((base)->SLTH)
-#define I2C_SLTL_REG(base) ((base)->SLTL)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
+} I2C_Type;
/* ----------------------------------------------------------------------------
-- I2C Register Masks
@@ -4503,190 +3176,159 @@ typedef struct {
* @{
*/
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD_WIDTH 7
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR_WIDTH 6
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT_WIDTH 2
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_DMAEN_WIDTH 1
-#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_WUEN_WIDTH 1
-#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_RSTA_WIDTH 1
-#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TXAK_WIDTH 1
-#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_TX_WIDTH 1
-#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_MST_WIDTH 1
-#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICIE_WIDTH 1
-#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-#define I2C_C1_IICEN_WIDTH 1
-#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_RXAK_WIDTH 1
-#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_IICIF_WIDTH 1
-#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_SRW_WIDTH 1
-#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_RAM_WIDTH 1
-#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_ARBL_WIDTH 1
-#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_BUSY_WIDTH 1
-#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_IAAS_WIDTH 1
-#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-#define I2C_S_TCF_WIDTH 1
-#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA_WIDTH 8
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD_WIDTH 3
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_RMEN_WIDTH 1
-#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_SBRC_WIDTH 1
-#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_HDRS_WIDTH 1
-#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_ADEXT_WIDTH 1
-#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-#define I2C_C2_GCAEN_WIDTH 1
-#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0xFu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT_WIDTH 4
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STARTF_MASK 0x10u
-#define I2C_FLT_STARTF_SHIFT 4
-#define I2C_FLT_STARTF_WIDTH 1
-#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
-#define I2C_FLT_SSIE_MASK 0x20u
-#define I2C_FLT_SSIE_SHIFT 5
-#define I2C_FLT_SSIE_WIDTH 1
-#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
-#define I2C_FLT_STOPF_MASK 0x40u
-#define I2C_FLT_STOPF_SHIFT 6
-#define I2C_FLT_STOPF_WIDTH 1
-#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
-#define I2C_FLT_SHEN_MASK 0x80u
-#define I2C_FLT_SHEN_SHIFT 7
-#define I2C_FLT_SHEN_WIDTH 1
-#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD_WIDTH 7
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2IE_WIDTH 1
-#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF2_WIDTH 1
-#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SHTF1_WIDTH 1
-#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_SLTF_WIDTH 1
-#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_TCKSEL_WIDTH 1
-#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_SIICAEN_WIDTH 1
-#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_ALERTEN_WIDTH 1
-#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-#define I2C_SMB_FACK_WIDTH 1
-#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD_WIDTH 7
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT_WIDTH 8
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT_WIDTH 8
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK (0xFEU)
+#define I2C_A1_AD_SHIFT (1U)
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK (0x3FU)
+#define I2C_F_ICR_SHIFT (0U)
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK (0xC0U)
+#define I2C_F_MULT_SHIFT (6U)
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK (0x1U)
+#define I2C_C1_DMAEN_SHIFT (0U)
+#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK (0x2U)
+#define I2C_C1_WUEN_SHIFT (1U)
+#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK (0x4U)
+#define I2C_C1_RSTA_SHIFT (2U)
+#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK (0x8U)
+#define I2C_C1_TXAK_SHIFT (3U)
+#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK (0x10U)
+#define I2C_C1_TX_SHIFT (4U)
+#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK (0x20U)
+#define I2C_C1_MST_SHIFT (5U)
+#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK (0x40U)
+#define I2C_C1_IICIE_SHIFT (6U)
+#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK (0x80U)
+#define I2C_C1_IICEN_SHIFT (7U)
+#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK (0x1U)
+#define I2C_S_RXAK_SHIFT (0U)
+#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK (0x2U)
+#define I2C_S_IICIF_SHIFT (1U)
+#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK (0x4U)
+#define I2C_S_SRW_SHIFT (2U)
+#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK (0x8U)
+#define I2C_S_RAM_SHIFT (3U)
+#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK (0x10U)
+#define I2C_S_ARBL_SHIFT (4U)
+#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK (0x20U)
+#define I2C_S_BUSY_SHIFT (5U)
+#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK (0x40U)
+#define I2C_S_IAAS_SHIFT (6U)
+#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK (0x80U)
+#define I2C_S_TCF_SHIFT (7U)
+#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK (0xFFU)
+#define I2C_D_DATA_SHIFT (0U)
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK (0x7U)
+#define I2C_C2_AD_SHIFT (0U)
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK (0x8U)
+#define I2C_C2_RMEN_SHIFT (3U)
+#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK (0x10U)
+#define I2C_C2_SBRC_SHIFT (4U)
+#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK (0x20U)
+#define I2C_C2_HDRS_SHIFT (5U)
+#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK (0x40U)
+#define I2C_C2_ADEXT_SHIFT (6U)
+#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK (0x80U)
+#define I2C_C2_GCAEN_SHIFT (7U)
+#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter register */
+#define I2C_FLT_FLT_MASK (0xFU)
+#define I2C_FLT_FLT_SHIFT (0U)
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK (0x10U)
+#define I2C_FLT_STARTF_SHIFT (4U)
+#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK (0x20U)
+#define I2C_FLT_SSIE_SHIFT (5U)
+#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK (0x40U)
+#define I2C_FLT_STOPF_SHIFT (6U)
+#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK (0x80U)
+#define I2C_FLT_SHEN_SHIFT (7U)
+#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK (0xFEU)
+#define I2C_RA_RAD_SHIFT (1U)
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT (0U)
+#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK (0x2U)
+#define I2C_SMB_SHTF2_SHIFT (1U)
+#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK (0x4U)
+#define I2C_SMB_SHTF1_SHIFT (2U)
+#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK (0x8U)
+#define I2C_SMB_SLTF_SHIFT (3U)
+#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT (4U)
+#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT (5U)
+#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT (6U)
+#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK (0x80U)
+#define I2C_SMB_FACK_SHIFT (7U)
+#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK (0xFEU)
+#define I2C_A2_SAD_SHIFT (1U)
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT (0U)
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT (0U)
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
/*!
* @}
@@ -4698,12 +3340,10 @@ typedef struct {
#define I2C0_BASE (0x40066000u)
/** Peripheral I2C0 base pointer */
#define I2C0 ((I2C_Type *)I2C0_BASE)
-#define I2C0_BASE_PTR (I2C0)
/** Peripheral I2C1 base address */
#define I2C1_BASE (0x40067000u)
/** Peripheral I2C1 base pointer */
#define I2C1 ((I2C_Type *)I2C1_BASE)
-#define I2C1_BASE_PTR (I2C1)
/** Array initializer of I2C peripheral base addresses */
#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
/** Array initializer of I2C peripheral base pointers */
@@ -4711,49 +3351,6 @@ typedef struct {
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register instance definitions */
-/* I2C0 */
-#define I2C0_A1 I2C_A1_REG(I2C0)
-#define I2C0_F I2C_F_REG(I2C0)
-#define I2C0_C1 I2C_C1_REG(I2C0)
-#define I2C0_S I2C_S_REG(I2C0)
-#define I2C0_D I2C_D_REG(I2C0)
-#define I2C0_C2 I2C_C2_REG(I2C0)
-#define I2C0_FLT I2C_FLT_REG(I2C0)
-#define I2C0_RA I2C_RA_REG(I2C0)
-#define I2C0_SMB I2C_SMB_REG(I2C0)
-#define I2C0_A2 I2C_A2_REG(I2C0)
-#define I2C0_SLTH I2C_SLTH_REG(I2C0)
-#define I2C0_SLTL I2C_SLTL_REG(I2C0)
-/* I2C1 */
-#define I2C1_A1 I2C_A1_REG(I2C1)
-#define I2C1_F I2C_F_REG(I2C1)
-#define I2C1_C1 I2C_C1_REG(I2C1)
-#define I2C1_S I2C_S_REG(I2C1)
-#define I2C1_D I2C_D_REG(I2C1)
-#define I2C1_C2 I2C_C2_REG(I2C1)
-#define I2C1_FLT I2C_FLT_REG(I2C1)
-#define I2C1_RA I2C_RA_REG(I2C1)
-#define I2C1_SMB I2C_SMB_REG(I2C1)
-#define I2C1_A2 I2C_A2_REG(I2C1)
-#define I2C1_SLTH I2C_SLTH_REG(I2C1)
-#define I2C1_SLTL I2C_SLTL_REG(I2C1)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
@@ -4798,48 +3395,7 @@ typedef struct {
uint8_t RESERVED_7[28];
__IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
__IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
-} I2S_Type, *I2S_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register accessors */
-#define I2S_TCSR_REG(base) ((base)->TCSR)
-#define I2S_TCR1_REG(base) ((base)->TCR1)
-#define I2S_TCR2_REG(base) ((base)->TCR2)
-#define I2S_TCR3_REG(base) ((base)->TCR3)
-#define I2S_TCR4_REG(base) ((base)->TCR4)
-#define I2S_TCR5_REG(base) ((base)->TCR5)
-#define I2S_TDR_REG(base,index) ((base)->TDR[index])
-#define I2S_TDR_COUNT 1
-#define I2S_TFR_REG(base,index) ((base)->TFR[index])
-#define I2S_TFR_COUNT 1
-#define I2S_TMR_REG(base) ((base)->TMR)
-#define I2S_RCSR_REG(base) ((base)->RCSR)
-#define I2S_RCR1_REG(base) ((base)->RCR1)
-#define I2S_RCR2_REG(base) ((base)->RCR2)
-#define I2S_RCR3_REG(base) ((base)->RCR3)
-#define I2S_RCR4_REG(base) ((base)->RCR4)
-#define I2S_RCR5_REG(base) ((base)->RCR5)
-#define I2S_RDR_REG(base,index) ((base)->RDR[index])
-#define I2S_RDR_COUNT 1
-#define I2S_RFR_REG(base,index) ((base)->RFR[index])
-#define I2S_RFR_COUNT 1
-#define I2S_RMR_REG(base) ((base)->RMR)
-#define I2S_MCR_REG(base) ((base)->MCR)
-#define I2S_MDR_REG(base) ((base)->MDR)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
+} I2S_Type;
/* ----------------------------------------------------------------------------
-- I2S Register Masks
@@ -4850,398 +3406,337 @@ typedef struct {
* @{
*/
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK 0x1u
-#define I2S_TCSR_FRDE_SHIFT 0
-#define I2S_TCSR_FRDE_WIDTH 1
-#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
-#define I2S_TCSR_FWDE_MASK 0x2u
-#define I2S_TCSR_FWDE_SHIFT 1
-#define I2S_TCSR_FWDE_WIDTH 1
-#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
-#define I2S_TCSR_FRIE_MASK 0x100u
-#define I2S_TCSR_FRIE_SHIFT 8
-#define I2S_TCSR_FRIE_WIDTH 1
-#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
-#define I2S_TCSR_FWIE_MASK 0x200u
-#define I2S_TCSR_FWIE_SHIFT 9
-#define I2S_TCSR_FWIE_WIDTH 1
-#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
-#define I2S_TCSR_FEIE_MASK 0x400u
-#define I2S_TCSR_FEIE_SHIFT 10
-#define I2S_TCSR_FEIE_WIDTH 1
-#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
-#define I2S_TCSR_SEIE_MASK 0x800u
-#define I2S_TCSR_SEIE_SHIFT 11
-#define I2S_TCSR_SEIE_WIDTH 1
-#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
-#define I2S_TCSR_WSIE_MASK 0x1000u
-#define I2S_TCSR_WSIE_SHIFT 12
-#define I2S_TCSR_WSIE_WIDTH 1
-#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
-#define I2S_TCSR_FRF_MASK 0x10000u
-#define I2S_TCSR_FRF_SHIFT 16
-#define I2S_TCSR_FRF_WIDTH 1
-#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
-#define I2S_TCSR_FWF_MASK 0x20000u
-#define I2S_TCSR_FWF_SHIFT 17
-#define I2S_TCSR_FWF_WIDTH 1
-#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
-#define I2S_TCSR_FEF_MASK 0x40000u
-#define I2S_TCSR_FEF_SHIFT 18
-#define I2S_TCSR_FEF_WIDTH 1
-#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
-#define I2S_TCSR_SEF_MASK 0x80000u
-#define I2S_TCSR_SEF_SHIFT 19
-#define I2S_TCSR_SEF_WIDTH 1
-#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
-#define I2S_TCSR_WSF_MASK 0x100000u
-#define I2S_TCSR_WSF_SHIFT 20
-#define I2S_TCSR_WSF_WIDTH 1
-#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
-#define I2S_TCSR_SR_MASK 0x1000000u
-#define I2S_TCSR_SR_SHIFT 24
-#define I2S_TCSR_SR_WIDTH 1
-#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
-#define I2S_TCSR_FR_MASK 0x2000000u
-#define I2S_TCSR_FR_SHIFT 25
-#define I2S_TCSR_FR_WIDTH 1
-#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
-#define I2S_TCSR_BCE_MASK 0x10000000u
-#define I2S_TCSR_BCE_SHIFT 28
-#define I2S_TCSR_BCE_WIDTH 1
-#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
-#define I2S_TCSR_DBGE_MASK 0x20000000u
-#define I2S_TCSR_DBGE_SHIFT 29
-#define I2S_TCSR_DBGE_WIDTH 1
-#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
-#define I2S_TCSR_STOPE_MASK 0x40000000u
-#define I2S_TCSR_STOPE_SHIFT 30
-#define I2S_TCSR_STOPE_WIDTH 1
-#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
-#define I2S_TCSR_TE_MASK 0x80000000u
-#define I2S_TCSR_TE_SHIFT 31
-#define I2S_TCSR_TE_WIDTH 1
-#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK 0x7u
-#define I2S_TCR1_TFW_SHIFT 0
-#define I2S_TCR1_TFW_WIDTH 3
-#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK 0xFFu
-#define I2S_TCR2_DIV_SHIFT 0
-#define I2S_TCR2_DIV_WIDTH 8
-#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK 0x1000000u
-#define I2S_TCR2_BCD_SHIFT 24
-#define I2S_TCR2_BCD_WIDTH 1
-#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
-#define I2S_TCR2_BCP_MASK 0x2000000u
-#define I2S_TCR2_BCP_SHIFT 25
-#define I2S_TCR2_BCP_WIDTH 1
-#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
-#define I2S_TCR2_MSEL_MASK 0xC000000u
-#define I2S_TCR2_MSEL_SHIFT 26
-#define I2S_TCR2_MSEL_WIDTH 2
-#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK 0x10000000u
-#define I2S_TCR2_BCI_SHIFT 28
-#define I2S_TCR2_BCI_WIDTH 1
-#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
-#define I2S_TCR2_BCS_MASK 0x20000000u
-#define I2S_TCR2_BCS_SHIFT 29
-#define I2S_TCR2_BCS_WIDTH 1
-#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
-#define I2S_TCR2_SYNC_MASK 0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT 30
-#define I2S_TCR2_SYNC_WIDTH 2
-#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK 0xFu
-#define I2S_TCR3_WDFL_SHIFT 0
-#define I2S_TCR3_WDFL_WIDTH 4
-#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK 0x10000u
-#define I2S_TCR3_TCE_SHIFT 16
-#define I2S_TCR3_TCE_WIDTH 1
-#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK 0x1u
-#define I2S_TCR4_FSD_SHIFT 0
-#define I2S_TCR4_FSD_WIDTH 1
-#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
-#define I2S_TCR4_FSP_MASK 0x2u
-#define I2S_TCR4_FSP_SHIFT 1
-#define I2S_TCR4_FSP_WIDTH 1
-#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
-#define I2S_TCR4_ONDEM_MASK 0x4u
-#define I2S_TCR4_ONDEM_SHIFT 2
-#define I2S_TCR4_ONDEM_WIDTH 1
-#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_ONDEM_SHIFT))&I2S_TCR4_ONDEM_MASK)
-#define I2S_TCR4_FSE_MASK 0x8u
-#define I2S_TCR4_FSE_SHIFT 3
-#define I2S_TCR4_FSE_WIDTH 1
-#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
-#define I2S_TCR4_MF_MASK 0x10u
-#define I2S_TCR4_MF_SHIFT 4
-#define I2S_TCR4_MF_WIDTH 1
-#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
-#define I2S_TCR4_SYWD_MASK 0x1F00u
-#define I2S_TCR4_SYWD_SHIFT 8
-#define I2S_TCR4_SYWD_WIDTH 5
-#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK 0xF0000u
-#define I2S_TCR4_FRSZ_SHIFT 16
-#define I2S_TCR4_FRSZ_WIDTH 4
-#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-#define I2S_TCR4_FPACK_MASK 0x3000000u
-#define I2S_TCR4_FPACK_SHIFT 24
-#define I2S_TCR4_FPACK_WIDTH 2
-#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
-#define I2S_TCR4_FCONT_MASK 0x10000000u
-#define I2S_TCR4_FCONT_SHIFT 28
-#define I2S_TCR4_FCONT_WIDTH 1
-#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FCONT_SHIFT))&I2S_TCR4_FCONT_MASK)
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK 0x1F00u
-#define I2S_TCR5_FBT_SHIFT 8
-#define I2S_TCR5_FBT_WIDTH 5
-#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK 0x1F0000u
-#define I2S_TCR5_W0W_SHIFT 16
-#define I2S_TCR5_W0W_WIDTH 5
-#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK 0x1F000000u
-#define I2S_TCR5_WNW_SHIFT 24
-#define I2S_TCR5_WNW_WIDTH 5
-#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT 0
-#define I2S_TDR_TDR_WIDTH 32
-#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK 0xFu
-#define I2S_TFR_RFP_SHIFT 0
-#define I2S_TFR_RFP_WIDTH 4
-#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK 0xF0000u
-#define I2S_TFR_WFP_SHIFT 16
-#define I2S_TFR_WFP_WIDTH 4
-#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK 0xFFFFu
-#define I2S_TMR_TWM_SHIFT 0
-#define I2S_TMR_TWM_WIDTH 16
-#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK 0x1u
-#define I2S_RCSR_FRDE_SHIFT 0
-#define I2S_RCSR_FRDE_WIDTH 1
-#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
-#define I2S_RCSR_FWDE_MASK 0x2u
-#define I2S_RCSR_FWDE_SHIFT 1
-#define I2S_RCSR_FWDE_WIDTH 1
-#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
-#define I2S_RCSR_FRIE_MASK 0x100u
-#define I2S_RCSR_FRIE_SHIFT 8
-#define I2S_RCSR_FRIE_WIDTH 1
-#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
-#define I2S_RCSR_FWIE_MASK 0x200u
-#define I2S_RCSR_FWIE_SHIFT 9
-#define I2S_RCSR_FWIE_WIDTH 1
-#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
-#define I2S_RCSR_FEIE_MASK 0x400u
-#define I2S_RCSR_FEIE_SHIFT 10
-#define I2S_RCSR_FEIE_WIDTH 1
-#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
-#define I2S_RCSR_SEIE_MASK 0x800u
-#define I2S_RCSR_SEIE_SHIFT 11
-#define I2S_RCSR_SEIE_WIDTH 1
-#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
-#define I2S_RCSR_WSIE_MASK 0x1000u
-#define I2S_RCSR_WSIE_SHIFT 12
-#define I2S_RCSR_WSIE_WIDTH 1
-#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
-#define I2S_RCSR_FRF_MASK 0x10000u
-#define I2S_RCSR_FRF_SHIFT 16
-#define I2S_RCSR_FRF_WIDTH 1
-#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
-#define I2S_RCSR_FWF_MASK 0x20000u
-#define I2S_RCSR_FWF_SHIFT 17
-#define I2S_RCSR_FWF_WIDTH 1
-#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
-#define I2S_RCSR_FEF_MASK 0x40000u
-#define I2S_RCSR_FEF_SHIFT 18
-#define I2S_RCSR_FEF_WIDTH 1
-#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
-#define I2S_RCSR_SEF_MASK 0x80000u
-#define I2S_RCSR_SEF_SHIFT 19
-#define I2S_RCSR_SEF_WIDTH 1
-#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
-#define I2S_RCSR_WSF_MASK 0x100000u
-#define I2S_RCSR_WSF_SHIFT 20
-#define I2S_RCSR_WSF_WIDTH 1
-#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
-#define I2S_RCSR_SR_MASK 0x1000000u
-#define I2S_RCSR_SR_SHIFT 24
-#define I2S_RCSR_SR_WIDTH 1
-#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
-#define I2S_RCSR_FR_MASK 0x2000000u
-#define I2S_RCSR_FR_SHIFT 25
-#define I2S_RCSR_FR_WIDTH 1
-#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
-#define I2S_RCSR_BCE_MASK 0x10000000u
-#define I2S_RCSR_BCE_SHIFT 28
-#define I2S_RCSR_BCE_WIDTH 1
-#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
-#define I2S_RCSR_DBGE_MASK 0x20000000u
-#define I2S_RCSR_DBGE_SHIFT 29
-#define I2S_RCSR_DBGE_WIDTH 1
-#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
-#define I2S_RCSR_STOPE_MASK 0x40000000u
-#define I2S_RCSR_STOPE_SHIFT 30
-#define I2S_RCSR_STOPE_WIDTH 1
-#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
-#define I2S_RCSR_RE_MASK 0x80000000u
-#define I2S_RCSR_RE_SHIFT 31
-#define I2S_RCSR_RE_WIDTH 1
-#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK 0x7u
-#define I2S_RCR1_RFW_SHIFT 0
-#define I2S_RCR1_RFW_WIDTH 3
-#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK 0xFFu
-#define I2S_RCR2_DIV_SHIFT 0
-#define I2S_RCR2_DIV_WIDTH 8
-#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK 0x1000000u
-#define I2S_RCR2_BCD_SHIFT 24
-#define I2S_RCR2_BCD_WIDTH 1
-#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
-#define I2S_RCR2_BCP_MASK 0x2000000u
-#define I2S_RCR2_BCP_SHIFT 25
-#define I2S_RCR2_BCP_WIDTH 1
-#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
-#define I2S_RCR2_MSEL_MASK 0xC000000u
-#define I2S_RCR2_MSEL_SHIFT 26
-#define I2S_RCR2_MSEL_WIDTH 2
-#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK 0x10000000u
-#define I2S_RCR2_BCI_SHIFT 28
-#define I2S_RCR2_BCI_WIDTH 1
-#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
-#define I2S_RCR2_BCS_MASK 0x20000000u
-#define I2S_RCR2_BCS_SHIFT 29
-#define I2S_RCR2_BCS_WIDTH 1
-#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
-#define I2S_RCR2_SYNC_MASK 0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT 30
-#define I2S_RCR2_SYNC_WIDTH 2
-#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK 0xFu
-#define I2S_RCR3_WDFL_SHIFT 0
-#define I2S_RCR3_WDFL_WIDTH 4
-#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK 0x10000u
-#define I2S_RCR3_RCE_SHIFT 16
-#define I2S_RCR3_RCE_WIDTH 1
-#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK 0x1u
-#define I2S_RCR4_FSD_SHIFT 0
-#define I2S_RCR4_FSD_WIDTH 1
-#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
-#define I2S_RCR4_FSP_MASK 0x2u
-#define I2S_RCR4_FSP_SHIFT 1
-#define I2S_RCR4_FSP_WIDTH 1
-#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
-#define I2S_RCR4_ONDEM_MASK 0x4u
-#define I2S_RCR4_ONDEM_SHIFT 2
-#define I2S_RCR4_ONDEM_WIDTH 1
-#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_ONDEM_SHIFT))&I2S_RCR4_ONDEM_MASK)
-#define I2S_RCR4_FSE_MASK 0x8u
-#define I2S_RCR4_FSE_SHIFT 3
-#define I2S_RCR4_FSE_WIDTH 1
-#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
-#define I2S_RCR4_MF_MASK 0x10u
-#define I2S_RCR4_MF_SHIFT 4
-#define I2S_RCR4_MF_WIDTH 1
-#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
-#define I2S_RCR4_SYWD_MASK 0x1F00u
-#define I2S_RCR4_SYWD_SHIFT 8
-#define I2S_RCR4_SYWD_WIDTH 5
-#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK 0xF0000u
-#define I2S_RCR4_FRSZ_SHIFT 16
-#define I2S_RCR4_FRSZ_WIDTH 4
-#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-#define I2S_RCR4_FPACK_MASK 0x3000000u
-#define I2S_RCR4_FPACK_SHIFT 24
-#define I2S_RCR4_FPACK_WIDTH 2
-#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
-#define I2S_RCR4_FCONT_MASK 0x10000000u
-#define I2S_RCR4_FCONT_SHIFT 28
-#define I2S_RCR4_FCONT_WIDTH 1
-#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FCONT_SHIFT))&I2S_RCR4_FCONT_MASK)
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK 0x1F00u
-#define I2S_RCR5_FBT_SHIFT 8
-#define I2S_RCR5_FBT_WIDTH 5
-#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK 0x1F0000u
-#define I2S_RCR5_W0W_SHIFT 16
-#define I2S_RCR5_W0W_WIDTH 5
-#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK 0x1F000000u
-#define I2S_RCR5_WNW_SHIFT 24
-#define I2S_RCR5_WNW_WIDTH 5
-#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT 0
-#define I2S_RDR_RDR_WIDTH 32
-#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK 0xFu
-#define I2S_RFR_RFP_SHIFT 0
-#define I2S_RFR_RFP_WIDTH 4
-#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK 0xF0000u
-#define I2S_RFR_WFP_SHIFT 16
-#define I2S_RFR_WFP_WIDTH 4
-#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK 0xFFFFu
-#define I2S_RMR_RWM_SHIFT 0
-#define I2S_RMR_RWM_WIDTH 16
-#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK 0x3000000u
-#define I2S_MCR_MICS_SHIFT 24
-#define I2S_MCR_MICS_WIDTH 2
-#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK 0x40000000u
-#define I2S_MCR_MOE_SHIFT 30
-#define I2S_MCR_MOE_WIDTH 1
-#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
-#define I2S_MCR_DUF_MASK 0x80000000u
-#define I2S_MCR_DUF_SHIFT 31
-#define I2S_MCR_DUF_WIDTH 1
-#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK 0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT 0
-#define I2S_MDR_DIVIDE_WIDTH 12
-#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK 0xFF000u
-#define I2S_MDR_FRACT_SHIFT 12
-#define I2S_MDR_FRACT_WIDTH 8
-#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FRDE_MASK (0x1U)
+#define I2S_TCSR_FRDE_SHIFT (0U)
+#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK (0x2U)
+#define I2S_TCSR_FWDE_SHIFT (1U)
+#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK (0x100U)
+#define I2S_TCSR_FRIE_SHIFT (8U)
+#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK (0x200U)
+#define I2S_TCSR_FWIE_SHIFT (9U)
+#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK (0x400U)
+#define I2S_TCSR_FEIE_SHIFT (10U)
+#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK (0x800U)
+#define I2S_TCSR_SEIE_SHIFT (11U)
+#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT (12U)
+#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK (0x10000U)
+#define I2S_TCSR_FRF_SHIFT (16U)
+#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK (0x20000U)
+#define I2S_TCSR_FWF_SHIFT (17U)
+#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK (0x40000U)
+#define I2S_TCSR_FEF_SHIFT (18U)
+#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK (0x80000U)
+#define I2S_TCSR_SEF_SHIFT (19U)
+#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK (0x100000U)
+#define I2S_TCSR_WSF_SHIFT (20U)
+#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK (0x1000000U)
+#define I2S_TCSR_SR_SHIFT (24U)
+#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK (0x2000000U)
+#define I2S_TCSR_FR_SHIFT (25U)
+#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT (28U)
+#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT (29U)
+#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT (30U)
+#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK (0x80000000U)
+#define I2S_TCSR_TE_SHIFT (31U)
+#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+#define I2S_TCR1_TFW_MASK (0x7U)
+#define I2S_TCR1_TFW_SHIFT (0U)
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK (0xFFU)
+#define I2S_TCR2_DIV_SHIFT (0U)
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT (24U)
+#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT (25U)
+#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT (26U)
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT (28U)
+#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT (29U)
+#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT (30U)
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK (0xFU)
+#define I2S_TCR3_WDFL_SHIFT (0U)
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK (0x10000U)
+#define I2S_TCR3_TCE_SHIFT (16U)
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK (0x1U)
+#define I2S_TCR4_FSD_SHIFT (0U)
+#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK (0x2U)
+#define I2S_TCR4_FSP_SHIFT (1U)
+#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_ONDEM_MASK (0x4U)
+#define I2S_TCR4_ONDEM_SHIFT (2U)
+#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_FSE_MASK (0x8U)
+#define I2S_TCR4_FSE_SHIFT (3U)
+#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK (0x10U)
+#define I2S_TCR4_MF_SHIFT (4U)
+#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT (8U)
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK (0xF0000U)
+#define I2S_TCR4_FRSZ_SHIFT (16U)
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK (0x3000000U)
+#define I2S_TCR4_FPACK_SHIFT (24U)
+#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCONT_MASK (0x10000000U)
+#define I2S_TCR4_FCONT_SHIFT (28U)
+#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT (8U)
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT (16U)
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT (24U)
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT (0U)
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT (1U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+#define I2S_TFR_RFP_MASK (0xFU)
+#define I2S_TFR_RFP_SHIFT (0U)
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK (0xF0000U)
+#define I2S_TFR_WFP_SHIFT (16U)
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT (1U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK (0xFFFFU)
+#define I2S_TMR_TWM_SHIFT (0U)
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FRDE_MASK (0x1U)
+#define I2S_RCSR_FRDE_SHIFT (0U)
+#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK (0x2U)
+#define I2S_RCSR_FWDE_SHIFT (1U)
+#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK (0x100U)
+#define I2S_RCSR_FRIE_SHIFT (8U)
+#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK (0x200U)
+#define I2S_RCSR_FWIE_SHIFT (9U)
+#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK (0x400U)
+#define I2S_RCSR_FEIE_SHIFT (10U)
+#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK (0x800U)
+#define I2S_RCSR_SEIE_SHIFT (11U)
+#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT (12U)
+#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK (0x10000U)
+#define I2S_RCSR_FRF_SHIFT (16U)
+#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK (0x20000U)
+#define I2S_RCSR_FWF_SHIFT (17U)
+#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK (0x40000U)
+#define I2S_RCSR_FEF_SHIFT (18U)
+#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK (0x80000U)
+#define I2S_RCSR_SEF_SHIFT (19U)
+#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK (0x100000U)
+#define I2S_RCSR_WSF_SHIFT (20U)
+#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK (0x1000000U)
+#define I2S_RCSR_SR_SHIFT (24U)
+#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK (0x2000000U)
+#define I2S_RCSR_FR_SHIFT (25U)
+#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT (28U)
+#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT (29U)
+#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT (30U)
+#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK (0x80000000U)
+#define I2S_RCSR_RE_SHIFT (31U)
+#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+#define I2S_RCR1_RFW_MASK (0x7U)
+#define I2S_RCR1_RFW_SHIFT (0U)
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK (0xFFU)
+#define I2S_RCR2_DIV_SHIFT (0U)
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT (24U)
+#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT (25U)
+#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT (26U)
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT (28U)
+#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT (29U)
+#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT (30U)
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK (0xFU)
+#define I2S_RCR3_WDFL_SHIFT (0U)
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK (0x10000U)
+#define I2S_RCR3_RCE_SHIFT (16U)
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK (0x1U)
+#define I2S_RCR4_FSD_SHIFT (0U)
+#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK (0x2U)
+#define I2S_RCR4_FSP_SHIFT (1U)
+#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_ONDEM_MASK (0x4U)
+#define I2S_RCR4_ONDEM_SHIFT (2U)
+#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_FSE_MASK (0x8U)
+#define I2S_RCR4_FSE_SHIFT (3U)
+#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK (0x10U)
+#define I2S_RCR4_MF_SHIFT (4U)
+#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT (8U)
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK (0xF0000U)
+#define I2S_RCR4_FRSZ_SHIFT (16U)
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK (0x3000000U)
+#define I2S_RCR4_FPACK_SHIFT (24U)
+#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCONT_MASK (0x10000000U)
+#define I2S_RCR4_FCONT_SHIFT (28U)
+#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT (8U)
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT (16U)
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT (24U)
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT (0U)
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT (1U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+#define I2S_RFR_RFP_MASK (0xFU)
+#define I2S_RFR_RFP_SHIFT (0U)
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK (0xF0000U)
+#define I2S_RFR_WFP_SHIFT (16U)
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT (1U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK (0xFFFFU)
+#define I2S_RMR_RWM_SHIFT (0U)
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK (0x3000000U)
+#define I2S_MCR_MICS_SHIFT (24U)
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK (0x40000000U)
+#define I2S_MCR_MOE_SHIFT (30U)
+#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK (0x80000000U)
+#define I2S_MCR_DUF_SHIFT (31U)
+#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT (0U)
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT (12U)
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
/*!
* @}
@@ -5253,7 +3748,6 @@ typedef struct {
#define I2S0_BASE (0x4002F000u)
/** Peripheral I2S0 base pointer */
#define I2S0 ((I2S_Type *)I2S0_BASE)
-#define I2S0_BASE_PTR (I2S0)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { I2S0_BASE }
/** Array initializer of I2S peripheral base pointers */
@@ -5262,50 +3756,6 @@ typedef struct {
#define I2S_RX_IRQS { I2S0_Rx_IRQn }
#define I2S_TX_IRQS { I2S0_Tx_IRQn }
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register instance definitions */
-/* I2S0 */
-#define I2S0_TCSR I2S_TCSR_REG(I2S0)
-#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
-#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
-#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
-#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
-#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
-#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
-#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
-#define I2S0_TMR I2S_TMR_REG(I2S0)
-#define I2S0_RCSR I2S_RCSR_REG(I2S0)
-#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
-#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
-#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
-#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
-#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
-#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
-#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
-#define I2S0_RMR I2S_RMR_REG(I2S0)
-#define I2S0_MCR I2S_MCR_REG(I2S0)
-#define I2S0_MDR I2S_MDR_REG(I2S0)
-
-/* I2S - Register array accessors */
-#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
-#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
-#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
-#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
@@ -5332,34 +3782,7 @@ typedef struct {
__I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
__IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
__IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
-} LLWU_Type, *LLWU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register accessors */
-#define LLWU_PE1_REG(base) ((base)->PE1)
-#define LLWU_PE2_REG(base) ((base)->PE2)
-#define LLWU_PE3_REG(base) ((base)->PE3)
-#define LLWU_PE4_REG(base) ((base)->PE4)
-#define LLWU_ME_REG(base) ((base)->ME)
-#define LLWU_F1_REG(base) ((base)->F1)
-#define LLWU_F2_REG(base) ((base)->F2)
-#define LLWU_F3_REG(base) ((base)->F3)
-#define LLWU_FILT1_REG(base) ((base)->FILT1)
-#define LLWU_FILT2_REG(base) ((base)->FILT2)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
+} LLWU_Type;
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
@@ -5370,232 +3793,188 @@ typedef struct {
* @{
*/
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0_WIDTH 2
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1_WIDTH 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2_WIDTH 2
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3_WIDTH 2
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4_WIDTH 2
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5_WIDTH 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6_WIDTH 2
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7_WIDTH 2
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8_WIDTH 2
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9_WIDTH 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10_WIDTH 2
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11_WIDTH 2
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12_WIDTH 2
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13_WIDTH 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14_WIDTH 2
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15_WIDTH 2
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME0_WIDTH 1
-#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME1_WIDTH 1
-#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME2_WIDTH 1
-#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME3_WIDTH 1
-#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME4_WIDTH 1
-#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME5_WIDTH 1
-#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME6_WIDTH 1
-#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-#define LLWU_ME_WUME7_WIDTH 1
-#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF0_WIDTH 1
-#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF1_WIDTH 1
-#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF2_WIDTH 1
-#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF3_WIDTH 1
-#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF4_WIDTH 1
-#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF5_WIDTH 1
-#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF6_WIDTH 1
-#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-#define LLWU_F1_WUF7_WIDTH 1
-#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF8_WIDTH 1
-#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF9_WIDTH 1
-#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF10_WIDTH 1
-#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF11_WIDTH 1
-#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF12_WIDTH 1
-#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF13_WIDTH 1
-#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF14_WIDTH 1
-#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-#define LLWU_F2_WUF15_WIDTH 1
-#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF0_WIDTH 1
-#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF1_WIDTH 1
-#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF2_WIDTH 1
-#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF3_WIDTH 1
-#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF4_WIDTH 1
-#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF5_WIDTH 1
-#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF6_WIDTH 1
-#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-#define LLWU_F3_MWUF7_WIDTH 1
-#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL_WIDTH 4
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE_WIDTH 2
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-#define LLWU_FILT1_FILTF_WIDTH 1
-#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL_WIDTH 4
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE_WIDTH 2
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-#define LLWU_FILT2_FILTF_WIDTH 1
-#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT (0U)
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT (2U)
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT (4U)
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT (6U)
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT (0U)
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT (2U)
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT (4U)
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT (6U)
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT (0U)
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT (2U)
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT (4U)
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT (6U)
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT (0U)
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT (2U)
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT (4U)
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT (6U)
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK (0x1U)
+#define LLWU_ME_WUME0_SHIFT (0U)
+#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK (0x2U)
+#define LLWU_ME_WUME1_SHIFT (1U)
+#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK (0x4U)
+#define LLWU_ME_WUME2_SHIFT (2U)
+#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK (0x8U)
+#define LLWU_ME_WUME3_SHIFT (3U)
+#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK (0x10U)
+#define LLWU_ME_WUME4_SHIFT (4U)
+#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK (0x20U)
+#define LLWU_ME_WUME5_SHIFT (5U)
+#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK (0x40U)
+#define LLWU_ME_WUME6_SHIFT (6U)
+#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK (0x80U)
+#define LLWU_ME_WUME7_SHIFT (7U)
+#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name F1 - LLWU Flag 1 register */
+#define LLWU_F1_WUF0_MASK (0x1U)
+#define LLWU_F1_WUF0_SHIFT (0U)
+#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK (0x2U)
+#define LLWU_F1_WUF1_SHIFT (1U)
+#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK (0x4U)
+#define LLWU_F1_WUF2_SHIFT (2U)
+#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK (0x8U)
+#define LLWU_F1_WUF3_SHIFT (3U)
+#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK (0x10U)
+#define LLWU_F1_WUF4_SHIFT (4U)
+#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK (0x20U)
+#define LLWU_F1_WUF5_SHIFT (5U)
+#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK (0x40U)
+#define LLWU_F1_WUF6_SHIFT (6U)
+#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK (0x80U)
+#define LLWU_F1_WUF7_SHIFT (7U)
+#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+
+/*! @name F2 - LLWU Flag 2 register */
+#define LLWU_F2_WUF8_MASK (0x1U)
+#define LLWU_F2_WUF8_SHIFT (0U)
+#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK (0x2U)
+#define LLWU_F2_WUF9_SHIFT (1U)
+#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK (0x4U)
+#define LLWU_F2_WUF10_SHIFT (2U)
+#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK (0x8U)
+#define LLWU_F2_WUF11_SHIFT (3U)
+#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK (0x10U)
+#define LLWU_F2_WUF12_SHIFT (4U)
+#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK (0x20U)
+#define LLWU_F2_WUF13_SHIFT (5U)
+#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK (0x40U)
+#define LLWU_F2_WUF14_SHIFT (6U)
+#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK (0x80U)
+#define LLWU_F2_WUF15_SHIFT (7U)
+#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+
+/*! @name F3 - LLWU Flag 3 register */
+#define LLWU_F3_MWUF0_MASK (0x1U)
+#define LLWU_F3_MWUF0_SHIFT (0U)
+#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK (0x2U)
+#define LLWU_F3_MWUF1_SHIFT (1U)
+#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK (0x4U)
+#define LLWU_F3_MWUF2_SHIFT (2U)
+#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK (0x8U)
+#define LLWU_F3_MWUF3_SHIFT (3U)
+#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK (0x10U)
+#define LLWU_F3_MWUF4_SHIFT (4U)
+#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK (0x20U)
+#define LLWU_F3_MWUF5_SHIFT (5U)
+#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK (0x40U)
+#define LLWU_F3_MWUF6_SHIFT (6U)
+#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK (0x80U)
+#define LLWU_F3_MWUF7_SHIFT (7U)
+#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT (0U)
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT (5U)
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT (7U)
+#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT (0U)
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT (5U)
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT (7U)
+#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
/*!
* @}
@@ -5607,7 +3986,6 @@ typedef struct {
#define LLWU_BASE (0x4007C000u)
/** Peripheral LLWU base pointer */
#define LLWU ((LLWU_Type *)LLWU_BASE)
-#define LLWU_BASE_PTR (LLWU)
/** Array initializer of LLWU peripheral base addresses */
#define LLWU_BASE_ADDRS { LLWU_BASE }
/** Array initializer of LLWU peripheral base pointers */
@@ -5615,34 +3993,6 @@ typedef struct {
/** Interrupt vectors for the LLWU peripheral type */
#define LLWU_IRQS { LLWU_IRQn }
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register instance definitions */
-/* LLWU */
-#define LLWU_PE1 LLWU_PE1_REG(LLWU)
-#define LLWU_PE2 LLWU_PE2_REG(LLWU)
-#define LLWU_PE3 LLWU_PE3_REG(LLWU)
-#define LLWU_PE4 LLWU_PE4_REG(LLWU)
-#define LLWU_ME LLWU_ME_REG(LLWU)
-#define LLWU_F1 LLWU_F1_REG(LLWU)
-#define LLWU_F2 LLWU_F2_REG(LLWU)
-#define LLWU_F3 LLWU_F3_REG(LLWU)
-#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
-#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
@@ -5663,28 +4013,7 @@ typedef struct {
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type, *LPTMR_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register accessors */
-#define LPTMR_CSR_REG(base) ((base)->CSR)
-#define LPTMR_PSR_REG(base) ((base)->PSR)
-#define LPTMR_CMR_REG(base) ((base)->CMR)
-#define LPTMR_CNR_REG(base) ((base)->CNR)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
+} LPTMR_Type;
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
@@ -5695,58 +4024,50 @@ typedef struct {
* @{
*/
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TEN_WIDTH 1
-#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TMS_WIDTH 1
-#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TFC_WIDTH 1
-#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPP_WIDTH 1
-#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS_WIDTH 2
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TIE_WIDTH 1
-#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-#define LPTMR_CSR_TCF_WIDTH 1
-#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS_WIDTH 2
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PBYP_WIDTH 1
-#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE_WIDTH 4
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE_WIDTH 16
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER_WIDTH 16
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK (0x1U)
+#define LPTMR_CSR_TEN_SHIFT (0U)
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK (0x2U)
+#define LPTMR_CSR_TMS_SHIFT (1U)
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK (0x4U)
+#define LPTMR_CSR_TFC_SHIFT (2U)
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK (0x8U)
+#define LPTMR_CSR_TPP_SHIFT (3U)
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK (0x30U)
+#define LPTMR_CSR_TPS_SHIFT (4U)
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK (0x40U)
+#define LPTMR_CSR_TIE_SHIFT (6U)
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK (0x80U)
+#define LPTMR_CSR_TCF_SHIFT (7U)
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK (0x3U)
+#define LPTMR_PSR_PCS_SHIFT (0U)
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT (2U)
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT (3U)
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT (0U)
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT (0U)
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
/*!
* @}
@@ -5758,7 +4079,6 @@ typedef struct {
#define LPTMR0_BASE (0x40040000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-#define LPTMR0_BASE_PTR (LPTMR0)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
/** Array initializer of LPTMR peripheral base pointers */
@@ -5766,28 +4086,6 @@ typedef struct {
/** Interrupt vectors for the LPTMR peripheral type */
#define LPTMR_IRQS { LPTMR0_IRQn }
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register instance definitions */
-/* LPTMR0 */
-#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
-#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
-#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
-#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
@@ -5810,30 +4108,7 @@ typedef struct {
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
-} LPUART_Type, *LPUART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPUART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
- * @{
- */
-
-
-/* LPUART - Register accessors */
-#define LPUART_BAUD_REG(base) ((base)->BAUD)
-#define LPUART_STAT_REG(base) ((base)->STAT)
-#define LPUART_CTRL_REG(base) ((base)->CTRL)
-#define LPUART_DATA_REG(base) ((base)->DATA)
-#define LPUART_MATCH_REG(base) ((base)->MATCH)
-#define LPUART_MODIR_REG(base) ((base)->MODIR)
-
-/*!
- * @}
- */ /* end of group LPUART_Register_Accessor_Macros */
-
+} LPUART_Type;
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
@@ -5844,344 +4119,267 @@ typedef struct {
* @{
*/
-/* BAUD Bit Fields */
-#define LPUART_BAUD_SBR_MASK 0x1FFFu
-#define LPUART_BAUD_SBR_SHIFT 0
-#define LPUART_BAUD_SBR_WIDTH 13
-#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
-#define LPUART_BAUD_SBNS_MASK 0x2000u
-#define LPUART_BAUD_SBNS_SHIFT 13
-#define LPUART_BAUD_SBNS_WIDTH 1
-#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
-#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
-#define LPUART_BAUD_RXEDGIE_SHIFT 14
-#define LPUART_BAUD_RXEDGIE_WIDTH 1
-#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
-#define LPUART_BAUD_LBKDIE_MASK 0x8000u
-#define LPUART_BAUD_LBKDIE_SHIFT 15
-#define LPUART_BAUD_LBKDIE_WIDTH 1
-#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
-#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
-#define LPUART_BAUD_RESYNCDIS_SHIFT 16
-#define LPUART_BAUD_RESYNCDIS_WIDTH 1
-#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
-#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
-#define LPUART_BAUD_BOTHEDGE_SHIFT 17
-#define LPUART_BAUD_BOTHEDGE_WIDTH 1
-#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
-#define LPUART_BAUD_MATCFG_MASK 0xC0000u
-#define LPUART_BAUD_MATCFG_SHIFT 18
-#define LPUART_BAUD_MATCFG_WIDTH 2
-#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
-#define LPUART_BAUD_RDMAE_MASK 0x200000u
-#define LPUART_BAUD_RDMAE_SHIFT 21
-#define LPUART_BAUD_RDMAE_WIDTH 1
-#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
-#define LPUART_BAUD_TDMAE_MASK 0x800000u
-#define LPUART_BAUD_TDMAE_SHIFT 23
-#define LPUART_BAUD_TDMAE_WIDTH 1
-#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
-#define LPUART_BAUD_OSR_MASK 0x1F000000u
-#define LPUART_BAUD_OSR_SHIFT 24
-#define LPUART_BAUD_OSR_WIDTH 5
-#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
-#define LPUART_BAUD_M10_MASK 0x20000000u
-#define LPUART_BAUD_M10_SHIFT 29
-#define LPUART_BAUD_M10_WIDTH 1
-#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
-#define LPUART_BAUD_MAEN2_MASK 0x40000000u
-#define LPUART_BAUD_MAEN2_SHIFT 30
-#define LPUART_BAUD_MAEN2_WIDTH 1
-#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
-#define LPUART_BAUD_MAEN1_MASK 0x80000000u
-#define LPUART_BAUD_MAEN1_SHIFT 31
-#define LPUART_BAUD_MAEN1_WIDTH 1
-#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
-/* STAT Bit Fields */
-#define LPUART_STAT_MA2F_MASK 0x4000u
-#define LPUART_STAT_MA2F_SHIFT 14
-#define LPUART_STAT_MA2F_WIDTH 1
-#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
-#define LPUART_STAT_MA1F_MASK 0x8000u
-#define LPUART_STAT_MA1F_SHIFT 15
-#define LPUART_STAT_MA1F_WIDTH 1
-#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
-#define LPUART_STAT_PF_MASK 0x10000u
-#define LPUART_STAT_PF_SHIFT 16
-#define LPUART_STAT_PF_WIDTH 1
-#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
-#define LPUART_STAT_FE_MASK 0x20000u
-#define LPUART_STAT_FE_SHIFT 17
-#define LPUART_STAT_FE_WIDTH 1
-#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
-#define LPUART_STAT_NF_MASK 0x40000u
-#define LPUART_STAT_NF_SHIFT 18
-#define LPUART_STAT_NF_WIDTH 1
-#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
-#define LPUART_STAT_OR_MASK 0x80000u
-#define LPUART_STAT_OR_SHIFT 19
-#define LPUART_STAT_OR_WIDTH 1
-#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
-#define LPUART_STAT_IDLE_MASK 0x100000u
-#define LPUART_STAT_IDLE_SHIFT 20
-#define LPUART_STAT_IDLE_WIDTH 1
-#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
-#define LPUART_STAT_RDRF_MASK 0x200000u
-#define LPUART_STAT_RDRF_SHIFT 21
-#define LPUART_STAT_RDRF_WIDTH 1
-#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
-#define LPUART_STAT_TC_MASK 0x400000u
-#define LPUART_STAT_TC_SHIFT 22
-#define LPUART_STAT_TC_WIDTH 1
-#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
-#define LPUART_STAT_TDRE_MASK 0x800000u
-#define LPUART_STAT_TDRE_SHIFT 23
-#define LPUART_STAT_TDRE_WIDTH 1
-#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
-#define LPUART_STAT_RAF_MASK 0x1000000u
-#define LPUART_STAT_RAF_SHIFT 24
-#define LPUART_STAT_RAF_WIDTH 1
-#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
-#define LPUART_STAT_LBKDE_MASK 0x2000000u
-#define LPUART_STAT_LBKDE_SHIFT 25
-#define LPUART_STAT_LBKDE_WIDTH 1
-#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
-#define LPUART_STAT_BRK13_MASK 0x4000000u
-#define LPUART_STAT_BRK13_SHIFT 26
-#define LPUART_STAT_BRK13_WIDTH 1
-#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
-#define LPUART_STAT_RWUID_MASK 0x8000000u
-#define LPUART_STAT_RWUID_SHIFT 27
-#define LPUART_STAT_RWUID_WIDTH 1
-#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
-#define LPUART_STAT_RXINV_MASK 0x10000000u
-#define LPUART_STAT_RXINV_SHIFT 28
-#define LPUART_STAT_RXINV_WIDTH 1
-#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
-#define LPUART_STAT_MSBF_MASK 0x20000000u
-#define LPUART_STAT_MSBF_SHIFT 29
-#define LPUART_STAT_MSBF_WIDTH 1
-#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
-#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
-#define LPUART_STAT_RXEDGIF_SHIFT 30
-#define LPUART_STAT_RXEDGIF_WIDTH 1
-#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
-#define LPUART_STAT_LBKDIF_MASK 0x80000000u
-#define LPUART_STAT_LBKDIF_SHIFT 31
-#define LPUART_STAT_LBKDIF_WIDTH 1
-#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
-/* CTRL Bit Fields */
-#define LPUART_CTRL_PT_MASK 0x1u
-#define LPUART_CTRL_PT_SHIFT 0
-#define LPUART_CTRL_PT_WIDTH 1
-#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
-#define LPUART_CTRL_PE_MASK 0x2u
-#define LPUART_CTRL_PE_SHIFT 1
-#define LPUART_CTRL_PE_WIDTH 1
-#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
-#define LPUART_CTRL_ILT_MASK 0x4u
-#define LPUART_CTRL_ILT_SHIFT 2
-#define LPUART_CTRL_ILT_WIDTH 1
-#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
-#define LPUART_CTRL_WAKE_MASK 0x8u
-#define LPUART_CTRL_WAKE_SHIFT 3
-#define LPUART_CTRL_WAKE_WIDTH 1
-#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
-#define LPUART_CTRL_M_MASK 0x10u
-#define LPUART_CTRL_M_SHIFT 4
-#define LPUART_CTRL_M_WIDTH 1
-#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
-#define LPUART_CTRL_RSRC_MASK 0x20u
-#define LPUART_CTRL_RSRC_SHIFT 5
-#define LPUART_CTRL_RSRC_WIDTH 1
-#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
-#define LPUART_CTRL_DOZEEN_MASK 0x40u
-#define LPUART_CTRL_DOZEEN_SHIFT 6
-#define LPUART_CTRL_DOZEEN_WIDTH 1
-#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
-#define LPUART_CTRL_LOOPS_MASK 0x80u
-#define LPUART_CTRL_LOOPS_SHIFT 7
-#define LPUART_CTRL_LOOPS_WIDTH 1
-#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
-#define LPUART_CTRL_IDLECFG_MASK 0x700u
-#define LPUART_CTRL_IDLECFG_SHIFT 8
-#define LPUART_CTRL_IDLECFG_WIDTH 3
-#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
-#define LPUART_CTRL_MA2IE_MASK 0x4000u
-#define LPUART_CTRL_MA2IE_SHIFT 14
-#define LPUART_CTRL_MA2IE_WIDTH 1
-#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
-#define LPUART_CTRL_MA1IE_MASK 0x8000u
-#define LPUART_CTRL_MA1IE_SHIFT 15
-#define LPUART_CTRL_MA1IE_WIDTH 1
-#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
-#define LPUART_CTRL_SBK_MASK 0x10000u
-#define LPUART_CTRL_SBK_SHIFT 16
-#define LPUART_CTRL_SBK_WIDTH 1
-#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
-#define LPUART_CTRL_RWU_MASK 0x20000u
-#define LPUART_CTRL_RWU_SHIFT 17
-#define LPUART_CTRL_RWU_WIDTH 1
-#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
-#define LPUART_CTRL_RE_MASK 0x40000u
-#define LPUART_CTRL_RE_SHIFT 18
-#define LPUART_CTRL_RE_WIDTH 1
-#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
-#define LPUART_CTRL_TE_MASK 0x80000u
-#define LPUART_CTRL_TE_SHIFT 19
-#define LPUART_CTRL_TE_WIDTH 1
-#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
-#define LPUART_CTRL_ILIE_MASK 0x100000u
-#define LPUART_CTRL_ILIE_SHIFT 20
-#define LPUART_CTRL_ILIE_WIDTH 1
-#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
-#define LPUART_CTRL_RIE_MASK 0x200000u
-#define LPUART_CTRL_RIE_SHIFT 21
-#define LPUART_CTRL_RIE_WIDTH 1
-#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
-#define LPUART_CTRL_TCIE_MASK 0x400000u
-#define LPUART_CTRL_TCIE_SHIFT 22
-#define LPUART_CTRL_TCIE_WIDTH 1
-#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
-#define LPUART_CTRL_TIE_MASK 0x800000u
-#define LPUART_CTRL_TIE_SHIFT 23
-#define LPUART_CTRL_TIE_WIDTH 1
-#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
-#define LPUART_CTRL_PEIE_MASK 0x1000000u
-#define LPUART_CTRL_PEIE_SHIFT 24
-#define LPUART_CTRL_PEIE_WIDTH 1
-#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
-#define LPUART_CTRL_FEIE_MASK 0x2000000u
-#define LPUART_CTRL_FEIE_SHIFT 25
-#define LPUART_CTRL_FEIE_WIDTH 1
-#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
-#define LPUART_CTRL_NEIE_MASK 0x4000000u
-#define LPUART_CTRL_NEIE_SHIFT 26
-#define LPUART_CTRL_NEIE_WIDTH 1
-#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
-#define LPUART_CTRL_ORIE_MASK 0x8000000u
-#define LPUART_CTRL_ORIE_SHIFT 27
-#define LPUART_CTRL_ORIE_WIDTH 1
-#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
-#define LPUART_CTRL_TXINV_MASK 0x10000000u
-#define LPUART_CTRL_TXINV_SHIFT 28
-#define LPUART_CTRL_TXINV_WIDTH 1
-#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
-#define LPUART_CTRL_TXDIR_MASK 0x20000000u
-#define LPUART_CTRL_TXDIR_SHIFT 29
-#define LPUART_CTRL_TXDIR_WIDTH 1
-#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
-#define LPUART_CTRL_R9T8_MASK 0x40000000u
-#define LPUART_CTRL_R9T8_SHIFT 30
-#define LPUART_CTRL_R9T8_WIDTH 1
-#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
-#define LPUART_CTRL_R8T9_MASK 0x80000000u
-#define LPUART_CTRL_R8T9_SHIFT 31
-#define LPUART_CTRL_R8T9_WIDTH 1
-#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
-/* DATA Bit Fields */
-#define LPUART_DATA_R0T0_MASK 0x1u
-#define LPUART_DATA_R0T0_SHIFT 0
-#define LPUART_DATA_R0T0_WIDTH 1
-#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
-#define LPUART_DATA_R1T1_MASK 0x2u
-#define LPUART_DATA_R1T1_SHIFT 1
-#define LPUART_DATA_R1T1_WIDTH 1
-#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
-#define LPUART_DATA_R2T2_MASK 0x4u
-#define LPUART_DATA_R2T2_SHIFT 2
-#define LPUART_DATA_R2T2_WIDTH 1
-#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
-#define LPUART_DATA_R3T3_MASK 0x8u
-#define LPUART_DATA_R3T3_SHIFT 3
-#define LPUART_DATA_R3T3_WIDTH 1
-#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
-#define LPUART_DATA_R4T4_MASK 0x10u
-#define LPUART_DATA_R4T4_SHIFT 4
-#define LPUART_DATA_R4T4_WIDTH 1
-#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
-#define LPUART_DATA_R5T5_MASK 0x20u
-#define LPUART_DATA_R5T5_SHIFT 5
-#define LPUART_DATA_R5T5_WIDTH 1
-#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
-#define LPUART_DATA_R6T6_MASK 0x40u
-#define LPUART_DATA_R6T6_SHIFT 6
-#define LPUART_DATA_R6T6_WIDTH 1
-#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
-#define LPUART_DATA_R7T7_MASK 0x80u
-#define LPUART_DATA_R7T7_SHIFT 7
-#define LPUART_DATA_R7T7_WIDTH 1
-#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
-#define LPUART_DATA_R8T8_MASK 0x100u
-#define LPUART_DATA_R8T8_SHIFT 8
-#define LPUART_DATA_R8T8_WIDTH 1
-#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
-#define LPUART_DATA_R9T9_MASK 0x200u
-#define LPUART_DATA_R9T9_SHIFT 9
-#define LPUART_DATA_R9T9_WIDTH 1
-#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
-#define LPUART_DATA_IDLINE_MASK 0x800u
-#define LPUART_DATA_IDLINE_SHIFT 11
-#define LPUART_DATA_IDLINE_WIDTH 1
-#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
-#define LPUART_DATA_RXEMPT_MASK 0x1000u
-#define LPUART_DATA_RXEMPT_SHIFT 12
-#define LPUART_DATA_RXEMPT_WIDTH 1
-#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
-#define LPUART_DATA_FRETSC_MASK 0x2000u
-#define LPUART_DATA_FRETSC_SHIFT 13
-#define LPUART_DATA_FRETSC_WIDTH 1
-#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
-#define LPUART_DATA_PARITYE_MASK 0x4000u
-#define LPUART_DATA_PARITYE_SHIFT 14
-#define LPUART_DATA_PARITYE_WIDTH 1
-#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
-#define LPUART_DATA_NOISY_MASK 0x8000u
-#define LPUART_DATA_NOISY_SHIFT 15
-#define LPUART_DATA_NOISY_WIDTH 1
-#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
-/* MATCH Bit Fields */
-#define LPUART_MATCH_MA1_MASK 0x3FFu
-#define LPUART_MATCH_MA1_SHIFT 0
-#define LPUART_MATCH_MA1_WIDTH 10
-#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
-#define LPUART_MATCH_MA2_MASK 0x3FF0000u
-#define LPUART_MATCH_MA2_SHIFT 16
-#define LPUART_MATCH_MA2_WIDTH 10
-#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
-/* MODIR Bit Fields */
-#define LPUART_MODIR_TXCTSE_MASK 0x1u
-#define LPUART_MODIR_TXCTSE_SHIFT 0
-#define LPUART_MODIR_TXCTSE_WIDTH 1
-#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
-#define LPUART_MODIR_TXRTSE_MASK 0x2u
-#define LPUART_MODIR_TXRTSE_SHIFT 1
-#define LPUART_MODIR_TXRTSE_WIDTH 1
-#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
-#define LPUART_MODIR_TXRTSPOL_MASK 0x4u
-#define LPUART_MODIR_TXRTSPOL_SHIFT 2
-#define LPUART_MODIR_TXRTSPOL_WIDTH 1
-#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
-#define LPUART_MODIR_RXRTSE_MASK 0x8u
-#define LPUART_MODIR_RXRTSE_SHIFT 3
-#define LPUART_MODIR_RXRTSE_WIDTH 1
-#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
-#define LPUART_MODIR_TXCTSC_MASK 0x10u
-#define LPUART_MODIR_TXCTSC_SHIFT 4
-#define LPUART_MODIR_TXCTSC_WIDTH 1
-#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
-#define LPUART_MODIR_TXCTSSRC_MASK 0x20u
-#define LPUART_MODIR_TXCTSSRC_SHIFT 5
-#define LPUART_MODIR_TXCTSSRC_WIDTH 1
-#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
-#define LPUART_MODIR_TNP_MASK 0x30000u
-#define LPUART_MODIR_TNP_SHIFT 16
-#define LPUART_MODIR_TNP_WIDTH 2
-#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
-#define LPUART_MODIR_IREN_MASK 0x40000u
-#define LPUART_MODIR_IREN_SHIFT 18
-#define LPUART_MODIR_IREN_WIDTH 1
-#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
+/*! @name BAUD - LPUART Baud Rate Register */
+#define LPUART_BAUD_SBR_MASK (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT (0U)
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT (13U)
+#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
+#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT (15U)
+#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
+#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
+#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT (18U)
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT (21U)
+#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT (23U)
+#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT (24U)
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT (29U)
+#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT (30U)
+#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT (31U)
+#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+
+/*! @name STAT - LPUART Status Register */
+#define LPUART_STAT_MA2F_MASK (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT (14U)
+#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT (15U)
+#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK (0x10000U)
+#define LPUART_STAT_PF_SHIFT (16U)
+#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK (0x20000U)
+#define LPUART_STAT_FE_SHIFT (17U)
+#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK (0x40000U)
+#define LPUART_STAT_NF_SHIFT (18U)
+#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK (0x80000U)
+#define LPUART_STAT_OR_SHIFT (19U)
+#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT (20U)
+#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT (21U)
+#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK (0x400000U)
+#define LPUART_STAT_TC_SHIFT (22U)
+#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT (23U)
+#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT (24U)
+#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT (25U)
+#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT (26U)
+#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT (27U)
+#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT (28U)
+#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT (29U)
+#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT (30U)
+#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT (31U)
+#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+
+/*! @name CTRL - LPUART Control Register */
+#define LPUART_CTRL_PT_MASK (0x1U)
+#define LPUART_CTRL_PT_SHIFT (0U)
+#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK (0x2U)
+#define LPUART_CTRL_PE_SHIFT (1U)
+#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK (0x4U)
+#define LPUART_CTRL_ILT_SHIFT (2U)
+#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT (3U)
+#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK (0x10U)
+#define LPUART_CTRL_M_SHIFT (4U)
+#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT (5U)
+#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT (6U)
+#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT (7U)
+#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT (8U)
+#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT (14U)
+#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT (15U)
+#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT (16U)
+#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT (17U)
+#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK (0x40000U)
+#define LPUART_CTRL_RE_SHIFT (18U)
+#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK (0x80000U)
+#define LPUART_CTRL_TE_SHIFT (19U)
+#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT (20U)
+#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT (21U)
+#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT (22U)
+#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT (23U)
+#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT (24U)
+#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT (25U)
+#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT (26U)
+#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT (27U)
+#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT (28U)
+#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT (29U)
+#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT (30U)
+#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT (31U)
+#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+
+/*! @name DATA - LPUART Data Register */
+#define LPUART_DATA_R0T0_MASK (0x1U)
+#define LPUART_DATA_R0T0_SHIFT (0U)
+#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK (0x2U)
+#define LPUART_DATA_R1T1_SHIFT (1U)
+#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK (0x4U)
+#define LPUART_DATA_R2T2_SHIFT (2U)
+#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK (0x8U)
+#define LPUART_DATA_R3T3_SHIFT (3U)
+#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK (0x10U)
+#define LPUART_DATA_R4T4_SHIFT (4U)
+#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK (0x20U)
+#define LPUART_DATA_R5T5_SHIFT (5U)
+#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK (0x40U)
+#define LPUART_DATA_R6T6_SHIFT (6U)
+#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK (0x80U)
+#define LPUART_DATA_R7T7_SHIFT (7U)
+#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK (0x100U)
+#define LPUART_DATA_R8T8_SHIFT (8U)
+#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK (0x200U)
+#define LPUART_DATA_R9T9_SHIFT (9U)
+#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT (11U)
+#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT (12U)
+#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT (13U)
+#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT (14U)
+#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT (15U)
+#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+
+/*! @name MATCH - LPUART Match Address Register */
+#define LPUART_MATCH_MA1_MASK (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT (0U)
+#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT (16U)
+#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+
+/*! @name MODIR - LPUART Modem IrDA Register */
+#define LPUART_MODIR_TXCTSE_MASK (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT (0U)
+#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+#define LPUART_MODIR_TXRTSE_MASK (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT (1U)
+#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
+#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+#define LPUART_MODIR_RXRTSE_MASK (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT (3U)
+#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+#define LPUART_MODIR_TXCTSC_MASK (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT (4U)
+#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
+#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+#define LPUART_MODIR_TNP_MASK (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT (16U)
+#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT (18U)
+#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+
/*!
* @}
@@ -6193,7 +4391,6 @@ typedef struct {
#define LPUART0_BASE (0x4002A000u)
/** Peripheral LPUART0 base pointer */
#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
-#define LPUART0_BASE_PTR (LPUART0)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { LPUART0_BASE }
/** Array initializer of LPUART peripheral base pointers */
@@ -6202,30 +4399,6 @@ typedef struct {
#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
#define LPUART_ERR_IRQS { LPUART0_IRQn }
-/* ----------------------------------------------------------------------------
- -- LPUART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
- * @{
- */
-
-
-/* LPUART - Register instance definitions */
-/* LPUART0 */
-#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
-#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
-#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
-#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
-#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
-#define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
-
-/*!
- * @}
- */ /* end of group LPUART_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
@@ -6256,36 +4429,7 @@ typedef struct {
__IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
__IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
__IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
-} MCG_Type, *MCG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register accessors */
-#define MCG_C1_REG(base) ((base)->C1)
-#define MCG_C2_REG(base) ((base)->C2)
-#define MCG_C3_REG(base) ((base)->C3)
-#define MCG_C4_REG(base) ((base)->C4)
-#define MCG_C5_REG(base) ((base)->C5)
-#define MCG_C6_REG(base) ((base)->C6)
-#define MCG_S_REG(base) ((base)->S)
-#define MCG_SC_REG(base) ((base)->SC)
-#define MCG_ATCVH_REG(base) ((base)->ATCVH)
-#define MCG_ATCVL_REG(base) ((base)->ATCVL)
-#define MCG_C7_REG(base) ((base)->C7)
-#define MCG_C8_REG(base) ((base)->C8)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
+} MCG_Type;
/* ----------------------------------------------------------------------------
-- MCG Register Masks
@@ -6296,153 +4440,130 @@ typedef struct {
* @{
*/
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IREFSTEN_WIDTH 1
-#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IRCLKEN_WIDTH 1
-#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_IREFS_WIDTH 1
-#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV_WIDTH 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS_WIDTH 2
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_IRCS_WIDTH 1
-#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_LP_WIDTH 1
-#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
-#define MCG_C2_EREFS_MASK 0x4u
-#define MCG_C2_EREFS_SHIFT 2
-#define MCG_C2_EREFS_WIDTH 1
-#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
-#define MCG_C2_HGO_MASK 0x8u
-#define MCG_C2_HGO_SHIFT 3
-#define MCG_C2_HGO_WIDTH 1
-#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
-#define MCG_C2_RANGE_MASK 0x30u
-#define MCG_C2_RANGE_SHIFT 4
-#define MCG_C2_RANGE_WIDTH 2
-#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
-#define MCG_C2_FCFTRIM_MASK 0x40u
-#define MCG_C2_FCFTRIM_SHIFT 6
-#define MCG_C2_FCFTRIM_WIDTH 1
-#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-#define MCG_C2_LOCRE0_WIDTH 1
-#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM_WIDTH 8
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_SCFTRIM_WIDTH 1
-#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM_WIDTH 4
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS_WIDTH 2
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-#define MCG_C4_DMX32_WIDTH 1
-#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
-/* C6 Bit Fields */
-#define MCG_C6_CME_MASK 0x20u
-#define MCG_C6_CME_SHIFT 5
-#define MCG_C6_CME_WIDTH 1
-#define MCG_C6_CME(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME_SHIFT))&MCG_C6_CME_MASK)
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_IRCST_WIDTH 1
-#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_OSCINIT0_WIDTH 1
-#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST_WIDTH 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_IREFST_WIDTH 1
-#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_LOCS0_WIDTH 1
-#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV_WIDTH 3
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_FLTPRSRV_WIDTH 1
-#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMF_WIDTH 1
-#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATMS_WIDTH 1
-#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-#define MCG_SC_ATME_WIDTH 1
-#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH_WIDTH 8
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL_WIDTH 8
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK 0x3u
-#define MCG_C7_OSCSEL_SHIFT 0
-#define MCG_C7_OSCSEL_WIDTH 2
-#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK 0x1u
-#define MCG_C8_LOCS1_SHIFT 0
-#define MCG_C8_LOCS1_WIDTH 1
-#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
-#define MCG_C8_CME1_MASK 0x20u
-#define MCG_C8_CME1_SHIFT 5
-#define MCG_C8_CME1_WIDTH 1
-#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
-#define MCG_C8_LOCRE1_MASK 0x80u
-#define MCG_C8_LOCRE1_SHIFT 7
-#define MCG_C8_LOCRE1_WIDTH 1
-#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT (0U)
+#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT (1U)
+#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK (0x4U)
+#define MCG_C1_IREFS_SHIFT (2U)
+#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK (0x38U)
+#define MCG_C1_FRDIV_SHIFT (3U)
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK (0xC0U)
+#define MCG_C1_CLKS_SHIFT (6U)
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK (0x1U)
+#define MCG_C2_IRCS_SHIFT (0U)
+#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK (0x2U)
+#define MCG_C2_LP_SHIFT (1U)
+#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK (0x4U)
+#define MCG_C2_EREFS_SHIFT (2U)
+#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK (0x8U)
+#define MCG_C2_HGO_SHIFT (3U)
+#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK (0x30U)
+#define MCG_C2_RANGE_SHIFT (4U)
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK (0x40U)
+#define MCG_C2_FCFTRIM_SHIFT (6U)
+#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK (0x80U)
+#define MCG_C2_LOCRE0_SHIFT (7U)
+#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT (0U)
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT (0U)
+#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT (1U)
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT (5U)
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK (0x80U)
+#define MCG_C4_DMX32_SHIFT (7U)
+#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_CME_MASK (0x20U)
+#define MCG_C6_CME_SHIFT (5U)
+#define MCG_C6_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME_SHIFT)) & MCG_C6_CME_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK (0x1U)
+#define MCG_S_IRCST_SHIFT (0U)
+#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK (0x2U)
+#define MCG_S_OSCINIT0_SHIFT (1U)
+#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK (0xCU)
+#define MCG_S_CLKST_SHIFT (2U)
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK (0x10U)
+#define MCG_S_IREFST_SHIFT (4U)
+#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK (0x1U)
+#define MCG_SC_LOCS0_SHIFT (0U)
+#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK (0xEU)
+#define MCG_SC_FCRDIV_SHIFT (1U)
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT (4U)
+#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK (0x20U)
+#define MCG_SC_ATMF_SHIFT (5U)
+#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK (0x40U)
+#define MCG_SC_ATMS_SHIFT (6U)
+#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK (0x80U)
+#define MCG_SC_ATME_SHIFT (7U)
+#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT (0U)
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT (0U)
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK (0x3U)
+#define MCG_C7_OSCSEL_SHIFT (0U)
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1_MASK (0x1U)
+#define MCG_C8_LOCS1_SHIFT (0U)
+#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK (0x20U)
+#define MCG_C8_CME1_SHIFT (5U)
+#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOCRE1_MASK (0x80U)
+#define MCG_C8_LOCRE1_SHIFT (7U)
+#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+
/*!
* @}
@@ -6454,42 +4575,11 @@ typedef struct {
#define MCG_BASE (0x40064000u)
/** Peripheral MCG base pointer */
#define MCG ((MCG_Type *)MCG_BASE)
-#define MCG_BASE_PTR (MCG)
/** Array initializer of MCG peripheral base addresses */
#define MCG_BASE_ADDRS { MCG_BASE }
/** Array initializer of MCG peripheral base pointers */
#define MCG_BASE_PTRS { MCG }
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register instance definitions */
-/* MCG */
-#define MCG_C1 MCG_C1_REG(MCG)
-#define MCG_C2 MCG_C2_REG(MCG)
-#define MCG_C3 MCG_C3_REG(MCG)
-#define MCG_C4 MCG_C4_REG(MCG)
-#define MCG_C5 MCG_C5_REG(MCG)
-#define MCG_C6 MCG_C6_REG(MCG)
-#define MCG_S MCG_S_REG(MCG)
-#define MCG_SC MCG_SC_REG(MCG)
-#define MCG_ATCVH MCG_ATCVH_REG(MCG)
-#define MCG_ATCVL MCG_ATCVL_REG(MCG)
-#define MCG_C7 MCG_C7_REG(MCG)
-#define MCG_C8 MCG_C8_REG(MCG)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group MCG_Peripheral_Access_Layer */
@@ -6513,29 +4603,7 @@ typedef struct {
__IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
uint8_t RESERVED_1[44];
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
-} MCM_Type, *MCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register accessors */
-#define MCM_PLASC_REG(base) ((base)->PLASC)
-#define MCM_PLAMC_REG(base) ((base)->PLAMC)
-#define MCM_PLACR_REG(base) ((base)->PLACR)
-#define MCM_ISCR_REG(base) ((base)->ISCR)
-#define MCM_CPO_REG(base) ((base)->CPO)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
+} MCM_Type;
/* ----------------------------------------------------------------------------
-- MCM Register Masks
@@ -6546,83 +4614,70 @@ typedef struct {
* @{
*/
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK 0xFFu
-#define MCM_PLASC_ASC_SHIFT 0
-#define MCM_PLASC_ASC_WIDTH 8
-#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK 0xFFu
-#define MCM_PLAMC_AMC_SHIFT 0
-#define MCM_PLAMC_AMC_WIDTH 8
-#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* PLACR Bit Fields */
-#define MCM_PLACR_ARB_MASK 0x200u
-#define MCM_PLACR_ARB_SHIFT 9
-#define MCM_PLACR_ARB_WIDTH 1
-#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ARB_SHIFT))&MCM_PLACR_ARB_MASK)
-/* ISCR Bit Fields */
-#define MCM_ISCR_FIOC_MASK 0x100u
-#define MCM_ISCR_FIOC_SHIFT 8
-#define MCM_ISCR_FIOC_WIDTH 1
-#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
-#define MCM_ISCR_FDZC_MASK 0x200u
-#define MCM_ISCR_FDZC_SHIFT 9
-#define MCM_ISCR_FDZC_WIDTH 1
-#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
-#define MCM_ISCR_FOFC_MASK 0x400u
-#define MCM_ISCR_FOFC_SHIFT 10
-#define MCM_ISCR_FOFC_WIDTH 1
-#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
-#define MCM_ISCR_FUFC_MASK 0x800u
-#define MCM_ISCR_FUFC_SHIFT 11
-#define MCM_ISCR_FUFC_WIDTH 1
-#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
-#define MCM_ISCR_FIXC_MASK 0x1000u
-#define MCM_ISCR_FIXC_SHIFT 12
-#define MCM_ISCR_FIXC_WIDTH 1
-#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
-#define MCM_ISCR_FIDC_MASK 0x8000u
-#define MCM_ISCR_FIDC_SHIFT 15
-#define MCM_ISCR_FIDC_WIDTH 1
-#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
-#define MCM_ISCR_FIOCE_MASK 0x1000000u
-#define MCM_ISCR_FIOCE_SHIFT 24
-#define MCM_ISCR_FIOCE_WIDTH 1
-#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
-#define MCM_ISCR_FDZCE_MASK 0x2000000u
-#define MCM_ISCR_FDZCE_SHIFT 25
-#define MCM_ISCR_FDZCE_WIDTH 1
-#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
-#define MCM_ISCR_FOFCE_MASK 0x4000000u
-#define MCM_ISCR_FOFCE_SHIFT 26
-#define MCM_ISCR_FOFCE_WIDTH 1
-#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
-#define MCM_ISCR_FUFCE_MASK 0x8000000u
-#define MCM_ISCR_FUFCE_SHIFT 27
-#define MCM_ISCR_FUFCE_WIDTH 1
-#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
-#define MCM_ISCR_FIXCE_MASK 0x10000000u
-#define MCM_ISCR_FIXCE_SHIFT 28
-#define MCM_ISCR_FIXCE_WIDTH 1
-#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
-#define MCM_ISCR_FIDCE_MASK 0x80000000u
-#define MCM_ISCR_FIDCE_SHIFT 31
-#define MCM_ISCR_FIDCE_WIDTH 1
-#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
-/* CPO Bit Fields */
-#define MCM_CPO_CPOREQ_MASK 0x1u
-#define MCM_CPO_CPOREQ_SHIFT 0
-#define MCM_CPO_CPOREQ_WIDTH 1
-#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
-#define MCM_CPO_CPOACK_MASK 0x2u
-#define MCM_CPO_CPOACK_SHIFT 1
-#define MCM_CPO_CPOACK_WIDTH 1
-#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
-#define MCM_CPO_CPOWOI_MASK 0x4u
-#define MCM_CPO_CPOWOI_SHIFT 2
-#define MCM_CPO_CPOWOI_WIDTH 1
-#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK (0xFFU)
+#define MCM_PLASC_ASC_SHIFT (0U)
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT (0U)
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name PLACR - Crossbar Switch (AXBS) Control Register */
+#define MCM_PLACR_ARB_MASK (0x200U)
+#define MCM_PLACR_ARB_SHIFT (9U)
+#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
+
+/*! @name ISCR - Interrupt Status and Control Register */
+#define MCM_ISCR_FIOC_MASK (0x100U)
+#define MCM_ISCR_FIOC_SHIFT (8U)
+#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK (0x200U)
+#define MCM_ISCR_FDZC_SHIFT (9U)
+#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK (0x400U)
+#define MCM_ISCR_FOFC_SHIFT (10U)
+#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK (0x800U)
+#define MCM_ISCR_FUFC_SHIFT (11U)
+#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK (0x1000U)
+#define MCM_ISCR_FIXC_SHIFT (12U)
+#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK (0x8000U)
+#define MCM_ISCR_FIDC_SHIFT (15U)
+#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK (0x1000000U)
+#define MCM_ISCR_FIOCE_SHIFT (24U)
+#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK (0x2000000U)
+#define MCM_ISCR_FDZCE_SHIFT (25U)
+#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK (0x4000000U)
+#define MCM_ISCR_FOFCE_SHIFT (26U)
+#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK (0x8000000U)
+#define MCM_ISCR_FUFCE_SHIFT (27U)
+#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK (0x10000000U)
+#define MCM_ISCR_FIXCE_SHIFT (28U)
+#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK (0x80000000U)
+#define MCM_ISCR_FIDCE_SHIFT (31U)
+#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+
+/*! @name CPO - Compute Operation Control Register */
+#define MCM_CPO_CPOREQ_MASK (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT (0U)
+#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK (0x2U)
+#define MCM_CPO_CPOACK_SHIFT (1U)
+#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT (2U)
+#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+
/*!
* @}
@@ -6634,7 +4689,6 @@ typedef struct {
#define MCM_BASE (0xE0080000u)
/** Peripheral MCM base pointer */
#define MCM ((MCM_Type *)MCM_BASE)
-#define MCM_BASE_PTR (MCM)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
@@ -6642,29 +4696,6 @@ typedef struct {
/** Interrupt vectors for the MCM peripheral type */
#define MCM_IRQS { MCM_IRQn }
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register instance definitions */
-/* MCM */
-#define MCM_PLASC MCM_PLASC_REG(MCM)
-#define MCM_PLAMC MCM_PLAMC_REG(MCM)
-#define MCM_PLACR MCM_PLACR_REG(MCM)
-#define MCM_ISCR MCM_ISCR_REG(MCM)
-#define MCM_CPO MCM_CPO_REG(MCM)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
@@ -6695,38 +4726,7 @@ typedef struct {
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
-} NV_Type, *NV_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register accessors */
-#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
-#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
-#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
-#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
-#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
-#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
-#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
-#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
-#define NV_FPROT3_REG(base) ((base)->FPROT3)
-#define NV_FPROT2_REG(base) ((base)->FPROT2)
-#define NV_FPROT1_REG(base) ((base)->FPROT1)
-#define NV_FPROT0_REG(base) ((base)->FPROT0)
-#define NV_FSEC_REG(base) ((base)->FSEC)
-#define NV_FOPT_REG(base) ((base)->FOPT)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
+} NV_Type;
/* ----------------------------------------------------------------------------
-- NV Register Masks
@@ -6737,100 +4737,94 @@ typedef struct {
* @{
*/
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY_WIDTH 8
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY_WIDTH 8
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY_WIDTH 8
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY_WIDTH 8
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY_WIDTH 8
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY_WIDTH 8
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY_WIDTH 8
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY_WIDTH 8
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT_WIDTH 8
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT_WIDTH 8
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT_WIDTH 8
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT_WIDTH 8
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC_WIDTH 2
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC_WIDTH 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN_WIDTH 2
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN_WIDTH 2
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK 0x1u
-#define NV_FOPT_LPBOOT_SHIFT 0
-#define NV_FOPT_LPBOOT_WIDTH 1
-#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-#define NV_FOPT_EZPORT_DIS_WIDTH 1
-#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
-#define NV_FOPT_NMI_DIS_MASK 0x4u
-#define NV_FOPT_NMI_DIS_SHIFT 2
-#define NV_FOPT_NMI_DIS_WIDTH 1
-#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
-#define NV_FOPT_FAST_INIT_MASK 0x20u
-#define NV_FOPT_FAST_INIT_SHIFT 5
-#define NV_FOPT_FAST_INIT_WIDTH 1
-#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_FAST_INIT_SHIFT))&NV_FOPT_FAST_INIT_MASK)
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT (0U)
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT (0U)
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT (0U)
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT (0U)
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT (0U)
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT (0U)
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT (0U)
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT (0U)
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK (0xFFU)
+#define NV_FPROT3_PROT_SHIFT (0U)
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK (0xFFU)
+#define NV_FPROT2_PROT_SHIFT (0U)
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK (0xFFU)
+#define NV_FPROT1_PROT_SHIFT (0U)
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK (0xFFU)
+#define NV_FPROT0_PROT_SHIFT (0U)
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK (0x3U)
+#define NV_FSEC_SEC_SHIFT (0U)
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK (0xCU)
+#define NV_FSEC_FSLACC_SHIFT (2U)
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK (0x30U)
+#define NV_FSEC_MEEN_SHIFT (4U)
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT (6U)
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT_MASK (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT (0U)
+#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
+#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
+#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_NMI_DIS_MASK (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT (2U)
+#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_FAST_INIT_MASK (0x20U)
+#define NV_FOPT_FAST_INIT_SHIFT (5U)
+#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
+
/*!
* @}
@@ -6842,44 +4836,11 @@ typedef struct {
#define FTFA_FlashConfig_BASE (0x400u)
/** Peripheral FTFA_FlashConfig base pointer */
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
-#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
/** Array initializer of NV peripheral base addresses */
#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
/** Array initializer of NV peripheral base pointers */
#define NV_BASE_PTRS { FTFA_FlashConfig }
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register instance definitions */
-/* FTFA_FlashConfig */
-#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
-#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
-#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
-#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
-#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
-#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
-#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
-#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
-#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
-#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
-#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
-#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
-#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
-#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
@@ -6899,26 +4860,7 @@ typedef struct {
__IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
uint8_t RESERVED_0[1];
__IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
-} OSC_Type, *OSC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register accessors */
-#define OSC_CR_REG(base) ((base)->CR)
-#define OSC_DIV_REG(base) ((base)->DIV)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
+} OSC_Type;
/* ----------------------------------------------------------------------------
-- OSC Register Masks
@@ -6929,36 +4871,31 @@ typedef struct {
* @{
*/
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC16P_WIDTH 1
-#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC8P_WIDTH 1
-#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC4P_WIDTH 1
-#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_SC2P_WIDTH 1
-#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_EREFSTEN_WIDTH 1
-#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-#define OSC_CR_ERCLKEN_WIDTH 1
-#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
-/* DIV Bit Fields */
-#define OSC_DIV_ERPS_MASK 0xC0u
-#define OSC_DIV_ERPS_SHIFT 6
-#define OSC_DIV_ERPS_WIDTH 2
-#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK (0x1U)
+#define OSC_CR_SC16P_SHIFT (0U)
+#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK (0x2U)
+#define OSC_CR_SC8P_SHIFT (1U)
+#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK (0x4U)
+#define OSC_CR_SC4P_SHIFT (2U)
+#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK (0x8U)
+#define OSC_CR_SC2P_SHIFT (3U)
+#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT (5U)
+#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT (7U)
+#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
+/*! @name DIV - OSC_DIV */
+#define OSC_DIV_ERPS_MASK (0xC0U)
+#define OSC_DIV_ERPS_SHIFT (6U)
+#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
+
/*!
* @}
@@ -6970,32 +4907,11 @@ typedef struct {
#define OSC_BASE (0x40065000u)
/** Peripheral OSC base pointer */
#define OSC ((OSC_Type *)OSC_BASE)
-#define OSC_BASE_PTR (OSC)
/** Array initializer of OSC peripheral base addresses */
#define OSC_BASE_ADDRS { OSC_BASE }
/** Array initializer of OSC peripheral base pointers */
#define OSC_BASE_PTRS { OSC }
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register instance definitions */
-/* OSC */
-#define OSC_CR OSC_CR_REG(OSC)
-#define OSC_DIV OSC_DIV_REG(OSC)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group OSC_Peripheral_Access_Layer */
@@ -7030,42 +4946,7 @@ typedef struct {
uint8_t RESERVED_1[56];
__IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
__IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
-} PDB_Type, *PDB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register accessors */
-#define PDB_SC_REG(base) ((base)->SC)
-#define PDB_MOD_REG(base) ((base)->MOD)
-#define PDB_CNT_REG(base) ((base)->CNT)
-#define PDB_IDLY_REG(base) ((base)->IDLY)
-#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
-#define PDB_C1_COUNT 2
-#define PDB_S_REG(base,index) ((base)->CH[index].S)
-#define PDB_S_COUNT 2
-#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
-#define PDB_DLY_COUNT 2
-#define PDB_DLY_COUNT2 2
-#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
-#define PDB_INTC_COUNT 1
-#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
-#define PDB_INT_COUNT 1
-#define PDB_POEN_REG(base) ((base)->POEN)
-#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
-#define PDB_PODLY_COUNT 2
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
+} PDB_Type;
/* ----------------------------------------------------------------------------
-- PDB Register Masks
@@ -7076,125 +4957,130 @@ typedef struct {
* @{
*/
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK 0x1u
-#define PDB_SC_LDOK_SHIFT 0
-#define PDB_SC_LDOK_WIDTH 1
-#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
-#define PDB_SC_CONT_MASK 0x2u
-#define PDB_SC_CONT_SHIFT 1
-#define PDB_SC_CONT_WIDTH 1
-#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
-#define PDB_SC_MULT_MASK 0xCu
-#define PDB_SC_MULT_SHIFT 2
-#define PDB_SC_MULT_WIDTH 2
-#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK 0x20u
-#define PDB_SC_PDBIE_SHIFT 5
-#define PDB_SC_PDBIE_WIDTH 1
-#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
-#define PDB_SC_PDBIF_MASK 0x40u
-#define PDB_SC_PDBIF_SHIFT 6
-#define PDB_SC_PDBIF_WIDTH 1
-#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
-#define PDB_SC_PDBEN_MASK 0x80u
-#define PDB_SC_PDBEN_SHIFT 7
-#define PDB_SC_PDBEN_WIDTH 1
-#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
-#define PDB_SC_TRGSEL_MASK 0xF00u
-#define PDB_SC_TRGSEL_SHIFT 8
-#define PDB_SC_TRGSEL_WIDTH 4
-#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK 0x7000u
-#define PDB_SC_PRESCALER_SHIFT 12
-#define PDB_SC_PRESCALER_WIDTH 3
-#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK 0x8000u
-#define PDB_SC_DMAEN_SHIFT 15
-#define PDB_SC_DMAEN_WIDTH 1
-#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
-#define PDB_SC_SWTRIG_MASK 0x10000u
-#define PDB_SC_SWTRIG_SHIFT 16
-#define PDB_SC_SWTRIG_WIDTH 1
-#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
-#define PDB_SC_PDBEIE_MASK 0x20000u
-#define PDB_SC_PDBEIE_SHIFT 17
-#define PDB_SC_PDBEIE_WIDTH 1
-#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
-#define PDB_SC_LDMOD_MASK 0xC0000u
-#define PDB_SC_LDMOD_SHIFT 18
-#define PDB_SC_LDMOD_WIDTH 2
-#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK 0xFFFFu
-#define PDB_MOD_MOD_SHIFT 0
-#define PDB_MOD_MOD_WIDTH 16
-#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK 0xFFFFu
-#define PDB_CNT_CNT_SHIFT 0
-#define PDB_CNT_CNT_WIDTH 16
-#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK 0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT 0
-#define PDB_IDLY_IDLY_WIDTH 16
-#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK 0xFFu
-#define PDB_C1_EN_SHIFT 0
-#define PDB_C1_EN_WIDTH 8
-#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK 0xFF00u
-#define PDB_C1_TOS_SHIFT 8
-#define PDB_C1_TOS_WIDTH 8
-#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK 0xFF0000u
-#define PDB_C1_BB_SHIFT 16
-#define PDB_C1_BB_WIDTH 8
-#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK 0xFFu
-#define PDB_S_ERR_SHIFT 0
-#define PDB_S_ERR_WIDTH 8
-#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK 0xFF0000u
-#define PDB_S_CF_SHIFT 16
-#define PDB_S_CF_WIDTH 8
-#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK 0xFFFFu
-#define PDB_DLY_DLY_SHIFT 0
-#define PDB_DLY_DLY_WIDTH 16
-#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* INTC Bit Fields */
-#define PDB_INTC_TOE_MASK 0x1u
-#define PDB_INTC_TOE_SHIFT 0
-#define PDB_INTC_TOE_WIDTH 1
-#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
-#define PDB_INTC_EXT_MASK 0x2u
-#define PDB_INTC_EXT_SHIFT 1
-#define PDB_INTC_EXT_WIDTH 1
-#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
-/* INT Bit Fields */
-#define PDB_INT_INT_MASK 0xFFFFu
-#define PDB_INT_INT_SHIFT 0
-#define PDB_INT_INT_WIDTH 16
-#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK 0xFFu
-#define PDB_POEN_POEN_SHIFT 0
-#define PDB_POEN_POEN_WIDTH 8
-#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK 0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT 0
-#define PDB_PODLY_DLY2_WIDTH 16
-#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT 16
-#define PDB_PODLY_DLY1_WIDTH 16
-#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+/*! @name SC - Status and Control register */
+#define PDB_SC_LDOK_MASK (0x1U)
+#define PDB_SC_LDOK_SHIFT (0U)
+#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK (0x2U)
+#define PDB_SC_CONT_SHIFT (1U)
+#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK (0xCU)
+#define PDB_SC_MULT_SHIFT (2U)
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK (0x20U)
+#define PDB_SC_PDBIE_SHIFT (5U)
+#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK (0x40U)
+#define PDB_SC_PDBIF_SHIFT (6U)
+#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK (0x80U)
+#define PDB_SC_PDBEN_SHIFT (7U)
+#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT (8U)
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT (12U)
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK (0x8000U)
+#define PDB_SC_DMAEN_SHIFT (15U)
+#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK (0x10000U)
+#define PDB_SC_SWTRIG_SHIFT (16U)
+#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK (0x20000U)
+#define PDB_SC_PDBEIE_SHIFT (17U)
+#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT (18U)
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+
+/*! @name MOD - Modulus register */
+#define PDB_MOD_MOD_MASK (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT (0U)
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+
+/*! @name CNT - Counter register */
+#define PDB_CNT_CNT_MASK (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT (0U)
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+
+/*! @name IDLY - Interrupt Delay register */
+#define PDB_IDLY_IDLY_MASK (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT (0U)
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+
+/*! @name C1 - Channel n Control register 1 */
+#define PDB_C1_EN_MASK (0xFFU)
+#define PDB_C1_EN_SHIFT (0U)
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK (0xFF00U)
+#define PDB_C1_TOS_SHIFT (8U)
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK (0xFF0000U)
+#define PDB_C1_BB_SHIFT (16U)
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT (2U)
+
+/*! @name S - Channel n Status register */
+#define PDB_S_ERR_MASK (0xFFU)
+#define PDB_S_ERR_SHIFT (0U)
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK (0xFF0000U)
+#define PDB_S_CF_SHIFT (16U)
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+
+/* The count of PDB_S */
+#define PDB_S_COUNT (2U)
+
+/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
+#define PDB_DLY_DLY_MASK (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT (0U)
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT (2U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2 (2U)
+
+/*! @name INTC - DAC Interval Trigger n Control register */
+#define PDB_INTC_TOE_MASK (0x1U)
+#define PDB_INTC_TOE_SHIFT (0U)
+#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK (0x2U)
+#define PDB_INTC_EXT_SHIFT (1U)
+#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+
+/* The count of PDB_INTC */
+#define PDB_INTC_COUNT (1U)
+
+/*! @name INT - DAC Interval n register */
+#define PDB_INT_INT_MASK (0xFFFFU)
+#define PDB_INT_INT_SHIFT (0U)
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+
+/* The count of PDB_INT */
+#define PDB_INT_COUNT (1U)
+
+/*! @name POEN - Pulse-Out n Enable register */
+#define PDB_POEN_POEN_MASK (0xFFU)
+#define PDB_POEN_POEN_SHIFT (0U)
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+
+/*! @name PODLY - Pulse-Out n Delay register */
+#define PDB_PODLY_DLY2_MASK (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT (0U)
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT (16U)
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT (2U)
+
/*!
* @}
@@ -7206,7 +5092,6 @@ typedef struct {
#define PDB0_BASE (0x40036000u)
/** Peripheral PDB0 base pointer */
#define PDB0 ((PDB_Type *)PDB0_BASE)
-#define PDB0_BASE_PTR (PDB0)
/** Array initializer of PDB peripheral base addresses */
#define PDB_BASE_ADDRS { PDB0_BASE }
/** Array initializer of PDB peripheral base pointers */
@@ -7214,49 +5099,6 @@ typedef struct {
/** Interrupt vectors for the PDB peripheral type */
#define PDB_IRQS { PDB0_IRQn }
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register instance definitions */
-/* PDB0 */
-#define PDB0_SC PDB_SC_REG(PDB0)
-#define PDB0_MOD PDB_MOD_REG(PDB0)
-#define PDB0_CNT PDB_CNT_REG(PDB0)
-#define PDB0_IDLY PDB_IDLY_REG(PDB0)
-#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
-#define PDB0_CH0S PDB_S_REG(PDB0,0)
-#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
-#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
-#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
-#define PDB0_CH1S PDB_S_REG(PDB0,1)
-#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
-#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
-#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
-#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
-#define PDB0_POEN PDB_POEN_REG(PDB0)
-#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
-#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
-
-/* PDB - Register array accessors */
-#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
-#define PDB0_S(index) PDB_S_REG(PDB0,index)
-#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
-#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
-#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
-#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PDB_Peripheral_Access_Layer */
@@ -7281,80 +5123,63 @@ typedef struct {
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[4];
-} PIT_Type, *PIT_MemMapPtr;
+} PIT_Type;
/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
+ -- PIT Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK (0x1U)
+#define PIT_MCR_FRZ_SHIFT (0U)
+#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK (0x2U)
+#define PIT_MCR_MDIS_SHIFT (1U)
+#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
-/* PIT - Register accessors */
-#define PIT_MCR_REG(base) ((base)->MCR)
-#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
-#define PIT_LDVAL_COUNT 4
-#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
-#define PIT_CVAL_COUNT 4
-#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
-#define PIT_TCTRL_COUNT 4
-#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
-#define PIT_TFLG_COUNT 4
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT (0U)
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT (4U)
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT (0U)
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT (4U)
-/*!
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK (0x1U)
+#define PIT_TCTRL_TEN_SHIFT (0U)
+#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK (0x2U)
+#define PIT_TCTRL_TIE_SHIFT (1U)
+#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK (0x4U)
+#define PIT_TCTRL_CHN_SHIFT (2U)
+#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK (0x1U)
+#define PIT_TFLG_TIF_SHIFT (0U)
+#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT (4U)
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_FRZ_WIDTH 1
-#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-#define PIT_MCR_MDIS_WIDTH 1
-#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV_WIDTH 32
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL_WIDTH 32
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TEN_WIDTH 1
-#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-#define PIT_TCTRL_TIE_WIDTH 1
-#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
-#define PIT_TCTRL_CHN_MASK 0x4u
-#define PIT_TCTRL_CHN_SHIFT 2
-#define PIT_TCTRL_CHN_WIDTH 1
-#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-#define PIT_TFLG_TIF_WIDTH 1
-#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
/*!
* @}
@@ -7366,54 +5191,12 @@ typedef struct {
#define PIT_BASE (0x40037000u)
/** Peripheral PIT base pointer */
#define PIT ((PIT_Type *)PIT_BASE)
-#define PIT_BASE_PTR (PIT)
/** Array initializer of PIT peripheral base addresses */
#define PIT_BASE_ADDRS { PIT_BASE }
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASE_PTRS { PIT }
/** Interrupt vectors for the PIT peripheral type */
-#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register instance definitions */
-/* PIT */
-#define PIT_MCR PIT_MCR_REG(PIT)
-#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
-#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
-#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
-#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
-#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
-#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
-#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
-#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
-#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
-#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
-#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
-#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
-#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
-#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
-#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
-#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
-
-/* PIT - Register array accessors */
-#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
-#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
-#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
-#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
+#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
/*!
* @}
@@ -7434,27 +5217,7 @@ typedef struct {
__IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
__IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
__IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type, *PMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register accessors */
-#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
-#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
-#define PMC_REGSC_REG(base) ((base)->REGSC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
+} PMC_Type;
/* ----------------------------------------------------------------------------
-- PMC Register Masks
@@ -7465,61 +5228,51 @@ typedef struct {
* @{
*/
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV_WIDTH 2
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDRE_WIDTH 1
-#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDIE_WIDTH 1
-#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDACK_WIDTH 1
-#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-#define PMC_LVDSC1_LVDF_WIDTH 1
-#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV_WIDTH 2
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWIE_WIDTH 1
-#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWACK_WIDTH 1
-#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-#define PMC_LVDSC2_LVWF_WIDTH 1
-#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_BGBE_WIDTH 1
-#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_REGONS_WIDTH 1
-#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-#define PMC_REGSC_ACKISO_WIDTH 1
-#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
-#define PMC_REGSC_BGEN_MASK 0x10u
-#define PMC_REGSC_BGEN_SHIFT 4
-#define PMC_REGSC_BGEN_WIDTH 1
-#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT (0U)
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT (4U)
+#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT (5U)
+#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT (6U)
+#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT (7U)
+#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT (0U)
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT (5U)
+#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT (6U)
+#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT (7U)
+#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK (0x1U)
+#define PMC_REGSC_BGBE_SHIFT (0U)
+#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK (0x4U)
+#define PMC_REGSC_REGONS_SHIFT (2U)
+#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT (3U)
+#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK (0x10U)
+#define PMC_REGSC_BGEN_SHIFT (4U)
+#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+
/*!
* @}
@@ -7531,7 +5284,6 @@ typedef struct {
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
-#define PMC_BASE_PTR (PMC)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS { PMC_BASE }
/** Array initializer of PMC peripheral base pointers */
@@ -7539,27 +5291,6 @@ typedef struct {
/** Interrupt vectors for the PMC peripheral type */
#define PMC_IRQS { LVD_LVW_IRQn }
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register instance definitions */
-/* PMC */
-#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
-#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
-#define PMC_REGSC PMC_REGSC_REG(PMC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
@@ -7585,32 +5316,7 @@ typedef struct {
__IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type, *PORT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register accessors */
-#define PORT_PCR_REG(base,index) ((base)->PCR[index])
-#define PORT_PCR_COUNT 32
-#define PORT_GPCLR_REG(base) ((base)->GPCLR)
-#define PORT_GPCHR_REG(base) ((base)->GPCHR)
-#define PORT_ISFR_REG(base) ((base)->ISFR)
-#define PORT_DFER_REG(base) ((base)->DFER)
-#define PORT_DFCR_REG(base) ((base)->DFCR)
-#define PORT_DFWR_REG(base) ((base)->DFWR)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
+} PORT_Type;
/* ----------------------------------------------------------------------------
-- PORT Register Masks
@@ -7621,85 +5327,77 @@ typedef struct {
* @{
*/
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PS_WIDTH 1
-#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_PE_WIDTH 1
-#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_SRE_WIDTH 1
-#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_PFE_WIDTH 1
-#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
-#define PORT_PCR_ODE_MASK 0x20u
-#define PORT_PCR_ODE_SHIFT 5
-#define PORT_PCR_ODE_WIDTH 1
-#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_DSE_WIDTH 1
-#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX_WIDTH 3
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK 0x8000u
-#define PORT_PCR_LK_SHIFT 15
-#define PORT_PCR_LK_WIDTH 1
-#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC_WIDTH 4
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-#define PORT_PCR_ISF_WIDTH 1
-#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD_WIDTH 16
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE_WIDTH 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD_WIDTH 16
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE_WIDTH 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF_WIDTH 32
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT 0
-#define PORT_DFER_DFE_WIDTH 32
-#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK 0x1u
-#define PORT_DFCR_CS_SHIFT 0
-#define PORT_DFCR_CS_WIDTH 1
-#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK 0x1Fu
-#define PORT_DFWR_FILT_SHIFT 0
-#define PORT_DFWR_FILT_WIDTH 5
-#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK (0x1U)
+#define PORT_PCR_PS_SHIFT (0U)
+#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK (0x2U)
+#define PORT_PCR_PE_SHIFT (1U)
+#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK (0x4U)
+#define PORT_PCR_SRE_SHIFT (2U)
+#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK (0x10U)
+#define PORT_PCR_PFE_SHIFT (4U)
+#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK (0x20U)
+#define PORT_PCR_ODE_SHIFT (5U)
+#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK (0x40U)
+#define PORT_PCR_DSE_SHIFT (6U)
+#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK (0x700U)
+#define PORT_PCR_MUX_SHIFT (8U)
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK (0x8000U)
+#define PORT_PCR_LK_SHIFT (15U)
+#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT (16U)
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK (0x1000000U)
+#define PORT_PCR_ISF_SHIFT (24U)
+#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT (0U)
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT (16U)
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT (0U)
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT (16U)
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT (0U)
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+/*! @name DFER - Digital Filter Enable Register */
+#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT (0U)
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+
+/*! @name DFCR - Digital Filter Clock Register */
+#define PORT_DFCR_CS_MASK (0x1U)
+#define PORT_DFCR_CS_SHIFT (0U)
+#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+
+/*! @name DFWR - Digital Filter Width Register */
+#define PORT_DFWR_FILT_MASK (0x1FU)
+#define PORT_DFWR_FILT_SHIFT (0U)
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+
/*!
* @}
@@ -7711,27 +5409,22 @@ typedef struct {
#define PORTA_BASE (0x40049000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
-#define PORTA_BASE_PTR (PORTA)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4004A000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
-#define PORTB_BASE_PTR (PORTB)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x4004B000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
-#define PORTC_BASE_PTR (PORTC)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4004C000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
-#define PORTD_BASE_PTR (PORTD)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4004D000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
-#define PORTE_BASE_PTR (PORTE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
/** Array initializer of PORT peripheral base pointers */
@@ -7739,213 +5432,6 @@ typedef struct {
/** Interrupt vectors for the PORT peripheral type */
#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register instance definitions */
-/* PORTA */
-#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
-#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
-#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
-#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
-#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
-#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
-#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
-#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
-#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
-#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
-#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
-#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
-#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
-#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
-#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
-#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
-#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
-#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
-#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
-#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
-#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
-#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
-#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
-#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
-#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
-#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
-#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
-#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
-#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
-#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
-#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
-#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
-#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
-#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
-#define PORTA_ISFR PORT_ISFR_REG(PORTA)
-/* PORTB */
-#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
-#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
-#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
-#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
-#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
-#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
-#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
-#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
-#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
-#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
-#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
-#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
-#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
-#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
-#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
-#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
-#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
-#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
-#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
-#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
-#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
-#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
-#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
-#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
-#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
-#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
-#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
-#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
-#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
-#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
-#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
-#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
-#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
-#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
-#define PORTB_ISFR PORT_ISFR_REG(PORTB)
-/* PORTC */
-#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
-#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
-#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
-#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
-#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
-#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
-#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
-#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
-#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
-#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
-#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
-#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
-#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
-#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
-#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
-#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
-#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
-#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
-#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
-#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
-#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
-#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
-#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
-#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
-#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
-#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
-#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
-#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
-#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
-#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
-#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
-#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
-#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
-#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
-#define PORTC_ISFR PORT_ISFR_REG(PORTC)
-/* PORTD */
-#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
-#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
-#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
-#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
-#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
-#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
-#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
-#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
-#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
-#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
-#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
-#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
-#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
-#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
-#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
-#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
-#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
-#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
-#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
-#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
-#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
-#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
-#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
-#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
-#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
-#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
-#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
-#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
-#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
-#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
-#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
-#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
-#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
-#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
-#define PORTD_ISFR PORT_ISFR_REG(PORTD)
-#define PORTD_DFER PORT_DFER_REG(PORTD)
-#define PORTD_DFCR PORT_DFCR_REG(PORTD)
-#define PORTD_DFWR PORT_DFWR_REG(PORTD)
-/* PORTE */
-#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
-#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
-#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
-#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
-#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
-#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
-#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
-#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
-#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
-#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
-#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
-#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
-#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
-#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
-#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
-#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
-#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
-#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
-#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
-#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
-#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
-#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
-#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
-#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
-#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
-#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
-#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
-#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
-#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
-#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
-#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
-#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
-#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
-#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
-#define PORTE_ISFR PORT_ISFR_REG(PORTE)
-
-/* PORT - Register array accessors */
-#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
-#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
-#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
-#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
-#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
@@ -7971,31 +5457,7 @@ typedef struct {
__I uint8_t MR; /**< Mode Register, offset: 0x7 */
__IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
__IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
-} RCM_Type, *RCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register accessors */
-#define RCM_SRS0_REG(base) ((base)->SRS0)
-#define RCM_SRS1_REG(base) ((base)->SRS1)
-#define RCM_RPFC_REG(base) ((base)->RPFC)
-#define RCM_RPFW_REG(base) ((base)->RPFW)
-#define RCM_MR_REG(base) ((base)->MR)
-#define RCM_SSRS0_REG(base) ((base)->SSRS0)
-#define RCM_SSRS1_REG(base) ((base)->SSRS1)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
+} RCM_Type;
/* ----------------------------------------------------------------------------
-- RCM Register Masks
@@ -8006,125 +5468,104 @@ typedef struct {
* @{
*/
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_WAKEUP_WIDTH 1
-#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LVD_WIDTH 1
-#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOC_WIDTH 1
-#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_WDOG_WIDTH 1
-#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_PIN_WIDTH 1
-#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-#define RCM_SRS0_POR_WIDTH 1
-#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK 0x1u
-#define RCM_SRS1_JTAG_SHIFT 0
-#define RCM_SRS1_JTAG_WIDTH 1
-#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_LOCKUP_WIDTH 1
-#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_SW_WIDTH 1
-#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_MDM_AP_WIDTH 1
-#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
-#define RCM_SRS1_EZPT_MASK 0x10u
-#define RCM_SRS1_EZPT_SHIFT 4
-#define RCM_SRS1_EZPT_WIDTH 1
-#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-#define RCM_SRS1_SACKERR_WIDTH 1
-#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW_WIDTH 2
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-#define RCM_RPFC_RSTFLTSS_WIDTH 1
-#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL_WIDTH 5
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK 0x2u
-#define RCM_MR_EZP_MS_SHIFT 1
-#define RCM_MR_EZP_MS_WIDTH 1
-#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
-/* SSRS0 Bit Fields */
-#define RCM_SSRS0_SWAKEUP_MASK 0x1u
-#define RCM_SSRS0_SWAKEUP_SHIFT 0
-#define RCM_SSRS0_SWAKEUP_WIDTH 1
-#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWAKEUP_SHIFT))&RCM_SSRS0_SWAKEUP_MASK)
-#define RCM_SSRS0_SLVD_MASK 0x2u
-#define RCM_SSRS0_SLVD_SHIFT 1
-#define RCM_SSRS0_SLVD_WIDTH 1
-#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLVD_SHIFT))&RCM_SSRS0_SLVD_MASK)
-#define RCM_SSRS0_SLOC_MASK 0x4u
-#define RCM_SSRS0_SLOC_SHIFT 2
-#define RCM_SSRS0_SLOC_WIDTH 1
-#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLOC_SHIFT))&RCM_SSRS0_SLOC_MASK)
-#define RCM_SSRS0_SWDOG_MASK 0x20u
-#define RCM_SSRS0_SWDOG_SHIFT 5
-#define RCM_SSRS0_SWDOG_WIDTH 1
-#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWDOG_SHIFT))&RCM_SSRS0_SWDOG_MASK)
-#define RCM_SSRS0_SPIN_MASK 0x40u
-#define RCM_SSRS0_SPIN_SHIFT 6
-#define RCM_SSRS0_SPIN_WIDTH 1
-#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPIN_SHIFT))&RCM_SSRS0_SPIN_MASK)
-#define RCM_SSRS0_SPOR_MASK 0x80u
-#define RCM_SSRS0_SPOR_SHIFT 7
-#define RCM_SSRS0_SPOR_WIDTH 1
-#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPOR_SHIFT))&RCM_SSRS0_SPOR_MASK)
-/* SSRS1 Bit Fields */
-#define RCM_SSRS1_SJTAG_MASK 0x1u
-#define RCM_SSRS1_SJTAG_SHIFT 0
-#define RCM_SSRS1_SJTAG_WIDTH 1
-#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SJTAG_SHIFT))&RCM_SSRS1_SJTAG_MASK)
-#define RCM_SSRS1_SLOCKUP_MASK 0x2u
-#define RCM_SSRS1_SLOCKUP_SHIFT 1
-#define RCM_SSRS1_SLOCKUP_WIDTH 1
-#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SLOCKUP_SHIFT))&RCM_SSRS1_SLOCKUP_MASK)
-#define RCM_SSRS1_SSW_MASK 0x4u
-#define RCM_SSRS1_SSW_SHIFT 2
-#define RCM_SSRS1_SSW_WIDTH 1
-#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSW_SHIFT))&RCM_SSRS1_SSW_MASK)
-#define RCM_SSRS1_SMDM_AP_MASK 0x8u
-#define RCM_SSRS1_SMDM_AP_SHIFT 3
-#define RCM_SSRS1_SMDM_AP_WIDTH 1
-#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SMDM_AP_SHIFT))&RCM_SSRS1_SMDM_AP_MASK)
-#define RCM_SSRS1_SEZPT_MASK 0x10u
-#define RCM_SSRS1_SEZPT_SHIFT 4
-#define RCM_SSRS1_SEZPT_WIDTH 1
-#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SEZPT_SHIFT))&RCM_SSRS1_SEZPT_MASK)
-#define RCM_SSRS1_SSACKERR_MASK 0x20u
-#define RCM_SSRS1_SSACKERR_SHIFT 5
-#define RCM_SSRS1_SSACKERR_WIDTH 1
-#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSACKERR_SHIFT))&RCM_SSRS1_SSACKERR_MASK)
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT (0U)
+#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK (0x2U)
+#define RCM_SRS0_LVD_SHIFT (1U)
+#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK (0x4U)
+#define RCM_SRS0_LOC_SHIFT (2U)
+#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_WDOG_MASK (0x20U)
+#define RCM_SRS0_WDOG_SHIFT (5U)
+#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK (0x40U)
+#define RCM_SRS0_PIN_SHIFT (6U)
+#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK (0x80U)
+#define RCM_SRS0_POR_SHIFT (7U)
+#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_JTAG_MASK (0x1U)
+#define RCM_SRS1_JTAG_SHIFT (0U)
+#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT (1U)
+#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK (0x4U)
+#define RCM_SRS1_SW_SHIFT (2U)
+#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT (3U)
+#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK (0x10U)
+#define RCM_SRS1_EZPT_SHIFT (4U)
+#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT (5U)
+#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
+#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_EZP_MS_MASK (0x2U)
+#define RCM_MR_EZP_MS_SHIFT (1U)
+#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+
+/*! @name SSRS0 - Sticky System Reset Status Register 0 */
+#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
+#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
+#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SLVD_MASK (0x2U)
+#define RCM_SSRS0_SLVD_SHIFT (1U)
+#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SLOC_MASK (0x4U)
+#define RCM_SSRS0_SLOC_SHIFT (2U)
+#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
+#define RCM_SSRS0_SWDOG_MASK (0x20U)
+#define RCM_SSRS0_SWDOG_SHIFT (5U)
+#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SPIN_MASK (0x40U)
+#define RCM_SSRS0_SPIN_SHIFT (6U)
+#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPOR_MASK (0x80U)
+#define RCM_SSRS0_SPOR_SHIFT (7U)
+#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+
+/*! @name SSRS1 - Sticky System Reset Status Register 1 */
+#define RCM_SSRS1_SJTAG_MASK (0x1U)
+#define RCM_SSRS1_SJTAG_SHIFT (0U)
+#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
+#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
+#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
+#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SSW_MASK (0x4U)
+#define RCM_SSRS1_SSW_SHIFT (2U)
+#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
+#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
+#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SEZPT_MASK (0x10U)
+#define RCM_SSRS1_SEZPT_SHIFT (4U)
+#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
+#define RCM_SSRS1_SSACKERR_MASK (0x20U)
+#define RCM_SSRS1_SSACKERR_SHIFT (5U)
+#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+
/*!
* @}
@@ -8136,37 +5577,11 @@ typedef struct {
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
-#define RCM_BASE_PTR (RCM)
/** Array initializer of RCM peripheral base addresses */
#define RCM_BASE_ADDRS { RCM_BASE }
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASE_PTRS { RCM }
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register instance definitions */
-/* RCM */
-#define RCM_SRS0 RCM_SRS0_REG(RCM)
-#define RCM_SRS1 RCM_SRS1_REG(RCM)
-#define RCM_RPFC RCM_RPFC_REG(RCM)
-#define RCM_RPFW RCM_RPFW_REG(RCM)
-#define RCM_MR RCM_MR_REG(RCM)
-#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
-#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
@@ -8184,26 +5599,7 @@ typedef struct {
/** RFSYS - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type, *RFSYS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register accessors */
-#define RFSYS_REG_REG(base,index) ((base)->REG[index])
-#define RFSYS_REG_COUNT 8
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
+} RFSYS_Type;
/* ----------------------------------------------------------------------------
-- RFSYS Register Masks
@@ -8214,23 +5610,23 @@ typedef struct {
* @{
*/
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK 0xFFu
-#define RFSYS_REG_LL_SHIFT 0
-#define RFSYS_REG_LL_WIDTH 8
-#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK 0xFF00u
-#define RFSYS_REG_LH_SHIFT 8
-#define RFSYS_REG_LH_WIDTH 8
-#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK 0xFF0000u
-#define RFSYS_REG_HL_SHIFT 16
-#define RFSYS_REG_HL_WIDTH 8
-#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK 0xFF000000u
-#define RFSYS_REG_HH_SHIFT 24
-#define RFSYS_REG_HH_WIDTH 8
-#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK (0xFFU)
+#define RFSYS_REG_LL_SHIFT (0U)
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK (0xFF00U)
+#define RFSYS_REG_LH_SHIFT (8U)
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT (16U)
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT (24U)
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT (8U)
+
/*!
* @}
@@ -8242,41 +5638,11 @@ typedef struct {
#define RFSYS_BASE (0x40041000u)
/** Peripheral RFSYS base pointer */
#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
-#define RFSYS_BASE_PTR (RFSYS)
/** Array initializer of RFSYS peripheral base addresses */
#define RFSYS_BASE_ADDRS { RFSYS_BASE }
/** Array initializer of RFSYS peripheral base pointers */
#define RFSYS_BASE_PTRS { RFSYS }
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register instance definitions */
-/* RFSYS */
-#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
-#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
-#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
-#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
-#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
-#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
-#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
-#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
-
-/* RFSYS - Register array accessors */
-#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RFSYS_Peripheral_Access_Layer */
@@ -8292,28 +5658,9 @@ typedef struct {
*/
/** RFVBAT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type, *RFVBAT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register accessors */
-#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
-#define RFVBAT_REG_COUNT 8
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
/* ----------------------------------------------------------------------------
-- RFVBAT Register Masks
@@ -8324,23 +5671,23 @@ typedef struct {
* @{
*/
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK 0xFFu
-#define RFVBAT_REG_LL_SHIFT 0
-#define RFVBAT_REG_LL_WIDTH 8
-#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK 0xFF00u
-#define RFVBAT_REG_LH_SHIFT 8
-#define RFVBAT_REG_LH_WIDTH 8
-#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK 0xFF0000u
-#define RFVBAT_REG_HL_SHIFT 16
-#define RFVBAT_REG_HL_WIDTH 8
-#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK 0xFF000000u
-#define RFVBAT_REG_HH_SHIFT 24
-#define RFVBAT_REG_HH_WIDTH 8
-#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK (0xFFU)
+#define RFVBAT_REG_LL_SHIFT (0U)
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT (8U)
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT (16U)
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT (24U)
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT (8U)
+
/*!
* @}
@@ -8352,41 +5699,11 @@ typedef struct {
#define RFVBAT_BASE (0x4003E000u)
/** Peripheral RFVBAT base pointer */
#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
-#define RFVBAT_BASE_PTR (RFVBAT)
/** Array initializer of RFVBAT peripheral base addresses */
#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
/** Array initializer of RFVBAT peripheral base pointers */
#define RFVBAT_BASE_PTRS { RFVBAT }
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register instance definitions */
-/* RFVBAT */
-#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
-#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
-#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
-#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
-#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
-#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
-#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
-#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
-
-/* RFVBAT - Register array accessors */
-#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RFVBAT_Peripheral_Access_Layer */
@@ -8414,34 +5731,7 @@ typedef struct {
uint8_t RESERVED_0[2016];
__IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
__IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type, *RTC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register accessors */
-#define RTC_TSR_REG(base) ((base)->TSR)
-#define RTC_TPR_REG(base) ((base)->TPR)
-#define RTC_TAR_REG(base) ((base)->TAR)
-#define RTC_TCR_REG(base) ((base)->TCR)
-#define RTC_CR_REG(base) ((base)->CR)
-#define RTC_SR_REG(base) ((base)->SR)
-#define RTC_LR_REG(base) ((base)->LR)
-#define RTC_IER_REG(base) ((base)->IER)
-#define RTC_WAR_REG(base) ((base)->WAR)
-#define RTC_RAR_REG(base) ((base)->RAR)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
+} RTC_Type;
/* ----------------------------------------------------------------------------
-- RTC Register Masks
@@ -8452,204 +5742,167 @@ typedef struct {
* @{
*/
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR_WIDTH 32
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR_WIDTH 16
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR_WIDTH 32
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR_WIDTH 8
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR_WIDTH 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV_WIDTH 8
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC_WIDTH 8
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_SWR_WIDTH 1
-#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_WPE_WIDTH 1
-#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_SUP_WIDTH 1
-#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_UM_WIDTH 1
-#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
-#define RTC_CR_WPS_MASK 0x10u
-#define RTC_CR_WPS_SHIFT 4
-#define RTC_CR_WPS_WIDTH 1
-#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_OSCE_WIDTH 1
-#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_CLKO_WIDTH 1
-#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC16P_WIDTH 1
-#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC8P_WIDTH 1
-#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC4P_WIDTH 1
-#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-#define RTC_CR_SC2P_WIDTH 1
-#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TIF_WIDTH 1
-#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TOF_WIDTH 1
-#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TAF_WIDTH 1
-#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-#define RTC_SR_TCE_WIDTH 1
-#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_TCL_WIDTH 1
-#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_CRL_WIDTH 1
-#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_SRL_WIDTH 1
-#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-#define RTC_LR_LRL_WIDTH 1
-#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TIIE_WIDTH 1
-#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TOIE_WIDTH 1
-#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TAIE_WIDTH 1
-#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-#define RTC_IER_TSIE_WIDTH 1
-#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
-#define RTC_IER_WPON_MASK 0x80u
-#define RTC_IER_WPON_SHIFT 7
-#define RTC_IER_WPON_WIDTH 1
-#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK 0x1u
-#define RTC_WAR_TSRW_SHIFT 0
-#define RTC_WAR_TSRW_WIDTH 1
-#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
-#define RTC_WAR_TPRW_MASK 0x2u
-#define RTC_WAR_TPRW_SHIFT 1
-#define RTC_WAR_TPRW_WIDTH 1
-#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
-#define RTC_WAR_TARW_MASK 0x4u
-#define RTC_WAR_TARW_SHIFT 2
-#define RTC_WAR_TARW_WIDTH 1
-#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
-#define RTC_WAR_TCRW_MASK 0x8u
-#define RTC_WAR_TCRW_SHIFT 3
-#define RTC_WAR_TCRW_WIDTH 1
-#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
-#define RTC_WAR_CRW_MASK 0x10u
-#define RTC_WAR_CRW_SHIFT 4
-#define RTC_WAR_CRW_WIDTH 1
-#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
-#define RTC_WAR_SRW_MASK 0x20u
-#define RTC_WAR_SRW_SHIFT 5
-#define RTC_WAR_SRW_WIDTH 1
-#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
-#define RTC_WAR_LRW_MASK 0x40u
-#define RTC_WAR_LRW_SHIFT 6
-#define RTC_WAR_LRW_WIDTH 1
-#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
-#define RTC_WAR_IERW_MASK 0x80u
-#define RTC_WAR_IERW_SHIFT 7
-#define RTC_WAR_IERW_WIDTH 1
-#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK 0x1u
-#define RTC_RAR_TSRR_SHIFT 0
-#define RTC_RAR_TSRR_WIDTH 1
-#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
-#define RTC_RAR_TPRR_MASK 0x2u
-#define RTC_RAR_TPRR_SHIFT 1
-#define RTC_RAR_TPRR_WIDTH 1
-#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
-#define RTC_RAR_TARR_MASK 0x4u
-#define RTC_RAR_TARR_SHIFT 2
-#define RTC_RAR_TARR_WIDTH 1
-#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
-#define RTC_RAR_TCRR_MASK 0x8u
-#define RTC_RAR_TCRR_SHIFT 3
-#define RTC_RAR_TCRR_WIDTH 1
-#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
-#define RTC_RAR_CRR_MASK 0x10u
-#define RTC_RAR_CRR_SHIFT 4
-#define RTC_RAR_CRR_WIDTH 1
-#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
-#define RTC_RAR_SRR_MASK 0x20u
-#define RTC_RAR_SRR_SHIFT 5
-#define RTC_RAR_SRR_WIDTH 1
-#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
-#define RTC_RAR_LRR_MASK 0x40u
-#define RTC_RAR_LRR_SHIFT 6
-#define RTC_RAR_LRR_WIDTH 1
-#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
-#define RTC_RAR_IERR_MASK 0x80u
-#define RTC_RAR_IERR_SHIFT 7
-#define RTC_RAR_IERR_WIDTH 1
-#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT (0U)
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT (0U)
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT (0U)
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK (0xFFU)
+#define RTC_TCR_TCR_SHIFT (0U)
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK (0xFF00U)
+#define RTC_TCR_CIR_SHIFT (8U)
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT (16U)
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT (24U)
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK (0x1U)
+#define RTC_CR_SWR_SHIFT (0U)
+#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK (0x2U)
+#define RTC_CR_WPE_SHIFT (1U)
+#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK (0x4U)
+#define RTC_CR_SUP_SHIFT (2U)
+#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK (0x8U)
+#define RTC_CR_UM_SHIFT (3U)
+#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK (0x10U)
+#define RTC_CR_WPS_SHIFT (4U)
+#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK (0x100U)
+#define RTC_CR_OSCE_SHIFT (8U)
+#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK (0x200U)
+#define RTC_CR_CLKO_SHIFT (9U)
+#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK (0x400U)
+#define RTC_CR_SC16P_SHIFT (10U)
+#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK (0x800U)
+#define RTC_CR_SC8P_SHIFT (11U)
+#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK (0x1000U)
+#define RTC_CR_SC4P_SHIFT (12U)
+#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK (0x2000U)
+#define RTC_CR_SC2P_SHIFT (13U)
+#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK (0x1U)
+#define RTC_SR_TIF_SHIFT (0U)
+#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK (0x2U)
+#define RTC_SR_TOF_SHIFT (1U)
+#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK (0x4U)
+#define RTC_SR_TAF_SHIFT (2U)
+#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK (0x10U)
+#define RTC_SR_TCE_SHIFT (4U)
+#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK (0x8U)
+#define RTC_LR_TCL_SHIFT (3U)
+#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK (0x10U)
+#define RTC_LR_CRL_SHIFT (4U)
+#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK (0x20U)
+#define RTC_LR_SRL_SHIFT (5U)
+#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK (0x40U)
+#define RTC_LR_LRL_SHIFT (6U)
+#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK (0x1U)
+#define RTC_IER_TIIE_SHIFT (0U)
+#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK (0x2U)
+#define RTC_IER_TOIE_SHIFT (1U)
+#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK (0x4U)
+#define RTC_IER_TAIE_SHIFT (2U)
+#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK (0x10U)
+#define RTC_IER_TSIE_SHIFT (4U)
+#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK (0x80U)
+#define RTC_IER_WPON_SHIFT (7U)
+#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW_MASK (0x1U)
+#define RTC_WAR_TSRW_SHIFT (0U)
+#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK (0x2U)
+#define RTC_WAR_TPRW_SHIFT (1U)
+#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK (0x4U)
+#define RTC_WAR_TARW_SHIFT (2U)
+#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK (0x8U)
+#define RTC_WAR_TCRW_SHIFT (3U)
+#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK (0x10U)
+#define RTC_WAR_CRW_SHIFT (4U)
+#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK (0x20U)
+#define RTC_WAR_SRW_SHIFT (5U)
+#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK (0x40U)
+#define RTC_WAR_LRW_SHIFT (6U)
+#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK (0x80U)
+#define RTC_WAR_IERW_SHIFT (7U)
+#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR_MASK (0x1U)
+#define RTC_RAR_TSRR_SHIFT (0U)
+#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK (0x2U)
+#define RTC_RAR_TPRR_SHIFT (1U)
+#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK (0x4U)
+#define RTC_RAR_TARR_SHIFT (2U)
+#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK (0x8U)
+#define RTC_RAR_TCRR_SHIFT (3U)
+#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK (0x10U)
+#define RTC_RAR_CRR_SHIFT (4U)
+#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK (0x20U)
+#define RTC_RAR_SRR_SHIFT (5U)
+#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK (0x40U)
+#define RTC_RAR_LRR_SHIFT (6U)
+#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK (0x80U)
+#define RTC_RAR_IERR_SHIFT (7U)
+#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+
/*!
* @}
@@ -8661,7 +5914,6 @@ typedef struct {
#define RTC_BASE (0x4003D000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
-#define RTC_BASE_PTR (RTC)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
@@ -8670,34 +5922,6 @@ typedef struct {
#define RTC_IRQS { RTC_IRQn }
#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register instance definitions */
-/* RTC */
-#define RTC_TSR RTC_TSR_REG(RTC)
-#define RTC_TPR RTC_TPR_REG(RTC)
-#define RTC_TAR RTC_TAR_REG(RTC)
-#define RTC_TCR RTC_TCR_REG(RTC)
-#define RTC_CR RTC_CR_REG(RTC)
-#define RTC_SR RTC_SR_REG(RTC)
-#define RTC_LR RTC_LR_REG(RTC)
-#define RTC_IER RTC_IER_REG(RTC)
-#define RTC_WAR RTC_WAR_REG(RTC)
-#define RTC_RAR RTC_RAR_REG(RTC)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
@@ -8739,44 +5963,7 @@ typedef struct {
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type, *SIM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register accessors */
-#define SIM_SOPT1_REG(base) ((base)->SOPT1)
-#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
-#define SIM_SOPT2_REG(base) ((base)->SOPT2)
-#define SIM_SOPT4_REG(base) ((base)->SOPT4)
-#define SIM_SOPT5_REG(base) ((base)->SOPT5)
-#define SIM_SOPT7_REG(base) ((base)->SOPT7)
-#define SIM_SOPT8_REG(base) ((base)->SOPT8)
-#define SIM_SDID_REG(base) ((base)->SDID)
-#define SIM_SCGC4_REG(base) ((base)->SCGC4)
-#define SIM_SCGC5_REG(base) ((base)->SCGC5)
-#define SIM_SCGC6_REG(base) ((base)->SCGC6)
-#define SIM_SCGC7_REG(base) ((base)->SCGC7)
-#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
-#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
-#define SIM_FCFG1_REG(base) ((base)->FCFG1)
-#define SIM_FCFG2_REG(base) ((base)->FCFG2)
-#define SIM_UIDH_REG(base) ((base)->UIDH)
-#define SIM_UIDMH_REG(base) ((base)->UIDMH)
-#define SIM_UIDML_REG(base) ((base)->UIDML)
-#define SIM_UIDL_REG(base) ((base)->UIDL)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
+} SIM_Type;
/* ----------------------------------------------------------------------------
-- SIM Register Masks
@@ -8787,409 +5974,332 @@ typedef struct {
* @{
*/
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT 12
-#define SIM_SOPT1_RAMSIZE_WIDTH 4
-#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
-#define SIM_SOPT1_OSC32KOUT_SHIFT 16
-#define SIM_SOPT1_OSC32KOUT_WIDTH 2
-#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL_WIDTH 2
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH 1
-#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL_WIDTH 3
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
-#define SIM_SOPT2_TRACECLKSEL_WIDTH 1
-#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_PLLFLLSEL_WIDTH 2
-#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-#define SIM_SOPT2_USBSRC_WIDTH 1
-#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
-#define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
-#define SIM_SOPT2_LPUARTSRC_SHIFT 26
-#define SIM_SOPT2_LPUARTSRC_WIDTH 2
-#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT 0
-#define SIM_SOPT4_FTM0FLT0_WIDTH 1
-#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
-#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT 1
-#define SIM_SOPT4_FTM0FLT1_WIDTH 1
-#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
-#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT 4
-#define SIM_SOPT4_FTM1FLT0_WIDTH 1
-#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
-#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
-#define SIM_SOPT4_FTM2FLT0_SHIFT 8
-#define SIM_SOPT4_FTM2FLT0_WIDTH 1
-#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
-#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_FTM1CH0SRC_WIDTH 2
-#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
-#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
-#define SIM_SOPT4_FTM2CH0SRC_WIDTH 2
-#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH1SRC_MASK 0x400000u
-#define SIM_SOPT4_FTM2CH1SRC_SHIFT 22
-#define SIM_SOPT4_FTM2CH1SRC_WIDTH 1
-#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH1SRC_SHIFT))&SIM_SOPT4_FTM2CH1SRC_MASK)
-#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_FTM0CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
-#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_FTM1CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
-#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
-#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
-#define SIM_SOPT4_FTM2CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
-#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
-#define SIM_SOPT4_FTM0TRG0SRC_WIDTH 1
-#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
-#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
-#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
-#define SIM_SOPT4_FTM0TRG1SRC_WIDTH 1
-#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0TXSRC_WIDTH 2
-#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART0RXSRC_WIDTH 2
-#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1TXSRC_WIDTH 2
-#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART1RXSRC_WIDTH 2
-#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-#define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
-#define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
-#define SIM_SOPT5_LPUART0RXSRC_WIDTH 2
-#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL_WIDTH 4
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH 1
-#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH 1
-#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
-#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
-#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
-#define SIM_SOPT7_ADC1TRGSEL_WIDTH 4
-#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
-#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
-#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
-#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH 1
-#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
-#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
-#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
-#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH 1
-#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
-/* SOPT8 Bit Fields */
-#define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
-#define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
-#define SIM_SOPT8_FTM0SYNCBIT_WIDTH 1
-#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0SYNCBIT_SHIFT))&SIM_SOPT8_FTM0SYNCBIT_MASK)
-#define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
-#define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
-#define SIM_SOPT8_FTM1SYNCBIT_WIDTH 1
-#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM1SYNCBIT_SHIFT))&SIM_SOPT8_FTM1SYNCBIT_MASK)
-#define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
-#define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
-#define SIM_SOPT8_FTM2SYNCBIT_WIDTH 1
-#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM2SYNCBIT_SHIFT))&SIM_SOPT8_FTM2SYNCBIT_MASK)
-#define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
-#define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
-#define SIM_SOPT8_FTM0OCH0SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH0SRC_SHIFT))&SIM_SOPT8_FTM0OCH0SRC_MASK)
-#define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
-#define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
-#define SIM_SOPT8_FTM0OCH1SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH1SRC_SHIFT))&SIM_SOPT8_FTM0OCH1SRC_MASK)
-#define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
-#define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
-#define SIM_SOPT8_FTM0OCH2SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH2SRC_SHIFT))&SIM_SOPT8_FTM0OCH2SRC_MASK)
-#define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
-#define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
-#define SIM_SOPT8_FTM0OCH3SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH3SRC_SHIFT))&SIM_SOPT8_FTM0OCH3SRC_MASK)
-#define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
-#define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
-#define SIM_SOPT8_FTM0OCH4SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH4SRC_SHIFT))&SIM_SOPT8_FTM0OCH4SRC_MASK)
-#define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
-#define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
-#define SIM_SOPT8_FTM0OCH5SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH5SRC_SHIFT))&SIM_SOPT8_FTM0OCH5SRC_MASK)
-#define SIM_SOPT8_FTM0OCH6SRC_MASK 0x400000u
-#define SIM_SOPT8_FTM0OCH6SRC_SHIFT 22
-#define SIM_SOPT8_FTM0OCH6SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH6SRC_SHIFT))&SIM_SOPT8_FTM0OCH6SRC_MASK)
-#define SIM_SOPT8_FTM0OCH7SRC_MASK 0x800000u
-#define SIM_SOPT8_FTM0OCH7SRC_SHIFT 23
-#define SIM_SOPT8_FTM0OCH7SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH7SRC_SHIFT))&SIM_SOPT8_FTM0OCH7SRC_MASK)
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID_WIDTH 4
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK 0x70u
-#define SIM_SDID_FAMID_SHIFT 4
-#define SIM_SDID_FAMID_WIDTH 3
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_DIEID_MASK 0xF80u
-#define SIM_SDID_DIEID_SHIFT 7
-#define SIM_SDID_DIEID_WIDTH 5
-#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID_WIDTH 4
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-#define SIM_SDID_SERIESID_MASK 0xF00000u
-#define SIM_SDID_SERIESID_SHIFT 20
-#define SIM_SDID_SERIESID_WIDTH 4
-#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
-#define SIM_SDID_SUBFAMID_MASK 0xF000000u
-#define SIM_SDID_SUBFAMID_SHIFT 24
-#define SIM_SDID_SUBFAMID_WIDTH 4
-#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
-#define SIM_SDID_FAMILYID_MASK 0xF0000000u
-#define SIM_SDID_FAMILYID_SHIFT 28
-#define SIM_SDID_FAMILYID_WIDTH 4
-#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK 0x2u
-#define SIM_SCGC4_EWM_SHIFT 1
-#define SIM_SCGC4_EWM_WIDTH 1
-#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_I2C0_WIDTH 1
-#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
-#define SIM_SCGC4_I2C1_MASK 0x80u
-#define SIM_SCGC4_I2C1_SHIFT 7
-#define SIM_SCGC4_I2C1_WIDTH 1
-#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART0_WIDTH 1
-#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART1_WIDTH 1
-#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_UART2_WIDTH 1
-#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_USBOTG_WIDTH 1
-#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_CMP_WIDTH 1
-#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
-#define SIM_SCGC4_VREF_MASK 0x100000u
-#define SIM_SCGC4_VREF_SHIFT 20
-#define SIM_SCGC4_VREF_WIDTH 1
-#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTMR_MASK 0x1u
-#define SIM_SCGC5_LPTMR_SHIFT 0
-#define SIM_SCGC5_LPTMR_WIDTH 1
-#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTA_WIDTH 1
-#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTB_WIDTH 1
-#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTC_WIDTH 1
-#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTD_WIDTH 1
-#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-#define SIM_SCGC5_PORTE_WIDTH 1
-#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTF_MASK 0x1u
-#define SIM_SCGC6_FTF_SHIFT 0
-#define SIM_SCGC6_FTF_WIDTH 1
-#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_DMAMUX_WIDTH 1
-#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
-#define SIM_SCGC6_ADC1_MASK 0x80u
-#define SIM_SCGC6_ADC1_SHIFT 7
-#define SIM_SCGC6_ADC1_WIDTH 1
-#define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC1_SHIFT))&SIM_SCGC6_ADC1_MASK)
-#define SIM_SCGC6_LPUART0_MASK 0x400u
-#define SIM_SCGC6_LPUART0_SHIFT 10
-#define SIM_SCGC6_LPUART0_WIDTH 1
-#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_LPUART0_SHIFT))&SIM_SCGC6_LPUART0_MASK)
-#define SIM_SCGC6_SPI0_MASK 0x1000u
-#define SIM_SCGC6_SPI0_SHIFT 12
-#define SIM_SCGC6_SPI0_WIDTH 1
-#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
-#define SIM_SCGC6_SPI1_MASK 0x2000u
-#define SIM_SCGC6_SPI1_SHIFT 13
-#define SIM_SCGC6_SPI1_WIDTH 1
-#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
-#define SIM_SCGC6_I2S_MASK 0x8000u
-#define SIM_SCGC6_I2S_SHIFT 15
-#define SIM_SCGC6_I2S_WIDTH 1
-#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
-#define SIM_SCGC6_CRC_MASK 0x40000u
-#define SIM_SCGC6_CRC_SHIFT 18
-#define SIM_SCGC6_CRC_WIDTH 1
-#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
-#define SIM_SCGC6_PDB_MASK 0x400000u
-#define SIM_SCGC6_PDB_SHIFT 22
-#define SIM_SCGC6_PDB_WIDTH 1
-#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_PIT_WIDTH 1
-#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
-#define SIM_SCGC6_FTM0_MASK 0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT 24
-#define SIM_SCGC6_FTM0_WIDTH 1
-#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
-#define SIM_SCGC6_FTM1_MASK 0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT 25
-#define SIM_SCGC6_FTM1_WIDTH 1
-#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
-#define SIM_SCGC6_FTM2_MASK 0x4000000u
-#define SIM_SCGC6_FTM2_SHIFT 26
-#define SIM_SCGC6_FTM2_WIDTH 1
-#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_ADC0_WIDTH 1
-#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-#define SIM_SCGC6_RTC_WIDTH 1
-#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
-#define SIM_SCGC6_DAC0_MASK 0x80000000u
-#define SIM_SCGC6_DAC0_SHIFT 31
-#define SIM_SCGC6_DAC0_WIDTH 1
-#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_DMA_MASK 0x2u
-#define SIM_SCGC7_DMA_SHIFT 1
-#define SIM_SCGC7_DMA_WIDTH 1
-#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
-#define SIM_CLKDIV1_OUTDIV2_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT 0
-#define SIM_CLKDIV2_USBFRAC_WIDTH 1
-#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
-#define SIM_CLKDIV2_USBDIV_MASK 0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT 1
-#define SIM_CLKDIV2_USBDIV_WIDTH 3
-#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDIS_WIDTH 1
-#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_FLASHDOZE_WIDTH 1
-#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE_WIDTH 4
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT 16
-#define SIM_FCFG2_MAXADDR1_WIDTH 7
-#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT 24
-#define SIM_FCFG2_MAXADDR0_WIDTH 7
-#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT 0
-#define SIM_UIDH_UID_WIDTH 32
-#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID_WIDTH 32
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID_WIDTH 32
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID_WIDTH 32
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
+#define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
+#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
+#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
+#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT (18U)
+#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
+#define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
+#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
+#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
+#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
+#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
+#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
+#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
+#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
+#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
+#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
+#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
+#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
+#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
+#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
+#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
+#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
+#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
+#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
+#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
+#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+
+/*! @name SOPT8 - System Options Register 8 */
+#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
+#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
+#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
+#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
+#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
+#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
+#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
+#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
+#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
+#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
+#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
+#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
+#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
+#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
+#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
+#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
+#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
+#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
+#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
+#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
+#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
+#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
+#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
+#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
+#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
+#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
+#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
+#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
+#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
+#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
+#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
+#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
+#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK (0xFU)
+#define SIM_SDID_PINID_SHIFT (0U)
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK (0x70U)
+#define SIM_SDID_FAMID_SHIFT (4U)
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK (0xF80U)
+#define SIM_SDID_DIEID_SHIFT (7U)
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK (0xF000U)
+#define SIM_SDID_REVID_SHIFT (12U)
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT (20U)
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT (24U)
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
+#define SIM_SDID_FAMILYID_SHIFT (28U)
+#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM_MASK (0x2U)
+#define SIM_SCGC4_EWM_SHIFT (1U)
+#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_I2C0_MASK (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT (6U)
+#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT (7U)
+#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK (0x400U)
+#define SIM_SCGC4_UART0_SHIFT (10U)
+#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK (0x800U)
+#define SIM_SCGC4_UART1_SHIFT (11U)
+#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT (12U)
+#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_USBOTG_MASK (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT (18U)
+#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT (19U)
+#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT (20U)
+#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR_MASK (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT (0U)
+#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT (9U)
+#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT (10U)
+#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT (11U)
+#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT (12U)
+#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT (13U)
+#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTF_MASK (0x1U)
+#define SIM_SCGC6_FTF_SHIFT (0U)
+#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT (1U)
+#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_ADC1_MASK (0x80U)
+#define SIM_SCGC6_ADC1_SHIFT (7U)
+#define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC1_SHIFT)) & SIM_SCGC6_ADC1_MASK)
+#define SIM_SCGC6_LPUART0_MASK (0x400U)
+#define SIM_SCGC6_LPUART0_SHIFT (10U)
+#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_LPUART0_SHIFT)) & SIM_SCGC6_LPUART0_MASK)
+#define SIM_SCGC6_SPI0_MASK (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT (12U)
+#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK (0x2000U)
+#define SIM_SCGC6_SPI1_SHIFT (13U)
+#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT (15U)
+#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT (18U)
+#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_PDB_MASK (0x400000U)
+#define SIM_SCGC6_PDB_SHIFT (22U)
+#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT (23U)
+#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK (0x1000000U)
+#define SIM_SCGC6_FTM0_SHIFT (24U)
+#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK (0x2000000U)
+#define SIM_SCGC6_FTM1_SHIFT (25U)
+#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK (0x4000000U)
+#define SIM_SCGC6_FTM2_SHIFT (26U)
+#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT (27U)
+#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT (29U)
+#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT (31U)
+#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_DMA_MASK (0x2U)
+#define SIM_SCGC7_DMA_SHIFT (1U)
+#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
+#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
+#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
+#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT (24U)
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+
+/*! @name UIDH - Unique Identification Register High */
+#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT (0U)
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT (0U)
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT (0U)
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT (0U)
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
/*!
* @}
@@ -9201,50 +6311,11 @@ typedef struct {
#define SIM_BASE (0x40047000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
-#define SIM_BASE_PTR (SIM)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register instance definitions */
-/* SIM */
-#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
-#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
-#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
-#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
-#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
-#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
-#define SIM_SOPT8 SIM_SOPT8_REG(SIM)
-#define SIM_SDID SIM_SDID_REG(SIM)
-#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
-#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
-#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
-#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
-#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
-#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
-#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
-#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
-#define SIM_UIDH SIM_UIDH_REG(SIM)
-#define SIM_UIDMH SIM_UIDMH_REG(SIM)
-#define SIM_UIDML SIM_UIDML_REG(SIM)
-#define SIM_UIDL SIM_UIDL_REG(SIM)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
@@ -9265,28 +6336,7 @@ typedef struct {
__IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
__IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
__I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type, *SMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register accessors */
-#define SMC_PMPROT_REG(base) ((base)->PMPROT)
-#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
-#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
-#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
+} SMC_Type;
/* ----------------------------------------------------------------------------
-- SMC Register Masks
@@ -9297,54 +6347,47 @@ typedef struct {
* @{
*/
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_AVLLS_WIDTH 1
-#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_ALLS_WIDTH 1
-#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-#define SMC_PMPROT_AVLP_WIDTH 1
-#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
-#define SMC_PMPROT_AHSRUN_MASK 0x80u
-#define SMC_PMPROT_AHSRUN_SHIFT 7
-#define SMC_PMPROT_AHSRUN_WIDTH 1
-#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM_WIDTH 3
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_STOPA_WIDTH 1
-#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM_WIDTH 2
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-/* STOPCTRL Bit Fields */
-#define SMC_STOPCTRL_LLSM_MASK 0x7u
-#define SMC_STOPCTRL_LLSM_SHIFT 0
-#define SMC_STOPCTRL_LLSM_WIDTH 3
-#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
-#define SMC_STOPCTRL_PORPO_MASK 0x20u
-#define SMC_STOPCTRL_PORPO_SHIFT 5
-#define SMC_STOPCTRL_PORPO_WIDTH 1
-#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PORPO_SHIFT))&SMC_STOPCTRL_PORPO_MASK)
-#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
-#define SMC_STOPCTRL_PSTOPO_SHIFT 6
-#define SMC_STOPCTRL_PSTOPO_WIDTH 2
-#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT_WIDTH 8
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT (1U)
+#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT (3U)
+#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT (5U)
+#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AHSRUN_MASK (0x80U)
+#define SMC_PMPROT_AHSRUN_SHIFT (7U)
+#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT (0U)
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT (3U)
+#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT (5U)
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+
+/*! @name STOPCTRL - Stop Control Register */
+#define SMC_STOPCTRL_LLSM_MASK (0x7U)
+#define SMC_STOPCTRL_LLSM_SHIFT (0U)
+#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT (5U)
+#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
/*!
* @}
@@ -9356,34 +6399,11 @@ typedef struct {
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
-#define SMC_BASE_PTR (SMC)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS { SMC_BASE }
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS { SMC }
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register instance definitions */
-/* SMC */
-#define SMC_PMPROT SMC_PMPROT_REG(SMC)
-#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
-#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
-#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
@@ -9424,43 +6444,7 @@ typedef struct {
__I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
__I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
__I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
-} SPI_Type, *SPI_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register accessors */
-#define SPI_MCR_REG(base) ((base)->MCR)
-#define SPI_TCR_REG(base) ((base)->TCR)
-#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
-#define SPI_CTAR_COUNT 2
-#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
-#define SPI_CTAR_SLAVE_COUNT 1
-#define SPI_SR_REG(base) ((base)->SR)
-#define SPI_RSER_REG(base) ((base)->RSER)
-#define SPI_PUSHR_REG(base) ((base)->PUSHR)
-#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
-#define SPI_POPR_REG(base) ((base)->POPR)
-#define SPI_TXFR0_REG(base) ((base)->TXFR0)
-#define SPI_TXFR1_REG(base) ((base)->TXFR1)
-#define SPI_TXFR2_REG(base) ((base)->TXFR2)
-#define SPI_TXFR3_REG(base) ((base)->TXFR3)
-#define SPI_RXFR0_REG(base) ((base)->RXFR0)
-#define SPI_RXFR1_REG(base) ((base)->RXFR1)
-#define SPI_RXFR2_REG(base) ((base)->RXFR2)
-#define SPI_RXFR3_REG(base) ((base)->RXFR3)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
+} SPI_Type;
/* ----------------------------------------------------------------------------
-- SPI Register Masks
@@ -9471,311 +6455,262 @@ typedef struct {
* @{
*/
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK 0x1u
-#define SPI_MCR_HALT_SHIFT 0
-#define SPI_MCR_HALT_WIDTH 1
-#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
-#define SPI_MCR_SMPL_PT_MASK 0x300u
-#define SPI_MCR_SMPL_PT_SHIFT 8
-#define SPI_MCR_SMPL_PT_WIDTH 2
-#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK 0x400u
-#define SPI_MCR_CLR_RXF_SHIFT 10
-#define SPI_MCR_CLR_RXF_WIDTH 1
-#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
-#define SPI_MCR_CLR_TXF_MASK 0x800u
-#define SPI_MCR_CLR_TXF_SHIFT 11
-#define SPI_MCR_CLR_TXF_WIDTH 1
-#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
-#define SPI_MCR_DIS_RXF_MASK 0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT 12
-#define SPI_MCR_DIS_RXF_WIDTH 1
-#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
-#define SPI_MCR_DIS_TXF_MASK 0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT 13
-#define SPI_MCR_DIS_TXF_WIDTH 1
-#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
-#define SPI_MCR_MDIS_MASK 0x4000u
-#define SPI_MCR_MDIS_SHIFT 14
-#define SPI_MCR_MDIS_WIDTH 1
-#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
-#define SPI_MCR_DOZE_MASK 0x8000u
-#define SPI_MCR_DOZE_SHIFT 15
-#define SPI_MCR_DOZE_WIDTH 1
-#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
-#define SPI_MCR_PCSIS_MASK 0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT 16
-#define SPI_MCR_PCSIS_WIDTH 6
-#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK 0x1000000u
-#define SPI_MCR_ROOE_SHIFT 24
-#define SPI_MCR_ROOE_WIDTH 1
-#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
-#define SPI_MCR_PCSSE_MASK 0x2000000u
-#define SPI_MCR_PCSSE_SHIFT 25
-#define SPI_MCR_PCSSE_WIDTH 1
-#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
-#define SPI_MCR_MTFE_MASK 0x4000000u
-#define SPI_MCR_MTFE_SHIFT 26
-#define SPI_MCR_MTFE_WIDTH 1
-#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
-#define SPI_MCR_FRZ_MASK 0x8000000u
-#define SPI_MCR_FRZ_SHIFT 27
-#define SPI_MCR_FRZ_WIDTH 1
-#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
-#define SPI_MCR_DCONF_MASK 0x30000000u
-#define SPI_MCR_DCONF_SHIFT 28
-#define SPI_MCR_DCONF_WIDTH 2
-#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT 30
-#define SPI_MCR_CONT_SCKE_WIDTH 1
-#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
-#define SPI_MCR_MSTR_MASK 0x80000000u
-#define SPI_MCR_MSTR_SHIFT 31
-#define SPI_MCR_MSTR_WIDTH 1
-#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT 16
-#define SPI_TCR_SPI_TCNT_WIDTH 16
-#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK 0xFu
-#define SPI_CTAR_BR_SHIFT 0
-#define SPI_CTAR_BR_WIDTH 4
-#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK 0xF0u
-#define SPI_CTAR_DT_SHIFT 4
-#define SPI_CTAR_DT_WIDTH 4
-#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK 0xF00u
-#define SPI_CTAR_ASC_SHIFT 8
-#define SPI_CTAR_ASC_WIDTH 4
-#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK 0xF000u
-#define SPI_CTAR_CSSCK_SHIFT 12
-#define SPI_CTAR_CSSCK_WIDTH 4
-#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK 0x30000u
-#define SPI_CTAR_PBR_SHIFT 16
-#define SPI_CTAR_PBR_WIDTH 2
-#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK 0xC0000u
-#define SPI_CTAR_PDT_SHIFT 18
-#define SPI_CTAR_PDT_WIDTH 2
-#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK 0x300000u
-#define SPI_CTAR_PASC_SHIFT 20
-#define SPI_CTAR_PASC_WIDTH 2
-#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK 0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT 22
-#define SPI_CTAR_PCSSCK_WIDTH 2
-#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK 0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT 24
-#define SPI_CTAR_LSBFE_WIDTH 1
-#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
-#define SPI_CTAR_CPHA_MASK 0x2000000u
-#define SPI_CTAR_CPHA_SHIFT 25
-#define SPI_CTAR_CPHA_WIDTH 1
-#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
-#define SPI_CTAR_CPOL_MASK 0x4000000u
-#define SPI_CTAR_CPOL_SHIFT 26
-#define SPI_CTAR_CPOL_WIDTH 1
-#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
-#define SPI_CTAR_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT 27
-#define SPI_CTAR_FMSZ_WIDTH 4
-#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK 0x80000000u
-#define SPI_CTAR_DBR_SHIFT 31
-#define SPI_CTAR_DBR_WIDTH 1
-#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
-#define SPI_CTAR_SLAVE_CPHA_WIDTH 1
-#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
-#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
-#define SPI_CTAR_SLAVE_CPOL_WIDTH 1
-#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
-#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
-#define SPI_CTAR_SLAVE_FMSZ_WIDTH 5
-#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK 0xFu
-#define SPI_SR_POPNXTPTR_SHIFT 0
-#define SPI_SR_POPNXTPTR_WIDTH 4
-#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK 0xF0u
-#define SPI_SR_RXCTR_SHIFT 4
-#define SPI_SR_RXCTR_WIDTH 4
-#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK 0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT 8
-#define SPI_SR_TXNXTPTR_WIDTH 4
-#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK 0xF000u
-#define SPI_SR_TXCTR_SHIFT 12
-#define SPI_SR_TXCTR_WIDTH 4
-#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK 0x20000u
-#define SPI_SR_RFDF_SHIFT 17
-#define SPI_SR_RFDF_WIDTH 1
-#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
-#define SPI_SR_RFOF_MASK 0x80000u
-#define SPI_SR_RFOF_SHIFT 19
-#define SPI_SR_RFOF_WIDTH 1
-#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
-#define SPI_SR_TFFF_MASK 0x2000000u
-#define SPI_SR_TFFF_SHIFT 25
-#define SPI_SR_TFFF_WIDTH 1
-#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
-#define SPI_SR_TFUF_MASK 0x8000000u
-#define SPI_SR_TFUF_SHIFT 27
-#define SPI_SR_TFUF_WIDTH 1
-#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
-#define SPI_SR_EOQF_MASK 0x10000000u
-#define SPI_SR_EOQF_SHIFT 28
-#define SPI_SR_EOQF_WIDTH 1
-#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
-#define SPI_SR_TXRXS_MASK 0x40000000u
-#define SPI_SR_TXRXS_SHIFT 30
-#define SPI_SR_TXRXS_WIDTH 1
-#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
-#define SPI_SR_TCF_MASK 0x80000000u
-#define SPI_SR_TCF_SHIFT 31
-#define SPI_SR_TCF_WIDTH 1
-#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT 16
-#define SPI_RSER_RFDF_DIRS_WIDTH 1
-#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
-#define SPI_RSER_RFDF_RE_MASK 0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT 17
-#define SPI_RSER_RFDF_RE_WIDTH 1
-#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
-#define SPI_RSER_RFOF_RE_MASK 0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT 19
-#define SPI_RSER_RFOF_RE_WIDTH 1
-#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
-#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT 24
-#define SPI_RSER_TFFF_DIRS_WIDTH 1
-#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
-#define SPI_RSER_TFFF_RE_MASK 0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT 25
-#define SPI_RSER_TFFF_RE_WIDTH 1
-#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
-#define SPI_RSER_TFUF_RE_MASK 0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT 27
-#define SPI_RSER_TFUF_RE_WIDTH 1
-#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
-#define SPI_RSER_EOQF_RE_MASK 0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT 28
-#define SPI_RSER_EOQF_RE_WIDTH 1
-#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
-#define SPI_RSER_TCF_RE_MASK 0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT 31
-#define SPI_RSER_TCF_RE_WIDTH 1
-#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT 0
-#define SPI_PUSHR_TXDATA_WIDTH 16
-#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK 0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT 16
-#define SPI_PUSHR_PCS_WIDTH 6
-#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK 0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT 26
-#define SPI_PUSHR_CTCNT_WIDTH 1
-#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
-#define SPI_PUSHR_EOQ_MASK 0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT 27
-#define SPI_PUSHR_EOQ_WIDTH 1
-#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
-#define SPI_PUSHR_CTAS_MASK 0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT 28
-#define SPI_PUSHR_CTAS_WIDTH 3
-#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK 0x80000000u
-#define SPI_PUSHR_CONT_SHIFT 31
-#define SPI_PUSHR_CONT_WIDTH 1
-#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
-#define SPI_PUSHR_SLAVE_TXDATA_WIDTH 32
-#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT 0
-#define SPI_POPR_RXDATA_WIDTH 32
-#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT 0
-#define SPI_TXFR0_TXDATA_WIDTH 16
-#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR0_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT 0
-#define SPI_TXFR1_TXDATA_WIDTH 16
-#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR1_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT 0
-#define SPI_TXFR2_TXDATA_WIDTH 16
-#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR2_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT 0
-#define SPI_TXFR3_TXDATA_WIDTH 16
-#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR3_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT 0
-#define SPI_RXFR0_RXDATA_WIDTH 32
-#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT 0
-#define SPI_RXFR1_RXDATA_WIDTH 32
-#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT 0
-#define SPI_RXFR2_RXDATA_WIDTH 32
-#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT 0
-#define SPI_RXFR3_RXDATA_WIDTH 32
-#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+/*! @name MCR - Module Configuration Register */
+#define SPI_MCR_HALT_MASK (0x1U)
+#define SPI_MCR_HALT_SHIFT (0U)
+#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT (8U)
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT (10U)
+#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT (11U)
+#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT (12U)
+#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT (13U)
+#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK (0x4000U)
+#define SPI_MCR_MDIS_SHIFT (14U)
+#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK (0x8000U)
+#define SPI_MCR_DOZE_SHIFT (15U)
+#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT (16U)
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT (24U)
+#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT (25U)
+#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT (26U)
+#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT (27U)
+#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT (28U)
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT (30U)
+#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT (31U)
+#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+
+/*! @name TCR - Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT (16U)
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK (0xFU)
+#define SPI_CTAR_BR_SHIFT (0U)
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK (0xF0U)
+#define SPI_CTAR_DT_SHIFT (4U)
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK (0xF00U)
+#define SPI_CTAR_ASC_SHIFT (8U)
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT (12U)
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK (0x30000U)
+#define SPI_CTAR_PBR_SHIFT (16U)
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT (18U)
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK (0x300000U)
+#define SPI_CTAR_PASC_SHIFT (20U)
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT (22U)
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT (24U)
+#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT (25U)
+#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT (26U)
+#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT (27U)
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT (31U)
+#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
+#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
+#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT (1U)
+
+/*! @name SR - Status Register */
+#define SPI_SR_POPNXTPTR_MASK (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT (0U)
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK (0xF0U)
+#define SPI_SR_RXCTR_SHIFT (4U)
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT (8U)
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK (0xF000U)
+#define SPI_SR_TXCTR_SHIFT (12U)
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK (0x20000U)
+#define SPI_SR_RFDF_SHIFT (17U)
+#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK (0x80000U)
+#define SPI_SR_RFOF_SHIFT (19U)
+#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK (0x2000000U)
+#define SPI_SR_TFFF_SHIFT (25U)
+#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK (0x8000000U)
+#define SPI_SR_TFUF_SHIFT (27U)
+#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK (0x10000000U)
+#define SPI_SR_EOQF_SHIFT (28U)
+#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT (30U)
+#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK (0x80000000U)
+#define SPI_SR_TCF_SHIFT (31U)
+#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
+#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT (17U)
+#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT (19U)
+#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
+#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT (25U)
+#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT (27U)
+#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT (28U)
+#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT (31U)
+#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT (16U)
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT (26U)
+#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT (27U)
+#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT (28U)
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT (31U)
+#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+
+/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+
+/*! @name POPR - POP RX FIFO Register */
+#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT (0U)
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+
+/*! @name TXFR0 - Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT (0U)
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT (0U)
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT (0U)
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT (0U)
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*! @name RXFR0 - Receive FIFO Registers */
+#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT (0U)
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+
+/*! @name RXFR1 - Receive FIFO Registers */
+#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT (0U)
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+
+/*! @name RXFR2 - Receive FIFO Registers */
+#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT (0U)
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+
+/*! @name RXFR3 - Receive FIFO Registers */
+#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT (0U)
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+
/*!
* @}
@@ -9787,12 +6722,10 @@ typedef struct {
#define SPI0_BASE (0x4002C000u)
/** Peripheral SPI0 base pointer */
#define SPI0 ((SPI_Type *)SPI0_BASE)
-#define SPI0_BASE_PTR (SPI0)
/** Peripheral SPI1 base address */
#define SPI1_BASE (0x4002D000u)
/** Peripheral SPI1 base pointer */
#define SPI1 ((SPI_Type *)SPI1_BASE)
-#define SPI1_BASE_PTR (SPI1)
/** Array initializer of SPI peripheral base addresses */
#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
/** Array initializer of SPI peripheral base pointers */
@@ -9800,67 +6733,6 @@ typedef struct {
/** Interrupt vectors for the SPI peripheral type */
#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register instance definitions */
-/* SPI0 */
-#define SPI0_MCR SPI_MCR_REG(SPI0)
-#define SPI0_TCR SPI_TCR_REG(SPI0)
-#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
-#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
-#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
-#define SPI0_SR SPI_SR_REG(SPI0)
-#define SPI0_RSER SPI_RSER_REG(SPI0)
-#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
-#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
-#define SPI0_POPR SPI_POPR_REG(SPI0)
-#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
-#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
-#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
-#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
-#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
-#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
-#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
-#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
-/* SPI1 */
-#define SPI1_MCR SPI_MCR_REG(SPI1)
-#define SPI1_TCR SPI_TCR_REG(SPI1)
-#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
-#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
-#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
-#define SPI1_SR SPI_SR_REG(SPI1)
-#define SPI1_RSER SPI_RSER_REG(SPI1)
-#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
-#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
-#define SPI1_POPR SPI_POPR_REG(SPI1)
-#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
-#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
-#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
-#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
-#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
-#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
-#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
-#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
-
-/* SPI - Register array accessors */
-#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
-#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
-#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
-#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
@@ -9924,62 +6796,7 @@ typedef struct {
};
__IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
__IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
-} UART_Type, *UART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register accessors */
-#define UART_BDH_REG(base) ((base)->BDH)
-#define UART_BDL_REG(base) ((base)->BDL)
-#define UART_C1_REG(base) ((base)->C1)
-#define UART_C2_REG(base) ((base)->C2)
-#define UART_S1_REG(base) ((base)->S1)
-#define UART_S2_REG(base) ((base)->S2)
-#define UART_C3_REG(base) ((base)->C3)
-#define UART_D_REG(base) ((base)->D)
-#define UART_MA1_REG(base) ((base)->MA1)
-#define UART_MA2_REG(base) ((base)->MA2)
-#define UART_C4_REG(base) ((base)->C4)
-#define UART_C5_REG(base) ((base)->C5)
-#define UART_ED_REG(base) ((base)->ED)
-#define UART_MODEM_REG(base) ((base)->MODEM)
-#define UART_IR_REG(base) ((base)->IR)
-#define UART_PFIFO_REG(base) ((base)->PFIFO)
-#define UART_CFIFO_REG(base) ((base)->CFIFO)
-#define UART_SFIFO_REG(base) ((base)->SFIFO)
-#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
-#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
-#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
-#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
-#define UART_C7816_REG(base) ((base)->C7816)
-#define UART_IE7816_REG(base) ((base)->IE7816)
-#define UART_IS7816_REG(base) ((base)->IS7816)
-#define UART_WP7816_REG(base) ((base)->WP7816)
-#define UART_WN7816_REG(base) ((base)->WN7816)
-#define UART_WF7816_REG(base) ((base)->WF7816)
-#define UART_ET7816_REG(base) ((base)->ET7816)
-#define UART_TL7816_REG(base) ((base)->TL7816)
-#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
-#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
-#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
-#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
-#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
-#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
-#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
-#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
+} UART_Type;
/* ----------------------------------------------------------------------------
-- UART Register Masks
@@ -9990,504 +6807,427 @@ typedef struct {
* @{
*/
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR_WIDTH 5
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_RXEDGIE_WIDTH 1
-#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-#define UART_BDH_LBKDIE_WIDTH 1
-#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR_WIDTH 8
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PT_WIDTH 1
-#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_PE_WIDTH 1
-#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_ILT_WIDTH 1
-#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_WAKE_WIDTH 1
-#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_M_WIDTH 1
-#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_RSRC_WIDTH 1
-#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_UARTSWAI_WIDTH 1
-#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-#define UART_C1_LOOPS_WIDTH 1
-#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_SBK_WIDTH 1
-#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RWU_WIDTH 1
-#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_RE_WIDTH 1
-#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_TE_WIDTH 1
-#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_ILIE_WIDTH 1
-#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_RIE_WIDTH 1
-#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TCIE_WIDTH 1
-#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-#define UART_C2_TIE_WIDTH 1
-#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_PF_WIDTH 1
-#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_FE_WIDTH 1
-#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_NF_WIDTH 1
-#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_OR_WIDTH 1
-#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_IDLE_WIDTH 1
-#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_RDRF_WIDTH 1
-#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TC_WIDTH 1
-#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-#define UART_S1_TDRE_WIDTH 1
-#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_RAF_WIDTH 1
-#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_LBKDE_WIDTH 1
-#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_BRK13_WIDTH 1
-#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RWUID_WIDTH 1
-#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_RXINV_WIDTH 1
-#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
-#define UART_S2_MSBF_MASK 0x20u
-#define UART_S2_MSBF_SHIFT 5
-#define UART_S2_MSBF_WIDTH 1
-#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_RXEDGIF_WIDTH 1
-#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-#define UART_S2_LBKDIF_WIDTH 1
-#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_PEIE_WIDTH 1
-#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_FEIE_WIDTH 1
-#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_NEIE_WIDTH 1
-#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_ORIE_WIDTH 1
-#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXINV_WIDTH 1
-#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_TXDIR_WIDTH 1
-#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_T8_WIDTH 1
-#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-#define UART_C3_R8_WIDTH 1
-#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
-/* D Bit Fields */
-#define UART_D_RT_MASK 0xFFu
-#define UART_D_RT_SHIFT 0
-#define UART_D_RT_WIDTH 8
-#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK 0xFFu
-#define UART_MA1_MA_SHIFT 0
-#define UART_MA1_MA_WIDTH 8
-#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK 0xFFu
-#define UART_MA2_MA_SHIFT 0
-#define UART_MA2_MA_WIDTH 8
-#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK 0x1Fu
-#define UART_C4_BRFA_SHIFT 0
-#define UART_C4_BRFA_WIDTH 5
-#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK 0x20u
-#define UART_C4_M10_SHIFT 5
-#define UART_C4_M10_WIDTH 1
-#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
-#define UART_C4_MAEN2_MASK 0x40u
-#define UART_C4_MAEN2_SHIFT 6
-#define UART_C4_MAEN2_WIDTH 1
-#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
-#define UART_C4_MAEN1_MASK 0x80u
-#define UART_C4_MAEN1_SHIFT 7
-#define UART_C4_MAEN1_WIDTH 1
-#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
-/* C5 Bit Fields */
-#define UART_C5_RDMAS_MASK 0x20u
-#define UART_C5_RDMAS_SHIFT 5
-#define UART_C5_RDMAS_WIDTH 1
-#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
-#define UART_C5_TDMAS_MASK 0x80u
-#define UART_C5_TDMAS_SHIFT 7
-#define UART_C5_TDMAS_WIDTH 1
-#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK 0x40u
-#define UART_ED_PARITYE_SHIFT 6
-#define UART_ED_PARITYE_WIDTH 1
-#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
-#define UART_ED_NOISY_MASK 0x80u
-#define UART_ED_NOISY_SHIFT 7
-#define UART_ED_NOISY_WIDTH 1
-#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK 0x1u
-#define UART_MODEM_TXCTSE_SHIFT 0
-#define UART_MODEM_TXCTSE_WIDTH 1
-#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
-#define UART_MODEM_TXRTSE_MASK 0x2u
-#define UART_MODEM_TXRTSE_SHIFT 1
-#define UART_MODEM_TXRTSE_WIDTH 1
-#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
-#define UART_MODEM_TXRTSPOL_MASK 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT 2
-#define UART_MODEM_TXRTSPOL_WIDTH 1
-#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
-#define UART_MODEM_RXRTSE_MASK 0x8u
-#define UART_MODEM_RXRTSE_SHIFT 3
-#define UART_MODEM_RXRTSE_WIDTH 1
-#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK 0x3u
-#define UART_IR_TNP_SHIFT 0
-#define UART_IR_TNP_WIDTH 2
-#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK 0x4u
-#define UART_IR_IREN_SHIFT 2
-#define UART_IR_IREN_WIDTH 1
-#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
-#define UART_PFIFO_RXFIFOSIZE_WIDTH 3
-#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK 0x8u
-#define UART_PFIFO_RXFE_SHIFT 3
-#define UART_PFIFO_RXFE_WIDTH 1
-#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
-#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
-#define UART_PFIFO_TXFIFOSIZE_WIDTH 3
-#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK 0x80u
-#define UART_PFIFO_TXFE_SHIFT 7
-#define UART_PFIFO_TXFE_WIDTH 1
-#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK 0x1u
-#define UART_CFIFO_RXUFE_SHIFT 0
-#define UART_CFIFO_RXUFE_WIDTH 1
-#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
-#define UART_CFIFO_TXOFE_MASK 0x2u
-#define UART_CFIFO_TXOFE_SHIFT 1
-#define UART_CFIFO_TXOFE_WIDTH 1
-#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
-#define UART_CFIFO_RXOFE_MASK 0x4u
-#define UART_CFIFO_RXOFE_SHIFT 2
-#define UART_CFIFO_RXOFE_WIDTH 1
-#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
-#define UART_CFIFO_RXFLUSH_MASK 0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT 6
-#define UART_CFIFO_RXFLUSH_WIDTH 1
-#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
-#define UART_CFIFO_TXFLUSH_MASK 0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT 7
-#define UART_CFIFO_TXFLUSH_WIDTH 1
-#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK 0x1u
-#define UART_SFIFO_RXUF_SHIFT 0
-#define UART_SFIFO_RXUF_WIDTH 1
-#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
-#define UART_SFIFO_TXOF_MASK 0x2u
-#define UART_SFIFO_TXOF_SHIFT 1
-#define UART_SFIFO_TXOF_WIDTH 1
-#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
-#define UART_SFIFO_RXOF_MASK 0x4u
-#define UART_SFIFO_RXOF_SHIFT 2
-#define UART_SFIFO_RXOF_WIDTH 1
-#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
-#define UART_SFIFO_RXEMPT_MASK 0x40u
-#define UART_SFIFO_RXEMPT_SHIFT 6
-#define UART_SFIFO_RXEMPT_WIDTH 1
-#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
-#define UART_SFIFO_TXEMPT_MASK 0x80u
-#define UART_SFIFO_TXEMPT_SHIFT 7
-#define UART_SFIFO_TXEMPT_WIDTH 1
-#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT 0
-#define UART_TWFIFO_TXWATER_WIDTH 8
-#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT 0
-#define UART_TCFIFO_TXCOUNT_WIDTH 8
-#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT 0
-#define UART_RWFIFO_RXWATER_WIDTH 8
-#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT 0
-#define UART_RCFIFO_RXCOUNT_WIDTH 8
-#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK 0x1u
-#define UART_C7816_ISO_7816E_SHIFT 0
-#define UART_C7816_ISO_7816E_WIDTH 1
-#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
-#define UART_C7816_TTYPE_MASK 0x2u
-#define UART_C7816_TTYPE_SHIFT 1
-#define UART_C7816_TTYPE_WIDTH 1
-#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
-#define UART_C7816_INIT_MASK 0x4u
-#define UART_C7816_INIT_SHIFT 2
-#define UART_C7816_INIT_WIDTH 1
-#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
-#define UART_C7816_ANACK_MASK 0x8u
-#define UART_C7816_ANACK_SHIFT 3
-#define UART_C7816_ANACK_WIDTH 1
-#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
-#define UART_C7816_ONACK_MASK 0x10u
-#define UART_C7816_ONACK_SHIFT 4
-#define UART_C7816_ONACK_WIDTH 1
-#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK 0x1u
-#define UART_IE7816_RXTE_SHIFT 0
-#define UART_IE7816_RXTE_WIDTH 1
-#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
-#define UART_IE7816_TXTE_MASK 0x2u
-#define UART_IE7816_TXTE_SHIFT 1
-#define UART_IE7816_TXTE_WIDTH 1
-#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
-#define UART_IE7816_GTVE_MASK 0x4u
-#define UART_IE7816_GTVE_SHIFT 2
-#define UART_IE7816_GTVE_WIDTH 1
-#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
-#define UART_IE7816_ADTE_MASK 0x8u
-#define UART_IE7816_ADTE_SHIFT 3
-#define UART_IE7816_ADTE_WIDTH 1
-#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_ADTE_SHIFT))&UART_IE7816_ADTE_MASK)
-#define UART_IE7816_INITDE_MASK 0x10u
-#define UART_IE7816_INITDE_SHIFT 4
-#define UART_IE7816_INITDE_WIDTH 1
-#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
-#define UART_IE7816_BWTE_MASK 0x20u
-#define UART_IE7816_BWTE_SHIFT 5
-#define UART_IE7816_BWTE_WIDTH 1
-#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
-#define UART_IE7816_CWTE_MASK 0x40u
-#define UART_IE7816_CWTE_SHIFT 6
-#define UART_IE7816_CWTE_WIDTH 1
-#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
-#define UART_IE7816_WTE_MASK 0x80u
-#define UART_IE7816_WTE_SHIFT 7
-#define UART_IE7816_WTE_WIDTH 1
-#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK 0x1u
-#define UART_IS7816_RXT_SHIFT 0
-#define UART_IS7816_RXT_WIDTH 1
-#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
-#define UART_IS7816_TXT_MASK 0x2u
-#define UART_IS7816_TXT_SHIFT 1
-#define UART_IS7816_TXT_WIDTH 1
-#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
-#define UART_IS7816_GTV_MASK 0x4u
-#define UART_IS7816_GTV_SHIFT 2
-#define UART_IS7816_GTV_WIDTH 1
-#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
-#define UART_IS7816_ADT_MASK 0x8u
-#define UART_IS7816_ADT_SHIFT 3
-#define UART_IS7816_ADT_WIDTH 1
-#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_ADT_SHIFT))&UART_IS7816_ADT_MASK)
-#define UART_IS7816_INITD_MASK 0x10u
-#define UART_IS7816_INITD_SHIFT 4
-#define UART_IS7816_INITD_WIDTH 1
-#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
-#define UART_IS7816_BWT_MASK 0x20u
-#define UART_IS7816_BWT_SHIFT 5
-#define UART_IS7816_BWT_WIDTH 1
-#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
-#define UART_IS7816_CWT_MASK 0x40u
-#define UART_IS7816_CWT_SHIFT 6
-#define UART_IS7816_CWT_WIDTH 1
-#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
-#define UART_IS7816_WT_MASK 0x80u
-#define UART_IS7816_WT_SHIFT 7
-#define UART_IS7816_WT_WIDTH 1
-#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
-/* WP7816 Bit Fields */
-#define UART_WP7816_WTX_MASK 0xFFu
-#define UART_WP7816_WTX_SHIFT 0
-#define UART_WP7816_WTX_WIDTH 8
-#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK 0xFFu
-#define UART_WN7816_GTN_SHIFT 0
-#define UART_WN7816_GTN_WIDTH 8
-#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK 0xFFu
-#define UART_WF7816_GTFD_SHIFT 0
-#define UART_WF7816_GTFD_WIDTH 8
-#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT 0
-#define UART_ET7816_RXTHRESHOLD_WIDTH 4
-#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT 4
-#define UART_ET7816_TXTHRESHOLD_WIDTH 4
-#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK 0xFFu
-#define UART_TL7816_TLEN_SHIFT 0
-#define UART_TL7816_TLEN_WIDTH 8
-#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-/* AP7816A_T0 Bit Fields */
-#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
-#define UART_AP7816A_T0_ADTI_H_SHIFT 0
-#define UART_AP7816A_T0_ADTI_H_WIDTH 8
-#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
-/* AP7816B_T0 Bit Fields */
-#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
-#define UART_AP7816B_T0_ADTI_L_SHIFT 0
-#define UART_AP7816B_T0_ADTI_L_WIDTH 8
-#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
-/* WP7816A_T0 Bit Fields */
-#define UART_WP7816A_T0_WI_H_MASK 0xFFu
-#define UART_WP7816A_T0_WI_H_SHIFT 0
-#define UART_WP7816A_T0_WI_H_WIDTH 8
-#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
-/* WP7816B_T0 Bit Fields */
-#define UART_WP7816B_T0_WI_L_MASK 0xFFu
-#define UART_WP7816B_T0_WI_L_SHIFT 0
-#define UART_WP7816B_T0_WI_L_WIDTH 8
-#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
-/* WP7816A_T1 Bit Fields */
-#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
-#define UART_WP7816A_T1_BWI_H_SHIFT 0
-#define UART_WP7816A_T1_BWI_H_WIDTH 8
-#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
-/* WP7816B_T1 Bit Fields */
-#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
-#define UART_WP7816B_T1_BWI_L_SHIFT 0
-#define UART_WP7816B_T1_BWI_L_WIDTH 8
-#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
-/* WGP7816_T1 Bit Fields */
-#define UART_WGP7816_T1_BGI_MASK 0xFu
-#define UART_WGP7816_T1_BGI_SHIFT 0
-#define UART_WGP7816_T1_BGI_WIDTH 4
-#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
-#define UART_WGP7816_T1_CWI1_MASK 0xF0u
-#define UART_WGP7816_T1_CWI1_SHIFT 4
-#define UART_WGP7816_T1_CWI1_WIDTH 4
-#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
-/* WP7816C_T1 Bit Fields */
-#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
-#define UART_WP7816C_T1_CWI2_SHIFT 0
-#define UART_WP7816C_T1_CWI2_WIDTH 5
-#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+/*! @name BDH - UART Baud Rate Registers: High */
+#define UART_BDH_SBR_MASK (0x1FU)
+#define UART_BDH_SBR_SHIFT (0U)
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT (6U)
+#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK (0x80U)
+#define UART_BDH_LBKDIE_SHIFT (7U)
+#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+#define UART_BDL_SBR_MASK (0xFFU)
+#define UART_BDL_SBR_SHIFT (0U)
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK (0x1U)
+#define UART_C1_PT_SHIFT (0U)
+#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK (0x2U)
+#define UART_C1_PE_SHIFT (1U)
+#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK (0x4U)
+#define UART_C1_ILT_SHIFT (2U)
+#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK (0x8U)
+#define UART_C1_WAKE_SHIFT (3U)
+#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK (0x10U)
+#define UART_C1_M_SHIFT (4U)
+#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK (0x20U)
+#define UART_C1_RSRC_SHIFT (5U)
+#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK (0x40U)
+#define UART_C1_UARTSWAI_SHIFT (6U)
+#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK (0x80U)
+#define UART_C1_LOOPS_SHIFT (7U)
+#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK (0x1U)
+#define UART_C2_SBK_SHIFT (0U)
+#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK (0x2U)
+#define UART_C2_RWU_SHIFT (1U)
+#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK (0x4U)
+#define UART_C2_RE_SHIFT (2U)
+#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK (0x8U)
+#define UART_C2_TE_SHIFT (3U)
+#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK (0x10U)
+#define UART_C2_ILIE_SHIFT (4U)
+#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK (0x20U)
+#define UART_C2_RIE_SHIFT (5U)
+#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK (0x40U)
+#define UART_C2_TCIE_SHIFT (6U)
+#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK (0x80U)
+#define UART_C2_TIE_SHIFT (7U)
+#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK (0x1U)
+#define UART_S1_PF_SHIFT (0U)
+#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK (0x2U)
+#define UART_S1_FE_SHIFT (1U)
+#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK (0x4U)
+#define UART_S1_NF_SHIFT (2U)
+#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK (0x8U)
+#define UART_S1_OR_SHIFT (3U)
+#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK (0x10U)
+#define UART_S1_IDLE_SHIFT (4U)
+#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK (0x20U)
+#define UART_S1_RDRF_SHIFT (5U)
+#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK (0x40U)
+#define UART_S1_TC_SHIFT (6U)
+#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK (0x80U)
+#define UART_S1_TDRE_SHIFT (7U)
+#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK (0x1U)
+#define UART_S2_RAF_SHIFT (0U)
+#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK (0x2U)
+#define UART_S2_LBKDE_SHIFT (1U)
+#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK (0x4U)
+#define UART_S2_BRK13_SHIFT (2U)
+#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK (0x8U)
+#define UART_S2_RWUID_SHIFT (3U)
+#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK (0x10U)
+#define UART_S2_RXINV_SHIFT (4U)
+#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK (0x20U)
+#define UART_S2_MSBF_SHIFT (5U)
+#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK (0x40U)
+#define UART_S2_RXEDGIF_SHIFT (6U)
+#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK (0x80U)
+#define UART_S2_LBKDIF_SHIFT (7U)
+#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK (0x1U)
+#define UART_C3_PEIE_SHIFT (0U)
+#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK (0x2U)
+#define UART_C3_FEIE_SHIFT (1U)
+#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK (0x4U)
+#define UART_C3_NEIE_SHIFT (2U)
+#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK (0x8U)
+#define UART_C3_ORIE_SHIFT (3U)
+#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK (0x10U)
+#define UART_C3_TXINV_SHIFT (4U)
+#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK (0x20U)
+#define UART_C3_TXDIR_SHIFT (5U)
+#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK (0x40U)
+#define UART_C3_T8_SHIFT (6U)
+#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK (0x80U)
+#define UART_C3_R8_SHIFT (7U)
+#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_RT_MASK (0xFFU)
+#define UART_D_RT_SHIFT (0U)
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART_MA1_MA_MASK (0xFFU)
+#define UART_MA1_MA_SHIFT (0U)
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART_MA2_MA_MASK (0xFFU)
+#define UART_MA2_MA_SHIFT (0U)
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_BRFA_MASK (0x1FU)
+#define UART_C4_BRFA_SHIFT (0U)
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK (0x20U)
+#define UART_C4_M10_SHIFT (5U)
+#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK (0x40U)
+#define UART_C4_MAEN2_SHIFT (6U)
+#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK (0x80U)
+#define UART_C4_MAEN1_SHIFT (7U)
+#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART_C5_RDMAS_MASK (0x20U)
+#define UART_C5_RDMAS_SHIFT (5U)
+#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK (0x80U)
+#define UART_C5_TDMAS_SHIFT (7U)
+#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+
+/*! @name ED - UART Extended Data Register */
+#define UART_ED_PARITYE_MASK (0x40U)
+#define UART_ED_PARITYE_SHIFT (6U)
+#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK (0x80U)
+#define UART_ED_NOISY_SHIFT (7U)
+#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+
+/*! @name MODEM - UART Modem Register */
+#define UART_MODEM_TXCTSE_MASK (0x1U)
+#define UART_MODEM_TXCTSE_SHIFT (0U)
+#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK (0x2U)
+#define UART_MODEM_TXRTSE_SHIFT (1U)
+#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK (0x4U)
+#define UART_MODEM_TXRTSPOL_SHIFT (2U)
+#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK (0x8U)
+#define UART_MODEM_RXRTSE_SHIFT (3U)
+#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+
+/*! @name IR - UART Infrared Register */
+#define UART_IR_TNP_MASK (0x3U)
+#define UART_IR_TNP_SHIFT (0U)
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK (0x4U)
+#define UART_IR_IREN_SHIFT (2U)
+#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+
+/*! @name PFIFO - UART FIFO Parameters */
+#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK (0x8U)
+#define UART_PFIFO_RXFE_SHIFT (3U)
+#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK (0x80U)
+#define UART_PFIFO_TXFE_SHIFT (7U)
+#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+
+/*! @name CFIFO - UART FIFO Control Register */
+#define UART_CFIFO_RXUFE_MASK (0x1U)
+#define UART_CFIFO_RXUFE_SHIFT (0U)
+#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK (0x2U)
+#define UART_CFIFO_TXOFE_SHIFT (1U)
+#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK (0x4U)
+#define UART_CFIFO_RXOFE_SHIFT (2U)
+#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK (0x40U)
+#define UART_CFIFO_RXFLUSH_SHIFT (6U)
+#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK (0x80U)
+#define UART_CFIFO_TXFLUSH_SHIFT (7U)
+#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+
+/*! @name SFIFO - UART FIFO Status Register */
+#define UART_SFIFO_RXUF_MASK (0x1U)
+#define UART_SFIFO_RXUF_SHIFT (0U)
+#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK (0x2U)
+#define UART_SFIFO_TXOF_SHIFT (1U)
+#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK (0x4U)
+#define UART_SFIFO_RXOF_SHIFT (2U)
+#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK (0x40U)
+#define UART_SFIFO_RXEMPT_SHIFT (6U)
+#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK (0x80U)
+#define UART_SFIFO_TXEMPT_SHIFT (7U)
+#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+#define UART_TWFIFO_TXWATER_MASK (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT (0U)
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+#define UART_RWFIFO_RXWATER_MASK (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT (0U)
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+
+/*! @name C7816 - UART 7816 Control Register */
+#define UART_C7816_ISO_7816E_MASK (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT (0U)
+#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK (0x2U)
+#define UART_C7816_TTYPE_SHIFT (1U)
+#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK (0x4U)
+#define UART_C7816_INIT_SHIFT (2U)
+#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK (0x8U)
+#define UART_C7816_ANACK_SHIFT (3U)
+#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK (0x10U)
+#define UART_C7816_ONACK_SHIFT (4U)
+#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+#define UART_IE7816_RXTE_MASK (0x1U)
+#define UART_IE7816_RXTE_SHIFT (0U)
+#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK (0x2U)
+#define UART_IE7816_TXTE_SHIFT (1U)
+#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK (0x4U)
+#define UART_IE7816_GTVE_SHIFT (2U)
+#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+#define UART_IE7816_ADTE_MASK (0x8U)
+#define UART_IE7816_ADTE_SHIFT (3U)
+#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
+#define UART_IE7816_INITDE_MASK (0x10U)
+#define UART_IE7816_INITDE_SHIFT (4U)
+#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK (0x20U)
+#define UART_IE7816_BWTE_SHIFT (5U)
+#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK (0x40U)
+#define UART_IE7816_CWTE_SHIFT (6U)
+#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK (0x80U)
+#define UART_IE7816_WTE_SHIFT (7U)
+#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+#define UART_IS7816_RXT_MASK (0x1U)
+#define UART_IS7816_RXT_SHIFT (0U)
+#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK (0x2U)
+#define UART_IS7816_TXT_SHIFT (1U)
+#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK (0x4U)
+#define UART_IS7816_GTV_SHIFT (2U)
+#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+#define UART_IS7816_ADT_MASK (0x8U)
+#define UART_IS7816_ADT_SHIFT (3U)
+#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
+#define UART_IS7816_INITD_MASK (0x10U)
+#define UART_IS7816_INITD_SHIFT (4U)
+#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK (0x20U)
+#define UART_IS7816_BWT_SHIFT (5U)
+#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK (0x40U)
+#define UART_IS7816_CWT_SHIFT (6U)
+#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK (0x80U)
+#define UART_IS7816_WT_SHIFT (7U)
+#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+
+/*! @name WP7816 - UART 7816 Wait Parameter Register */
+#define UART_WP7816_WTX_MASK (0xFFU)
+#define UART_WP7816_WTX_SHIFT (0U)
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+#define UART_WN7816_GTN_MASK (0xFFU)
+#define UART_WN7816_GTN_SHIFT (0U)
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+#define UART_WF7816_GTFD_MASK (0xFFU)
+#define UART_WF7816_GTFD_SHIFT (0U)
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+#define UART_TL7816_TLEN_MASK (0xFFU)
+#define UART_TL7816_TLEN_SHIFT (0U)
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+
+/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
+#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
+#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
+
+/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
+#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
+#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
+
+/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
+#define UART_WP7816A_T0_WI_H_SHIFT (0U)
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
+
+/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
+#define UART_WP7816B_T0_WI_L_SHIFT (0U)
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
+
+/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
+#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
+
+/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
+#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
+
+/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
+#define UART_WGP7816_T1_BGI_MASK (0xFU)
+#define UART_WGP7816_T1_BGI_SHIFT (0U)
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
+#define UART_WGP7816_T1_CWI1_SHIFT (4U)
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
+
+/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
+#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
+#define UART_WP7816C_T1_CWI2_SHIFT (0U)
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
+
/*!
* @}
@@ -10499,17 +7239,14 @@ typedef struct {
#define UART0_BASE (0x4006A000u)
/** Peripheral UART0 base pointer */
#define UART0 ((UART_Type *)UART0_BASE)
-#define UART0_BASE_PTR (UART0)
/** Peripheral UART1 base address */
#define UART1_BASE (0x4006B000u)
/** Peripheral UART1 base pointer */
#define UART1 ((UART_Type *)UART1_BASE)
-#define UART1_BASE_PTR (UART1)
/** Peripheral UART2 base address */
#define UART2_BASE (0x4006C000u)
/** Peripheral UART2 base pointer */
#define UART2 ((UART_Type *)UART2_BASE)
-#define UART2_BASE_PTR (UART2)
/** Array initializer of UART peripheral base addresses */
#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
/** Array initializer of UART peripheral base pointers */
@@ -10518,108 +7255,6 @@ typedef struct {
#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register instance definitions */
-/* UART0 */
-#define UART0_BDH UART_BDH_REG(UART0)
-#define UART0_BDL UART_BDL_REG(UART0)
-#define UART0_C1 UART_C1_REG(UART0)
-#define UART0_C2 UART_C2_REG(UART0)
-#define UART0_S1 UART_S1_REG(UART0)
-#define UART0_S2 UART_S2_REG(UART0)
-#define UART0_C3 UART_C3_REG(UART0)
-#define UART0_D UART_D_REG(UART0)
-#define UART0_MA1 UART_MA1_REG(UART0)
-#define UART0_MA2 UART_MA2_REG(UART0)
-#define UART0_C4 UART_C4_REG(UART0)
-#define UART0_C5 UART_C5_REG(UART0)
-#define UART0_ED UART_ED_REG(UART0)
-#define UART0_MODEM UART_MODEM_REG(UART0)
-#define UART0_IR UART_IR_REG(UART0)
-#define UART0_PFIFO UART_PFIFO_REG(UART0)
-#define UART0_CFIFO UART_CFIFO_REG(UART0)
-#define UART0_SFIFO UART_SFIFO_REG(UART0)
-#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
-#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
-#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
-#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
-#define UART0_C7816 UART_C7816_REG(UART0)
-#define UART0_IE7816 UART_IE7816_REG(UART0)
-#define UART0_IS7816 UART_IS7816_REG(UART0)
-#define UART0_WP7816 UART_WP7816_REG(UART0)
-#define UART0_WN7816 UART_WN7816_REG(UART0)
-#define UART0_WF7816 UART_WF7816_REG(UART0)
-#define UART0_ET7816 UART_ET7816_REG(UART0)
-#define UART0_TL7816 UART_TL7816_REG(UART0)
-#define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
-#define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
-#define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
-#define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
-#define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
-#define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
-#define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
-#define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
-/* UART1 */
-#define UART1_BDH UART_BDH_REG(UART1)
-#define UART1_BDL UART_BDL_REG(UART1)
-#define UART1_C1 UART_C1_REG(UART1)
-#define UART1_C2 UART_C2_REG(UART1)
-#define UART1_S1 UART_S1_REG(UART1)
-#define UART1_S2 UART_S2_REG(UART1)
-#define UART1_C3 UART_C3_REG(UART1)
-#define UART1_D UART_D_REG(UART1)
-#define UART1_MA1 UART_MA1_REG(UART1)
-#define UART1_MA2 UART_MA2_REG(UART1)
-#define UART1_C4 UART_C4_REG(UART1)
-#define UART1_C5 UART_C5_REG(UART1)
-#define UART1_ED UART_ED_REG(UART1)
-#define UART1_MODEM UART_MODEM_REG(UART1)
-#define UART1_IR UART_IR_REG(UART1)
-#define UART1_PFIFO UART_PFIFO_REG(UART1)
-#define UART1_CFIFO UART_CFIFO_REG(UART1)
-#define UART1_SFIFO UART_SFIFO_REG(UART1)
-#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
-#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
-#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
-#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
-/* UART2 */
-#define UART2_BDH UART_BDH_REG(UART2)
-#define UART2_BDL UART_BDL_REG(UART2)
-#define UART2_C1 UART_C1_REG(UART2)
-#define UART2_C2 UART_C2_REG(UART2)
-#define UART2_S1 UART_S1_REG(UART2)
-#define UART2_S2 UART_S2_REG(UART2)
-#define UART2_C3 UART_C3_REG(UART2)
-#define UART2_D UART_D_REG(UART2)
-#define UART2_MA1 UART_MA1_REG(UART2)
-#define UART2_MA2 UART_MA2_REG(UART2)
-#define UART2_C4 UART_C4_REG(UART2)
-#define UART2_C5 UART_C5_REG(UART2)
-#define UART2_ED UART_ED_REG(UART2)
-#define UART2_MODEM UART_MODEM_REG(UART2)
-#define UART2_IR UART_IR_REG(UART2)
-#define UART2_PFIFO UART_PFIFO_REG(UART2)
-#define UART2_CFIFO UART_CFIFO_REG(UART2)
-#define UART2_SFIFO UART_SFIFO_REG(UART2)
-#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
-#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
-#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
-#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group UART_Peripheral_Access_Layer */
@@ -10701,57 +7336,7 @@ typedef struct {
__IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
uint8_t RESERVED_29[7];
__IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
-} USB_Type, *USB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register accessors */
-#define USB_PERID_REG(base) ((base)->PERID)
-#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
-#define USB_REV_REG(base) ((base)->REV)
-#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
-#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
-#define USB_OTGICR_REG(base) ((base)->OTGICR)
-#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
-#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
-#define USB_ISTAT_REG(base) ((base)->ISTAT)
-#define USB_INTEN_REG(base) ((base)->INTEN)
-#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
-#define USB_ERREN_REG(base) ((base)->ERREN)
-#define USB_STAT_REG(base) ((base)->STAT)
-#define USB_CTL_REG(base) ((base)->CTL)
-#define USB_ADDR_REG(base) ((base)->ADDR)
-#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
-#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
-#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
-#define USB_TOKEN_REG(base) ((base)->TOKEN)
-#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
-#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
-#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
-#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
-#define USB_ENDPT_COUNT 16
-#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
-#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
-#define USB_CONTROL_REG(base) ((base)->CONTROL)
-#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
-#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
-#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
-#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
-#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
-#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
+} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
@@ -10762,450 +7347,382 @@ typedef struct {
* @{
*/
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID_WIDTH 6
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID_WIDTH 6
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV_WIDTH 8
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-#define USB_ADDINFO_IEHOST_WIDTH 1
-#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_AVBUSCHG_WIDTH 1
-#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_B_SESS_CHG_WIDTH 1
-#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_SESSVLDCHG_WIDTH 1
-#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH 1
-#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_ONEMSEC_WIDTH 1
-#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-#define USB_OTGISTAT_IDCHG_WIDTH 1
-#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_AVBUSEN_WIDTH 1
-#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_BSESSEN_WIDTH 1
-#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_SESSVLDEN_WIDTH 1
-#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_LINESTATEEN_WIDTH 1
-#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_ONEMSECEN_WIDTH 1
-#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-#define USB_OTGICR_IDEN_WIDTH 1
-#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_AVBUSVLD_WIDTH 1
-#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_BSESSEND_WIDTH 1
-#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_SESS_VLD_WIDTH 1
-#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_LINESTATESTABLE_WIDTH 1
-#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ONEMSECEN_WIDTH 1
-#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-#define USB_OTGSTAT_ID_WIDTH 1
-#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_OTGEN_WIDTH 1
-#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DMLOW_WIDTH 1
-#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPLOW_WIDTH 1
-#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-#define USB_OTGCTL_DPHIGH_WIDTH 1
-#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_USBRST_WIDTH 1
-#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_ERROR_WIDTH 1
-#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_SOFTOK_WIDTH 1
-#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_TOKDNE_WIDTH 1
-#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_SLEEP_WIDTH 1
-#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_RESUME_WIDTH 1
-#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_ATTACH_WIDTH 1
-#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-#define USB_ISTAT_STALL_WIDTH 1
-#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_USBRSTEN_WIDTH 1
-#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_ERROREN_WIDTH 1
-#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_SOFTOKEN_WIDTH 1
-#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_TOKDNEEN_WIDTH 1
-#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_SLEEPEN_WIDTH 1
-#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_RESUMEEN_WIDTH 1
-#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_ATTACHEN_WIDTH 1
-#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-#define USB_INTEN_STALLEN_WIDTH 1
-#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_PIDERR_WIDTH 1
-#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC5EOF_WIDTH 1
-#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_CRC16_WIDTH 1
-#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_DFN8_WIDTH 1
-#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_BTOERR_WIDTH 1
-#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_DMAERR_WIDTH 1
-#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-#define USB_ERRSTAT_BTSERR_WIDTH 1
-#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_PIDERREN_WIDTH 1
-#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC5EOFEN_WIDTH 1
-#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_CRC16EN_WIDTH 1
-#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_DFN8EN_WIDTH 1
-#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_BTOERREN_WIDTH 1
-#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_DMAERREN_WIDTH 1
-#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-#define USB_ERREN_BTSERREN_WIDTH 1
-#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_ODD_WIDTH 1
-#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_TX_WIDTH 1
-#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP_WIDTH 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_USBENSOFEN_WIDTH 1
-#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_ODDRST_WIDTH 1
-#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_RESUME_WIDTH 1
-#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_HOSTMODEEN_WIDTH 1
-#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_RESET_WIDTH 1
-#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH 1
-#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_SE0_WIDTH 1
-#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-#define USB_CTL_JSTATE_WIDTH 1
-#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR_WIDTH 7
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-#define USB_ADDR_LSEN_WIDTH 1
-#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA_WIDTH 7
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM_WIDTH 8
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM_WIDTH 3
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT_WIDTH 4
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID_WIDTH 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT_WIDTH 8
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA_WIDTH 8
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA_WIDTH 8
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPHSHK_WIDTH 1
-#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPSTALL_WIDTH 1
-#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPTXEN_WIDTH 1
-#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPRXEN_WIDTH 1
-#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_EPCTLDIS_WIDTH 1
-#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_RETRYDIS_WIDTH 1
-#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-#define USB_ENDPT_HOSTWOHUB_WIDTH 1
-#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_PDE_WIDTH 1
-#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-#define USB_USBCTRL_SUSP_WIDTH 1
-#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DMPD_WIDTH 1
-#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPD_WIDTH 1
-#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-#define USB_OBSERVE_DPPU_WIDTH 1
-#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-#define USB_CONTROL_DPPULLUPNONOTG_WIDTH 1
-#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_USB_RESUME_INT_WIDTH 1
-#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_SYNC_DET_WIDTH 1
-#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH 1
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESMEN_WIDTH 1
-#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-#define USB_USBTRC0_USBRESET_WIDTH 1
-#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT 0
-#define USB_USBFRMADJUST_ADJ_WIDTH 8
-#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
-/* CLK_RECOVER_CTRL Bit Fields */
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
-/* CLK_RECOVER_IRC_EN Bit Fields */
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH 1
-#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH 1
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
-/* CLK_RECOVER_INT_EN Bit Fields */
-#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
-#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
-#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_WIDTH 1
-#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT))&USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
-/* CLK_RECOVER_INT_STATUS Bit Fields */
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
+#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT (7U)
+#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_AVBUSEN_MASK (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT (0U)
+#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT (2U)
+#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
+#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK (0x80U)
+#define USB_OTGICR_IDEN_SHIFT (7U)
+#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
+#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
+#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
+#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK (0x80U)
+#define USB_OTGSTAT_ID_SHIFT (7U)
+#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
/*!
* @}
@@ -11217,7 +7734,6 @@ typedef struct {
#define USB0_BASE (0x40072000u)
/** Peripheral USB0 base pointer */
#define USB0 ((USB_Type *)USB0_BASE)
-#define USB0_BASE_PTR (USB0)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { USB0_BASE }
/** Array initializer of USB peripheral base pointers */
@@ -11225,74 +7741,6 @@ typedef struct {
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS { USB0_IRQn }
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register instance definitions */
-/* USB0 */
-#define USB0_PERID USB_PERID_REG(USB0)
-#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
-#define USB0_REV USB_REV_REG(USB0)
-#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
-#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
-#define USB0_OTGICR USB_OTGICR_REG(USB0)
-#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
-#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
-#define USB0_ISTAT USB_ISTAT_REG(USB0)
-#define USB0_INTEN USB_INTEN_REG(USB0)
-#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
-#define USB0_ERREN USB_ERREN_REG(USB0)
-#define USB0_STAT USB_STAT_REG(USB0)
-#define USB0_CTL USB_CTL_REG(USB0)
-#define USB0_ADDR USB_ADDR_REG(USB0)
-#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
-#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
-#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
-#define USB0_TOKEN USB_TOKEN_REG(USB0)
-#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
-#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
-#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
-#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
-#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
-#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
-#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
-#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
-#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
-#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
-#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
-#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
-#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
-#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
-#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
-#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
-#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
-#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
-#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
-#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
-#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
-#define USB0_CONTROL USB_CONTROL_REG(USB0)
-#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
-#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
-#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
-#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
-#define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
-#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
-
-/* USB - Register array accessors */
-#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
@@ -11311,26 +7759,7 @@ typedef struct {
typedef struct {
__IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
__IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type, *VREF_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register accessors */
-#define VREF_TRM_REG(base) ((base)->TRM)
-#define VREF_SC_REG(base) ((base)->SC)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
+} VREF_Type;
/* ----------------------------------------------------------------------------
-- VREF Register Masks
@@ -11341,36 +7770,31 @@ typedef struct {
* @{
*/
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK 0x3Fu
-#define VREF_TRM_TRIM_SHIFT 0
-#define VREF_TRM_TRIM_WIDTH 6
-#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK 0x40u
-#define VREF_TRM_CHOPEN_SHIFT 6
-#define VREF_TRM_CHOPEN_WIDTH 1
-#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK 0x3u
-#define VREF_SC_MODE_LV_SHIFT 0
-#define VREF_SC_MODE_LV_WIDTH 2
-#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK 0x4u
-#define VREF_SC_VREFST_SHIFT 2
-#define VREF_SC_VREFST_WIDTH 1
-#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
-#define VREF_SC_ICOMPEN_MASK 0x20u
-#define VREF_SC_ICOMPEN_SHIFT 5
-#define VREF_SC_ICOMPEN_WIDTH 1
-#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
-#define VREF_SC_REGEN_MASK 0x40u
-#define VREF_SC_REGEN_SHIFT 6
-#define VREF_SC_REGEN_WIDTH 1
-#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
-#define VREF_SC_VREFEN_MASK 0x80u
-#define VREF_SC_VREFEN_SHIFT 7
-#define VREF_SC_VREFEN_WIDTH 1
-#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK (0x3FU)
+#define VREF_TRM_TRIM_SHIFT (0U)
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT (6U)
+#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK (0x3U)
+#define VREF_SC_MODE_LV_SHIFT (0U)
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK (0x4U)
+#define VREF_SC_VREFST_SHIFT (2U)
+#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT (5U)
+#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK (0x40U)
+#define VREF_SC_REGEN_SHIFT (6U)
+#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK (0x80U)
+#define VREF_SC_VREFEN_SHIFT (7U)
+#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+
/*!
* @}
@@ -11382,32 +7806,11 @@ typedef struct {
#define VREF_BASE (0x40074000u)
/** Peripheral VREF base pointer */
#define VREF ((VREF_Type *)VREF_BASE)
-#define VREF_BASE_PTR (VREF)
/** Array initializer of VREF peripheral base addresses */
#define VREF_BASE_ADDRS { VREF_BASE }
/** Array initializer of VREF peripheral base pointers */
#define VREF_BASE_PTRS { VREF }
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register instance definitions */
-/* VREF */
-#define VREF_TRM VREF_TRM_REG(VREF)
-#define VREF_SC VREF_SC_REG(VREF)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group VREF_Peripheral_Access_Layer */
@@ -11436,36 +7839,7 @@ typedef struct {
__IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
__IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
__IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
-} WDOG_Type, *WDOG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register accessors */
-#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
-#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
-#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
-#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
-#define WDOG_WINH_REG(base) ((base)->WINH)
-#define WDOG_WINL_REG(base) ((base)->WINL)
-#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
-#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
-#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
-#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
-#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
-#define WDOG_PRESC_REG(base) ((base)->PRESC)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
+} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
@@ -11476,110 +7850,99 @@ typedef struct {
* @{
*/
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT 0
-#define WDOG_STCTRLH_WDOGEN_WIDTH 1
-#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
-#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT 1
-#define WDOG_STCTRLH_CLKSRC_WIDTH 1
-#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
-#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
-#define WDOG_STCTRLH_IRQRSTEN_WIDTH 1
-#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
-#define WDOG_STCTRLH_WINEN_MASK 0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT 3
-#define WDOG_STCTRLH_WINEN_WIDTH 1
-#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
-#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH 1
-#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
-#define WDOG_STCTRLH_DBGEN_MASK 0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT 5
-#define WDOG_STCTRLH_DBGEN_WIDTH 1
-#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
-#define WDOG_STCTRLH_STOPEN_MASK 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT 6
-#define WDOG_STCTRLH_STOPEN_WIDTH 1
-#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
-#define WDOG_STCTRLH_WAITEN_MASK 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT 7
-#define WDOG_STCTRLH_WAITEN_WIDTH 1
-#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
-#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
-#define WDOG_STCTRLH_TESTWDOG_WIDTH 1
-#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
-#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT 11
-#define WDOG_STCTRLH_TESTSEL_WIDTH 1
-#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
-#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT 12
-#define WDOG_STCTRLH_BYTESEL_WIDTH 2
-#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
-#define WDOG_STCTRLH_DISTESTWDOG_WIDTH 1
-#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT 15
-#define WDOG_STCTRLL_INTFLG_WIDTH 1
-#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
-#define WDOG_TOVALH_TOVALHIGH_WIDTH 16
-#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT 0
-#define WDOG_TOVALL_TOVALLOW_WIDTH 16
-#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT 0
-#define WDOG_WINH_WINHIGH_WIDTH 16
-#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK 0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT 0
-#define WDOG_WINL_WINLOW_WIDTH 16
-#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
-#define WDOG_REFRESH_WDOGREFRESH_WIDTH 16
-#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
-#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH 16
-#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
-#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH 16
-#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
-#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH 16
-#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT 0
-#define WDOG_RSTCNT_RSTCNT_WIDTH 16
-#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT 8
-#define WDOG_PRESC_PRESCVAL_WIDTH 3
-#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
+#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
+#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
+#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT (3U)
+#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
+#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
+#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
+#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
+#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
+#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
+#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
+#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
+#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+
+/*! @name WINH - Watchdog Window Register High */
+#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT (0U)
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+
+/*! @name WINL - Watchdog Window Register Low */
+#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT (0U)
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+
+/*! @name REFRESH - Watchdog Refresh register */
+#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+
+/*! @name UNLOCK - Watchdog Unlock register */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+
+/*! @name RSTCNT - Watchdog Reset Count register */
+#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+
+/*! @name PRESC - Watchdog Prescaler register */
+#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
/*!
* @}
@@ -11591,7 +7954,6 @@ typedef struct {
#define WDOG_BASE (0x40052000u)
/** Peripheral WDOG base pointer */
#define WDOG ((WDOG_Type *)WDOG_BASE)
-#define WDOG_BASE_PTR (WDOG)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { WDOG_BASE }
/** Array initializer of WDOG peripheral base pointers */
@@ -11599,36 +7961,6 @@ typedef struct {
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS { WDOG_EWM_IRQn }
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register instance definitions */
-/* WDOG */
-#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
-#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
-#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
-#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
-#define WDOG_WINH WDOG_WINH_REG(WDOG)
-#define WDOG_WINL WDOG_WINL_REG(WDOG)
-#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
-#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
-#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
-#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
-#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
-#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
@@ -11656,33 +7988,53 @@ typedef struct {
/* ----------------------------------------------------------------------------
- -- Backward Compatibility
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
-#define ADC_BASES ADC_BASE_PTRS
-#define CMP_BASES CMP_BASE_PTRS
-#define CRC_BASES CRC_BASE_PTRS
-#define DAC_BASES DAC_BASE_PTRS
-#define DMA_BASES DMA_BASE_PTRS
-#define DMAMUX_BASES DMAMUX_BASE_PTRS
-#define EWM_BASES EWM_BASE_PTRS
-#define FMC_BASES FMC_BASE_PTRS
-#define FTFA_BASES FTFA_BASE_PTRS
-#define FTM_BASES FTM_BASE_PTRS
-#define GPIO_BASES GPIO_BASE_PTRS
-#define I2C_BASES I2C_BASE_PTRS
#define I2C0_S1 I2C0_S
#define I2C1_S1 I2C1_S
-#define I2S_BASES I2S_BASE_PTRS
-#define LLWU_BASES LLWU_BASE_PTRS
-#define LPTMR_BASES LPTMR_BASE_PTRS
-#define LPUART_BASES LPUART_BASE_PTRS
-#define MCG_BASES MCG_BASE_PTRS
#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
@@ -11708,28 +8060,23 @@ typedef struct {
#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
-#define MCM_BASES MCM_BASE_PTRS
-#define NV_BASES NV_BASE_PTRS
-#define OSC_BASES OSC_BASE_PTRS
#define PDB0_DACINTC1 This_symbol_has_been_deprecated
#define PDB0_DACINT1 This_symbol_has_been_deprecated
-#define PDB_BASES PDB_BASE_PTRS
-#define PIT_BASES PIT_BASE_PTRS
-#define PMC_BASES PMC_BASE_PTRS
-#define PORT_BASES PORT_BASE_PTRS
-#define RCM_BASES RCM_BASE_PTRS
-#define RFSYS_BASES RFSYS_BASE_PTRS
-#define RFVBAT_BASES RFVBAT_BASE_PTRS
-#define RTC_BASES RTC_BASE_PTRS
-#define SIM_BASES SIM_BASE_PTRS
+#define DSPI0 SPI0
+#define DSPI1 SPI1
+#define PTA_BASE GPIOA_BASE
+#define PTA GPIOA
+#define PTB_BASE GPIOB_BASE
+#define PTB GPIOB
+#define PTC_BASE GPIOC_BASE
+#define PTC GPIOC
+#define PTD_BASE GPIOD_BASE
+#define PTD GPIOD
+#define PTE_BASE GPIOE_BASE
+#define PTE GPIOE
+#define DMAMUX0 DMAMUX
#define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated
#define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated
-#define SMC_BASES SMC_BASE_PTRS
-#define SPI_BASES SPI_BASE_PTRS
-#define UART_BASES UART_BASE_PTRS
-#define USB_BASES USB_BASE_PTRS
-#define VREF_BASES VREF_BASE_PTRS
-#define WDOG_BASES WDOG_BASE_PTRS
#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
@@ -11742,31 +8089,8 @@ typedef struct {
#define LLW_IRQn LLWU_IRQn
#define LLW_IRQHandler LLWU_IRQHandler
-#define GPIOA_BASE PTA_BASE
-#define GPIOB_BASE PTB_BASE
-#define GPIOC_BASE PTC_BASE
-#define GPIOD_BASE PTD_BASE
-#define GPIOE_BASE PTE_BASE
-#define GPIOF_BASE PTF_BASE
-#define GPIOG_BASE PTG_BASE
-#define GPIOA PTA
-#define GPIOB PTB
-#define GPIOC PTC
-#define GPIOD PTD
-#define GPIOE PTE
-#define GPIOF PTF
-#define GPIOG PTG
-#define OSC0 OSC
/*!
* @}
- */ /* end of group Backward_Compatibility_Symbols */
-
+ */ /* end of group SDK_Compatibility_Symbols */
-#else /* #if !defined(MK22F12810_H_) */
- /* There is already included the same memory map. Check if it is compatible (has the same major version) */
- #if (MCU_MEM_MAP_VERSION != 0x0100u)
- #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
- #warning There are included two not compatible versions of memory maps. Please check possible differences.
- #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
- #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
-#endif /* #if !defined(MK22F12810_H_) */
+#endif /* _MK22F12810_H_ */
diff --git a/cpu/k22f/include/vendor/MK22F25612.h b/cpu/k22f/include/vendor/MK22F25612.h
index 4f34837667..c005c2789b 100644
--- a/cpu/k22f/include/vendor/MK22F25612.h
+++ b/cpu/k22f/include/vendor/MK22F25612.h
@@ -1,21 +1,27 @@
/*
** ###################################################################
+** Processors: MK22FN128CAH12
+** MK22FN256CAH12
+** MK22FN256VDC12
+** MK22FN256VLH12
+** MK22FN256VLL12
+** MK22FN256VMP12
+**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
**
** Reference manual: K22P121M120SF8RM, Rev. 1, March 24, 2014
** Version: rev. 1.8, 2015-02-19
-** Build: b150225
+** Build: b170112
**
** Abstract:
** CMSIS Peripheral Access Layer for MK22F25612
**
-** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
+** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
@@ -26,7 +32,7 @@
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
@@ -41,8 +47,8 @@
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
-** http: www.freescale.com
-** mail: support@freescale.com
+** http: www.nxp.com
+** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2013-09-17)
@@ -79,29 +85,14 @@
* CMSIS Peripheral Access Layer for MK22F25612
*/
-
-/* ----------------------------------------------------------------------------
- -- MCU activation
- ---------------------------------------------------------------------------- */
-
-/* Prevention from multiple including the same memory map */
-#if !defined(MK22F25612_H_) /* Check if memory map has not been already included */
-#define MK22F25612_H_
-#define MCU_MK22F25612
-
-/* Check if another memory map has not been also included */
-#if (defined(MCU_ACTIVE))
- #error MK22F25612 memory map: There is already included another memory map. Only one memory map can be included.
-#endif /* (defined(MCU_ACTIVE)) */
-#define MCU_ACTIVE
-
-#include <stdint.h>
+#ifndef _MK22F25612_H_
+#define _MK22F25612_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
+#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0008u
+#define MCU_MEM_MAP_VERSION_MINOR 0x0008U
/**
* @brief Macro to calculate address of an aliased word in the peripheral
@@ -120,8 +111,8 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -130,7 +121,7 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -139,7 +130,7 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
@@ -283,6 +274,108 @@ typedef enum IRQn {
*/ /* end of group Cortex_Core_Configuration */
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
+ kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
+ kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
+ kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
+ kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
+ kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
+ kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
+ kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
+ kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
+ kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
+ kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
+ kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
+ kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
+ kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
+ kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
+ kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
+ kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
+ kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */
+ kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
+ kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1. */
+ kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
+ kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
+ kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
+ kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
+ kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
+ kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
+ kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
+ kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
+ kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
+ kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
+ kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
+ kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
+ kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */
+ kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */
+ kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */
+ kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */
+ kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
+ kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
+ kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
+ kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
+ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
+ kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
+ kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
+ kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
+ kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
+ kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
+ kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
+ kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
+ kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
+ kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
+ kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
+ kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
+ kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
+ kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
+ kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
+ kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
+ kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
+ kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
+ kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
+ kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
+ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -348,51 +441,7 @@ typedef struct {
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type, *ADC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register accessors */
-#define ADC_SC1_REG(base,index) ((base)->SC1[index])
-#define ADC_SC1_COUNT 2
-#define ADC_CFG1_REG(base) ((base)->CFG1)
-#define ADC_CFG2_REG(base) ((base)->CFG2)
-#define ADC_R_REG(base,index) ((base)->R[index])
-#define ADC_R_COUNT 2
-#define ADC_CV1_REG(base) ((base)->CV1)
-#define ADC_CV2_REG(base) ((base)->CV2)
-#define ADC_SC2_REG(base) ((base)->SC2)
-#define ADC_SC3_REG(base) ((base)->SC3)
-#define ADC_OFS_REG(base) ((base)->OFS)
-#define ADC_PG_REG(base) ((base)->PG)
-#define ADC_MG_REG(base) ((base)->MG)
-#define ADC_CLPD_REG(base) ((base)->CLPD)
-#define ADC_CLPS_REG(base) ((base)->CLPS)
-#define ADC_CLP4_REG(base) ((base)->CLP4)
-#define ADC_CLP3_REG(base) ((base)->CLP3)
-#define ADC_CLP2_REG(base) ((base)->CLP2)
-#define ADC_CLP1_REG(base) ((base)->CLP1)
-#define ADC_CLP0_REG(base) ((base)->CLP0)
-#define ADC_CLMD_REG(base) ((base)->CLMD)
-#define ADC_CLMS_REG(base) ((base)->CLMS)
-#define ADC_CLM4_REG(base) ((base)->CLM4)
-#define ADC_CLM3_REG(base) ((base)->CLM3)
-#define ADC_CLM2_REG(base) ((base)->CLM2)
-#define ADC_CLM1_REG(base) ((base)->CLM1)
-#define ADC_CLM0_REG(base) ((base)->CLM0)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
+} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
@@ -403,211 +452,197 @@ typedef struct {
* @{
*/
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH_WIDTH 5
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_DIFF_WIDTH 1
-#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_AIEN_WIDTH 1
-#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-#define ADC_SC1_COCO_WIDTH 1
-#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK_WIDTH 2
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE_WIDTH 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADLSMP_WIDTH 1
-#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV_WIDTH 2
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-#define ADC_CFG1_ADLPC_WIDTH 1
-#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS_WIDTH 2
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADHSC_WIDTH 1
-#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_ADACKEN_WIDTH 1
-#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-#define ADC_CFG2_MUXSEL_WIDTH 1
-#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D_WIDTH 16
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV_WIDTH 16
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV_WIDTH 16
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL_WIDTH 2
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_DMAEN_WIDTH 1
-#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACREN_WIDTH 1
-#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFGT_WIDTH 1
-#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ACFE_WIDTH 1
-#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADTRG_WIDTH 1
-#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-#define ADC_SC2_ADACT_WIDTH 1
-#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS_WIDTH 2
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_AVGE_WIDTH 1
-#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_ADCO_WIDTH 1
-#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CALF_WIDTH 1
-#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-#define ADC_SC3_CAL_WIDTH 1
-#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS_WIDTH 16
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG_WIDTH 16
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG_WIDTH 16
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD_WIDTH 6
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS_WIDTH 6
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4_WIDTH 10
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3_WIDTH 9
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2_WIDTH 8
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1_WIDTH 7
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0_WIDTH 6
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD_WIDTH 6
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS_WIDTH 6
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4_WIDTH 10
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3_WIDTH 9
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2_WIDTH 8
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1_WIDTH 7
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0_WIDTH 6
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK (0x1FU)
+#define ADC_SC1_ADCH_SHIFT (0U)
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK (0x20U)
+#define ADC_SC1_DIFF_SHIFT (5U)
+#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK (0x40U)
+#define ADC_SC1_AIEN_SHIFT (6U)
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK (0x80U)
+#define ADC_SC1_COCO_SHIFT (7U)
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT (0U)
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK (0xCU)
+#define ADC_CFG1_MODE_SHIFT (2U)
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT (4U)
+#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK (0x60U)
+#define ADC_CFG1_ADIV_SHIFT (5U)
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT (7U)
+#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT (0U)
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT (2U)
+#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT (3U)
+#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT (4U)
+#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK (0xFFFFU)
+#define ADC_R_D_SHIFT (0U)
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK (0xFFFFU)
+#define ADC_CV1_CV_SHIFT (0U)
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK (0xFFFFU)
+#define ADC_CV2_CV_SHIFT (0U)
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK (0x3U)
+#define ADC_SC2_REFSEL_SHIFT (0U)
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK (0x4U)
+#define ADC_SC2_DMAEN_SHIFT (2U)
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK (0x8U)
+#define ADC_SC2_ACREN_SHIFT (3U)
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK (0x10U)
+#define ADC_SC2_ACFGT_SHIFT (4U)
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK (0x20U)
+#define ADC_SC2_ACFE_SHIFT (5U)
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK (0x40U)
+#define ADC_SC2_ADTRG_SHIFT (6U)
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK (0x80U)
+#define ADC_SC2_ADACT_SHIFT (7U)
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK (0x3U)
+#define ADC_SC3_AVGS_SHIFT (0U)
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK (0x4U)
+#define ADC_SC3_AVGE_SHIFT (2U)
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK (0x8U)
+#define ADC_SC3_ADCO_SHIFT (3U)
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK (0x40U)
+#define ADC_SC3_CALF_SHIFT (6U)
+#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK (0x80U)
+#define ADC_SC3_CAL_SHIFT (7U)
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK (0xFFFFU)
+#define ADC_PG_PG_SHIFT (0U)
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK (0xFFFFU)
+#define ADC_MG_MG_SHIFT (0U)
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT (0U)
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT (0U)
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT (0U)
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT (0U)
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT (0U)
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT (0U)
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT (0U)
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT (0U)
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT (0U)
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT (0U)
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT (0U)
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT (0U)
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT (0U)
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT (0U)
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
/*!
* @}
@@ -619,12 +654,10 @@ typedef struct {
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
-#define ADC0_BASE_PTR (ADC0)
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x40027000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
-#define ADC1_BASE_PTR (ADC1)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
/** Array initializer of ADC peripheral base pointers */
@@ -632,85 +665,6 @@ typedef struct {
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register instance definitions */
-/* ADC0 */
-#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
-#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
-#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
-#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
-#define ADC0_RA ADC_R_REG(ADC0,0)
-#define ADC0_RB ADC_R_REG(ADC0,1)
-#define ADC0_CV1 ADC_CV1_REG(ADC0)
-#define ADC0_CV2 ADC_CV2_REG(ADC0)
-#define ADC0_SC2 ADC_SC2_REG(ADC0)
-#define ADC0_SC3 ADC_SC3_REG(ADC0)
-#define ADC0_OFS ADC_OFS_REG(ADC0)
-#define ADC0_PG ADC_PG_REG(ADC0)
-#define ADC0_MG ADC_MG_REG(ADC0)
-#define ADC0_CLPD ADC_CLPD_REG(ADC0)
-#define ADC0_CLPS ADC_CLPS_REG(ADC0)
-#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
-#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
-#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
-#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
-#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
-#define ADC0_CLMD ADC_CLMD_REG(ADC0)
-#define ADC0_CLMS ADC_CLMS_REG(ADC0)
-#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
-#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
-#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
-#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
-#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
-/* ADC1 */
-#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
-#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
-#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
-#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
-#define ADC1_RA ADC_R_REG(ADC1,0)
-#define ADC1_RB ADC_R_REG(ADC1,1)
-#define ADC1_CV1 ADC_CV1_REG(ADC1)
-#define ADC1_CV2 ADC_CV2_REG(ADC1)
-#define ADC1_SC2 ADC_SC2_REG(ADC1)
-#define ADC1_SC3 ADC_SC3_REG(ADC1)
-#define ADC1_OFS ADC_OFS_REG(ADC1)
-#define ADC1_PG ADC_PG_REG(ADC1)
-#define ADC1_MG ADC_MG_REG(ADC1)
-#define ADC1_CLPD ADC_CLPD_REG(ADC1)
-#define ADC1_CLPS ADC_CLPS_REG(ADC1)
-#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
-#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
-#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
-#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
-#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
-#define ADC1_CLMD ADC_CLMD_REG(ADC1)
-#define ADC1_CLMS ADC_CLMS_REG(ADC1)
-#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
-#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
-#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
-#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
-#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
-
-/* ADC - Register array accessors */
-#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
-#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
-#define ADC0_R(index) ADC_R_REG(ADC0,index)
-#define ADC1_R(index) ADC_R_REG(ADC1,index)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
@@ -733,30 +687,7 @@ typedef struct {
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type, *CMP_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register accessors */
-#define CMP_CR0_REG(base) ((base)->CR0)
-#define CMP_CR1_REG(base) ((base)->CR1)
-#define CMP_FPR_REG(base) ((base)->FPR)
-#define CMP_SCR_REG(base) ((base)->SCR)
-#define CMP_DACCR_REG(base) ((base)->DACCR)
-#define CMP_MUXCR_REG(base) ((base)->MUXCR)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
+} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
@@ -767,100 +698,84 @@ typedef struct {
* @{
*/
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR_WIDTH 2
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT_WIDTH 3
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_EN_WIDTH 1
-#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_OPE_WIDTH 1
-#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_COS_WIDTH 1
-#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_INV_WIDTH 1
-#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_PMODE_WIDTH 1
-#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
-#define CMP_CR1_TRIGM_MASK 0x20u
-#define CMP_CR1_TRIGM_SHIFT 5
-#define CMP_CR1_TRIGM_WIDTH 1
-#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_TRIGM_SHIFT))&CMP_CR1_TRIGM_MASK)
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_WE_WIDTH 1
-#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-#define CMP_CR1_SE_WIDTH 1
-#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER_WIDTH 8
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_COUT_WIDTH 1
-#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFF_WIDTH 1
-#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_CFR_WIDTH 1
-#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IEF_WIDTH 1
-#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_IER_WIDTH 1
-#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-#define CMP_SCR_DMAEN_WIDTH 1
-#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL_WIDTH 6
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_VRSEL_WIDTH 1
-#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-#define CMP_DACCR_DACEN_WIDTH 1
-#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL_WIDTH 3
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL_WIDTH 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK (0x20U)
+#define CMP_CR1_TRIGM_SHIFT (5U)
+#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+
/*!
* @}
@@ -872,12 +787,10 @@ typedef struct {
#define CMP0_BASE (0x40073000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
-#define CMP0_BASE_PTR (CMP0)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x40073008u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
-#define CMP1_BASE_PTR (CMP1)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
/** Array initializer of CMP peripheral base pointers */
@@ -885,37 +798,6 @@ typedef struct {
/** Interrupt vectors for the CMP peripheral type */
#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register instance definitions */
-/* CMP0 */
-#define CMP0_CR0 CMP_CR0_REG(CMP0)
-#define CMP0_CR1 CMP_CR1_REG(CMP0)
-#define CMP0_FPR CMP_FPR_REG(CMP0)
-#define CMP0_SCR CMP_SCR_REG(CMP0)
-#define CMP0_DACCR CMP_DACCR_REG(CMP0)
-#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
-/* CMP1 */
-#define CMP1_CR0 CMP_CR0_REG(CMP1)
-#define CMP1_CR1 CMP_CR1_REG(CMP1)
-#define CMP1_FPR CMP_FPR_REG(CMP1)
-#define CMP1_SCR CMP_SCR_REG(CMP1)
-#define CMP1_DACCR CMP_DACCR_REG(CMP1)
-#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
@@ -965,40 +847,7 @@ typedef struct {
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
-} CRC_Type, *CRC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register accessors */
-#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
-#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
-#define CRC_DATA_REG(base) ((base)->DATA)
-#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
-#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
-#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
-#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
-#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
-#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
-#define CRC_GPOLY_REG(base) ((base)->GPOLY)
-#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
-#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
-#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
-#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
-#define CRC_CTRL_REG(base) ((base)->CTRL)
-#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
+} CRC_Type;
/* ----------------------------------------------------------------------------
-- CRC Register Masks
@@ -1009,134 +858,122 @@ typedef struct {
* @{
*/
-/* DATAL Bit Fields */
-#define CRC_DATAL_DATAL_MASK 0xFFFFu
-#define CRC_DATAL_DATAL_SHIFT 0
-#define CRC_DATAL_DATAL_WIDTH 16
-#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
-/* DATAH Bit Fields */
-#define CRC_DATAH_DATAH_MASK 0xFFFFu
-#define CRC_DATAH_DATAH_SHIFT 0
-#define CRC_DATAH_DATAH_WIDTH 16
-#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
-/* DATA Bit Fields */
-#define CRC_DATA_LL_MASK 0xFFu
-#define CRC_DATA_LL_SHIFT 0
-#define CRC_DATA_LL_WIDTH 8
-#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
-#define CRC_DATA_LU_MASK 0xFF00u
-#define CRC_DATA_LU_SHIFT 8
-#define CRC_DATA_LU_WIDTH 8
-#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
-#define CRC_DATA_HL_MASK 0xFF0000u
-#define CRC_DATA_HL_SHIFT 16
-#define CRC_DATA_HL_WIDTH 8
-#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
-#define CRC_DATA_HU_MASK 0xFF000000u
-#define CRC_DATA_HU_SHIFT 24
-#define CRC_DATA_HU_WIDTH 8
-#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
-/* DATALL Bit Fields */
-#define CRC_DATALL_DATALL_MASK 0xFFu
-#define CRC_DATALL_DATALL_SHIFT 0
-#define CRC_DATALL_DATALL_WIDTH 8
-#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
-/* DATALU Bit Fields */
-#define CRC_DATALU_DATALU_MASK 0xFFu
-#define CRC_DATALU_DATALU_SHIFT 0
-#define CRC_DATALU_DATALU_WIDTH 8
-#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
-/* DATAHL Bit Fields */
-#define CRC_DATAHL_DATAHL_MASK 0xFFu
-#define CRC_DATAHL_DATAHL_SHIFT 0
-#define CRC_DATAHL_DATAHL_WIDTH 8
-#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
-/* DATAHU Bit Fields */
-#define CRC_DATAHU_DATAHU_MASK 0xFFu
-#define CRC_DATAHU_DATAHU_SHIFT 0
-#define CRC_DATAHU_DATAHU_WIDTH 8
-#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT 0
-#define CRC_GPOLYL_GPOLYL_WIDTH 16
-#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT 0
-#define CRC_GPOLYH_GPOLYH_WIDTH 16
-#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK 0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT 0
-#define CRC_GPOLY_LOW_WIDTH 16
-#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT 16
-#define CRC_GPOLY_HIGH_WIDTH 16
-#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
-#define CRC_GPOLYLL_GPOLYLL_WIDTH 8
-#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
-#define CRC_GPOLYLU_GPOLYLU_WIDTH 8
-#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
-#define CRC_GPOLYHL_GPOLYHL_WIDTH 8
-#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
-#define CRC_GPOLYHU_GPOLYHU_WIDTH 8
-#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK 0x1000000u
-#define CRC_CTRL_TCRC_SHIFT 24
-#define CRC_CTRL_TCRC_WIDTH 1
-#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
-#define CRC_CTRL_WAS_MASK 0x2000000u
-#define CRC_CTRL_WAS_SHIFT 25
-#define CRC_CTRL_WAS_WIDTH 1
-#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
-#define CRC_CTRL_FXOR_MASK 0x4000000u
-#define CRC_CTRL_FXOR_SHIFT 26
-#define CRC_CTRL_FXOR_WIDTH 1
-#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
-#define CRC_CTRL_TOTR_MASK 0x30000000u
-#define CRC_CTRL_TOTR_SHIFT 28
-#define CRC_CTRL_TOTR_WIDTH 2
-#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK 0xC0000000u
-#define CRC_CTRL_TOT_SHIFT 30
-#define CRC_CTRL_TOT_WIDTH 2
-#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK 0x1u
-#define CRC_CTRLHU_TCRC_SHIFT 0
-#define CRC_CTRLHU_TCRC_WIDTH 1
-#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
-#define CRC_CTRLHU_WAS_MASK 0x2u
-#define CRC_CTRLHU_WAS_SHIFT 1
-#define CRC_CTRLHU_WAS_WIDTH 1
-#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
-#define CRC_CTRLHU_FXOR_MASK 0x4u
-#define CRC_CTRLHU_FXOR_SHIFT 2
-#define CRC_CTRLHU_FXOR_WIDTH 1
-#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
-#define CRC_CTRLHU_TOTR_MASK 0x30u
-#define CRC_CTRLHU_TOTR_SHIFT 4
-#define CRC_CTRLHU_TOTR_WIDTH 2
-#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK 0xC0u
-#define CRC_CTRLHU_TOT_SHIFT 6
-#define CRC_CTRLHU_TOT_WIDTH 2
-#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+/*! @name DATAL - CRC_DATAL register. */
+#define CRC_DATAL_DATAL_MASK (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT (0U)
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+
+/*! @name DATAH - CRC_DATAH register. */
+#define CRC_DATAH_DATAH_MASK (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT (0U)
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+
+/*! @name DATA - CRC Data register */
+#define CRC_DATA_LL_MASK (0xFFU)
+#define CRC_DATA_LL_SHIFT (0U)
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK (0xFF00U)
+#define CRC_DATA_LU_SHIFT (8U)
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK (0xFF0000U)
+#define CRC_DATA_HL_SHIFT (16U)
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK (0xFF000000U)
+#define CRC_DATA_HU_SHIFT (24U)
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+
+/*! @name DATALL - CRC_DATALL register. */
+#define CRC_DATALL_DATALL_MASK (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT (0U)
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+
+/*! @name DATALU - CRC_DATALU register. */
+#define CRC_DATALU_DATALU_MASK (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT (0U)
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+
+/*! @name DATAHL - CRC_DATAHL register. */
+#define CRC_DATAHL_DATAHL_MASK (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT (0U)
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+
+/*! @name DATAHU - CRC_DATAHU register. */
+#define CRC_DATAHU_DATAHU_MASK (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT (0U)
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial register */
+#define CRC_GPOLY_LOW_MASK (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT (0U)
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT (16U)
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control register */
+#define CRC_CTRL_TCRC_MASK (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT (24U)
+#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT (25U)
+#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT (26U)
+#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT (28U)
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT (30U)
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC_MASK (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT (0U)
+#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT (1U)
+#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT (2U)
+#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT (4U)
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT (6U)
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
/*!
* @}
@@ -1148,46 +985,11 @@ typedef struct {
#define CRC_BASE (0x40032000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
-#define CRC_BASE_PTR (CRC0)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS { CRC_BASE }
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS { CRC0 }
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register instance definitions */
-/* CRC */
-#define CRC_DATA CRC_DATA_REG(CRC0)
-#define CRC_DATAL CRC_DATAL_REG(CRC0)
-#define CRC_DATALL CRC_DATALL_REG(CRC0)
-#define CRC_DATALU CRC_DATALU_REG(CRC0)
-#define CRC_DATAH CRC_DATAH_REG(CRC0)
-#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
-#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
-#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
-#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
-#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
-#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
-#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
-#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
-#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
-#define CRC_CTRL CRC_CTRL_REG(CRC0)
-#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
@@ -1212,32 +1014,7 @@ typedef struct {
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type, *DAC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register accessors */
-#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
-#define DAC_DATL_COUNT 16
-#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
-#define DAC_DATH_COUNT 16
-#define DAC_SR_REG(base) ((base)->SR)
-#define DAC_C0_REG(base) ((base)->C0)
-#define DAC_C1_REG(base) ((base)->C1)
-#define DAC_C2_REG(base) ((base)->C2)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
+} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
@@ -1248,88 +1025,81 @@ typedef struct {
* @{
*/
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0_WIDTH 8
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1_WIDTH 4
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPBF_WIDTH 1
-#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-#define DAC_SR_DACBFRPTF_WIDTH 1
-#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
-#define DAC_SR_DACBFWMF_MASK 0x4u
-#define DAC_SR_DACBFWMF_SHIFT 2
-#define DAC_SR_DACBFWMF_WIDTH 1
-#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBBIEN_WIDTH 1
-#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_DACBTIEN_WIDTH 1
-#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
-#define DAC_C0_DACBWIEN_MASK 0x4u
-#define DAC_C0_DACBWIEN_SHIFT 2
-#define DAC_C0_DACBWIEN_WIDTH 1
-#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_LPEN_WIDTH 1
-#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACSWTRG_WIDTH 1
-#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACTRGSEL_WIDTH 1
-#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACRFS_WIDTH 1
-#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-#define DAC_C0_DACEN_WIDTH 1
-#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFEN_WIDTH 1
-#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
-#define DAC_C1_DACBFMD_MASK 0x6u
-#define DAC_C1_DACBFMD_SHIFT 1
-#define DAC_C1_DACBFMD_WIDTH 2
-#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
-#define DAC_C1_DACBFWM_MASK 0x18u
-#define DAC_C1_DACBFWM_SHIFT 3
-#define DAC_C1_DACBFWM_WIDTH 2
-#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-#define DAC_C1_DMAEN_WIDTH 1
-#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0xFu
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFUP_WIDTH 4
-#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
-#define DAC_C2_DACBFRP_MASK 0xF0u
-#define DAC_C2_DACBFRP_SHIFT 4
-#define DAC_C2_DACBFRP_WIDTH 4
-#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK (0xFFU)
+#define DAC_DATL_DATA0_SHIFT (0U)
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT (16U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK (0xFU)
+#define DAC_DATH_DATA1_SHIFT (0U)
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT (16U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT (0U)
+#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT (1U)
+#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK (0x4U)
+#define DAC_SR_DACBFWMF_SHIFT (2U)
+#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT (0U)
+#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT (1U)
+#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK (0x4U)
+#define DAC_C0_DACBWIEN_SHIFT (2U)
+#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK (0x8U)
+#define DAC_C0_LPEN_SHIFT (3U)
+#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT (4U)
+#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT (5U)
+#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK (0x40U)
+#define DAC_C0_DACRFS_SHIFT (6U)
+#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK (0x80U)
+#define DAC_C0_DACEN_SHIFT (7U)
+#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK (0x1U)
+#define DAC_C1_DACBFEN_SHIFT (0U)
+#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK (0x6U)
+#define DAC_C1_DACBFMD_SHIFT (1U)
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK (0x18U)
+#define DAC_C1_DACBFWM_SHIFT (3U)
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK (0x80U)
+#define DAC_C1_DMAEN_SHIFT (7U)
+#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK (0xFU)
+#define DAC_C2_DACBFUP_SHIFT (0U)
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT (4U)
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
/*!
* @}
@@ -1341,7 +1111,6 @@ typedef struct {
#define DAC0_BASE (0x4003F000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
-#define DAC0_BASE_PTR (DAC0)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS { DAC0_BASE }
/** Array initializer of DAC peripheral base pointers */
@@ -1349,64 +1118,6 @@ typedef struct {
/** Interrupt vectors for the DAC peripheral type */
#define DAC_IRQS { DAC0_IRQn }
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register instance definitions */
-/* DAC0 */
-#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
-#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
-#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
-#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
-#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
-#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
-#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
-#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
-#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
-#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
-#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
-#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
-#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
-#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
-#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
-#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
-#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
-#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
-#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
-#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
-#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
-#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
-#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
-#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
-#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
-#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
-#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
-#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
-#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
-#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
-#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
-#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
-#define DAC0_SR DAC_SR_REG(DAC0)
-#define DAC0_C0 DAC_C0_REG(DAC0)
-#define DAC0_C1 DAC_C1_REG(DAC0)
-#define DAC0_C2 DAC_C2_REG(DAC0)
-
-/* DAC - Register array accessors */
-#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
-#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
@@ -1486,86 +1197,7 @@ typedef struct {
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[16];
-} DMA_Type, *DMA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register accessors */
-#define DMA_CR_REG(base) ((base)->CR)
-#define DMA_ES_REG(base) ((base)->ES)
-#define DMA_ERQ_REG(base) ((base)->ERQ)
-#define DMA_EEI_REG(base) ((base)->EEI)
-#define DMA_CEEI_REG(base) ((base)->CEEI)
-#define DMA_SEEI_REG(base) ((base)->SEEI)
-#define DMA_CERQ_REG(base) ((base)->CERQ)
-#define DMA_SERQ_REG(base) ((base)->SERQ)
-#define DMA_CDNE_REG(base) ((base)->CDNE)
-#define DMA_SSRT_REG(base) ((base)->SSRT)
-#define DMA_CERR_REG(base) ((base)->CERR)
-#define DMA_CINT_REG(base) ((base)->CINT)
-#define DMA_INT_REG(base) ((base)->INT)
-#define DMA_ERR_REG(base) ((base)->ERR)
-#define DMA_HRS_REG(base) ((base)->HRS)
-#define DMA_EARS_REG(base) ((base)->EARS)
-#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
-#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
-#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
-#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
-#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
-#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
-#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
-#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
-#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
-#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
-#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
-#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
-#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
-#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
-#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
-#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
-#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
-#define DMA_SADDR_COUNT 16
-#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
-#define DMA_SOFF_COUNT 16
-#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
-#define DMA_ATTR_COUNT 16
-#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
-#define DMA_NBYTES_MLNO_COUNT 16
-#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
-#define DMA_NBYTES_MLOFFNO_COUNT 16
-#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
-#define DMA_NBYTES_MLOFFYES_COUNT 16
-#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
-#define DMA_SLAST_COUNT 16
-#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
-#define DMA_DADDR_COUNT 16
-#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
-#define DMA_DOFF_COUNT 16
-#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
-#define DMA_CITER_ELINKNO_COUNT 16
-#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
-#define DMA_CITER_ELINKYES_COUNT 16
-#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
-#define DMA_DLAST_SGA_COUNT 16
-#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
-#define DMA_CSR_COUNT 16
-#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
-#define DMA_BITER_ELINKNO_COUNT 16
-#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
-#define DMA_BITER_ELINKYES_COUNT 16
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
+} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
@@ -1576,957 +1208,823 @@ typedef struct {
* @{
*/
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK 0x2u
-#define DMA_CR_EDBG_SHIFT 1
-#define DMA_CR_EDBG_WIDTH 1
-#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
-#define DMA_CR_ERCA_MASK 0x4u
-#define DMA_CR_ERCA_SHIFT 2
-#define DMA_CR_ERCA_WIDTH 1
-#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
-#define DMA_CR_HOE_MASK 0x10u
-#define DMA_CR_HOE_SHIFT 4
-#define DMA_CR_HOE_WIDTH 1
-#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
-#define DMA_CR_HALT_MASK 0x20u
-#define DMA_CR_HALT_SHIFT 5
-#define DMA_CR_HALT_WIDTH 1
-#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
-#define DMA_CR_CLM_MASK 0x40u
-#define DMA_CR_CLM_SHIFT 6
-#define DMA_CR_CLM_WIDTH 1
-#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
-#define DMA_CR_EMLM_MASK 0x80u
-#define DMA_CR_EMLM_SHIFT 7
-#define DMA_CR_EMLM_WIDTH 1
-#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
-#define DMA_CR_ECX_MASK 0x10000u
-#define DMA_CR_ECX_SHIFT 16
-#define DMA_CR_ECX_WIDTH 1
-#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
-#define DMA_CR_CX_MASK 0x20000u
-#define DMA_CR_CX_SHIFT 17
-#define DMA_CR_CX_WIDTH 1
-#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK 0x1u
-#define DMA_ES_DBE_SHIFT 0
-#define DMA_ES_DBE_WIDTH 1
-#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
-#define DMA_ES_SBE_MASK 0x2u
-#define DMA_ES_SBE_SHIFT 1
-#define DMA_ES_SBE_WIDTH 1
-#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
-#define DMA_ES_SGE_MASK 0x4u
-#define DMA_ES_SGE_SHIFT 2
-#define DMA_ES_SGE_WIDTH 1
-#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
-#define DMA_ES_NCE_MASK 0x8u
-#define DMA_ES_NCE_SHIFT 3
-#define DMA_ES_NCE_WIDTH 1
-#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
-#define DMA_ES_DOE_MASK 0x10u
-#define DMA_ES_DOE_SHIFT 4
-#define DMA_ES_DOE_WIDTH 1
-#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
-#define DMA_ES_DAE_MASK 0x20u
-#define DMA_ES_DAE_SHIFT 5
-#define DMA_ES_DAE_WIDTH 1
-#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
-#define DMA_ES_SOE_MASK 0x40u
-#define DMA_ES_SOE_SHIFT 6
-#define DMA_ES_SOE_WIDTH 1
-#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
-#define DMA_ES_SAE_MASK 0x80u
-#define DMA_ES_SAE_SHIFT 7
-#define DMA_ES_SAE_WIDTH 1
-#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
-#define DMA_ES_ERRCHN_MASK 0xF00u
-#define DMA_ES_ERRCHN_SHIFT 8
-#define DMA_ES_ERRCHN_WIDTH 4
-#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK 0x4000u
-#define DMA_ES_CPE_SHIFT 14
-#define DMA_ES_CPE_WIDTH 1
-#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
-#define DMA_ES_ECX_MASK 0x10000u
-#define DMA_ES_ECX_SHIFT 16
-#define DMA_ES_ECX_WIDTH 1
-#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
-#define DMA_ES_VLD_MASK 0x80000000u
-#define DMA_ES_VLD_SHIFT 31
-#define DMA_ES_VLD_WIDTH 1
-#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK 0x1u
-#define DMA_ERQ_ERQ0_SHIFT 0
-#define DMA_ERQ_ERQ0_WIDTH 1
-#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
-#define DMA_ERQ_ERQ1_MASK 0x2u
-#define DMA_ERQ_ERQ1_SHIFT 1
-#define DMA_ERQ_ERQ1_WIDTH 1
-#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
-#define DMA_ERQ_ERQ2_MASK 0x4u
-#define DMA_ERQ_ERQ2_SHIFT 2
-#define DMA_ERQ_ERQ2_WIDTH 1
-#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
-#define DMA_ERQ_ERQ3_MASK 0x8u
-#define DMA_ERQ_ERQ3_SHIFT 3
-#define DMA_ERQ_ERQ3_WIDTH 1
-#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
-#define DMA_ERQ_ERQ4_MASK 0x10u
-#define DMA_ERQ_ERQ4_SHIFT 4
-#define DMA_ERQ_ERQ4_WIDTH 1
-#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
-#define DMA_ERQ_ERQ5_MASK 0x20u
-#define DMA_ERQ_ERQ5_SHIFT 5
-#define DMA_ERQ_ERQ5_WIDTH 1
-#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
-#define DMA_ERQ_ERQ6_MASK 0x40u
-#define DMA_ERQ_ERQ6_SHIFT 6
-#define DMA_ERQ_ERQ6_WIDTH 1
-#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
-#define DMA_ERQ_ERQ7_MASK 0x80u
-#define DMA_ERQ_ERQ7_SHIFT 7
-#define DMA_ERQ_ERQ7_WIDTH 1
-#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
-#define DMA_ERQ_ERQ8_MASK 0x100u
-#define DMA_ERQ_ERQ8_SHIFT 8
-#define DMA_ERQ_ERQ8_WIDTH 1
-#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
-#define DMA_ERQ_ERQ9_MASK 0x200u
-#define DMA_ERQ_ERQ9_SHIFT 9
-#define DMA_ERQ_ERQ9_WIDTH 1
-#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
-#define DMA_ERQ_ERQ10_MASK 0x400u
-#define DMA_ERQ_ERQ10_SHIFT 10
-#define DMA_ERQ_ERQ10_WIDTH 1
-#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
-#define DMA_ERQ_ERQ11_MASK 0x800u
-#define DMA_ERQ_ERQ11_SHIFT 11
-#define DMA_ERQ_ERQ11_WIDTH 1
-#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
-#define DMA_ERQ_ERQ12_MASK 0x1000u
-#define DMA_ERQ_ERQ12_SHIFT 12
-#define DMA_ERQ_ERQ12_WIDTH 1
-#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
-#define DMA_ERQ_ERQ13_MASK 0x2000u
-#define DMA_ERQ_ERQ13_SHIFT 13
-#define DMA_ERQ_ERQ13_WIDTH 1
-#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
-#define DMA_ERQ_ERQ14_MASK 0x4000u
-#define DMA_ERQ_ERQ14_SHIFT 14
-#define DMA_ERQ_ERQ14_WIDTH 1
-#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
-#define DMA_ERQ_ERQ15_MASK 0x8000u
-#define DMA_ERQ_ERQ15_SHIFT 15
-#define DMA_ERQ_ERQ15_WIDTH 1
-#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK 0x1u
-#define DMA_EEI_EEI0_SHIFT 0
-#define DMA_EEI_EEI0_WIDTH 1
-#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
-#define DMA_EEI_EEI1_MASK 0x2u
-#define DMA_EEI_EEI1_SHIFT 1
-#define DMA_EEI_EEI1_WIDTH 1
-#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
-#define DMA_EEI_EEI2_MASK 0x4u
-#define DMA_EEI_EEI2_SHIFT 2
-#define DMA_EEI_EEI2_WIDTH 1
-#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
-#define DMA_EEI_EEI3_MASK 0x8u
-#define DMA_EEI_EEI3_SHIFT 3
-#define DMA_EEI_EEI3_WIDTH 1
-#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
-#define DMA_EEI_EEI4_MASK 0x10u
-#define DMA_EEI_EEI4_SHIFT 4
-#define DMA_EEI_EEI4_WIDTH 1
-#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
-#define DMA_EEI_EEI5_MASK 0x20u
-#define DMA_EEI_EEI5_SHIFT 5
-#define DMA_EEI_EEI5_WIDTH 1
-#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
-#define DMA_EEI_EEI6_MASK 0x40u
-#define DMA_EEI_EEI6_SHIFT 6
-#define DMA_EEI_EEI6_WIDTH 1
-#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
-#define DMA_EEI_EEI7_MASK 0x80u
-#define DMA_EEI_EEI7_SHIFT 7
-#define DMA_EEI_EEI7_WIDTH 1
-#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
-#define DMA_EEI_EEI8_MASK 0x100u
-#define DMA_EEI_EEI8_SHIFT 8
-#define DMA_EEI_EEI8_WIDTH 1
-#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
-#define DMA_EEI_EEI9_MASK 0x200u
-#define DMA_EEI_EEI9_SHIFT 9
-#define DMA_EEI_EEI9_WIDTH 1
-#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
-#define DMA_EEI_EEI10_MASK 0x400u
-#define DMA_EEI_EEI10_SHIFT 10
-#define DMA_EEI_EEI10_WIDTH 1
-#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
-#define DMA_EEI_EEI11_MASK 0x800u
-#define DMA_EEI_EEI11_SHIFT 11
-#define DMA_EEI_EEI11_WIDTH 1
-#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
-#define DMA_EEI_EEI12_MASK 0x1000u
-#define DMA_EEI_EEI12_SHIFT 12
-#define DMA_EEI_EEI12_WIDTH 1
-#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
-#define DMA_EEI_EEI13_MASK 0x2000u
-#define DMA_EEI_EEI13_SHIFT 13
-#define DMA_EEI_EEI13_WIDTH 1
-#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
-#define DMA_EEI_EEI14_MASK 0x4000u
-#define DMA_EEI_EEI14_SHIFT 14
-#define DMA_EEI_EEI14_WIDTH 1
-#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
-#define DMA_EEI_EEI15_MASK 0x8000u
-#define DMA_EEI_EEI15_SHIFT 15
-#define DMA_EEI_EEI15_WIDTH 1
-#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK 0xFu
-#define DMA_CEEI_CEEI_SHIFT 0
-#define DMA_CEEI_CEEI_WIDTH 4
-#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK 0x40u
-#define DMA_CEEI_CAEE_SHIFT 6
-#define DMA_CEEI_CAEE_WIDTH 1
-#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
-#define DMA_CEEI_NOP_MASK 0x80u
-#define DMA_CEEI_NOP_SHIFT 7
-#define DMA_CEEI_NOP_WIDTH 1
-#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK 0xFu
-#define DMA_SEEI_SEEI_SHIFT 0
-#define DMA_SEEI_SEEI_WIDTH 4
-#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK 0x40u
-#define DMA_SEEI_SAEE_SHIFT 6
-#define DMA_SEEI_SAEE_WIDTH 1
-#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
-#define DMA_SEEI_NOP_MASK 0x80u
-#define DMA_SEEI_NOP_SHIFT 7
-#define DMA_SEEI_NOP_WIDTH 1
-#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK 0xFu
-#define DMA_CERQ_CERQ_SHIFT 0
-#define DMA_CERQ_CERQ_WIDTH 4
-#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK 0x40u
-#define DMA_CERQ_CAER_SHIFT 6
-#define DMA_CERQ_CAER_WIDTH 1
-#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
-#define DMA_CERQ_NOP_MASK 0x80u
-#define DMA_CERQ_NOP_SHIFT 7
-#define DMA_CERQ_NOP_WIDTH 1
-#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK 0xFu
-#define DMA_SERQ_SERQ_SHIFT 0
-#define DMA_SERQ_SERQ_WIDTH 4
-#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK 0x40u
-#define DMA_SERQ_SAER_SHIFT 6
-#define DMA_SERQ_SAER_WIDTH 1
-#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
-#define DMA_SERQ_NOP_MASK 0x80u
-#define DMA_SERQ_NOP_SHIFT 7
-#define DMA_SERQ_NOP_WIDTH 1
-#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK 0xFu
-#define DMA_CDNE_CDNE_SHIFT 0
-#define DMA_CDNE_CDNE_WIDTH 4
-#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK 0x40u
-#define DMA_CDNE_CADN_SHIFT 6
-#define DMA_CDNE_CADN_WIDTH 1
-#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
-#define DMA_CDNE_NOP_MASK 0x80u
-#define DMA_CDNE_NOP_SHIFT 7
-#define DMA_CDNE_NOP_WIDTH 1
-#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK 0xFu
-#define DMA_SSRT_SSRT_SHIFT 0
-#define DMA_SSRT_SSRT_WIDTH 4
-#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK 0x40u
-#define DMA_SSRT_SAST_SHIFT 6
-#define DMA_SSRT_SAST_WIDTH 1
-#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
-#define DMA_SSRT_NOP_MASK 0x80u
-#define DMA_SSRT_NOP_SHIFT 7
-#define DMA_SSRT_NOP_WIDTH 1
-#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK 0xFu
-#define DMA_CERR_CERR_SHIFT 0
-#define DMA_CERR_CERR_WIDTH 4
-#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK 0x40u
-#define DMA_CERR_CAEI_SHIFT 6
-#define DMA_CERR_CAEI_WIDTH 1
-#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
-#define DMA_CERR_NOP_MASK 0x80u
-#define DMA_CERR_NOP_SHIFT 7
-#define DMA_CERR_NOP_WIDTH 1
-#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK 0xFu
-#define DMA_CINT_CINT_SHIFT 0
-#define DMA_CINT_CINT_WIDTH 4
-#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK 0x40u
-#define DMA_CINT_CAIR_SHIFT 6
-#define DMA_CINT_CAIR_WIDTH 1
-#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
-#define DMA_CINT_NOP_MASK 0x80u
-#define DMA_CINT_NOP_SHIFT 7
-#define DMA_CINT_NOP_WIDTH 1
-#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK 0x1u
-#define DMA_INT_INT0_SHIFT 0
-#define DMA_INT_INT0_WIDTH 1
-#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
-#define DMA_INT_INT1_MASK 0x2u
-#define DMA_INT_INT1_SHIFT 1
-#define DMA_INT_INT1_WIDTH 1
-#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
-#define DMA_INT_INT2_MASK 0x4u
-#define DMA_INT_INT2_SHIFT 2
-#define DMA_INT_INT2_WIDTH 1
-#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
-#define DMA_INT_INT3_MASK 0x8u
-#define DMA_INT_INT3_SHIFT 3
-#define DMA_INT_INT3_WIDTH 1
-#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
-#define DMA_INT_INT4_MASK 0x10u
-#define DMA_INT_INT4_SHIFT 4
-#define DMA_INT_INT4_WIDTH 1
-#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
-#define DMA_INT_INT5_MASK 0x20u
-#define DMA_INT_INT5_SHIFT 5
-#define DMA_INT_INT5_WIDTH 1
-#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
-#define DMA_INT_INT6_MASK 0x40u
-#define DMA_INT_INT6_SHIFT 6
-#define DMA_INT_INT6_WIDTH 1
-#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
-#define DMA_INT_INT7_MASK 0x80u
-#define DMA_INT_INT7_SHIFT 7
-#define DMA_INT_INT7_WIDTH 1
-#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
-#define DMA_INT_INT8_MASK 0x100u
-#define DMA_INT_INT8_SHIFT 8
-#define DMA_INT_INT8_WIDTH 1
-#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
-#define DMA_INT_INT9_MASK 0x200u
-#define DMA_INT_INT9_SHIFT 9
-#define DMA_INT_INT9_WIDTH 1
-#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
-#define DMA_INT_INT10_MASK 0x400u
-#define DMA_INT_INT10_SHIFT 10
-#define DMA_INT_INT10_WIDTH 1
-#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
-#define DMA_INT_INT11_MASK 0x800u
-#define DMA_INT_INT11_SHIFT 11
-#define DMA_INT_INT11_WIDTH 1
-#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
-#define DMA_INT_INT12_MASK 0x1000u
-#define DMA_INT_INT12_SHIFT 12
-#define DMA_INT_INT12_WIDTH 1
-#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
-#define DMA_INT_INT13_MASK 0x2000u
-#define DMA_INT_INT13_SHIFT 13
-#define DMA_INT_INT13_WIDTH 1
-#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
-#define DMA_INT_INT14_MASK 0x4000u
-#define DMA_INT_INT14_SHIFT 14
-#define DMA_INT_INT14_WIDTH 1
-#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
-#define DMA_INT_INT15_MASK 0x8000u
-#define DMA_INT_INT15_SHIFT 15
-#define DMA_INT_INT15_WIDTH 1
-#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK 0x1u
-#define DMA_ERR_ERR0_SHIFT 0
-#define DMA_ERR_ERR0_WIDTH 1
-#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
-#define DMA_ERR_ERR1_MASK 0x2u
-#define DMA_ERR_ERR1_SHIFT 1
-#define DMA_ERR_ERR1_WIDTH 1
-#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
-#define DMA_ERR_ERR2_MASK 0x4u
-#define DMA_ERR_ERR2_SHIFT 2
-#define DMA_ERR_ERR2_WIDTH 1
-#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
-#define DMA_ERR_ERR3_MASK 0x8u
-#define DMA_ERR_ERR3_SHIFT 3
-#define DMA_ERR_ERR3_WIDTH 1
-#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
-#define DMA_ERR_ERR4_MASK 0x10u
-#define DMA_ERR_ERR4_SHIFT 4
-#define DMA_ERR_ERR4_WIDTH 1
-#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
-#define DMA_ERR_ERR5_MASK 0x20u
-#define DMA_ERR_ERR5_SHIFT 5
-#define DMA_ERR_ERR5_WIDTH 1
-#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
-#define DMA_ERR_ERR6_MASK 0x40u
-#define DMA_ERR_ERR6_SHIFT 6
-#define DMA_ERR_ERR6_WIDTH 1
-#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
-#define DMA_ERR_ERR7_MASK 0x80u
-#define DMA_ERR_ERR7_SHIFT 7
-#define DMA_ERR_ERR7_WIDTH 1
-#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
-#define DMA_ERR_ERR8_MASK 0x100u
-#define DMA_ERR_ERR8_SHIFT 8
-#define DMA_ERR_ERR8_WIDTH 1
-#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
-#define DMA_ERR_ERR9_MASK 0x200u
-#define DMA_ERR_ERR9_SHIFT 9
-#define DMA_ERR_ERR9_WIDTH 1
-#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
-#define DMA_ERR_ERR10_MASK 0x400u
-#define DMA_ERR_ERR10_SHIFT 10
-#define DMA_ERR_ERR10_WIDTH 1
-#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
-#define DMA_ERR_ERR11_MASK 0x800u
-#define DMA_ERR_ERR11_SHIFT 11
-#define DMA_ERR_ERR11_WIDTH 1
-#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
-#define DMA_ERR_ERR12_MASK 0x1000u
-#define DMA_ERR_ERR12_SHIFT 12
-#define DMA_ERR_ERR12_WIDTH 1
-#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
-#define DMA_ERR_ERR13_MASK 0x2000u
-#define DMA_ERR_ERR13_SHIFT 13
-#define DMA_ERR_ERR13_WIDTH 1
-#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
-#define DMA_ERR_ERR14_MASK 0x4000u
-#define DMA_ERR_ERR14_SHIFT 14
-#define DMA_ERR_ERR14_WIDTH 1
-#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
-#define DMA_ERR_ERR15_MASK 0x8000u
-#define DMA_ERR_ERR15_SHIFT 15
-#define DMA_ERR_ERR15_WIDTH 1
-#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK 0x1u
-#define DMA_HRS_HRS0_SHIFT 0
-#define DMA_HRS_HRS0_WIDTH 1
-#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
-#define DMA_HRS_HRS1_MASK 0x2u
-#define DMA_HRS_HRS1_SHIFT 1
-#define DMA_HRS_HRS1_WIDTH 1
-#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
-#define DMA_HRS_HRS2_MASK 0x4u
-#define DMA_HRS_HRS2_SHIFT 2
-#define DMA_HRS_HRS2_WIDTH 1
-#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
-#define DMA_HRS_HRS3_MASK 0x8u
-#define DMA_HRS_HRS3_SHIFT 3
-#define DMA_HRS_HRS3_WIDTH 1
-#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
-#define DMA_HRS_HRS4_MASK 0x10u
-#define DMA_HRS_HRS4_SHIFT 4
-#define DMA_HRS_HRS4_WIDTH 1
-#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
-#define DMA_HRS_HRS5_MASK 0x20u
-#define DMA_HRS_HRS5_SHIFT 5
-#define DMA_HRS_HRS5_WIDTH 1
-#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
-#define DMA_HRS_HRS6_MASK 0x40u
-#define DMA_HRS_HRS6_SHIFT 6
-#define DMA_HRS_HRS6_WIDTH 1
-#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
-#define DMA_HRS_HRS7_MASK 0x80u
-#define DMA_HRS_HRS7_SHIFT 7
-#define DMA_HRS_HRS7_WIDTH 1
-#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
-#define DMA_HRS_HRS8_MASK 0x100u
-#define DMA_HRS_HRS8_SHIFT 8
-#define DMA_HRS_HRS8_WIDTH 1
-#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
-#define DMA_HRS_HRS9_MASK 0x200u
-#define DMA_HRS_HRS9_SHIFT 9
-#define DMA_HRS_HRS9_WIDTH 1
-#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
-#define DMA_HRS_HRS10_MASK 0x400u
-#define DMA_HRS_HRS10_SHIFT 10
-#define DMA_HRS_HRS10_WIDTH 1
-#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
-#define DMA_HRS_HRS11_MASK 0x800u
-#define DMA_HRS_HRS11_SHIFT 11
-#define DMA_HRS_HRS11_WIDTH 1
-#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
-#define DMA_HRS_HRS12_MASK 0x1000u
-#define DMA_HRS_HRS12_SHIFT 12
-#define DMA_HRS_HRS12_WIDTH 1
-#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
-#define DMA_HRS_HRS13_MASK 0x2000u
-#define DMA_HRS_HRS13_SHIFT 13
-#define DMA_HRS_HRS13_WIDTH 1
-#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
-#define DMA_HRS_HRS14_MASK 0x4000u
-#define DMA_HRS_HRS14_SHIFT 14
-#define DMA_HRS_HRS14_WIDTH 1
-#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
-#define DMA_HRS_HRS15_MASK 0x8000u
-#define DMA_HRS_HRS15_SHIFT 15
-#define DMA_HRS_HRS15_WIDTH 1
-#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
-/* EARS Bit Fields */
-#define DMA_EARS_EDREQ_0_MASK 0x1u
-#define DMA_EARS_EDREQ_0_SHIFT 0
-#define DMA_EARS_EDREQ_0_WIDTH 1
-#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
-#define DMA_EARS_EDREQ_1_MASK 0x2u
-#define DMA_EARS_EDREQ_1_SHIFT 1
-#define DMA_EARS_EDREQ_1_WIDTH 1
-#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
-#define DMA_EARS_EDREQ_2_MASK 0x4u
-#define DMA_EARS_EDREQ_2_SHIFT 2
-#define DMA_EARS_EDREQ_2_WIDTH 1
-#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
-#define DMA_EARS_EDREQ_3_MASK 0x8u
-#define DMA_EARS_EDREQ_3_SHIFT 3
-#define DMA_EARS_EDREQ_3_WIDTH 1
-#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
-#define DMA_EARS_EDREQ_4_MASK 0x10u
-#define DMA_EARS_EDREQ_4_SHIFT 4
-#define DMA_EARS_EDREQ_4_WIDTH 1
-#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
-#define DMA_EARS_EDREQ_5_MASK 0x20u
-#define DMA_EARS_EDREQ_5_SHIFT 5
-#define DMA_EARS_EDREQ_5_WIDTH 1
-#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
-#define DMA_EARS_EDREQ_6_MASK 0x40u
-#define DMA_EARS_EDREQ_6_SHIFT 6
-#define DMA_EARS_EDREQ_6_WIDTH 1
-#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
-#define DMA_EARS_EDREQ_7_MASK 0x80u
-#define DMA_EARS_EDREQ_7_SHIFT 7
-#define DMA_EARS_EDREQ_7_WIDTH 1
-#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
-#define DMA_EARS_EDREQ_8_MASK 0x100u
-#define DMA_EARS_EDREQ_8_SHIFT 8
-#define DMA_EARS_EDREQ_8_WIDTH 1
-#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
-#define DMA_EARS_EDREQ_9_MASK 0x200u
-#define DMA_EARS_EDREQ_9_SHIFT 9
-#define DMA_EARS_EDREQ_9_WIDTH 1
-#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
-#define DMA_EARS_EDREQ_10_MASK 0x400u
-#define DMA_EARS_EDREQ_10_SHIFT 10
-#define DMA_EARS_EDREQ_10_WIDTH 1
-#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
-#define DMA_EARS_EDREQ_11_MASK 0x800u
-#define DMA_EARS_EDREQ_11_SHIFT 11
-#define DMA_EARS_EDREQ_11_WIDTH 1
-#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
-#define DMA_EARS_EDREQ_12_MASK 0x1000u
-#define DMA_EARS_EDREQ_12_SHIFT 12
-#define DMA_EARS_EDREQ_12_WIDTH 1
-#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
-#define DMA_EARS_EDREQ_13_MASK 0x2000u
-#define DMA_EARS_EDREQ_13_SHIFT 13
-#define DMA_EARS_EDREQ_13_WIDTH 1
-#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
-#define DMA_EARS_EDREQ_14_MASK 0x4000u
-#define DMA_EARS_EDREQ_14_SHIFT 14
-#define DMA_EARS_EDREQ_14_WIDTH 1
-#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
-#define DMA_EARS_EDREQ_15_MASK 0x8000u
-#define DMA_EARS_EDREQ_15_SHIFT 15
-#define DMA_EARS_EDREQ_15_WIDTH 1
-#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK 0xFu
-#define DMA_DCHPRI3_CHPRI_SHIFT 0
-#define DMA_DCHPRI3_CHPRI_WIDTH 4
-#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK 0x40u
-#define DMA_DCHPRI3_DPA_SHIFT 6
-#define DMA_DCHPRI3_DPA_WIDTH 1
-#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
-#define DMA_DCHPRI3_ECP_MASK 0x80u
-#define DMA_DCHPRI3_ECP_SHIFT 7
-#define DMA_DCHPRI3_ECP_WIDTH 1
-#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK 0xFu
-#define DMA_DCHPRI2_CHPRI_SHIFT 0
-#define DMA_DCHPRI2_CHPRI_WIDTH 4
-#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK 0x40u
-#define DMA_DCHPRI2_DPA_SHIFT 6
-#define DMA_DCHPRI2_DPA_WIDTH 1
-#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
-#define DMA_DCHPRI2_ECP_MASK 0x80u
-#define DMA_DCHPRI2_ECP_SHIFT 7
-#define DMA_DCHPRI2_ECP_WIDTH 1
-#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK 0xFu
-#define DMA_DCHPRI1_CHPRI_SHIFT 0
-#define DMA_DCHPRI1_CHPRI_WIDTH 4
-#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK 0x40u
-#define DMA_DCHPRI1_DPA_SHIFT 6
-#define DMA_DCHPRI1_DPA_WIDTH 1
-#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
-#define DMA_DCHPRI1_ECP_MASK 0x80u
-#define DMA_DCHPRI1_ECP_SHIFT 7
-#define DMA_DCHPRI1_ECP_WIDTH 1
-#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK 0xFu
-#define DMA_DCHPRI0_CHPRI_SHIFT 0
-#define DMA_DCHPRI0_CHPRI_WIDTH 4
-#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK 0x40u
-#define DMA_DCHPRI0_DPA_SHIFT 6
-#define DMA_DCHPRI0_DPA_WIDTH 1
-#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
-#define DMA_DCHPRI0_ECP_MASK 0x80u
-#define DMA_DCHPRI0_ECP_SHIFT 7
-#define DMA_DCHPRI0_ECP_WIDTH 1
-#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
-/* DCHPRI7 Bit Fields */
-#define DMA_DCHPRI7_CHPRI_MASK 0xFu
-#define DMA_DCHPRI7_CHPRI_SHIFT 0
-#define DMA_DCHPRI7_CHPRI_WIDTH 4
-#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
-#define DMA_DCHPRI7_DPA_MASK 0x40u
-#define DMA_DCHPRI7_DPA_SHIFT 6
-#define DMA_DCHPRI7_DPA_WIDTH 1
-#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
-#define DMA_DCHPRI7_ECP_MASK 0x80u
-#define DMA_DCHPRI7_ECP_SHIFT 7
-#define DMA_DCHPRI7_ECP_WIDTH 1
-#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
-/* DCHPRI6 Bit Fields */
-#define DMA_DCHPRI6_CHPRI_MASK 0xFu
-#define DMA_DCHPRI6_CHPRI_SHIFT 0
-#define DMA_DCHPRI6_CHPRI_WIDTH 4
-#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
-#define DMA_DCHPRI6_DPA_MASK 0x40u
-#define DMA_DCHPRI6_DPA_SHIFT 6
-#define DMA_DCHPRI6_DPA_WIDTH 1
-#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
-#define DMA_DCHPRI6_ECP_MASK 0x80u
-#define DMA_DCHPRI6_ECP_SHIFT 7
-#define DMA_DCHPRI6_ECP_WIDTH 1
-#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
-/* DCHPRI5 Bit Fields */
-#define DMA_DCHPRI5_CHPRI_MASK 0xFu
-#define DMA_DCHPRI5_CHPRI_SHIFT 0
-#define DMA_DCHPRI5_CHPRI_WIDTH 4
-#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
-#define DMA_DCHPRI5_DPA_MASK 0x40u
-#define DMA_DCHPRI5_DPA_SHIFT 6
-#define DMA_DCHPRI5_DPA_WIDTH 1
-#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
-#define DMA_DCHPRI5_ECP_MASK 0x80u
-#define DMA_DCHPRI5_ECP_SHIFT 7
-#define DMA_DCHPRI5_ECP_WIDTH 1
-#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
-/* DCHPRI4 Bit Fields */
-#define DMA_DCHPRI4_CHPRI_MASK 0xFu
-#define DMA_DCHPRI4_CHPRI_SHIFT 0
-#define DMA_DCHPRI4_CHPRI_WIDTH 4
-#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
-#define DMA_DCHPRI4_DPA_MASK 0x40u
-#define DMA_DCHPRI4_DPA_SHIFT 6
-#define DMA_DCHPRI4_DPA_WIDTH 1
-#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
-#define DMA_DCHPRI4_ECP_MASK 0x80u
-#define DMA_DCHPRI4_ECP_SHIFT 7
-#define DMA_DCHPRI4_ECP_WIDTH 1
-#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
-/* DCHPRI11 Bit Fields */
-#define DMA_DCHPRI11_CHPRI_MASK 0xFu
-#define DMA_DCHPRI11_CHPRI_SHIFT 0
-#define DMA_DCHPRI11_CHPRI_WIDTH 4
-#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
-#define DMA_DCHPRI11_DPA_MASK 0x40u
-#define DMA_DCHPRI11_DPA_SHIFT 6
-#define DMA_DCHPRI11_DPA_WIDTH 1
-#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
-#define DMA_DCHPRI11_ECP_MASK 0x80u
-#define DMA_DCHPRI11_ECP_SHIFT 7
-#define DMA_DCHPRI11_ECP_WIDTH 1
-#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
-/* DCHPRI10 Bit Fields */
-#define DMA_DCHPRI10_CHPRI_MASK 0xFu
-#define DMA_DCHPRI10_CHPRI_SHIFT 0
-#define DMA_DCHPRI10_CHPRI_WIDTH 4
-#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
-#define DMA_DCHPRI10_DPA_MASK 0x40u
-#define DMA_DCHPRI10_DPA_SHIFT 6
-#define DMA_DCHPRI10_DPA_WIDTH 1
-#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
-#define DMA_DCHPRI10_ECP_MASK 0x80u
-#define DMA_DCHPRI10_ECP_SHIFT 7
-#define DMA_DCHPRI10_ECP_WIDTH 1
-#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
-/* DCHPRI9 Bit Fields */
-#define DMA_DCHPRI9_CHPRI_MASK 0xFu
-#define DMA_DCHPRI9_CHPRI_SHIFT 0
-#define DMA_DCHPRI9_CHPRI_WIDTH 4
-#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
-#define DMA_DCHPRI9_DPA_MASK 0x40u
-#define DMA_DCHPRI9_DPA_SHIFT 6
-#define DMA_DCHPRI9_DPA_WIDTH 1
-#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
-#define DMA_DCHPRI9_ECP_MASK 0x80u
-#define DMA_DCHPRI9_ECP_SHIFT 7
-#define DMA_DCHPRI9_ECP_WIDTH 1
-#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
-/* DCHPRI8 Bit Fields */
-#define DMA_DCHPRI8_CHPRI_MASK 0xFu
-#define DMA_DCHPRI8_CHPRI_SHIFT 0
-#define DMA_DCHPRI8_CHPRI_WIDTH 4
-#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
-#define DMA_DCHPRI8_DPA_MASK 0x40u
-#define DMA_DCHPRI8_DPA_SHIFT 6
-#define DMA_DCHPRI8_DPA_WIDTH 1
-#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
-#define DMA_DCHPRI8_ECP_MASK 0x80u
-#define DMA_DCHPRI8_ECP_SHIFT 7
-#define DMA_DCHPRI8_ECP_WIDTH 1
-#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
-/* DCHPRI15 Bit Fields */
-#define DMA_DCHPRI15_CHPRI_MASK 0xFu
-#define DMA_DCHPRI15_CHPRI_SHIFT 0
-#define DMA_DCHPRI15_CHPRI_WIDTH 4
-#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
-#define DMA_DCHPRI15_DPA_MASK 0x40u
-#define DMA_DCHPRI15_DPA_SHIFT 6
-#define DMA_DCHPRI15_DPA_WIDTH 1
-#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
-#define DMA_DCHPRI15_ECP_MASK 0x80u
-#define DMA_DCHPRI15_ECP_SHIFT 7
-#define DMA_DCHPRI15_ECP_WIDTH 1
-#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
-/* DCHPRI14 Bit Fields */
-#define DMA_DCHPRI14_CHPRI_MASK 0xFu
-#define DMA_DCHPRI14_CHPRI_SHIFT 0
-#define DMA_DCHPRI14_CHPRI_WIDTH 4
-#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
-#define DMA_DCHPRI14_DPA_MASK 0x40u
-#define DMA_DCHPRI14_DPA_SHIFT 6
-#define DMA_DCHPRI14_DPA_WIDTH 1
-#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
-#define DMA_DCHPRI14_ECP_MASK 0x80u
-#define DMA_DCHPRI14_ECP_SHIFT 7
-#define DMA_DCHPRI14_ECP_WIDTH 1
-#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
-/* DCHPRI13 Bit Fields */
-#define DMA_DCHPRI13_CHPRI_MASK 0xFu
-#define DMA_DCHPRI13_CHPRI_SHIFT 0
-#define DMA_DCHPRI13_CHPRI_WIDTH 4
-#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
-#define DMA_DCHPRI13_DPA_MASK 0x40u
-#define DMA_DCHPRI13_DPA_SHIFT 6
-#define DMA_DCHPRI13_DPA_WIDTH 1
-#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
-#define DMA_DCHPRI13_ECP_MASK 0x80u
-#define DMA_DCHPRI13_ECP_SHIFT 7
-#define DMA_DCHPRI13_ECP_WIDTH 1
-#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
-/* DCHPRI12 Bit Fields */
-#define DMA_DCHPRI12_CHPRI_MASK 0xFu
-#define DMA_DCHPRI12_CHPRI_SHIFT 0
-#define DMA_DCHPRI12_CHPRI_WIDTH 4
-#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
-#define DMA_DCHPRI12_DPA_MASK 0x40u
-#define DMA_DCHPRI12_DPA_SHIFT 6
-#define DMA_DCHPRI12_DPA_WIDTH 1
-#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
-#define DMA_DCHPRI12_ECP_MASK 0x80u
-#define DMA_DCHPRI12_ECP_SHIFT 7
-#define DMA_DCHPRI12_ECP_WIDTH 1
-#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT 0
-#define DMA_SADDR_SADDR_WIDTH 32
-#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK 0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT 0
-#define DMA_SOFF_SOFF_WIDTH 16
-#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK 0x7u
-#define DMA_ATTR_DSIZE_SHIFT 0
-#define DMA_ATTR_DSIZE_WIDTH 3
-#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK 0xF8u
-#define DMA_ATTR_DMOD_SHIFT 3
-#define DMA_ATTR_DMOD_WIDTH 5
-#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK 0x700u
-#define DMA_ATTR_SSIZE_SHIFT 8
-#define DMA_ATTR_SSIZE_WIDTH 3
-#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK 0xF800u
-#define DMA_ATTR_SMOD_SHIFT 11
-#define DMA_ATTR_SMOD_WIDTH 5
-#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLNO_NBYTES_WIDTH 32
-#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH 30
-#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
-#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH 10
-#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
-#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH 20
-#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
-#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT 0
-#define DMA_SLAST_SLAST_WIDTH 32
-#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT 0
-#define DMA_DADDR_DADDR_WIDTH 32
-#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK 0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT 0
-#define DMA_DOFF_DOFF_WIDTH 16
-#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT 0
-#define DMA_CITER_ELINKNO_CITER_WIDTH 15
-#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
-#define DMA_CITER_ELINKNO_ELINK_WIDTH 1
-#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT 0
-#define DMA_CITER_ELINKYES_CITER_WIDTH 9
-#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_CITER_ELINKYES_LINKCH_WIDTH 4
-#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
-#define DMA_CITER_ELINKYES_ELINK_WIDTH 1
-#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
-#define DMA_DLAST_SGA_DLASTSGA_WIDTH 32
-#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK 0x1u
-#define DMA_CSR_START_SHIFT 0
-#define DMA_CSR_START_WIDTH 1
-#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
-#define DMA_CSR_INTMAJOR_MASK 0x2u
-#define DMA_CSR_INTMAJOR_SHIFT 1
-#define DMA_CSR_INTMAJOR_WIDTH 1
-#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
-#define DMA_CSR_INTHALF_MASK 0x4u
-#define DMA_CSR_INTHALF_SHIFT 2
-#define DMA_CSR_INTHALF_WIDTH 1
-#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
-#define DMA_CSR_DREQ_MASK 0x8u
-#define DMA_CSR_DREQ_SHIFT 3
-#define DMA_CSR_DREQ_WIDTH 1
-#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
-#define DMA_CSR_ESG_MASK 0x10u
-#define DMA_CSR_ESG_SHIFT 4
-#define DMA_CSR_ESG_WIDTH 1
-#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
-#define DMA_CSR_MAJORELINK_MASK 0x20u
-#define DMA_CSR_MAJORELINK_SHIFT 5
-#define DMA_CSR_MAJORELINK_WIDTH 1
-#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
-#define DMA_CSR_ACTIVE_MASK 0x40u
-#define DMA_CSR_ACTIVE_SHIFT 6
-#define DMA_CSR_ACTIVE_WIDTH 1
-#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
-#define DMA_CSR_DONE_MASK 0x80u
-#define DMA_CSR_DONE_SHIFT 7
-#define DMA_CSR_DONE_WIDTH 1
-#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
-#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
-#define DMA_CSR_MAJORLINKCH_SHIFT 8
-#define DMA_CSR_MAJORLINKCH_WIDTH 4
-#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK 0xC000u
-#define DMA_CSR_BWC_SHIFT 14
-#define DMA_CSR_BWC_WIDTH 2
-#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT 0
-#define DMA_BITER_ELINKNO_BITER_WIDTH 15
-#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
-#define DMA_BITER_ELINKNO_ELINK_WIDTH 1
-#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT 0
-#define DMA_BITER_ELINKYES_BITER_WIDTH 9
-#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_BITER_ELINKYES_LINKCH_WIDTH 4
-#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
-#define DMA_BITER_ELINKYES_ELINK_WIDTH 1
-#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG_MASK (0x2U)
+#define DMA_CR_EDBG_SHIFT (1U)
+#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK (0x4U)
+#define DMA_CR_ERCA_SHIFT (2U)
+#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK (0x10U)
+#define DMA_CR_HOE_SHIFT (4U)
+#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK (0x20U)
+#define DMA_CR_HALT_SHIFT (5U)
+#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK (0x40U)
+#define DMA_CR_CLM_SHIFT (6U)
+#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK (0x80U)
+#define DMA_CR_EMLM_SHIFT (7U)
+#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK (0x10000U)
+#define DMA_CR_ECX_SHIFT (16U)
+#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK (0x20000U)
+#define DMA_CR_CX_SHIFT (17U)
+#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE_MASK (0x1U)
+#define DMA_ES_DBE_SHIFT (0U)
+#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK (0x2U)
+#define DMA_ES_SBE_SHIFT (1U)
+#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK (0x4U)
+#define DMA_ES_SGE_SHIFT (2U)
+#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK (0x8U)
+#define DMA_ES_NCE_SHIFT (3U)
+#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK (0x10U)
+#define DMA_ES_DOE_SHIFT (4U)
+#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK (0x20U)
+#define DMA_ES_DAE_SHIFT (5U)
+#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK (0x40U)
+#define DMA_ES_SOE_SHIFT (6U)
+#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK (0x80U)
+#define DMA_ES_SAE_SHIFT (7U)
+#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK (0xF00U)
+#define DMA_ES_ERRCHN_SHIFT (8U)
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK (0x4000U)
+#define DMA_ES_CPE_SHIFT (14U)
+#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK (0x10000U)
+#define DMA_ES_ECX_SHIFT (16U)
+#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK (0x80000000U)
+#define DMA_ES_VLD_SHIFT (31U)
+#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+
+/*! @name ERQ - Enable Request Register */
+#define DMA_ERQ_ERQ0_MASK (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT (0U)
+#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT (1U)
+#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT (2U)
+#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT (3U)
+#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT (4U)
+#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT (5U)
+#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT (6U)
+#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT (7U)
+#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK (0x100U)
+#define DMA_ERQ_ERQ8_SHIFT (8U)
+#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK (0x200U)
+#define DMA_ERQ_ERQ9_SHIFT (9U)
+#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK (0x400U)
+#define DMA_ERQ_ERQ10_SHIFT (10U)
+#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK (0x800U)
+#define DMA_ERQ_ERQ11_SHIFT (11U)
+#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK (0x1000U)
+#define DMA_ERQ_ERQ12_SHIFT (12U)
+#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK (0x2000U)
+#define DMA_ERQ_ERQ13_SHIFT (13U)
+#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK (0x4000U)
+#define DMA_ERQ_ERQ14_SHIFT (14U)
+#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK (0x8000U)
+#define DMA_ERQ_ERQ15_SHIFT (15U)
+#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+
+/*! @name EEI - Enable Error Interrupt Register */
+#define DMA_EEI_EEI0_MASK (0x1U)
+#define DMA_EEI_EEI0_SHIFT (0U)
+#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK (0x2U)
+#define DMA_EEI_EEI1_SHIFT (1U)
+#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK (0x4U)
+#define DMA_EEI_EEI2_SHIFT (2U)
+#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK (0x8U)
+#define DMA_EEI_EEI3_SHIFT (3U)
+#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK (0x10U)
+#define DMA_EEI_EEI4_SHIFT (4U)
+#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK (0x20U)
+#define DMA_EEI_EEI5_SHIFT (5U)
+#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK (0x40U)
+#define DMA_EEI_EEI6_SHIFT (6U)
+#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK (0x80U)
+#define DMA_EEI_EEI7_SHIFT (7U)
+#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK (0x100U)
+#define DMA_EEI_EEI8_SHIFT (8U)
+#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK (0x200U)
+#define DMA_EEI_EEI9_SHIFT (9U)
+#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK (0x400U)
+#define DMA_EEI_EEI10_SHIFT (10U)
+#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK (0x800U)
+#define DMA_EEI_EEI11_SHIFT (11U)
+#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK (0x1000U)
+#define DMA_EEI_EEI12_SHIFT (12U)
+#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK (0x2000U)
+#define DMA_EEI_EEI13_SHIFT (13U)
+#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK (0x4000U)
+#define DMA_EEI_EEI14_SHIFT (14U)
+#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK (0x8000U)
+#define DMA_EEI_EEI15_SHIFT (15U)
+#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK (0xFU)
+#define DMA_CEEI_CEEI_SHIFT (0U)
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK (0x40U)
+#define DMA_CEEI_CAEE_SHIFT (6U)
+#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK (0x80U)
+#define DMA_CEEI_NOP_SHIFT (7U)
+#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK (0xFU)
+#define DMA_SEEI_SEEI_SHIFT (0U)
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK (0x40U)
+#define DMA_SEEI_SAEE_SHIFT (6U)
+#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK (0x80U)
+#define DMA_SEEI_NOP_SHIFT (7U)
+#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK (0xFU)
+#define DMA_CERQ_CERQ_SHIFT (0U)
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK (0x40U)
+#define DMA_CERQ_CAER_SHIFT (6U)
+#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK (0x80U)
+#define DMA_CERQ_NOP_SHIFT (7U)
+#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK (0xFU)
+#define DMA_SERQ_SERQ_SHIFT (0U)
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK (0x40U)
+#define DMA_SERQ_SAER_SHIFT (6U)
+#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK (0x80U)
+#define DMA_SERQ_NOP_SHIFT (7U)
+#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK (0xFU)
+#define DMA_CDNE_CDNE_SHIFT (0U)
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK (0x40U)
+#define DMA_CDNE_CADN_SHIFT (6U)
+#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK (0x80U)
+#define DMA_CDNE_NOP_SHIFT (7U)
+#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK (0xFU)
+#define DMA_SSRT_SSRT_SHIFT (0U)
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK (0x40U)
+#define DMA_SSRT_SAST_SHIFT (6U)
+#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK (0x80U)
+#define DMA_SSRT_NOP_SHIFT (7U)
+#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK (0xFU)
+#define DMA_CERR_CERR_SHIFT (0U)
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK (0x40U)
+#define DMA_CERR_CAEI_SHIFT (6U)
+#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK (0x80U)
+#define DMA_CERR_NOP_SHIFT (7U)
+#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK (0xFU)
+#define DMA_CINT_CINT_SHIFT (0U)
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK (0x40U)
+#define DMA_CINT_CAIR_SHIFT (6U)
+#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK (0x80U)
+#define DMA_CINT_NOP_SHIFT (7U)
+#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+
+/*! @name INT - Interrupt Request Register */
+#define DMA_INT_INT0_MASK (0x1U)
+#define DMA_INT_INT0_SHIFT (0U)
+#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK (0x2U)
+#define DMA_INT_INT1_SHIFT (1U)
+#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK (0x4U)
+#define DMA_INT_INT2_SHIFT (2U)
+#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK (0x8U)
+#define DMA_INT_INT3_SHIFT (3U)
+#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK (0x10U)
+#define DMA_INT_INT4_SHIFT (4U)
+#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK (0x20U)
+#define DMA_INT_INT5_SHIFT (5U)
+#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK (0x40U)
+#define DMA_INT_INT6_SHIFT (6U)
+#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK (0x80U)
+#define DMA_INT_INT7_SHIFT (7U)
+#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK (0x100U)
+#define DMA_INT_INT8_SHIFT (8U)
+#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK (0x200U)
+#define DMA_INT_INT9_SHIFT (9U)
+#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK (0x400U)
+#define DMA_INT_INT10_SHIFT (10U)
+#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK (0x800U)
+#define DMA_INT_INT11_SHIFT (11U)
+#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK (0x1000U)
+#define DMA_INT_INT12_SHIFT (12U)
+#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK (0x2000U)
+#define DMA_INT_INT13_SHIFT (13U)
+#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK (0x4000U)
+#define DMA_INT_INT14_SHIFT (14U)
+#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK (0x8000U)
+#define DMA_INT_INT15_SHIFT (15U)
+#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+
+/*! @name ERR - Error Register */
+#define DMA_ERR_ERR0_MASK (0x1U)
+#define DMA_ERR_ERR0_SHIFT (0U)
+#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK (0x2U)
+#define DMA_ERR_ERR1_SHIFT (1U)
+#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK (0x4U)
+#define DMA_ERR_ERR2_SHIFT (2U)
+#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK (0x8U)
+#define DMA_ERR_ERR3_SHIFT (3U)
+#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK (0x10U)
+#define DMA_ERR_ERR4_SHIFT (4U)
+#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK (0x20U)
+#define DMA_ERR_ERR5_SHIFT (5U)
+#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK (0x40U)
+#define DMA_ERR_ERR6_SHIFT (6U)
+#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK (0x80U)
+#define DMA_ERR_ERR7_SHIFT (7U)
+#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK (0x100U)
+#define DMA_ERR_ERR8_SHIFT (8U)
+#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK (0x200U)
+#define DMA_ERR_ERR9_SHIFT (9U)
+#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK (0x400U)
+#define DMA_ERR_ERR10_SHIFT (10U)
+#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK (0x800U)
+#define DMA_ERR_ERR11_SHIFT (11U)
+#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK (0x1000U)
+#define DMA_ERR_ERR12_SHIFT (12U)
+#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK (0x2000U)
+#define DMA_ERR_ERR13_SHIFT (13U)
+#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK (0x4000U)
+#define DMA_ERR_ERR14_SHIFT (14U)
+#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK (0x8000U)
+#define DMA_ERR_ERR15_SHIFT (15U)
+#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+
+/*! @name HRS - Hardware Request Status Register */
+#define DMA_HRS_HRS0_MASK (0x1U)
+#define DMA_HRS_HRS0_SHIFT (0U)
+#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK (0x2U)
+#define DMA_HRS_HRS1_SHIFT (1U)
+#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK (0x4U)
+#define DMA_HRS_HRS2_SHIFT (2U)
+#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK (0x8U)
+#define DMA_HRS_HRS3_SHIFT (3U)
+#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK (0x10U)
+#define DMA_HRS_HRS4_SHIFT (4U)
+#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK (0x20U)
+#define DMA_HRS_HRS5_SHIFT (5U)
+#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK (0x40U)
+#define DMA_HRS_HRS6_SHIFT (6U)
+#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK (0x80U)
+#define DMA_HRS_HRS7_SHIFT (7U)
+#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK (0x100U)
+#define DMA_HRS_HRS8_SHIFT (8U)
+#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK (0x200U)
+#define DMA_HRS_HRS9_SHIFT (9U)
+#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK (0x400U)
+#define DMA_HRS_HRS10_SHIFT (10U)
+#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK (0x800U)
+#define DMA_HRS_HRS11_SHIFT (11U)
+#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK (0x1000U)
+#define DMA_HRS_HRS12_SHIFT (12U)
+#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK (0x2000U)
+#define DMA_HRS_HRS13_SHIFT (13U)
+#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK (0x4000U)
+#define DMA_HRS_HRS14_SHIFT (14U)
+#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK (0x8000U)
+#define DMA_HRS_HRS15_SHIFT (15U)
+#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+
+/*! @name EARS - Enable Asynchronous Request in Stop Register */
+#define DMA_EARS_EDREQ_0_MASK (0x1U)
+#define DMA_EARS_EDREQ_0_SHIFT (0U)
+#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK (0x2U)
+#define DMA_EARS_EDREQ_1_SHIFT (1U)
+#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK (0x4U)
+#define DMA_EARS_EDREQ_2_SHIFT (2U)
+#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK (0x8U)
+#define DMA_EARS_EDREQ_3_SHIFT (3U)
+#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_4_MASK (0x10U)
+#define DMA_EARS_EDREQ_4_SHIFT (4U)
+#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_5_MASK (0x20U)
+#define DMA_EARS_EDREQ_5_SHIFT (5U)
+#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_6_MASK (0x40U)
+#define DMA_EARS_EDREQ_6_SHIFT (6U)
+#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_7_MASK (0x80U)
+#define DMA_EARS_EDREQ_7_SHIFT (7U)
+#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+#define DMA_EARS_EDREQ_8_MASK (0x100U)
+#define DMA_EARS_EDREQ_8_SHIFT (8U)
+#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
+#define DMA_EARS_EDREQ_9_MASK (0x200U)
+#define DMA_EARS_EDREQ_9_SHIFT (9U)
+#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
+#define DMA_EARS_EDREQ_10_MASK (0x400U)
+#define DMA_EARS_EDREQ_10_SHIFT (10U)
+#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
+#define DMA_EARS_EDREQ_11_MASK (0x800U)
+#define DMA_EARS_EDREQ_11_SHIFT (11U)
+#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
+#define DMA_EARS_EDREQ_12_MASK (0x1000U)
+#define DMA_EARS_EDREQ_12_SHIFT (12U)
+#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
+#define DMA_EARS_EDREQ_13_MASK (0x2000U)
+#define DMA_EARS_EDREQ_13_SHIFT (13U)
+#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
+#define DMA_EARS_EDREQ_14_MASK (0x4000U)
+#define DMA_EARS_EDREQ_14_SHIFT (14U)
+#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
+#define DMA_EARS_EDREQ_15_MASK (0x8000U)
+#define DMA_EARS_EDREQ_15_SHIFT (15U)
+#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT (6U)
+#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT (7U)
+#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT (6U)
+#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT (7U)
+#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT (6U)
+#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT (7U)
+#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT (6U)
+#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT (7U)
+#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+
+/*! @name DCHPRI7 - Channel n Priority Register */
+#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT (6U)
+#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT (7U)
+#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+
+/*! @name DCHPRI6 - Channel n Priority Register */
+#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT (6U)
+#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT (7U)
+#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+
+/*! @name DCHPRI5 - Channel n Priority Register */
+#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT (6U)
+#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT (7U)
+#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+
+/*! @name DCHPRI4 - Channel n Priority Register */
+#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT (6U)
+#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT (7U)
+#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+
+/*! @name DCHPRI11 - Channel n Priority Register */
+#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK (0x40U)
+#define DMA_DCHPRI11_DPA_SHIFT (6U)
+#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK (0x80U)
+#define DMA_DCHPRI11_ECP_SHIFT (7U)
+#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+
+/*! @name DCHPRI10 - Channel n Priority Register */
+#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK (0x40U)
+#define DMA_DCHPRI10_DPA_SHIFT (6U)
+#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK (0x80U)
+#define DMA_DCHPRI10_ECP_SHIFT (7U)
+#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+
+/*! @name DCHPRI9 - Channel n Priority Register */
+#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK (0x40U)
+#define DMA_DCHPRI9_DPA_SHIFT (6U)
+#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK (0x80U)
+#define DMA_DCHPRI9_ECP_SHIFT (7U)
+#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+
+/*! @name DCHPRI8 - Channel n Priority Register */
+#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK (0x40U)
+#define DMA_DCHPRI8_DPA_SHIFT (6U)
+#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK (0x80U)
+#define DMA_DCHPRI8_ECP_SHIFT (7U)
+#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+
+/*! @name DCHPRI15 - Channel n Priority Register */
+#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK (0x40U)
+#define DMA_DCHPRI15_DPA_SHIFT (6U)
+#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK (0x80U)
+#define DMA_DCHPRI15_ECP_SHIFT (7U)
+#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+
+/*! @name DCHPRI14 - Channel n Priority Register */
+#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK (0x40U)
+#define DMA_DCHPRI14_DPA_SHIFT (6U)
+#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK (0x80U)
+#define DMA_DCHPRI14_ECP_SHIFT (7U)
+#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+
+/*! @name DCHPRI13 - Channel n Priority Register */
+#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK (0x40U)
+#define DMA_DCHPRI13_DPA_SHIFT (6U)
+#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK (0x80U)
+#define DMA_DCHPRI13_ECP_SHIFT (7U)
+#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+
+/*! @name DCHPRI12 - Channel n Priority Register */
+#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK (0x40U)
+#define DMA_DCHPRI12_DPA_SHIFT (6U)
+#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK (0x80U)
+#define DMA_DCHPRI12_ECP_SHIFT (7U)
+#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+
+/*! @name SADDR - TCD Source Address */
+#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT (0U)
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT (16U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT (0U)
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT (16U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT (0U)
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT (3U)
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT (8U)
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT (11U)
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT (16U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
+#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT (16U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT (16U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT (16U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT (0U)
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT (16U)
+
+/*! @name DADDR - TCD Destination Address */
+#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT (0U)
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT (16U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT (0U)
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT (16U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT (16U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT (16U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT (16U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START_MASK (0x1U)
+#define DMA_CSR_START_SHIFT (0U)
+#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT (1U)
+#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK (0x4U)
+#define DMA_CSR_INTHALF_SHIFT (2U)
+#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK (0x8U)
+#define DMA_CSR_DREQ_SHIFT (3U)
+#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK (0x10U)
+#define DMA_CSR_ESG_SHIFT (4U)
+#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT (5U)
+#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT (6U)
+#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK (0x80U)
+#define DMA_CSR_DONE_SHIFT (7U)
+#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK (0xC000U)
+#define DMA_CSR_BWC_SHIFT (14U)
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT (16U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT (16U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT (16U)
+
/*!
* @}
@@ -2538,322 +2036,14 @@ typedef struct {
#define DMA_BASE (0x40008000u)
/** Peripheral DMA base pointer */
#define DMA0 ((DMA_Type *)DMA_BASE)
-#define DMA_BASE_PTR (DMA0)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0 }
/** Interrupt vectors for the DMA peripheral type */
-#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
#define DMA_ERROR_IRQS { DMA_Error_IRQn }
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register instance definitions */
-/* DMA */
-#define DMA_CR DMA_CR_REG(DMA0)
-#define DMA_ES DMA_ES_REG(DMA0)
-#define DMA_ERQ DMA_ERQ_REG(DMA0)
-#define DMA_EEI DMA_EEI_REG(DMA0)
-#define DMA_CEEI DMA_CEEI_REG(DMA0)
-#define DMA_SEEI DMA_SEEI_REG(DMA0)
-#define DMA_CERQ DMA_CERQ_REG(DMA0)
-#define DMA_SERQ DMA_SERQ_REG(DMA0)
-#define DMA_CDNE DMA_CDNE_REG(DMA0)
-#define DMA_SSRT DMA_SSRT_REG(DMA0)
-#define DMA_CERR DMA_CERR_REG(DMA0)
-#define DMA_CINT DMA_CINT_REG(DMA0)
-#define DMA_INT DMA_INT_REG(DMA0)
-#define DMA_ERR DMA_ERR_REG(DMA0)
-#define DMA_HRS DMA_HRS_REG(DMA0)
-#define DMA_EARS DMA_EARS_REG(DMA0)
-#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
-#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
-#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
-#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
-#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
-#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
-#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
-#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
-#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
-#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
-#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
-#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
-#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
-#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
-#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
-#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
-#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
-#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
-#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
-#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
-#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
-#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
-#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
-#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
-#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
-#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
-#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
-#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
-#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
-#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
-#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
-#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
-#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
-#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
-#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
-#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
-#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
-#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
-#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
-#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
-#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
-#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
-#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
-#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
-#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
-#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
-#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
-#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
-#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
-#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
-#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
-#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
-#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
-#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
-#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
-#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
-#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
-#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
-#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
-#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
-#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
-#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
-#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
-#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
-#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
-#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
-#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
-#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
-#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
-#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
-#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
-#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
-#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
-#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
-#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
-#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
-#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
-#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
-#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
-#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
-#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
-#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
-#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
-#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
-#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
-#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
-#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
-#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
-#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
-#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
-#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
-#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
-#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
-#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
-#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
-#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
-#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
-#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
-#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
-#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
-#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
-#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
-#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
-#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
-#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
-#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
-#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
-#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
-#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
-#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
-#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
-#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
-#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
-#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
-
-/* DMA - Register array accessors */
-#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
-#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
-#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
-#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
-#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
-#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
-#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
-#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
-#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
-#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
-#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
-#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
-#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
@@ -2871,26 +2061,7 @@ typedef struct {
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type, *DMAMUX_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register accessors */
-#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
-#define DMAMUX_CHCFG_COUNT 16
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
+} DMAMUX_Type;
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
@@ -2901,19 +2072,20 @@ typedef struct {
* @{
*/
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE_WIDTH 6
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_TRIG_WIDTH 1
-#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-#define DMAMUX_CHCFG_ENBL_WIDTH 1
-#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT (16U)
+
/*!
* @}
@@ -2925,49 +2097,11 @@ typedef struct {
#define DMAMUX_BASE (0x40021000u)
/** Peripheral DMAMUX base pointer */
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
-#define DMAMUX_BASE_PTR (DMAMUX)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX }
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register instance definitions */
-/* DMAMUX */
-#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
-#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
-#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
-#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
-#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
-#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
-#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
-#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
-#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
-#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
-#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
-#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
-#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
-#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
-#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
-#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
-
-/* DMAMUX - Register array accessors */
-#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
@@ -2990,76 +2124,51 @@ typedef struct {
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
uint8_t RESERVED_0[1];
__IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
-} EWM_Type, *EWM_MemMapPtr;
+} EWM_Type;
/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
+ -- EWM Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN_MASK (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT (0U)
+#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT (1U)
+#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK (0x4U)
+#define EWM_CTRL_INEN_SHIFT (2U)
+#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK (0x8U)
+#define EWM_CTRL_INTEN_SHIFT (3U)
+#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
-/* EWM - Register accessors */
-#define EWM_CTRL_REG(base) ((base)->CTRL)
-#define EWM_SERV_REG(base) ((base)->SERV)
-#define EWM_CMPL_REG(base) ((base)->CMPL)
-#define EWM_CMPH_REG(base) ((base)->CMPH)
-#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT (0U)
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT (0U)
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
-/* ----------------------------------------------------------------------------
- -- EWM Register Masks
- ---------------------------------------------------------------------------- */
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT (0U)
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
-/*!
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
+/*! @name CLKPRESCALER - Clock Prescaler Register */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
+#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK 0x1u
-#define EWM_CTRL_EWMEN_SHIFT 0
-#define EWM_CTRL_EWMEN_WIDTH 1
-#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
-#define EWM_CTRL_ASSIN_MASK 0x2u
-#define EWM_CTRL_ASSIN_SHIFT 1
-#define EWM_CTRL_ASSIN_WIDTH 1
-#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
-#define EWM_CTRL_INEN_MASK 0x4u
-#define EWM_CTRL_INEN_SHIFT 2
-#define EWM_CTRL_INEN_WIDTH 1
-#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
-#define EWM_CTRL_INTEN_MASK 0x8u
-#define EWM_CTRL_INTEN_SHIFT 3
-#define EWM_CTRL_INTEN_WIDTH 1
-#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK 0xFFu
-#define EWM_SERV_SERVICE_SHIFT 0
-#define EWM_SERV_SERVICE_WIDTH 8
-#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK 0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT 0
-#define EWM_CMPL_COMPAREL_WIDTH 8
-#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK 0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT 0
-#define EWM_CMPH_COMPAREH_WIDTH 8
-#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
-/* CLKPRESCALER Bit Fields */
-#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
-#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
-#define EWM_CLKPRESCALER_CLK_DIV_WIDTH 8
-#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
/*!
* @}
@@ -3071,7 +2180,6 @@ typedef struct {
#define EWM_BASE (0x40061000u)
/** Peripheral EWM base pointer */
#define EWM ((EWM_Type *)EWM_BASE)
-#define EWM_BASE_PTR (EWM)
/** Array initializer of EWM peripheral base addresses */
#define EWM_BASE_ADDRS { EWM_BASE }
/** Array initializer of EWM peripheral base pointers */
@@ -3079,29 +2187,6 @@ typedef struct {
/** Interrupt vectors for the EWM peripheral type */
#define EWM_IRQS { WDOG_EWM_IRQn }
-/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register instance definitions */
-/* EWM */
-#define EWM_CTRL EWM_CTRL_REG(EWM)
-#define EWM_SERV EWM_SERV_REG(EWM)
-#define EWM_CMPL EWM_CMPL_REG(EWM)
-#define EWM_CMPH EWM_CMPH_REG(EWM)
-#define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group EWM_Peripheral_Access_Layer */
@@ -3131,41 +2216,7 @@ typedef struct {
__IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
__IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
} SET[4][8];
-} FMC_Type, *FMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register accessors */
-#define FMC_PFAPR_REG(base) ((base)->PFAPR)
-#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
-#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
-#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
-#define FMC_TAGVDW0S_COUNT 8
-#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
-#define FMC_TAGVDW1S_COUNT 8
-#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
-#define FMC_TAGVDW2S_COUNT 8
-#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
-#define FMC_TAGVDW3S_COUNT 8
-#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
-#define FMC_DATA_U_COUNT 4
-#define FMC_DATA_U_COUNT2 8
-#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
-#define FMC_DATA_L_COUNT 4
-#define FMC_DATA_L_COUNT2 8
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
+} FMC_Type;
/* ----------------------------------------------------------------------------
-- FMC Register Masks
@@ -3176,191 +2227,180 @@ typedef struct {
* @{
*/
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK 0x3u
-#define FMC_PFAPR_M0AP_SHIFT 0
-#define FMC_PFAPR_M0AP_WIDTH 2
-#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK 0xCu
-#define FMC_PFAPR_M1AP_SHIFT 2
-#define FMC_PFAPR_M1AP_WIDTH 2
-#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK 0x30u
-#define FMC_PFAPR_M2AP_SHIFT 4
-#define FMC_PFAPR_M2AP_WIDTH 2
-#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK 0xC0u
-#define FMC_PFAPR_M3AP_SHIFT 6
-#define FMC_PFAPR_M3AP_WIDTH 2
-#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M4AP_MASK 0x300u
-#define FMC_PFAPR_M4AP_SHIFT 8
-#define FMC_PFAPR_M4AP_WIDTH 2
-#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
-#define FMC_PFAPR_M5AP_MASK 0xC00u
-#define FMC_PFAPR_M5AP_SHIFT 10
-#define FMC_PFAPR_M5AP_WIDTH 2
-#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
-#define FMC_PFAPR_M6AP_MASK 0x3000u
-#define FMC_PFAPR_M6AP_SHIFT 12
-#define FMC_PFAPR_M6AP_WIDTH 2
-#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
-#define FMC_PFAPR_M7AP_MASK 0xC000u
-#define FMC_PFAPR_M7AP_SHIFT 14
-#define FMC_PFAPR_M7AP_WIDTH 2
-#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK 0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT 16
-#define FMC_PFAPR_M0PFD_WIDTH 1
-#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
-#define FMC_PFAPR_M1PFD_MASK 0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT 17
-#define FMC_PFAPR_M1PFD_WIDTH 1
-#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
-#define FMC_PFAPR_M2PFD_MASK 0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT 18
-#define FMC_PFAPR_M2PFD_WIDTH 1
-#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
-#define FMC_PFAPR_M3PFD_MASK 0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT 19
-#define FMC_PFAPR_M3PFD_WIDTH 1
-#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
-#define FMC_PFAPR_M4PFD_MASK 0x100000u
-#define FMC_PFAPR_M4PFD_SHIFT 20
-#define FMC_PFAPR_M4PFD_WIDTH 1
-#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
-#define FMC_PFAPR_M5PFD_MASK 0x200000u
-#define FMC_PFAPR_M5PFD_SHIFT 21
-#define FMC_PFAPR_M5PFD_WIDTH 1
-#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
-#define FMC_PFAPR_M6PFD_MASK 0x400000u
-#define FMC_PFAPR_M6PFD_SHIFT 22
-#define FMC_PFAPR_M6PFD_WIDTH 1
-#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
-#define FMC_PFAPR_M7PFD_MASK 0x800000u
-#define FMC_PFAPR_M7PFD_SHIFT 23
-#define FMC_PFAPR_M7PFD_WIDTH 1
-#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK 0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT 0
-#define FMC_PFB0CR_B0SEBE_WIDTH 1
-#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
-#define FMC_PFB0CR_B0IPE_MASK 0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT 1
-#define FMC_PFB0CR_B0IPE_WIDTH 1
-#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
-#define FMC_PFB0CR_B0DPE_MASK 0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT 2
-#define FMC_PFB0CR_B0DPE_WIDTH 1
-#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
-#define FMC_PFB0CR_B0ICE_MASK 0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT 3
-#define FMC_PFB0CR_B0ICE_WIDTH 1
-#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
-#define FMC_PFB0CR_B0DCE_MASK 0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT 4
-#define FMC_PFB0CR_B0DCE_WIDTH 1
-#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
-#define FMC_PFB0CR_CRC_MASK 0xE0u
-#define FMC_PFB0CR_CRC_SHIFT 5
-#define FMC_PFB0CR_CRC_WIDTH 3
-#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK 0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT 17
-#define FMC_PFB0CR_B0MW_WIDTH 2
-#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT 19
-#define FMC_PFB0CR_S_B_INV_WIDTH 1
-#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
-#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT 20
-#define FMC_PFB0CR_CINV_WAY_WIDTH 4
-#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
-#define FMC_PFB0CR_CLCK_WAY_WIDTH 4
-#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT 28
-#define FMC_PFB0CR_B0RWSC_WIDTH 4
-#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* PFB1CR Bit Fields */
-#define FMC_PFB1CR_B1SEBE_MASK 0x1u
-#define FMC_PFB1CR_B1SEBE_SHIFT 0
-#define FMC_PFB1CR_B1SEBE_WIDTH 1
-#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
-#define FMC_PFB1CR_B1IPE_MASK 0x2u
-#define FMC_PFB1CR_B1IPE_SHIFT 1
-#define FMC_PFB1CR_B1IPE_WIDTH 1
-#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
-#define FMC_PFB1CR_B1DPE_MASK 0x4u
-#define FMC_PFB1CR_B1DPE_SHIFT 2
-#define FMC_PFB1CR_B1DPE_WIDTH 1
-#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
-#define FMC_PFB1CR_B1ICE_MASK 0x8u
-#define FMC_PFB1CR_B1ICE_SHIFT 3
-#define FMC_PFB1CR_B1ICE_WIDTH 1
-#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
-#define FMC_PFB1CR_B1DCE_MASK 0x10u
-#define FMC_PFB1CR_B1DCE_SHIFT 4
-#define FMC_PFB1CR_B1DCE_WIDTH 1
-#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
-#define FMC_PFB1CR_B1MW_MASK 0x60000u
-#define FMC_PFB1CR_B1MW_SHIFT 17
-#define FMC_PFB1CR_B1MW_WIDTH 2
-#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
-#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
-#define FMC_PFB1CR_B1RWSC_SHIFT 28
-#define FMC_PFB1CR_B1RWSC_WIDTH 4
-#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
-/* TAGVDW0S Bit Fields */
-#define FMC_TAGVDW0S_valid_MASK 0x1u
-#define FMC_TAGVDW0S_valid_SHIFT 0
-#define FMC_TAGVDW0S_valid_WIDTH 1
-#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
-#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW0S_tag_SHIFT 5
-#define FMC_TAGVDW0S_tag_WIDTH 14
-#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
-/* TAGVDW1S Bit Fields */
-#define FMC_TAGVDW1S_valid_MASK 0x1u
-#define FMC_TAGVDW1S_valid_SHIFT 0
-#define FMC_TAGVDW1S_valid_WIDTH 1
-#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
-#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW1S_tag_SHIFT 5
-#define FMC_TAGVDW1S_tag_WIDTH 14
-#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
-/* TAGVDW2S Bit Fields */
-#define FMC_TAGVDW2S_valid_MASK 0x1u
-#define FMC_TAGVDW2S_valid_SHIFT 0
-#define FMC_TAGVDW2S_valid_WIDTH 1
-#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
-#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW2S_tag_SHIFT 5
-#define FMC_TAGVDW2S_tag_WIDTH 14
-#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
-/* TAGVDW3S Bit Fields */
-#define FMC_TAGVDW3S_valid_MASK 0x1u
-#define FMC_TAGVDW3S_valid_SHIFT 0
-#define FMC_TAGVDW3S_valid_WIDTH 1
-#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
-#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
-#define FMC_TAGVDW3S_tag_SHIFT 5
-#define FMC_TAGVDW3S_tag_WIDTH 14
-#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
-/* DATA_U Bit Fields */
-#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_U_data_SHIFT 0
-#define FMC_DATA_U_data_WIDTH 32
-#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
-/* DATA_L Bit Fields */
-#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_L_data_SHIFT 0
-#define FMC_DATA_L_data_WIDTH 32
-#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+/*! @name PFAPR - Flash Access Protection Register */
+#define FMC_PFAPR_M0AP_MASK (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT (0U)
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT (2U)
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT (4U)
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT (6U)
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK (0x300U)
+#define FMC_PFAPR_M4AP_SHIFT (8U)
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK (0xC00U)
+#define FMC_PFAPR_M5AP_SHIFT (10U)
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK (0x3000U)
+#define FMC_PFAPR_M6AP_SHIFT (12U)
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK (0xC000U)
+#define FMC_PFAPR_M7AP_SHIFT (14U)
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK (0x10000U)
+#define FMC_PFAPR_M0PFD_SHIFT (16U)
+#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK (0x20000U)
+#define FMC_PFAPR_M1PFD_SHIFT (17U)
+#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK (0x40000U)
+#define FMC_PFAPR_M2PFD_SHIFT (18U)
+#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK (0x80000U)
+#define FMC_PFAPR_M3PFD_SHIFT (19U)
+#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK (0x100000U)
+#define FMC_PFAPR_M4PFD_SHIFT (20U)
+#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK (0x200000U)
+#define FMC_PFAPR_M5PFD_SHIFT (21U)
+#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK (0x400000U)
+#define FMC_PFAPR_M6PFD_SHIFT (22U)
+#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK (0x800000U)
+#define FMC_PFAPR_M7PFD_SHIFT (23U)
+#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+
+/*! @name PFB0CR - Flash Bank 0 Control Register */
+#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
+#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
+#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK (0x2U)
+#define FMC_PFB0CR_B0IPE_SHIFT (1U)
+#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK (0x4U)
+#define FMC_PFB0CR_B0DPE_SHIFT (2U)
+#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK (0x8U)
+#define FMC_PFB0CR_B0ICE_SHIFT (3U)
+#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK (0x10U)
+#define FMC_PFB0CR_B0DCE_SHIFT (4U)
+#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK (0xE0U)
+#define FMC_PFB0CR_CRC_SHIFT (5U)
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK (0x60000U)
+#define FMC_PFB0CR_B0MW_SHIFT (17U)
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
+#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
+#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
+#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
+#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
+#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
+
+/*! @name PFB1CR - Flash Bank 1 Control Register */
+#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
+#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
+#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK (0x2U)
+#define FMC_PFB1CR_B1IPE_SHIFT (1U)
+#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK (0x4U)
+#define FMC_PFB1CR_B1DPE_SHIFT (2U)
+#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK (0x8U)
+#define FMC_PFB1CR_B1ICE_SHIFT (3U)
+#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK (0x10U)
+#define FMC_PFB1CR_B1DCE_SHIFT (4U)
+#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK (0x60000U)
+#define FMC_PFB1CR_B1MW_SHIFT (17U)
+#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
+#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
+#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
+
+/*! @name TAGVDW0S - Cache Tag Storage */
+#define FMC_TAGVDW0S_valid_MASK (0x1U)
+#define FMC_TAGVDW0S_valid_SHIFT (0U)
+#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW0S_tag_SHIFT (5U)
+#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
+
+/* The count of FMC_TAGVDW0S */
+#define FMC_TAGVDW0S_COUNT (8U)
+
+/*! @name TAGVDW1S - Cache Tag Storage */
+#define FMC_TAGVDW1S_valid_MASK (0x1U)
+#define FMC_TAGVDW1S_valid_SHIFT (0U)
+#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW1S_tag_SHIFT (5U)
+#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
+
+/* The count of FMC_TAGVDW1S */
+#define FMC_TAGVDW1S_COUNT (8U)
+
+/*! @name TAGVDW2S - Cache Tag Storage */
+#define FMC_TAGVDW2S_valid_MASK (0x1U)
+#define FMC_TAGVDW2S_valid_SHIFT (0U)
+#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW2S_tag_SHIFT (5U)
+#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
+
+/* The count of FMC_TAGVDW2S */
+#define FMC_TAGVDW2S_COUNT (8U)
+
+/*! @name TAGVDW3S - Cache Tag Storage */
+#define FMC_TAGVDW3S_valid_MASK (0x1U)
+#define FMC_TAGVDW3S_valid_SHIFT (0U)
+#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
+#define FMC_TAGVDW3S_tag_SHIFT (5U)
+#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
+
+/* The count of FMC_TAGVDW3S */
+#define FMC_TAGVDW3S_COUNT (8U)
+
+/*! @name DATA_U - Cache Data Storage (upper word) */
+#define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_U_data_SHIFT (0U)
+#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT (4U)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT2 (8U)
+
+/*! @name DATA_L - Cache Data Storage (lower word) */
+#define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_L_data_SHIFT (0U)
+#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT (4U)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT2 (8U)
+
/*!
* @}
@@ -3372,137 +2412,11 @@ typedef struct {
#define FMC_BASE (0x4001F000u)
/** Peripheral FMC base pointer */
#define FMC ((FMC_Type *)FMC_BASE)
-#define FMC_BASE_PTR (FMC)
/** Array initializer of FMC peripheral base addresses */
#define FMC_BASE_ADDRS { FMC_BASE }
/** Array initializer of FMC peripheral base pointers */
#define FMC_BASE_PTRS { FMC }
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register instance definitions */
-/* FMC */
-#define FMC_PFAPR FMC_PFAPR_REG(FMC)
-#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
-#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
-#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
-#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
-#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
-#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
-#define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
-#define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
-#define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
-#define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
-#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
-#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
-#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
-#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
-#define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
-#define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
-#define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
-#define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
-#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
-#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
-#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
-#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
-#define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
-#define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
-#define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
-#define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
-#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
-#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
-#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
-#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
-#define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
-#define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
-#define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
-#define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
-#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
-#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
-#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
-#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
-#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
-#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
-#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
-#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
-#define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
-#define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
-#define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
-#define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
-#define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
-#define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
-#define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
-#define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
-#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
-#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
-#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
-#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
-#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
-#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
-#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
-#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
-#define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
-#define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
-#define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
-#define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
-#define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
-#define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
-#define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
-#define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
-#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
-#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
-#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
-#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
-#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
-#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
-#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
-#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
-#define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
-#define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
-#define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
-#define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
-#define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
-#define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
-#define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
-#define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
-#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
-#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
-#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
-#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
-#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
-#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
-#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
-#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
-#define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
-#define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
-#define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
-#define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
-#define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
-#define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
-#define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
-#define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
-
-/* FMC - Register array accessors */
-#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
-#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
-#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
-#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
-#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
-#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FMC_Peripheral_Access_Layer */
@@ -3559,62 +2473,7 @@ typedef struct {
__I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
uint8_t RESERVED_1[2];
__I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
-} FTFA_Type, *FTFA_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTFA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
- * @{
- */
-
-
-/* FTFA - Register accessors */
-#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
-#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
-#define FTFA_FSEC_REG(base) ((base)->FSEC)
-#define FTFA_FOPT_REG(base) ((base)->FOPT)
-#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
-#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
-#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
-#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
-#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
-#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
-#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
-#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
-#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
-#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
-#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
-#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
-#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
-#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
-#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
-#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
-#define FTFA_XACCH3_REG(base) ((base)->XACCH3)
-#define FTFA_XACCH2_REG(base) ((base)->XACCH2)
-#define FTFA_XACCH1_REG(base) ((base)->XACCH1)
-#define FTFA_XACCH0_REG(base) ((base)->XACCH0)
-#define FTFA_XACCL3_REG(base) ((base)->XACCL3)
-#define FTFA_XACCL2_REG(base) ((base)->XACCL2)
-#define FTFA_XACCL1_REG(base) ((base)->XACCL1)
-#define FTFA_XACCL0_REG(base) ((base)->XACCL0)
-#define FTFA_SACCH3_REG(base) ((base)->SACCH3)
-#define FTFA_SACCH2_REG(base) ((base)->SACCH2)
-#define FTFA_SACCH1_REG(base) ((base)->SACCH1)
-#define FTFA_SACCH0_REG(base) ((base)->SACCH0)
-#define FTFA_SACCL3_REG(base) ((base)->SACCL3)
-#define FTFA_SACCL2_REG(base) ((base)->SACCL2)
-#define FTFA_SACCL1_REG(base) ((base)->SACCL1)
-#define FTFA_SACCL0_REG(base) ((base)->SACCL0)
-#define FTFA_FACSS_REG(base) ((base)->FACSS)
-#define FTFA_FACSN_REG(base) ((base)->FACSN)
-
-/*!
- * @}
- */ /* end of group FTFA_Register_Accessor_Macros */
-
+} FTFA_Type;
/* ----------------------------------------------------------------------------
-- FTFA Register Masks
@@ -3625,236 +2484,226 @@ typedef struct {
* @{
*/
-/* FSTAT Bit Fields */
-#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFA_FSTAT_MGSTAT0_SHIFT 0
-#define FTFA_FSTAT_MGSTAT0_WIDTH 1
-#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_MGSTAT0_SHIFT))&FTFA_FSTAT_MGSTAT0_MASK)
-#define FTFA_FSTAT_FPVIOL_MASK 0x10u
-#define FTFA_FSTAT_FPVIOL_SHIFT 4
-#define FTFA_FSTAT_FPVIOL_WIDTH 1
-#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_FPVIOL_SHIFT))&FTFA_FSTAT_FPVIOL_MASK)
-#define FTFA_FSTAT_ACCERR_MASK 0x20u
-#define FTFA_FSTAT_ACCERR_SHIFT 5
-#define FTFA_FSTAT_ACCERR_WIDTH 1
-#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_ACCERR_SHIFT))&FTFA_FSTAT_ACCERR_MASK)
-#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFA_FSTAT_RDCOLERR_SHIFT 6
-#define FTFA_FSTAT_RDCOLERR_WIDTH 1
-#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_RDCOLERR_SHIFT))&FTFA_FSTAT_RDCOLERR_MASK)
-#define FTFA_FSTAT_CCIF_MASK 0x80u
-#define FTFA_FSTAT_CCIF_SHIFT 7
-#define FTFA_FSTAT_CCIF_WIDTH 1
-#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_CCIF_SHIFT))&FTFA_FSTAT_CCIF_MASK)
-/* FCNFG Bit Fields */
-#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFA_FCNFG_ERSSUSP_SHIFT 4
-#define FTFA_FCNFG_ERSSUSP_WIDTH 1
-#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSSUSP_SHIFT))&FTFA_FCNFG_ERSSUSP_MASK)
-#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFA_FCNFG_ERSAREQ_SHIFT 5
-#define FTFA_FCNFG_ERSAREQ_WIDTH 1
-#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSAREQ_SHIFT))&FTFA_FCNFG_ERSAREQ_MASK)
-#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFA_FCNFG_RDCOLLIE_WIDTH 1
-#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_RDCOLLIE_SHIFT))&FTFA_FCNFG_RDCOLLIE_MASK)
-#define FTFA_FCNFG_CCIE_MASK 0x80u
-#define FTFA_FCNFG_CCIE_SHIFT 7
-#define FTFA_FCNFG_CCIE_WIDTH 1
-#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_CCIE_SHIFT))&FTFA_FCNFG_CCIE_MASK)
-/* FSEC Bit Fields */
-#define FTFA_FSEC_SEC_MASK 0x3u
-#define FTFA_FSEC_SEC_SHIFT 0
-#define FTFA_FSEC_SEC_WIDTH 2
-#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
-#define FTFA_FSEC_FSLACC_MASK 0xCu
-#define FTFA_FSEC_FSLACC_SHIFT 2
-#define FTFA_FSEC_FSLACC_WIDTH 2
-#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
-#define FTFA_FSEC_MEEN_MASK 0x30u
-#define FTFA_FSEC_MEEN_SHIFT 4
-#define FTFA_FSEC_MEEN_WIDTH 2
-#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
-#define FTFA_FSEC_KEYEN_MASK 0xC0u
-#define FTFA_FSEC_KEYEN_SHIFT 6
-#define FTFA_FSEC_KEYEN_WIDTH 2
-#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFA_FOPT_OPT_MASK 0xFFu
-#define FTFA_FOPT_OPT_SHIFT 0
-#define FTFA_FOPT_OPT_WIDTH 8
-#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB3_CCOBn_SHIFT 0
-#define FTFA_FCCOB3_CCOBn_WIDTH 8
-#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB2_CCOBn_SHIFT 0
-#define FTFA_FCCOB2_CCOBn_WIDTH 8
-#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB1_CCOBn_SHIFT 0
-#define FTFA_FCCOB1_CCOBn_WIDTH 8
-#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB0_CCOBn_SHIFT 0
-#define FTFA_FCCOB0_CCOBn_WIDTH 8
-#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB7_CCOBn_SHIFT 0
-#define FTFA_FCCOB7_CCOBn_WIDTH 8
-#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB6_CCOBn_SHIFT 0
-#define FTFA_FCCOB6_CCOBn_WIDTH 8
-#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB5_CCOBn_SHIFT 0
-#define FTFA_FCCOB5_CCOBn_WIDTH 8
-#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB4_CCOBn_SHIFT 0
-#define FTFA_FCCOB4_CCOBn_WIDTH 8
-#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBB_CCOBn_SHIFT 0
-#define FTFA_FCCOBB_CCOBn_WIDTH 8
-#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBA_CCOBn_SHIFT 0
-#define FTFA_FCCOBA_CCOBn_WIDTH 8
-#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB9_CCOBn_SHIFT 0
-#define FTFA_FCCOB9_CCOBn_WIDTH 8
-#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB8_CCOBn_SHIFT 0
-#define FTFA_FCCOB8_CCOBn_WIDTH 8
-#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFA_FPROT3_PROT_MASK 0xFFu
-#define FTFA_FPROT3_PROT_SHIFT 0
-#define FTFA_FPROT3_PROT_WIDTH 8
-#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFA_FPROT2_PROT_MASK 0xFFu
-#define FTFA_FPROT2_PROT_SHIFT 0
-#define FTFA_FPROT2_PROT_WIDTH 8
-#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFA_FPROT1_PROT_MASK 0xFFu
-#define FTFA_FPROT1_PROT_SHIFT 0
-#define FTFA_FPROT1_PROT_WIDTH 8
-#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFA_FPROT0_PROT_MASK 0xFFu
-#define FTFA_FPROT0_PROT_SHIFT 0
-#define FTFA_FPROT0_PROT_WIDTH 8
-#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
-/* XACCH3 Bit Fields */
-#define FTFA_XACCH3_XA_MASK 0xFFu
-#define FTFA_XACCH3_XA_SHIFT 0
-#define FTFA_XACCH3_XA_WIDTH 8
-#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
-/* XACCH2 Bit Fields */
-#define FTFA_XACCH2_XA_MASK 0xFFu
-#define FTFA_XACCH2_XA_SHIFT 0
-#define FTFA_XACCH2_XA_WIDTH 8
-#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
-/* XACCH1 Bit Fields */
-#define FTFA_XACCH1_XA_MASK 0xFFu
-#define FTFA_XACCH1_XA_SHIFT 0
-#define FTFA_XACCH1_XA_WIDTH 8
-#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
-/* XACCH0 Bit Fields */
-#define FTFA_XACCH0_XA_MASK 0xFFu
-#define FTFA_XACCH0_XA_SHIFT 0
-#define FTFA_XACCH0_XA_WIDTH 8
-#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
-/* XACCL3 Bit Fields */
-#define FTFA_XACCL3_XA_MASK 0xFFu
-#define FTFA_XACCL3_XA_SHIFT 0
-#define FTFA_XACCL3_XA_WIDTH 8
-#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
-/* XACCL2 Bit Fields */
-#define FTFA_XACCL2_XA_MASK 0xFFu
-#define FTFA_XACCL2_XA_SHIFT 0
-#define FTFA_XACCL2_XA_WIDTH 8
-#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
-/* XACCL1 Bit Fields */
-#define FTFA_XACCL1_XA_MASK 0xFFu
-#define FTFA_XACCL1_XA_SHIFT 0
-#define FTFA_XACCL1_XA_WIDTH 8
-#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
-/* XACCL0 Bit Fields */
-#define FTFA_XACCL0_XA_MASK 0xFFu
-#define FTFA_XACCL0_XA_SHIFT 0
-#define FTFA_XACCL0_XA_WIDTH 8
-#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
-/* SACCH3 Bit Fields */
-#define FTFA_SACCH3_SA_MASK 0xFFu
-#define FTFA_SACCH3_SA_SHIFT 0
-#define FTFA_SACCH3_SA_WIDTH 8
-#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
-/* SACCH2 Bit Fields */
-#define FTFA_SACCH2_SA_MASK 0xFFu
-#define FTFA_SACCH2_SA_SHIFT 0
-#define FTFA_SACCH2_SA_WIDTH 8
-#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
-/* SACCH1 Bit Fields */
-#define FTFA_SACCH1_SA_MASK 0xFFu
-#define FTFA_SACCH1_SA_SHIFT 0
-#define FTFA_SACCH1_SA_WIDTH 8
-#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
-/* SACCH0 Bit Fields */
-#define FTFA_SACCH0_SA_MASK 0xFFu
-#define FTFA_SACCH0_SA_SHIFT 0
-#define FTFA_SACCH0_SA_WIDTH 8
-#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
-/* SACCL3 Bit Fields */
-#define FTFA_SACCL3_SA_MASK 0xFFu
-#define FTFA_SACCL3_SA_SHIFT 0
-#define FTFA_SACCL3_SA_WIDTH 8
-#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
-/* SACCL2 Bit Fields */
-#define FTFA_SACCL2_SA_MASK 0xFFu
-#define FTFA_SACCL2_SA_SHIFT 0
-#define FTFA_SACCL2_SA_WIDTH 8
-#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
-/* SACCL1 Bit Fields */
-#define FTFA_SACCL1_SA_MASK 0xFFu
-#define FTFA_SACCL1_SA_SHIFT 0
-#define FTFA_SACCL1_SA_WIDTH 8
-#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
-/* SACCL0 Bit Fields */
-#define FTFA_SACCL0_SA_MASK 0xFFu
-#define FTFA_SACCL0_SA_SHIFT 0
-#define FTFA_SACCL0_SA_WIDTH 8
-#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
-/* FACSS Bit Fields */
-#define FTFA_FACSS_SGSIZE_MASK 0xFFu
-#define FTFA_FACSS_SGSIZE_SHIFT 0
-#define FTFA_FACSS_SGSIZE_WIDTH 8
-#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
-/* FACSN Bit Fields */
-#define FTFA_FACSN_NUMSG_MASK 0xFFu
-#define FTFA_FACSN_NUMSG_SHIFT 0
-#define FTFA_FACSN_NUMSG_WIDTH 8
-#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
+/*! @name FSTAT - Flash Status Register */
+#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
+#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
+#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
+#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
+#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
+#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
+#define FTFA_FSTAT_ACCERR_MASK (0x20U)
+#define FTFA_FSTAT_ACCERR_SHIFT (5U)
+#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
+#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
+#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
+#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
+#define FTFA_FSTAT_CCIF_MASK (0x80U)
+#define FTFA_FSTAT_CCIF_SHIFT (7U)
+#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
+#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
+#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
+#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
+#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
+#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
+#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
+#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
+#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
+#define FTFA_FCNFG_CCIE_MASK (0x80U)
+#define FTFA_FCNFG_CCIE_SHIFT (7U)
+#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFA_FSEC_SEC_MASK (0x3U)
+#define FTFA_FSEC_SEC_SHIFT (0U)
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK (0xCU)
+#define FTFA_FSEC_FSLACC_SHIFT (2U)
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK (0x30U)
+#define FTFA_FSEC_MEEN_SHIFT (4U)
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK (0xC0U)
+#define FTFA_FSEC_KEYEN_SHIFT (6U)
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFA_FOPT_OPT_MASK (0xFFU)
+#define FTFA_FOPT_OPT_SHIFT (0U)
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
+#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFA_FPROT3_PROT_MASK (0xFFU)
+#define FTFA_FPROT3_PROT_SHIFT (0U)
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFA_FPROT2_PROT_MASK (0xFFU)
+#define FTFA_FPROT2_PROT_SHIFT (0U)
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFA_FPROT1_PROT_MASK (0xFFU)
+#define FTFA_FPROT1_PROT_SHIFT (0U)
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFA_FPROT0_PROT_MASK (0xFFU)
+#define FTFA_FPROT0_PROT_SHIFT (0U)
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
+
+/*! @name XACCH3 - Execute-only Access Registers */
+#define FTFA_XACCH3_XA_MASK (0xFFU)
+#define FTFA_XACCH3_XA_SHIFT (0U)
+#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
+
+/*! @name XACCH2 - Execute-only Access Registers */
+#define FTFA_XACCH2_XA_MASK (0xFFU)
+#define FTFA_XACCH2_XA_SHIFT (0U)
+#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
+
+/*! @name XACCH1 - Execute-only Access Registers */
+#define FTFA_XACCH1_XA_MASK (0xFFU)
+#define FTFA_XACCH1_XA_SHIFT (0U)
+#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
+
+/*! @name XACCH0 - Execute-only Access Registers */
+#define FTFA_XACCH0_XA_MASK (0xFFU)
+#define FTFA_XACCH0_XA_SHIFT (0U)
+#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
+
+/*! @name XACCL3 - Execute-only Access Registers */
+#define FTFA_XACCL3_XA_MASK (0xFFU)
+#define FTFA_XACCL3_XA_SHIFT (0U)
+#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
+
+/*! @name XACCL2 - Execute-only Access Registers */
+#define FTFA_XACCL2_XA_MASK (0xFFU)
+#define FTFA_XACCL2_XA_SHIFT (0U)
+#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
+
+/*! @name XACCL1 - Execute-only Access Registers */
+#define FTFA_XACCL1_XA_MASK (0xFFU)
+#define FTFA_XACCL1_XA_SHIFT (0U)
+#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
+
+/*! @name XACCL0 - Execute-only Access Registers */
+#define FTFA_XACCL0_XA_MASK (0xFFU)
+#define FTFA_XACCL0_XA_SHIFT (0U)
+#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
+
+/*! @name SACCH3 - Supervisor-only Access Registers */
+#define FTFA_SACCH3_SA_MASK (0xFFU)
+#define FTFA_SACCH3_SA_SHIFT (0U)
+#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
+
+/*! @name SACCH2 - Supervisor-only Access Registers */
+#define FTFA_SACCH2_SA_MASK (0xFFU)
+#define FTFA_SACCH2_SA_SHIFT (0U)
+#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
+
+/*! @name SACCH1 - Supervisor-only Access Registers */
+#define FTFA_SACCH1_SA_MASK (0xFFU)
+#define FTFA_SACCH1_SA_SHIFT (0U)
+#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
+
+/*! @name SACCH0 - Supervisor-only Access Registers */
+#define FTFA_SACCH0_SA_MASK (0xFFU)
+#define FTFA_SACCH0_SA_SHIFT (0U)
+#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
+
+/*! @name SACCL3 - Supervisor-only Access Registers */
+#define FTFA_SACCL3_SA_MASK (0xFFU)
+#define FTFA_SACCL3_SA_SHIFT (0U)
+#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
+
+/*! @name SACCL2 - Supervisor-only Access Registers */
+#define FTFA_SACCL2_SA_MASK (0xFFU)
+#define FTFA_SACCL2_SA_SHIFT (0U)
+#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
+
+/*! @name SACCL1 - Supervisor-only Access Registers */
+#define FTFA_SACCL1_SA_MASK (0xFFU)
+#define FTFA_SACCL1_SA_SHIFT (0U)
+#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
+
+/*! @name SACCL0 - Supervisor-only Access Registers */
+#define FTFA_SACCL0_SA_MASK (0xFFU)
+#define FTFA_SACCL0_SA_SHIFT (0U)
+#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
+
+/*! @name FACSS - Flash Access Segment Size Register */
+#define FTFA_FACSS_SGSIZE_MASK (0xFFU)
+#define FTFA_FACSS_SGSIZE_SHIFT (0U)
+#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
+
+/*! @name FACSN - Flash Access Segment Number Register */
+#define FTFA_FACSN_NUMSG_MASK (0xFFU)
+#define FTFA_FACSN_NUMSG_SHIFT (0U)
+#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
+
/*!
* @}
@@ -3866,7 +2715,6 @@ typedef struct {
#define FTFA_BASE (0x40020000u)
/** Peripheral FTFA base pointer */
#define FTFA ((FTFA_Type *)FTFA_BASE)
-#define FTFA_BASE_PTR (FTFA)
/** Array initializer of FTFA peripheral base addresses */
#define FTFA_BASE_ADDRS { FTFA_BASE }
/** Array initializer of FTFA peripheral base pointers */
@@ -3875,62 +2723,6 @@ typedef struct {
#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
-/* ----------------------------------------------------------------------------
- -- FTFA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
- * @{
- */
-
-
-/* FTFA - Register instance definitions */
-/* FTFA */
-#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
-#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
-#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
-#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
-#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
-#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
-#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
-#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
-#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
-#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
-#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
-#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
-#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
-#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
-#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
-#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
-#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
-#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
-#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
-#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
-#define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
-#define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
-#define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
-#define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
-#define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
-#define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
-#define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
-#define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
-#define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
-#define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
-#define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
-#define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
-#define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
-#define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
-#define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
-#define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
-#define FTFA_FACSS FTFA_FACSS_REG(FTFA)
-#define FTFA_FACSN FTFA_FACSN_REG(FTFA)
-
-/*!
- * @}
- */ /* end of group FTFA_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FTFA_Peripheral_Access_Layer */
@@ -3974,51 +2766,7 @@ typedef struct {
__IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
__IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
__IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type, *FTM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register accessors */
-#define FTM_SC_REG(base) ((base)->SC)
-#define FTM_CNT_REG(base) ((base)->CNT)
-#define FTM_MOD_REG(base) ((base)->MOD)
-#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
-#define FTM_CnSC_COUNT 8
-#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
-#define FTM_CnV_COUNT 8
-#define FTM_CNTIN_REG(base) ((base)->CNTIN)
-#define FTM_STATUS_REG(base) ((base)->STATUS)
-#define FTM_MODE_REG(base) ((base)->MODE)
-#define FTM_SYNC_REG(base) ((base)->SYNC)
-#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
-#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
-#define FTM_COMBINE_REG(base) ((base)->COMBINE)
-#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
-#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
-#define FTM_POL_REG(base) ((base)->POL)
-#define FTM_FMS_REG(base) ((base)->FMS)
-#define FTM_FILTER_REG(base) ((base)->FILTER)
-#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
-#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
-#define FTM_CONF_REG(base) ((base)->CONF)
-#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
-#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
-#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
-#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
-#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
+} FTM_Type;
/* ----------------------------------------------------------------------------
-- FTM Register Masks
@@ -4029,759 +2777,608 @@ typedef struct {
* @{
*/
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK 0x7u
-#define FTM_SC_PS_SHIFT 0
-#define FTM_SC_PS_WIDTH 3
-#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK 0x18u
-#define FTM_SC_CLKS_SHIFT 3
-#define FTM_SC_CLKS_WIDTH 2
-#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK 0x20u
-#define FTM_SC_CPWMS_SHIFT 5
-#define FTM_SC_CPWMS_WIDTH 1
-#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
-#define FTM_SC_TOIE_MASK 0x40u
-#define FTM_SC_TOIE_SHIFT 6
-#define FTM_SC_TOIE_WIDTH 1
-#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
-#define FTM_SC_TOF_MASK 0x80u
-#define FTM_SC_TOF_SHIFT 7
-#define FTM_SC_TOF_WIDTH 1
-#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK 0xFFFFu
-#define FTM_CNT_COUNT_SHIFT 0
-#define FTM_CNT_COUNT_WIDTH 16
-#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK 0xFFFFu
-#define FTM_MOD_MOD_SHIFT 0
-#define FTM_MOD_MOD_WIDTH 16
-#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK 0x1u
-#define FTM_CnSC_DMA_SHIFT 0
-#define FTM_CnSC_DMA_WIDTH 1
-#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
-#define FTM_CnSC_ICRST_MASK 0x2u
-#define FTM_CnSC_ICRST_SHIFT 1
-#define FTM_CnSC_ICRST_WIDTH 1
-#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ICRST_SHIFT))&FTM_CnSC_ICRST_MASK)
-#define FTM_CnSC_ELSA_MASK 0x4u
-#define FTM_CnSC_ELSA_SHIFT 2
-#define FTM_CnSC_ELSA_WIDTH 1
-#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
-#define FTM_CnSC_ELSB_MASK 0x8u
-#define FTM_CnSC_ELSB_SHIFT 3
-#define FTM_CnSC_ELSB_WIDTH 1
-#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
-#define FTM_CnSC_MSA_MASK 0x10u
-#define FTM_CnSC_MSA_SHIFT 4
-#define FTM_CnSC_MSA_WIDTH 1
-#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
-#define FTM_CnSC_MSB_MASK 0x20u
-#define FTM_CnSC_MSB_SHIFT 5
-#define FTM_CnSC_MSB_WIDTH 1
-#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
-#define FTM_CnSC_CHIE_MASK 0x40u
-#define FTM_CnSC_CHIE_SHIFT 6
-#define FTM_CnSC_CHIE_WIDTH 1
-#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
-#define FTM_CnSC_CHF_MASK 0x80u
-#define FTM_CnSC_CHF_SHIFT 7
-#define FTM_CnSC_CHF_WIDTH 1
-#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK 0xFFFFu
-#define FTM_CnV_VAL_SHIFT 0
-#define FTM_CnV_VAL_WIDTH 16
-#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK 0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT 0
-#define FTM_CNTIN_INIT_WIDTH 16
-#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK 0x1u
-#define FTM_STATUS_CH0F_SHIFT 0
-#define FTM_STATUS_CH0F_WIDTH 1
-#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
-#define FTM_STATUS_CH1F_MASK 0x2u
-#define FTM_STATUS_CH1F_SHIFT 1
-#define FTM_STATUS_CH1F_WIDTH 1
-#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
-#define FTM_STATUS_CH2F_MASK 0x4u
-#define FTM_STATUS_CH2F_SHIFT 2
-#define FTM_STATUS_CH2F_WIDTH 1
-#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
-#define FTM_STATUS_CH3F_MASK 0x8u
-#define FTM_STATUS_CH3F_SHIFT 3
-#define FTM_STATUS_CH3F_WIDTH 1
-#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
-#define FTM_STATUS_CH4F_MASK 0x10u
-#define FTM_STATUS_CH4F_SHIFT 4
-#define FTM_STATUS_CH4F_WIDTH 1
-#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
-#define FTM_STATUS_CH5F_MASK 0x20u
-#define FTM_STATUS_CH5F_SHIFT 5
-#define FTM_STATUS_CH5F_WIDTH 1
-#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
-#define FTM_STATUS_CH6F_MASK 0x40u
-#define FTM_STATUS_CH6F_SHIFT 6
-#define FTM_STATUS_CH6F_WIDTH 1
-#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
-#define FTM_STATUS_CH7F_MASK 0x80u
-#define FTM_STATUS_CH7F_SHIFT 7
-#define FTM_STATUS_CH7F_WIDTH 1
-#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK 0x1u
-#define FTM_MODE_FTMEN_SHIFT 0
-#define FTM_MODE_FTMEN_WIDTH 1
-#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
-#define FTM_MODE_INIT_MASK 0x2u
-#define FTM_MODE_INIT_SHIFT 1
-#define FTM_MODE_INIT_WIDTH 1
-#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
-#define FTM_MODE_WPDIS_MASK 0x4u
-#define FTM_MODE_WPDIS_SHIFT 2
-#define FTM_MODE_WPDIS_WIDTH 1
-#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
-#define FTM_MODE_PWMSYNC_MASK 0x8u
-#define FTM_MODE_PWMSYNC_SHIFT 3
-#define FTM_MODE_PWMSYNC_WIDTH 1
-#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
-#define FTM_MODE_CAPTEST_MASK 0x10u
-#define FTM_MODE_CAPTEST_SHIFT 4
-#define FTM_MODE_CAPTEST_WIDTH 1
-#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
-#define FTM_MODE_FAULTM_MASK 0x60u
-#define FTM_MODE_FAULTM_SHIFT 5
-#define FTM_MODE_FAULTM_WIDTH 2
-#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK 0x80u
-#define FTM_MODE_FAULTIE_SHIFT 7
-#define FTM_MODE_FAULTIE_WIDTH 1
-#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK 0x1u
-#define FTM_SYNC_CNTMIN_SHIFT 0
-#define FTM_SYNC_CNTMIN_WIDTH 1
-#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
-#define FTM_SYNC_CNTMAX_MASK 0x2u
-#define FTM_SYNC_CNTMAX_SHIFT 1
-#define FTM_SYNC_CNTMAX_WIDTH 1
-#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
-#define FTM_SYNC_REINIT_MASK 0x4u
-#define FTM_SYNC_REINIT_SHIFT 2
-#define FTM_SYNC_REINIT_WIDTH 1
-#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
-#define FTM_SYNC_SYNCHOM_MASK 0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT 3
-#define FTM_SYNC_SYNCHOM_WIDTH 1
-#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
-#define FTM_SYNC_TRIG0_MASK 0x10u
-#define FTM_SYNC_TRIG0_SHIFT 4
-#define FTM_SYNC_TRIG0_WIDTH 1
-#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
-#define FTM_SYNC_TRIG1_MASK 0x20u
-#define FTM_SYNC_TRIG1_SHIFT 5
-#define FTM_SYNC_TRIG1_WIDTH 1
-#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
-#define FTM_SYNC_TRIG2_MASK 0x40u
-#define FTM_SYNC_TRIG2_SHIFT 6
-#define FTM_SYNC_TRIG2_WIDTH 1
-#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
-#define FTM_SYNC_SWSYNC_MASK 0x80u
-#define FTM_SYNC_SWSYNC_SHIFT 7
-#define FTM_SYNC_SWSYNC_WIDTH 1
-#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK 0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT 0
-#define FTM_OUTINIT_CH0OI_WIDTH 1
-#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
-#define FTM_OUTINIT_CH1OI_MASK 0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT 1
-#define FTM_OUTINIT_CH1OI_WIDTH 1
-#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
-#define FTM_OUTINIT_CH2OI_MASK 0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT 2
-#define FTM_OUTINIT_CH2OI_WIDTH 1
-#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
-#define FTM_OUTINIT_CH3OI_MASK 0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT 3
-#define FTM_OUTINIT_CH3OI_WIDTH 1
-#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
-#define FTM_OUTINIT_CH4OI_MASK 0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT 4
-#define FTM_OUTINIT_CH4OI_WIDTH 1
-#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
-#define FTM_OUTINIT_CH5OI_MASK 0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT 5
-#define FTM_OUTINIT_CH5OI_WIDTH 1
-#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
-#define FTM_OUTINIT_CH6OI_MASK 0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT 6
-#define FTM_OUTINIT_CH6OI_WIDTH 1
-#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
-#define FTM_OUTINIT_CH7OI_MASK 0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT 7
-#define FTM_OUTINIT_CH7OI_WIDTH 1
-#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK 0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT 0
-#define FTM_OUTMASK_CH0OM_WIDTH 1
-#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
-#define FTM_OUTMASK_CH1OM_MASK 0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT 1
-#define FTM_OUTMASK_CH1OM_WIDTH 1
-#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
-#define FTM_OUTMASK_CH2OM_MASK 0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT 2
-#define FTM_OUTMASK_CH2OM_WIDTH 1
-#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
-#define FTM_OUTMASK_CH3OM_MASK 0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT 3
-#define FTM_OUTMASK_CH3OM_WIDTH 1
-#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
-#define FTM_OUTMASK_CH4OM_MASK 0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT 4
-#define FTM_OUTMASK_CH4OM_WIDTH 1
-#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
-#define FTM_OUTMASK_CH5OM_MASK 0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT 5
-#define FTM_OUTMASK_CH5OM_WIDTH 1
-#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
-#define FTM_OUTMASK_CH6OM_MASK 0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT 6
-#define FTM_OUTMASK_CH6OM_WIDTH 1
-#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
-#define FTM_OUTMASK_CH7OM_MASK 0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT 7
-#define FTM_OUTMASK_CH7OM_WIDTH 1
-#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK 0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT 0
-#define FTM_COMBINE_COMBINE0_WIDTH 1
-#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
-#define FTM_COMBINE_COMP0_MASK 0x2u
-#define FTM_COMBINE_COMP0_SHIFT 1
-#define FTM_COMBINE_COMP0_WIDTH 1
-#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
-#define FTM_COMBINE_DECAPEN0_MASK 0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT 2
-#define FTM_COMBINE_DECAPEN0_WIDTH 1
-#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
-#define FTM_COMBINE_DECAP0_MASK 0x8u
-#define FTM_COMBINE_DECAP0_SHIFT 3
-#define FTM_COMBINE_DECAP0_WIDTH 1
-#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
-#define FTM_COMBINE_DTEN0_MASK 0x10u
-#define FTM_COMBINE_DTEN0_SHIFT 4
-#define FTM_COMBINE_DTEN0_WIDTH 1
-#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
-#define FTM_COMBINE_SYNCEN0_MASK 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT 5
-#define FTM_COMBINE_SYNCEN0_WIDTH 1
-#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
-#define FTM_COMBINE_FAULTEN0_MASK 0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT 6
-#define FTM_COMBINE_FAULTEN0_WIDTH 1
-#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
-#define FTM_COMBINE_COMBINE1_MASK 0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT 8
-#define FTM_COMBINE_COMBINE1_WIDTH 1
-#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
-#define FTM_COMBINE_COMP1_MASK 0x200u
-#define FTM_COMBINE_COMP1_SHIFT 9
-#define FTM_COMBINE_COMP1_WIDTH 1
-#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
-#define FTM_COMBINE_DECAPEN1_MASK 0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT 10
-#define FTM_COMBINE_DECAPEN1_WIDTH 1
-#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
-#define FTM_COMBINE_DECAP1_MASK 0x800u
-#define FTM_COMBINE_DECAP1_SHIFT 11
-#define FTM_COMBINE_DECAP1_WIDTH 1
-#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
-#define FTM_COMBINE_DTEN1_MASK 0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT 12
-#define FTM_COMBINE_DTEN1_WIDTH 1
-#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
-#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT 13
-#define FTM_COMBINE_SYNCEN1_WIDTH 1
-#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
-#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT 14
-#define FTM_COMBINE_FAULTEN1_WIDTH 1
-#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
-#define FTM_COMBINE_COMBINE2_MASK 0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT 16
-#define FTM_COMBINE_COMBINE2_WIDTH 1
-#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
-#define FTM_COMBINE_COMP2_MASK 0x20000u
-#define FTM_COMBINE_COMP2_SHIFT 17
-#define FTM_COMBINE_COMP2_WIDTH 1
-#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
-#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT 18
-#define FTM_COMBINE_DECAPEN2_WIDTH 1
-#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
-#define FTM_COMBINE_DECAP2_MASK 0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT 19
-#define FTM_COMBINE_DECAP2_WIDTH 1
-#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
-#define FTM_COMBINE_DTEN2_MASK 0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT 20
-#define FTM_COMBINE_DTEN2_WIDTH 1
-#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
-#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT 21
-#define FTM_COMBINE_SYNCEN2_WIDTH 1
-#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
-#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT 22
-#define FTM_COMBINE_FAULTEN2_WIDTH 1
-#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
-#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT 24
-#define FTM_COMBINE_COMBINE3_WIDTH 1
-#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
-#define FTM_COMBINE_COMP3_MASK 0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT 25
-#define FTM_COMBINE_COMP3_WIDTH 1
-#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
-#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT 26
-#define FTM_COMBINE_DECAPEN3_WIDTH 1
-#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
-#define FTM_COMBINE_DECAP3_MASK 0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT 27
-#define FTM_COMBINE_DECAP3_WIDTH 1
-#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
-#define FTM_COMBINE_DTEN3_MASK 0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT 28
-#define FTM_COMBINE_DTEN3_WIDTH 1
-#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
-#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT 29
-#define FTM_COMBINE_SYNCEN3_WIDTH 1
-#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
-#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT 30
-#define FTM_COMBINE_FAULTEN3_WIDTH 1
-#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT 0
-#define FTM_DEADTIME_DTVAL_WIDTH 6
-#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK 0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT 6
-#define FTM_DEADTIME_DTPS_WIDTH 2
-#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
-#define FTM_EXTTRIG_CH2TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
-#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
-#define FTM_EXTTRIG_CH3TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
-#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
-#define FTM_EXTTRIG_CH4TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
-#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
-#define FTM_EXTTRIG_CH5TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
-#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
-#define FTM_EXTTRIG_CH0TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
-#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
-#define FTM_EXTTRIG_CH1TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
-#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
-#define FTM_EXTTRIG_INITTRIGEN_WIDTH 1
-#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
-#define FTM_EXTTRIG_TRIGF_MASK 0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT 7
-#define FTM_EXTTRIG_TRIGF_WIDTH 1
-#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK 0x1u
-#define FTM_POL_POL0_SHIFT 0
-#define FTM_POL_POL0_WIDTH 1
-#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
-#define FTM_POL_POL1_MASK 0x2u
-#define FTM_POL_POL1_SHIFT 1
-#define FTM_POL_POL1_WIDTH 1
-#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
-#define FTM_POL_POL2_MASK 0x4u
-#define FTM_POL_POL2_SHIFT 2
-#define FTM_POL_POL2_WIDTH 1
-#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
-#define FTM_POL_POL3_MASK 0x8u
-#define FTM_POL_POL3_SHIFT 3
-#define FTM_POL_POL3_WIDTH 1
-#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
-#define FTM_POL_POL4_MASK 0x10u
-#define FTM_POL_POL4_SHIFT 4
-#define FTM_POL_POL4_WIDTH 1
-#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
-#define FTM_POL_POL5_MASK 0x20u
-#define FTM_POL_POL5_SHIFT 5
-#define FTM_POL_POL5_WIDTH 1
-#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
-#define FTM_POL_POL6_MASK 0x40u
-#define FTM_POL_POL6_SHIFT 6
-#define FTM_POL_POL6_WIDTH 1
-#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
-#define FTM_POL_POL7_MASK 0x80u
-#define FTM_POL_POL7_SHIFT 7
-#define FTM_POL_POL7_WIDTH 1
-#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK 0x1u
-#define FTM_FMS_FAULTF0_SHIFT 0
-#define FTM_FMS_FAULTF0_WIDTH 1
-#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
-#define FTM_FMS_FAULTF1_MASK 0x2u
-#define FTM_FMS_FAULTF1_SHIFT 1
-#define FTM_FMS_FAULTF1_WIDTH 1
-#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
-#define FTM_FMS_FAULTF2_MASK 0x4u
-#define FTM_FMS_FAULTF2_SHIFT 2
-#define FTM_FMS_FAULTF2_WIDTH 1
-#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
-#define FTM_FMS_FAULTF3_MASK 0x8u
-#define FTM_FMS_FAULTF3_SHIFT 3
-#define FTM_FMS_FAULTF3_WIDTH 1
-#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
-#define FTM_FMS_FAULTIN_MASK 0x20u
-#define FTM_FMS_FAULTIN_SHIFT 5
-#define FTM_FMS_FAULTIN_WIDTH 1
-#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
-#define FTM_FMS_WPEN_MASK 0x40u
-#define FTM_FMS_WPEN_SHIFT 6
-#define FTM_FMS_WPEN_WIDTH 1
-#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
-#define FTM_FMS_FAULTF_MASK 0x80u
-#define FTM_FMS_FAULTF_SHIFT 7
-#define FTM_FMS_FAULTF_WIDTH 1
-#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK 0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT 0
-#define FTM_FILTER_CH0FVAL_WIDTH 4
-#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK 0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT 4
-#define FTM_FILTER_CH1FVAL_WIDTH 4
-#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK 0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT 8
-#define FTM_FILTER_CH2FVAL_WIDTH 4
-#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK 0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT 12
-#define FTM_FILTER_CH3FVAL_WIDTH 4
-#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
-#define FTM_FLTCTRL_FAULT0EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
-#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
-#define FTM_FLTCTRL_FAULT1EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
-#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
-#define FTM_FLTCTRL_FAULT2EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
-#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
-#define FTM_FLTCTRL_FAULT3EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
-#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
-#define FTM_FLTCTRL_FFLTR0EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
-#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
-#define FTM_FLTCTRL_FFLTR1EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
-#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
-#define FTM_FLTCTRL_FFLTR2EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
-#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
-#define FTM_FLTCTRL_FFLTR3EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
-#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT 8
-#define FTM_FLTCTRL_FFVAL_WIDTH 4
-#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK 0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT 0
-#define FTM_QDCTRL_QUADEN_WIDTH 1
-#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
-#define FTM_QDCTRL_TOFDIR_MASK 0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT 1
-#define FTM_QDCTRL_TOFDIR_WIDTH 1
-#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
-#define FTM_QDCTRL_QUADIR_MASK 0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT 2
-#define FTM_QDCTRL_QUADIR_WIDTH 1
-#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
-#define FTM_QDCTRL_QUADMODE_MASK 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT 3
-#define FTM_QDCTRL_QUADMODE_WIDTH 1
-#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
-#define FTM_QDCTRL_PHBPOL_MASK 0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT 4
-#define FTM_QDCTRL_PHBPOL_WIDTH 1
-#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
-#define FTM_QDCTRL_PHAPOL_MASK 0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT 5
-#define FTM_QDCTRL_PHAPOL_WIDTH 1
-#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
-#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
-#define FTM_QDCTRL_PHBFLTREN_WIDTH 1
-#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
-#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
-#define FTM_QDCTRL_PHAFLTREN_WIDTH 1
-#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK 0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT 0
-#define FTM_CONF_NUMTOF_WIDTH 5
-#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK 0xC0u
-#define FTM_CONF_BDMMODE_SHIFT 6
-#define FTM_CONF_BDMMODE_WIDTH 2
-#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK 0x200u
-#define FTM_CONF_GTBEEN_SHIFT 9
-#define FTM_CONF_GTBEEN_WIDTH 1
-#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
-#define FTM_CONF_GTBEOUT_MASK 0x400u
-#define FTM_CONF_GTBEOUT_SHIFT 10
-#define FTM_CONF_GTBEOUT_WIDTH 1
-#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK 0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT 0
-#define FTM_FLTPOL_FLT0POL_WIDTH 1
-#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
-#define FTM_FLTPOL_FLT1POL_MASK 0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT 1
-#define FTM_FLTPOL_FLT1POL_WIDTH 1
-#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
-#define FTM_FLTPOL_FLT2POL_MASK 0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT 2
-#define FTM_FLTPOL_FLT2POL_WIDTH 1
-#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
-#define FTM_FLTPOL_FLT3POL_MASK 0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT 3
-#define FTM_FLTPOL_FLT3POL_WIDTH 1
-#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
-#define FTM_SYNCONF_HWTRIGMODE_WIDTH 1
-#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
-#define FTM_SYNCONF_CNTINC_MASK 0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT 2
-#define FTM_SYNCONF_CNTINC_WIDTH 1
-#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
-#define FTM_SYNCONF_INVC_MASK 0x10u
-#define FTM_SYNCONF_INVC_SHIFT 4
-#define FTM_SYNCONF_INVC_WIDTH 1
-#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
-#define FTM_SYNCONF_SWOC_MASK 0x20u
-#define FTM_SYNCONF_SWOC_SHIFT 5
-#define FTM_SYNCONF_SWOC_WIDTH 1
-#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
-#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT 7
-#define FTM_SYNCONF_SYNCMODE_WIDTH 1
-#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
-#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
-#define FTM_SYNCONF_SWRSTCNT_WIDTH 1
-#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
-#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT 9
-#define FTM_SYNCONF_SWWRBUF_WIDTH 1
-#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
-#define FTM_SYNCONF_SWOM_MASK 0x400u
-#define FTM_SYNCONF_SWOM_SHIFT 10
-#define FTM_SYNCONF_SWOM_WIDTH 1
-#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
-#define FTM_SYNCONF_SWINVC_MASK 0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT 11
-#define FTM_SYNCONF_SWINVC_WIDTH 1
-#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
-#define FTM_SYNCONF_SWSOC_MASK 0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT 12
-#define FTM_SYNCONF_SWSOC_WIDTH 1
-#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
-#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
-#define FTM_SYNCONF_HWRSTCNT_WIDTH 1
-#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
-#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT 17
-#define FTM_SYNCONF_HWWRBUF_WIDTH 1
-#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
-#define FTM_SYNCONF_HWOM_MASK 0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT 18
-#define FTM_SYNCONF_HWOM_WIDTH 1
-#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
-#define FTM_SYNCONF_HWINVC_MASK 0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT 19
-#define FTM_SYNCONF_HWINVC_WIDTH 1
-#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
-#define FTM_SYNCONF_HWSOC_MASK 0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT 20
-#define FTM_SYNCONF_HWSOC_WIDTH 1
-#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK 0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT 0
-#define FTM_INVCTRL_INV0EN_WIDTH 1
-#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
-#define FTM_INVCTRL_INV1EN_MASK 0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT 1
-#define FTM_INVCTRL_INV1EN_WIDTH 1
-#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
-#define FTM_INVCTRL_INV2EN_MASK 0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT 2
-#define FTM_INVCTRL_INV2EN_WIDTH 1
-#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
-#define FTM_INVCTRL_INV3EN_MASK 0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT 3
-#define FTM_INVCTRL_INV3EN_WIDTH 1
-#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK 0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT 0
-#define FTM_SWOCTRL_CH0OC_WIDTH 1
-#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
-#define FTM_SWOCTRL_CH1OC_MASK 0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT 1
-#define FTM_SWOCTRL_CH1OC_WIDTH 1
-#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
-#define FTM_SWOCTRL_CH2OC_MASK 0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT 2
-#define FTM_SWOCTRL_CH2OC_WIDTH 1
-#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
-#define FTM_SWOCTRL_CH3OC_MASK 0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT 3
-#define FTM_SWOCTRL_CH3OC_WIDTH 1
-#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
-#define FTM_SWOCTRL_CH4OC_MASK 0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT 4
-#define FTM_SWOCTRL_CH4OC_WIDTH 1
-#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
-#define FTM_SWOCTRL_CH5OC_MASK 0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT 5
-#define FTM_SWOCTRL_CH5OC_WIDTH 1
-#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
-#define FTM_SWOCTRL_CH6OC_MASK 0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT 6
-#define FTM_SWOCTRL_CH6OC_WIDTH 1
-#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
-#define FTM_SWOCTRL_CH7OC_MASK 0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT 7
-#define FTM_SWOCTRL_CH7OC_WIDTH 1
-#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
-#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT 8
-#define FTM_SWOCTRL_CH0OCV_WIDTH 1
-#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
-#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT 9
-#define FTM_SWOCTRL_CH1OCV_WIDTH 1
-#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
-#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT 10
-#define FTM_SWOCTRL_CH2OCV_WIDTH 1
-#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
-#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT 11
-#define FTM_SWOCTRL_CH3OCV_WIDTH 1
-#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
-#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT 12
-#define FTM_SWOCTRL_CH4OCV_WIDTH 1
-#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
-#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT 13
-#define FTM_SWOCTRL_CH5OCV_WIDTH 1
-#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
-#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT 14
-#define FTM_SWOCTRL_CH6OCV_WIDTH 1
-#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
-#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT 15
-#define FTM_SWOCTRL_CH7OCV_WIDTH 1
-#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT 0
-#define FTM_PWMLOAD_CH0SEL_WIDTH 1
-#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
-#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT 1
-#define FTM_PWMLOAD_CH1SEL_WIDTH 1
-#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
-#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT 2
-#define FTM_PWMLOAD_CH2SEL_WIDTH 1
-#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
-#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT 3
-#define FTM_PWMLOAD_CH3SEL_WIDTH 1
-#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
-#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT 4
-#define FTM_PWMLOAD_CH4SEL_WIDTH 1
-#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
-#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT 5
-#define FTM_PWMLOAD_CH5SEL_WIDTH 1
-#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
-#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT 6
-#define FTM_PWMLOAD_CH6SEL_WIDTH 1
-#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
-#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT 7
-#define FTM_PWMLOAD_CH7SEL_WIDTH 1
-#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
-#define FTM_PWMLOAD_LDOK_MASK 0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT 9
-#define FTM_PWMLOAD_LDOK_WIDTH 1
-#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+/*! @name SC - Status And Control */
+#define FTM_SC_PS_MASK (0x7U)
+#define FTM_SC_PS_SHIFT (0U)
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK (0x18U)
+#define FTM_SC_CLKS_SHIFT (3U)
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK (0x20U)
+#define FTM_SC_CPWMS_SHIFT (5U)
+#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK (0x40U)
+#define FTM_SC_TOIE_SHIFT (6U)
+#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK (0x80U)
+#define FTM_SC_TOF_SHIFT (7U)
+#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+
+/*! @name CNT - Counter */
+#define FTM_CNT_COUNT_MASK (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT (0U)
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define FTM_MOD_MOD_MASK (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT (0U)
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status And Control */
+#define FTM_CnSC_DMA_MASK (0x1U)
+#define FTM_CnSC_DMA_SHIFT (0U)
+#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ICRST_MASK (0x2U)
+#define FTM_CnSC_ICRST_SHIFT (1U)
+#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
+#define FTM_CnSC_ELSA_MASK (0x4U)
+#define FTM_CnSC_ELSA_SHIFT (2U)
+#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK (0x8U)
+#define FTM_CnSC_ELSB_SHIFT (3U)
+#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK (0x10U)
+#define FTM_CnSC_MSA_SHIFT (4U)
+#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK (0x20U)
+#define FTM_CnSC_MSB_SHIFT (5U)
+#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK (0x40U)
+#define FTM_CnSC_CHIE_SHIFT (6U)
+#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK (0x80U)
+#define FTM_CnSC_CHF_SHIFT (7U)
+#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT (8U)
+
+/*! @name CnV - Channel (n) Value */
+#define FTM_CnV_VAL_MASK (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT (0U)
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+#define FTM_CNTIN_INIT_MASK (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT (0U)
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+
+/*! @name STATUS - Capture And Compare Status */
+#define FTM_STATUS_CH0F_MASK (0x1U)
+#define FTM_STATUS_CH0F_SHIFT (0U)
+#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK (0x2U)
+#define FTM_STATUS_CH1F_SHIFT (1U)
+#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK (0x4U)
+#define FTM_STATUS_CH2F_SHIFT (2U)
+#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK (0x8U)
+#define FTM_STATUS_CH3F_SHIFT (3U)
+#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK (0x10U)
+#define FTM_STATUS_CH4F_SHIFT (4U)
+#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK (0x20U)
+#define FTM_STATUS_CH5F_SHIFT (5U)
+#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK (0x40U)
+#define FTM_STATUS_CH6F_SHIFT (6U)
+#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK (0x80U)
+#define FTM_STATUS_CH7F_SHIFT (7U)
+#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+
+/*! @name MODE - Features Mode Selection */
+#define FTM_MODE_FTMEN_MASK (0x1U)
+#define FTM_MODE_FTMEN_SHIFT (0U)
+#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK (0x2U)
+#define FTM_MODE_INIT_SHIFT (1U)
+#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK (0x4U)
+#define FTM_MODE_WPDIS_SHIFT (2U)
+#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK (0x8U)
+#define FTM_MODE_PWMSYNC_SHIFT (3U)
+#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK (0x10U)
+#define FTM_MODE_CAPTEST_SHIFT (4U)
+#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK (0x60U)
+#define FTM_MODE_FAULTM_SHIFT (5U)
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK (0x80U)
+#define FTM_MODE_FAULTIE_SHIFT (7U)
+#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+
+/*! @name SYNC - Synchronization */
+#define FTM_SYNC_CNTMIN_MASK (0x1U)
+#define FTM_SYNC_CNTMIN_SHIFT (0U)
+#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK (0x2U)
+#define FTM_SYNC_CNTMAX_SHIFT (1U)
+#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK (0x4U)
+#define FTM_SYNC_REINIT_SHIFT (2U)
+#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK (0x8U)
+#define FTM_SYNC_SYNCHOM_SHIFT (3U)
+#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK (0x10U)
+#define FTM_SYNC_TRIG0_SHIFT (4U)
+#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK (0x20U)
+#define FTM_SYNC_TRIG1_SHIFT (5U)
+#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK (0x40U)
+#define FTM_SYNC_TRIG2_SHIFT (6U)
+#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK (0x80U)
+#define FTM_SYNC_SWSYNC_SHIFT (7U)
+#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+
+/*! @name OUTINIT - Initial State For Channels Output */
+#define FTM_OUTINIT_CH0OI_MASK (0x1U)
+#define FTM_OUTINIT_CH0OI_SHIFT (0U)
+#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK (0x2U)
+#define FTM_OUTINIT_CH1OI_SHIFT (1U)
+#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK (0x4U)
+#define FTM_OUTINIT_CH2OI_SHIFT (2U)
+#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK (0x8U)
+#define FTM_OUTINIT_CH3OI_SHIFT (3U)
+#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK (0x10U)
+#define FTM_OUTINIT_CH4OI_SHIFT (4U)
+#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK (0x20U)
+#define FTM_OUTINIT_CH5OI_SHIFT (5U)
+#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK (0x40U)
+#define FTM_OUTINIT_CH6OI_SHIFT (6U)
+#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK (0x80U)
+#define FTM_OUTINIT_CH7OI_SHIFT (7U)
+#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+
+/*! @name OUTMASK - Output Mask */
+#define FTM_OUTMASK_CH0OM_MASK (0x1U)
+#define FTM_OUTMASK_CH0OM_SHIFT (0U)
+#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK (0x2U)
+#define FTM_OUTMASK_CH1OM_SHIFT (1U)
+#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK (0x4U)
+#define FTM_OUTMASK_CH2OM_SHIFT (2U)
+#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK (0x8U)
+#define FTM_OUTMASK_CH3OM_SHIFT (3U)
+#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK (0x10U)
+#define FTM_OUTMASK_CH4OM_SHIFT (4U)
+#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK (0x20U)
+#define FTM_OUTMASK_CH5OM_SHIFT (5U)
+#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK (0x40U)
+#define FTM_OUTMASK_CH6OM_SHIFT (6U)
+#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK (0x80U)
+#define FTM_OUTMASK_CH7OM_SHIFT (7U)
+#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+
+/*! @name COMBINE - Function For Linked Channels */
+#define FTM_COMBINE_COMBINE0_MASK (0x1U)
+#define FTM_COMBINE_COMBINE0_SHIFT (0U)
+#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK (0x2U)
+#define FTM_COMBINE_COMP0_SHIFT (1U)
+#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
+#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
+#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK (0x8U)
+#define FTM_COMBINE_DECAP0_SHIFT (3U)
+#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK (0x10U)
+#define FTM_COMBINE_DTEN0_SHIFT (4U)
+#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
+#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
+#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
+#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
+#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK (0x100U)
+#define FTM_COMBINE_COMBINE1_SHIFT (8U)
+#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK (0x200U)
+#define FTM_COMBINE_COMP1_SHIFT (9U)
+#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
+#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
+#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK (0x800U)
+#define FTM_COMBINE_DECAP1_SHIFT (11U)
+#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK (0x1000U)
+#define FTM_COMBINE_DTEN1_SHIFT (12U)
+#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
+#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
+#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
+#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
+#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
+#define FTM_COMBINE_COMBINE2_SHIFT (16U)
+#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK (0x20000U)
+#define FTM_COMBINE_COMP2_SHIFT (17U)
+#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
+#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
+#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK (0x80000U)
+#define FTM_COMBINE_DECAP2_SHIFT (19U)
+#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK (0x100000U)
+#define FTM_COMBINE_DTEN2_SHIFT (20U)
+#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
+#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
+#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
+#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
+#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
+#define FTM_COMBINE_COMBINE3_SHIFT (24U)
+#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK (0x2000000U)
+#define FTM_COMBINE_COMP3_SHIFT (25U)
+#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
+#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
+#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
+#define FTM_COMBINE_DECAP3_SHIFT (27U)
+#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
+#define FTM_COMBINE_DTEN3_SHIFT (28U)
+#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
+#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
+#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
+#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
+#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT (0U)
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT (6U)
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+
+/*! @name EXTTRIG - FTM External Trigger */
+#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
+#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
+#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
+#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
+#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
+#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
+#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
+#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
+#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
+#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
+#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
+#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
+#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
+#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
+#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
+#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+
+/*! @name POL - Channels Polarity */
+#define FTM_POL_POL0_MASK (0x1U)
+#define FTM_POL_POL0_SHIFT (0U)
+#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK (0x2U)
+#define FTM_POL_POL1_SHIFT (1U)
+#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK (0x4U)
+#define FTM_POL_POL2_SHIFT (2U)
+#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK (0x8U)
+#define FTM_POL_POL3_SHIFT (3U)
+#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK (0x10U)
+#define FTM_POL_POL4_SHIFT (4U)
+#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK (0x20U)
+#define FTM_POL_POL5_SHIFT (5U)
+#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK (0x40U)
+#define FTM_POL_POL6_SHIFT (6U)
+#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK (0x80U)
+#define FTM_POL_POL7_SHIFT (7U)
+#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+
+/*! @name FMS - Fault Mode Status */
+#define FTM_FMS_FAULTF0_MASK (0x1U)
+#define FTM_FMS_FAULTF0_SHIFT (0U)
+#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK (0x2U)
+#define FTM_FMS_FAULTF1_SHIFT (1U)
+#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK (0x4U)
+#define FTM_FMS_FAULTF2_SHIFT (2U)
+#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK (0x8U)
+#define FTM_FMS_FAULTF3_SHIFT (3U)
+#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK (0x20U)
+#define FTM_FMS_FAULTIN_SHIFT (5U)
+#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK (0x40U)
+#define FTM_FMS_WPEN_SHIFT (6U)
+#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK (0x80U)
+#define FTM_FMS_FAULTF_SHIFT (7U)
+#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+
+/*! @name FILTER - Input Capture Filter Control */
+#define FTM_FILTER_CH0FVAL_MASK (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT (0U)
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT (4U)
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT (8U)
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT (12U)
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+
+/*! @name FLTCTRL - Fault Control */
+#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
+#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
+#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
+#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
+#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
+#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
+#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
+#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
+#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
+#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
+#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
+#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
+#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control And Status */
+#define FTM_QDCTRL_QUADEN_MASK (0x1U)
+#define FTM_QDCTRL_QUADEN_SHIFT (0U)
+#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
+#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
+#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK (0x4U)
+#define FTM_QDCTRL_QUADIR_SHIFT (2U)
+#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
+#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
+#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
+#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
+#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
+#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
+#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
+#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
+#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
+#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
+#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+
+/*! @name CONF - Configuration */
+#define FTM_CONF_NUMTOF_MASK (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT (0U)
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT (6U)
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK (0x200U)
+#define FTM_CONF_GTBEEN_SHIFT (9U)
+#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK (0x400U)
+#define FTM_CONF_GTBEOUT_SHIFT (10U)
+#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
+#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
+#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
+#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
+#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
+#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
+#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
+#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
+#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+
+/*! @name SYNCONF - Synchronization Configuration */
+#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
+#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK (0x4U)
+#define FTM_SYNCONF_CNTINC_SHIFT (2U)
+#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK (0x10U)
+#define FTM_SYNCONF_INVC_SHIFT (4U)
+#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK (0x20U)
+#define FTM_SYNCONF_SWOC_SHIFT (5U)
+#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
+#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
+#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
+#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
+#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
+#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
+#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK (0x400U)
+#define FTM_SYNCONF_SWOM_SHIFT (10U)
+#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK (0x800U)
+#define FTM_SYNCONF_SWINVC_SHIFT (11U)
+#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
+#define FTM_SYNCONF_SWSOC_SHIFT (12U)
+#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
+#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
+#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
+#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
+#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK (0x40000U)
+#define FTM_SYNCONF_HWOM_SHIFT (18U)
+#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
+#define FTM_SYNCONF_HWINVC_SHIFT (19U)
+#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
+#define FTM_SYNCONF_HWSOC_SHIFT (20U)
+#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+
+/*! @name INVCTRL - FTM Inverting Control */
+#define FTM_INVCTRL_INV0EN_MASK (0x1U)
+#define FTM_INVCTRL_INV0EN_SHIFT (0U)
+#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK (0x2U)
+#define FTM_INVCTRL_INV1EN_SHIFT (1U)
+#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK (0x4U)
+#define FTM_INVCTRL_INV2EN_SHIFT (2U)
+#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK (0x8U)
+#define FTM_INVCTRL_INV3EN_SHIFT (3U)
+#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+
+/*! @name SWOCTRL - FTM Software Output Control */
+#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
+#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
+#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
+#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
+#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
+#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
+#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
+#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
+#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
+#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
+#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
+#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
+#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
+#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
+#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
+#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
+#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
+#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
+#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
+#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
+#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
+#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
+#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
+#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
+#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
+#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
+#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
+#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
+#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
+#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
+#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
+#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
+#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+
+/*! @name PWMLOAD - FTM PWM Load */
+#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
+#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
+#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
+#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
+#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
+#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
+#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
+#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
+#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
+#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
+#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
+#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
+#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
+#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
+#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
+#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
+#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK (0x200U)
+#define FTM_PWMLOAD_LDOK_SHIFT (9U)
+#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+
/*!
* @}
@@ -4793,17 +3390,14 @@ typedef struct {
#define FTM0_BASE (0x40038000u)
/** Peripheral FTM0 base pointer */
#define FTM0 ((FTM_Type *)FTM0_BASE)
-#define FTM0_BASE_PTR (FTM0)
/** Peripheral FTM1 base address */
#define FTM1_BASE (0x40039000u)
/** Peripheral FTM1 base pointer */
#define FTM1 ((FTM_Type *)FTM1_BASE)
-#define FTM1_BASE_PTR (FTM1)
/** Peripheral FTM2 base address */
#define FTM2_BASE (0x4003A000u)
/** Peripheral FTM2 base pointer */
#define FTM2 ((FTM_Type *)FTM2_BASE)
-#define FTM2_BASE_PTR (FTM2)
/** Array initializer of FTM peripheral base addresses */
#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE }
/** Array initializer of FTM peripheral base pointers */
@@ -4811,127 +3405,6 @@ typedef struct {
/** Interrupt vectors for the FTM peripheral type */
#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register instance definitions */
-/* FTM0 */
-#define FTM0_SC FTM_SC_REG(FTM0)
-#define FTM0_CNT FTM_CNT_REG(FTM0)
-#define FTM0_MOD FTM_MOD_REG(FTM0)
-#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
-#define FTM0_C0V FTM_CnV_REG(FTM0,0)
-#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
-#define FTM0_C1V FTM_CnV_REG(FTM0,1)
-#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
-#define FTM0_C2V FTM_CnV_REG(FTM0,2)
-#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
-#define FTM0_C3V FTM_CnV_REG(FTM0,3)
-#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
-#define FTM0_C4V FTM_CnV_REG(FTM0,4)
-#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
-#define FTM0_C5V FTM_CnV_REG(FTM0,5)
-#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
-#define FTM0_C6V FTM_CnV_REG(FTM0,6)
-#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
-#define FTM0_C7V FTM_CnV_REG(FTM0,7)
-#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
-#define FTM0_STATUS FTM_STATUS_REG(FTM0)
-#define FTM0_MODE FTM_MODE_REG(FTM0)
-#define FTM0_SYNC FTM_SYNC_REG(FTM0)
-#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
-#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
-#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
-#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
-#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
-#define FTM0_POL FTM_POL_REG(FTM0)
-#define FTM0_FMS FTM_FMS_REG(FTM0)
-#define FTM0_FILTER FTM_FILTER_REG(FTM0)
-#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
-#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
-#define FTM0_CONF FTM_CONF_REG(FTM0)
-#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
-#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
-#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
-#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
-#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
-/* FTM1 */
-#define FTM1_SC FTM_SC_REG(FTM1)
-#define FTM1_CNT FTM_CNT_REG(FTM1)
-#define FTM1_MOD FTM_MOD_REG(FTM1)
-#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
-#define FTM1_C0V FTM_CnV_REG(FTM1,0)
-#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
-#define FTM1_C1V FTM_CnV_REG(FTM1,1)
-#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
-#define FTM1_STATUS FTM_STATUS_REG(FTM1)
-#define FTM1_MODE FTM_MODE_REG(FTM1)
-#define FTM1_SYNC FTM_SYNC_REG(FTM1)
-#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
-#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
-#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
-#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
-#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
-#define FTM1_POL FTM_POL_REG(FTM1)
-#define FTM1_FMS FTM_FMS_REG(FTM1)
-#define FTM1_FILTER FTM_FILTER_REG(FTM1)
-#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
-#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
-#define FTM1_CONF FTM_CONF_REG(FTM1)
-#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
-#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
-#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
-#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
-#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
-/* FTM2 */
-#define FTM2_SC FTM_SC_REG(FTM2)
-#define FTM2_CNT FTM_CNT_REG(FTM2)
-#define FTM2_MOD FTM_MOD_REG(FTM2)
-#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
-#define FTM2_C0V FTM_CnV_REG(FTM2,0)
-#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
-#define FTM2_C1V FTM_CnV_REG(FTM2,1)
-#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
-#define FTM2_STATUS FTM_STATUS_REG(FTM2)
-#define FTM2_MODE FTM_MODE_REG(FTM2)
-#define FTM2_SYNC FTM_SYNC_REG(FTM2)
-#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
-#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
-#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
-#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
-#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
-#define FTM2_POL FTM_POL_REG(FTM2)
-#define FTM2_FMS FTM_FMS_REG(FTM2)
-#define FTM2_FILTER FTM_FILTER_REG(FTM2)
-#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
-#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
-#define FTM2_CONF FTM_CONF_REG(FTM2)
-#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
-#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
-#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
-#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
-#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
-
-/* FTM - Register array accessors */
-#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
-#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
-#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
-#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
-#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
-#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FTM_Peripheral_Access_Layer */
@@ -4954,70 +3427,47 @@ typedef struct {
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type, *GPIO_MemMapPtr;
+} GPIO_Type;
/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
+ -- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT (0U)
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
-/* GPIO - Register accessors */
-#define GPIO_PDOR_REG(base) ((base)->PDOR)
-#define GPIO_PSOR_REG(base) ((base)->PSOR)
-#define GPIO_PCOR_REG(base) ((base)->PCOR)
-#define GPIO_PTOR_REG(base) ((base)->PTOR)
-#define GPIO_PDIR_REG(base) ((base)->PDIR)
-#define GPIO_PDDR_REG(base) ((base)->PDDR)
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT (0U)
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT (0U)
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT (0U)
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT (0U)
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT (0U)
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO_WIDTH 32
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO_WIDTH 32
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO_WIDTH 32
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO_WIDTH 32
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI_WIDTH 32
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD_WIDTH 32
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/*!
* @}
@@ -5025,87 +3475,30 @@ typedef struct {
/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-#define PTA_BASE_PTR (PTA)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-#define PTB_BASE_PTR (PTB)
-/** Peripheral PTC base address */
-#define PTC_BASE (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC ((GPIO_Type *)PTC_BASE)
-#define PTC_BASE_PTR (PTC)
-/** Peripheral PTD base address */
-#define PTD_BASE (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD ((GPIO_Type *)PTD_BASE)
-#define PTD_BASE_PTR (PTD)
-/** Peripheral PTE base address */
-#define PTE_BASE (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE ((GPIO_Type *)PTE_BASE)
-#define PTE_BASE_PTR (PTE)
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE ((GPIO_Type *)GPIOE_BASE)
/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
-
-/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register instance definitions */
-/* PTA */
-#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
-#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
-#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
-#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
-#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
-#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
-/* PTB */
-#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
-#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
-#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
-#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
-#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
-#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
-/* PTC */
-#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
-#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
-#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
-#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
-#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
-#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
-/* PTD */
-#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
-#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
-#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
-#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
-#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
-#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
-/* PTE */
-#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
-#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
-#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
-#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
-#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
-#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
+#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
/*!
* @}
@@ -5135,36 +3528,7 @@ typedef struct {
__IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
__IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
__IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type, *I2C_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register accessors */
-#define I2C_A1_REG(base) ((base)->A1)
-#define I2C_F_REG(base) ((base)->F)
-#define I2C_C1_REG(base) ((base)->C1)
-#define I2C_S_REG(base) ((base)->S)
-#define I2C_D_REG(base) ((base)->D)
-#define I2C_C2_REG(base) ((base)->C2)
-#define I2C_FLT_REG(base) ((base)->FLT)
-#define I2C_RA_REG(base) ((base)->RA)
-#define I2C_SMB_REG(base) ((base)->SMB)
-#define I2C_A2_REG(base) ((base)->A2)
-#define I2C_SLTH_REG(base) ((base)->SLTH)
-#define I2C_SLTL_REG(base) ((base)->SLTL)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
+} I2C_Type;
/* ----------------------------------------------------------------------------
-- I2C Register Masks
@@ -5175,190 +3539,159 @@ typedef struct {
* @{
*/
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD_WIDTH 7
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR_WIDTH 6
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT_WIDTH 2
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_DMAEN_WIDTH 1
-#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_WUEN_WIDTH 1
-#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_RSTA_WIDTH 1
-#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TXAK_WIDTH 1
-#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_TX_WIDTH 1
-#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_MST_WIDTH 1
-#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICIE_WIDTH 1
-#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-#define I2C_C1_IICEN_WIDTH 1
-#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_RXAK_WIDTH 1
-#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_IICIF_WIDTH 1
-#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_SRW_WIDTH 1
-#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_RAM_WIDTH 1
-#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_ARBL_WIDTH 1
-#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_BUSY_WIDTH 1
-#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_IAAS_WIDTH 1
-#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-#define I2C_S_TCF_WIDTH 1
-#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA_WIDTH 8
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD_WIDTH 3
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_RMEN_WIDTH 1
-#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_SBRC_WIDTH 1
-#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_HDRS_WIDTH 1
-#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_ADEXT_WIDTH 1
-#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-#define I2C_C2_GCAEN_WIDTH 1
-#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0xFu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT_WIDTH 4
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STARTF_MASK 0x10u
-#define I2C_FLT_STARTF_SHIFT 4
-#define I2C_FLT_STARTF_WIDTH 1
-#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
-#define I2C_FLT_SSIE_MASK 0x20u
-#define I2C_FLT_SSIE_SHIFT 5
-#define I2C_FLT_SSIE_WIDTH 1
-#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
-#define I2C_FLT_STOPF_MASK 0x40u
-#define I2C_FLT_STOPF_SHIFT 6
-#define I2C_FLT_STOPF_WIDTH 1
-#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
-#define I2C_FLT_SHEN_MASK 0x80u
-#define I2C_FLT_SHEN_SHIFT 7
-#define I2C_FLT_SHEN_WIDTH 1
-#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD_WIDTH 7
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2IE_WIDTH 1
-#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF2_WIDTH 1
-#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SHTF1_WIDTH 1
-#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_SLTF_WIDTH 1
-#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_TCKSEL_WIDTH 1
-#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_SIICAEN_WIDTH 1
-#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_ALERTEN_WIDTH 1
-#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-#define I2C_SMB_FACK_WIDTH 1
-#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD_WIDTH 7
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT_WIDTH 8
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT_WIDTH 8
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK (0xFEU)
+#define I2C_A1_AD_SHIFT (1U)
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK (0x3FU)
+#define I2C_F_ICR_SHIFT (0U)
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK (0xC0U)
+#define I2C_F_MULT_SHIFT (6U)
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK (0x1U)
+#define I2C_C1_DMAEN_SHIFT (0U)
+#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK (0x2U)
+#define I2C_C1_WUEN_SHIFT (1U)
+#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK (0x4U)
+#define I2C_C1_RSTA_SHIFT (2U)
+#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK (0x8U)
+#define I2C_C1_TXAK_SHIFT (3U)
+#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK (0x10U)
+#define I2C_C1_TX_SHIFT (4U)
+#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK (0x20U)
+#define I2C_C1_MST_SHIFT (5U)
+#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK (0x40U)
+#define I2C_C1_IICIE_SHIFT (6U)
+#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK (0x80U)
+#define I2C_C1_IICEN_SHIFT (7U)
+#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK (0x1U)
+#define I2C_S_RXAK_SHIFT (0U)
+#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK (0x2U)
+#define I2C_S_IICIF_SHIFT (1U)
+#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK (0x4U)
+#define I2C_S_SRW_SHIFT (2U)
+#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK (0x8U)
+#define I2C_S_RAM_SHIFT (3U)
+#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK (0x10U)
+#define I2C_S_ARBL_SHIFT (4U)
+#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK (0x20U)
+#define I2C_S_BUSY_SHIFT (5U)
+#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK (0x40U)
+#define I2C_S_IAAS_SHIFT (6U)
+#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK (0x80U)
+#define I2C_S_TCF_SHIFT (7U)
+#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK (0xFFU)
+#define I2C_D_DATA_SHIFT (0U)
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK (0x7U)
+#define I2C_C2_AD_SHIFT (0U)
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK (0x8U)
+#define I2C_C2_RMEN_SHIFT (3U)
+#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK (0x10U)
+#define I2C_C2_SBRC_SHIFT (4U)
+#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK (0x20U)
+#define I2C_C2_HDRS_SHIFT (5U)
+#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK (0x40U)
+#define I2C_C2_ADEXT_SHIFT (6U)
+#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK (0x80U)
+#define I2C_C2_GCAEN_SHIFT (7U)
+#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter register */
+#define I2C_FLT_FLT_MASK (0xFU)
+#define I2C_FLT_FLT_SHIFT (0U)
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK (0x10U)
+#define I2C_FLT_STARTF_SHIFT (4U)
+#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK (0x20U)
+#define I2C_FLT_SSIE_SHIFT (5U)
+#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK (0x40U)
+#define I2C_FLT_STOPF_SHIFT (6U)
+#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK (0x80U)
+#define I2C_FLT_SHEN_SHIFT (7U)
+#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK (0xFEU)
+#define I2C_RA_RAD_SHIFT (1U)
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT (0U)
+#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK (0x2U)
+#define I2C_SMB_SHTF2_SHIFT (1U)
+#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK (0x4U)
+#define I2C_SMB_SHTF1_SHIFT (2U)
+#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK (0x8U)
+#define I2C_SMB_SLTF_SHIFT (3U)
+#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT (4U)
+#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT (5U)
+#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT (6U)
+#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK (0x80U)
+#define I2C_SMB_FACK_SHIFT (7U)
+#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK (0xFEU)
+#define I2C_A2_SAD_SHIFT (1U)
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT (0U)
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT (0U)
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
/*!
* @}
@@ -5370,12 +3703,10 @@ typedef struct {
#define I2C0_BASE (0x40066000u)
/** Peripheral I2C0 base pointer */
#define I2C0 ((I2C_Type *)I2C0_BASE)
-#define I2C0_BASE_PTR (I2C0)
/** Peripheral I2C1 base address */
#define I2C1_BASE (0x40067000u)
/** Peripheral I2C1 base pointer */
#define I2C1 ((I2C_Type *)I2C1_BASE)
-#define I2C1_BASE_PTR (I2C1)
/** Array initializer of I2C peripheral base addresses */
#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
/** Array initializer of I2C peripheral base pointers */
@@ -5383,49 +3714,6 @@ typedef struct {
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register instance definitions */
-/* I2C0 */
-#define I2C0_A1 I2C_A1_REG(I2C0)
-#define I2C0_F I2C_F_REG(I2C0)
-#define I2C0_C1 I2C_C1_REG(I2C0)
-#define I2C0_S I2C_S_REG(I2C0)
-#define I2C0_D I2C_D_REG(I2C0)
-#define I2C0_C2 I2C_C2_REG(I2C0)
-#define I2C0_FLT I2C_FLT_REG(I2C0)
-#define I2C0_RA I2C_RA_REG(I2C0)
-#define I2C0_SMB I2C_SMB_REG(I2C0)
-#define I2C0_A2 I2C_A2_REG(I2C0)
-#define I2C0_SLTH I2C_SLTH_REG(I2C0)
-#define I2C0_SLTL I2C_SLTL_REG(I2C0)
-/* I2C1 */
-#define I2C1_A1 I2C_A1_REG(I2C1)
-#define I2C1_F I2C_F_REG(I2C1)
-#define I2C1_C1 I2C_C1_REG(I2C1)
-#define I2C1_S I2C_S_REG(I2C1)
-#define I2C1_D I2C_D_REG(I2C1)
-#define I2C1_C2 I2C_C2_REG(I2C1)
-#define I2C1_FLT I2C_FLT_REG(I2C1)
-#define I2C1_RA I2C_RA_REG(I2C1)
-#define I2C1_SMB I2C_SMB_REG(I2C1)
-#define I2C1_A2 I2C_A2_REG(I2C1)
-#define I2C1_SLTH I2C_SLTH_REG(I2C1)
-#define I2C1_SLTL I2C_SLTL_REG(I2C1)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
@@ -5470,48 +3758,7 @@ typedef struct {
uint8_t RESERVED_7[28];
__IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
__IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
-} I2S_Type, *I2S_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register accessors */
-#define I2S_TCSR_REG(base) ((base)->TCSR)
-#define I2S_TCR1_REG(base) ((base)->TCR1)
-#define I2S_TCR2_REG(base) ((base)->TCR2)
-#define I2S_TCR3_REG(base) ((base)->TCR3)
-#define I2S_TCR4_REG(base) ((base)->TCR4)
-#define I2S_TCR5_REG(base) ((base)->TCR5)
-#define I2S_TDR_REG(base,index) ((base)->TDR[index])
-#define I2S_TDR_COUNT 1
-#define I2S_TFR_REG(base,index) ((base)->TFR[index])
-#define I2S_TFR_COUNT 1
-#define I2S_TMR_REG(base) ((base)->TMR)
-#define I2S_RCSR_REG(base) ((base)->RCSR)
-#define I2S_RCR1_REG(base) ((base)->RCR1)
-#define I2S_RCR2_REG(base) ((base)->RCR2)
-#define I2S_RCR3_REG(base) ((base)->RCR3)
-#define I2S_RCR4_REG(base) ((base)->RCR4)
-#define I2S_RCR5_REG(base) ((base)->RCR5)
-#define I2S_RDR_REG(base,index) ((base)->RDR[index])
-#define I2S_RDR_COUNT 1
-#define I2S_RFR_REG(base,index) ((base)->RFR[index])
-#define I2S_RFR_COUNT 1
-#define I2S_RMR_REG(base) ((base)->RMR)
-#define I2S_MCR_REG(base) ((base)->MCR)
-#define I2S_MDR_REG(base) ((base)->MDR)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
+} I2S_Type;
/* ----------------------------------------------------------------------------
-- I2S Register Masks
@@ -5522,398 +3769,337 @@ typedef struct {
* @{
*/
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK 0x1u
-#define I2S_TCSR_FRDE_SHIFT 0
-#define I2S_TCSR_FRDE_WIDTH 1
-#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
-#define I2S_TCSR_FWDE_MASK 0x2u
-#define I2S_TCSR_FWDE_SHIFT 1
-#define I2S_TCSR_FWDE_WIDTH 1
-#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
-#define I2S_TCSR_FRIE_MASK 0x100u
-#define I2S_TCSR_FRIE_SHIFT 8
-#define I2S_TCSR_FRIE_WIDTH 1
-#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
-#define I2S_TCSR_FWIE_MASK 0x200u
-#define I2S_TCSR_FWIE_SHIFT 9
-#define I2S_TCSR_FWIE_WIDTH 1
-#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
-#define I2S_TCSR_FEIE_MASK 0x400u
-#define I2S_TCSR_FEIE_SHIFT 10
-#define I2S_TCSR_FEIE_WIDTH 1
-#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
-#define I2S_TCSR_SEIE_MASK 0x800u
-#define I2S_TCSR_SEIE_SHIFT 11
-#define I2S_TCSR_SEIE_WIDTH 1
-#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
-#define I2S_TCSR_WSIE_MASK 0x1000u
-#define I2S_TCSR_WSIE_SHIFT 12
-#define I2S_TCSR_WSIE_WIDTH 1
-#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
-#define I2S_TCSR_FRF_MASK 0x10000u
-#define I2S_TCSR_FRF_SHIFT 16
-#define I2S_TCSR_FRF_WIDTH 1
-#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
-#define I2S_TCSR_FWF_MASK 0x20000u
-#define I2S_TCSR_FWF_SHIFT 17
-#define I2S_TCSR_FWF_WIDTH 1
-#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
-#define I2S_TCSR_FEF_MASK 0x40000u
-#define I2S_TCSR_FEF_SHIFT 18
-#define I2S_TCSR_FEF_WIDTH 1
-#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
-#define I2S_TCSR_SEF_MASK 0x80000u
-#define I2S_TCSR_SEF_SHIFT 19
-#define I2S_TCSR_SEF_WIDTH 1
-#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
-#define I2S_TCSR_WSF_MASK 0x100000u
-#define I2S_TCSR_WSF_SHIFT 20
-#define I2S_TCSR_WSF_WIDTH 1
-#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
-#define I2S_TCSR_SR_MASK 0x1000000u
-#define I2S_TCSR_SR_SHIFT 24
-#define I2S_TCSR_SR_WIDTH 1
-#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
-#define I2S_TCSR_FR_MASK 0x2000000u
-#define I2S_TCSR_FR_SHIFT 25
-#define I2S_TCSR_FR_WIDTH 1
-#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
-#define I2S_TCSR_BCE_MASK 0x10000000u
-#define I2S_TCSR_BCE_SHIFT 28
-#define I2S_TCSR_BCE_WIDTH 1
-#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
-#define I2S_TCSR_DBGE_MASK 0x20000000u
-#define I2S_TCSR_DBGE_SHIFT 29
-#define I2S_TCSR_DBGE_WIDTH 1
-#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
-#define I2S_TCSR_STOPE_MASK 0x40000000u
-#define I2S_TCSR_STOPE_SHIFT 30
-#define I2S_TCSR_STOPE_WIDTH 1
-#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
-#define I2S_TCSR_TE_MASK 0x80000000u
-#define I2S_TCSR_TE_SHIFT 31
-#define I2S_TCSR_TE_WIDTH 1
-#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK 0x7u
-#define I2S_TCR1_TFW_SHIFT 0
-#define I2S_TCR1_TFW_WIDTH 3
-#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK 0xFFu
-#define I2S_TCR2_DIV_SHIFT 0
-#define I2S_TCR2_DIV_WIDTH 8
-#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK 0x1000000u
-#define I2S_TCR2_BCD_SHIFT 24
-#define I2S_TCR2_BCD_WIDTH 1
-#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
-#define I2S_TCR2_BCP_MASK 0x2000000u
-#define I2S_TCR2_BCP_SHIFT 25
-#define I2S_TCR2_BCP_WIDTH 1
-#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
-#define I2S_TCR2_MSEL_MASK 0xC000000u
-#define I2S_TCR2_MSEL_SHIFT 26
-#define I2S_TCR2_MSEL_WIDTH 2
-#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK 0x10000000u
-#define I2S_TCR2_BCI_SHIFT 28
-#define I2S_TCR2_BCI_WIDTH 1
-#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
-#define I2S_TCR2_BCS_MASK 0x20000000u
-#define I2S_TCR2_BCS_SHIFT 29
-#define I2S_TCR2_BCS_WIDTH 1
-#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
-#define I2S_TCR2_SYNC_MASK 0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT 30
-#define I2S_TCR2_SYNC_WIDTH 2
-#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK 0xFu
-#define I2S_TCR3_WDFL_SHIFT 0
-#define I2S_TCR3_WDFL_WIDTH 4
-#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK 0x10000u
-#define I2S_TCR3_TCE_SHIFT 16
-#define I2S_TCR3_TCE_WIDTH 1
-#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK 0x1u
-#define I2S_TCR4_FSD_SHIFT 0
-#define I2S_TCR4_FSD_WIDTH 1
-#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
-#define I2S_TCR4_FSP_MASK 0x2u
-#define I2S_TCR4_FSP_SHIFT 1
-#define I2S_TCR4_FSP_WIDTH 1
-#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
-#define I2S_TCR4_ONDEM_MASK 0x4u
-#define I2S_TCR4_ONDEM_SHIFT 2
-#define I2S_TCR4_ONDEM_WIDTH 1
-#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_ONDEM_SHIFT))&I2S_TCR4_ONDEM_MASK)
-#define I2S_TCR4_FSE_MASK 0x8u
-#define I2S_TCR4_FSE_SHIFT 3
-#define I2S_TCR4_FSE_WIDTH 1
-#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
-#define I2S_TCR4_MF_MASK 0x10u
-#define I2S_TCR4_MF_SHIFT 4
-#define I2S_TCR4_MF_WIDTH 1
-#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
-#define I2S_TCR4_SYWD_MASK 0x1F00u
-#define I2S_TCR4_SYWD_SHIFT 8
-#define I2S_TCR4_SYWD_WIDTH 5
-#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK 0xF0000u
-#define I2S_TCR4_FRSZ_SHIFT 16
-#define I2S_TCR4_FRSZ_WIDTH 4
-#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-#define I2S_TCR4_FPACK_MASK 0x3000000u
-#define I2S_TCR4_FPACK_SHIFT 24
-#define I2S_TCR4_FPACK_WIDTH 2
-#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
-#define I2S_TCR4_FCONT_MASK 0x10000000u
-#define I2S_TCR4_FCONT_SHIFT 28
-#define I2S_TCR4_FCONT_WIDTH 1
-#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FCONT_SHIFT))&I2S_TCR4_FCONT_MASK)
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK 0x1F00u
-#define I2S_TCR5_FBT_SHIFT 8
-#define I2S_TCR5_FBT_WIDTH 5
-#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK 0x1F0000u
-#define I2S_TCR5_W0W_SHIFT 16
-#define I2S_TCR5_W0W_WIDTH 5
-#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK 0x1F000000u
-#define I2S_TCR5_WNW_SHIFT 24
-#define I2S_TCR5_WNW_WIDTH 5
-#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT 0
-#define I2S_TDR_TDR_WIDTH 32
-#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK 0xFu
-#define I2S_TFR_RFP_SHIFT 0
-#define I2S_TFR_RFP_WIDTH 4
-#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK 0xF0000u
-#define I2S_TFR_WFP_SHIFT 16
-#define I2S_TFR_WFP_WIDTH 4
-#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK 0xFFFFu
-#define I2S_TMR_TWM_SHIFT 0
-#define I2S_TMR_TWM_WIDTH 16
-#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK 0x1u
-#define I2S_RCSR_FRDE_SHIFT 0
-#define I2S_RCSR_FRDE_WIDTH 1
-#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
-#define I2S_RCSR_FWDE_MASK 0x2u
-#define I2S_RCSR_FWDE_SHIFT 1
-#define I2S_RCSR_FWDE_WIDTH 1
-#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
-#define I2S_RCSR_FRIE_MASK 0x100u
-#define I2S_RCSR_FRIE_SHIFT 8
-#define I2S_RCSR_FRIE_WIDTH 1
-#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
-#define I2S_RCSR_FWIE_MASK 0x200u
-#define I2S_RCSR_FWIE_SHIFT 9
-#define I2S_RCSR_FWIE_WIDTH 1
-#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
-#define I2S_RCSR_FEIE_MASK 0x400u
-#define I2S_RCSR_FEIE_SHIFT 10
-#define I2S_RCSR_FEIE_WIDTH 1
-#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
-#define I2S_RCSR_SEIE_MASK 0x800u
-#define I2S_RCSR_SEIE_SHIFT 11
-#define I2S_RCSR_SEIE_WIDTH 1
-#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
-#define I2S_RCSR_WSIE_MASK 0x1000u
-#define I2S_RCSR_WSIE_SHIFT 12
-#define I2S_RCSR_WSIE_WIDTH 1
-#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
-#define I2S_RCSR_FRF_MASK 0x10000u
-#define I2S_RCSR_FRF_SHIFT 16
-#define I2S_RCSR_FRF_WIDTH 1
-#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
-#define I2S_RCSR_FWF_MASK 0x20000u
-#define I2S_RCSR_FWF_SHIFT 17
-#define I2S_RCSR_FWF_WIDTH 1
-#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
-#define I2S_RCSR_FEF_MASK 0x40000u
-#define I2S_RCSR_FEF_SHIFT 18
-#define I2S_RCSR_FEF_WIDTH 1
-#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
-#define I2S_RCSR_SEF_MASK 0x80000u
-#define I2S_RCSR_SEF_SHIFT 19
-#define I2S_RCSR_SEF_WIDTH 1
-#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
-#define I2S_RCSR_WSF_MASK 0x100000u
-#define I2S_RCSR_WSF_SHIFT 20
-#define I2S_RCSR_WSF_WIDTH 1
-#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
-#define I2S_RCSR_SR_MASK 0x1000000u
-#define I2S_RCSR_SR_SHIFT 24
-#define I2S_RCSR_SR_WIDTH 1
-#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
-#define I2S_RCSR_FR_MASK 0x2000000u
-#define I2S_RCSR_FR_SHIFT 25
-#define I2S_RCSR_FR_WIDTH 1
-#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
-#define I2S_RCSR_BCE_MASK 0x10000000u
-#define I2S_RCSR_BCE_SHIFT 28
-#define I2S_RCSR_BCE_WIDTH 1
-#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
-#define I2S_RCSR_DBGE_MASK 0x20000000u
-#define I2S_RCSR_DBGE_SHIFT 29
-#define I2S_RCSR_DBGE_WIDTH 1
-#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
-#define I2S_RCSR_STOPE_MASK 0x40000000u
-#define I2S_RCSR_STOPE_SHIFT 30
-#define I2S_RCSR_STOPE_WIDTH 1
-#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
-#define I2S_RCSR_RE_MASK 0x80000000u
-#define I2S_RCSR_RE_SHIFT 31
-#define I2S_RCSR_RE_WIDTH 1
-#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK 0x7u
-#define I2S_RCR1_RFW_SHIFT 0
-#define I2S_RCR1_RFW_WIDTH 3
-#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK 0xFFu
-#define I2S_RCR2_DIV_SHIFT 0
-#define I2S_RCR2_DIV_WIDTH 8
-#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK 0x1000000u
-#define I2S_RCR2_BCD_SHIFT 24
-#define I2S_RCR2_BCD_WIDTH 1
-#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
-#define I2S_RCR2_BCP_MASK 0x2000000u
-#define I2S_RCR2_BCP_SHIFT 25
-#define I2S_RCR2_BCP_WIDTH 1
-#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
-#define I2S_RCR2_MSEL_MASK 0xC000000u
-#define I2S_RCR2_MSEL_SHIFT 26
-#define I2S_RCR2_MSEL_WIDTH 2
-#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK 0x10000000u
-#define I2S_RCR2_BCI_SHIFT 28
-#define I2S_RCR2_BCI_WIDTH 1
-#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
-#define I2S_RCR2_BCS_MASK 0x20000000u
-#define I2S_RCR2_BCS_SHIFT 29
-#define I2S_RCR2_BCS_WIDTH 1
-#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
-#define I2S_RCR2_SYNC_MASK 0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT 30
-#define I2S_RCR2_SYNC_WIDTH 2
-#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK 0xFu
-#define I2S_RCR3_WDFL_SHIFT 0
-#define I2S_RCR3_WDFL_WIDTH 4
-#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK 0x10000u
-#define I2S_RCR3_RCE_SHIFT 16
-#define I2S_RCR3_RCE_WIDTH 1
-#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK 0x1u
-#define I2S_RCR4_FSD_SHIFT 0
-#define I2S_RCR4_FSD_WIDTH 1
-#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
-#define I2S_RCR4_FSP_MASK 0x2u
-#define I2S_RCR4_FSP_SHIFT 1
-#define I2S_RCR4_FSP_WIDTH 1
-#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
-#define I2S_RCR4_ONDEM_MASK 0x4u
-#define I2S_RCR4_ONDEM_SHIFT 2
-#define I2S_RCR4_ONDEM_WIDTH 1
-#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_ONDEM_SHIFT))&I2S_RCR4_ONDEM_MASK)
-#define I2S_RCR4_FSE_MASK 0x8u
-#define I2S_RCR4_FSE_SHIFT 3
-#define I2S_RCR4_FSE_WIDTH 1
-#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
-#define I2S_RCR4_MF_MASK 0x10u
-#define I2S_RCR4_MF_SHIFT 4
-#define I2S_RCR4_MF_WIDTH 1
-#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
-#define I2S_RCR4_SYWD_MASK 0x1F00u
-#define I2S_RCR4_SYWD_SHIFT 8
-#define I2S_RCR4_SYWD_WIDTH 5
-#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK 0xF0000u
-#define I2S_RCR4_FRSZ_SHIFT 16
-#define I2S_RCR4_FRSZ_WIDTH 4
-#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-#define I2S_RCR4_FPACK_MASK 0x3000000u
-#define I2S_RCR4_FPACK_SHIFT 24
-#define I2S_RCR4_FPACK_WIDTH 2
-#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
-#define I2S_RCR4_FCONT_MASK 0x10000000u
-#define I2S_RCR4_FCONT_SHIFT 28
-#define I2S_RCR4_FCONT_WIDTH 1
-#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FCONT_SHIFT))&I2S_RCR4_FCONT_MASK)
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK 0x1F00u
-#define I2S_RCR5_FBT_SHIFT 8
-#define I2S_RCR5_FBT_WIDTH 5
-#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK 0x1F0000u
-#define I2S_RCR5_W0W_SHIFT 16
-#define I2S_RCR5_W0W_WIDTH 5
-#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK 0x1F000000u
-#define I2S_RCR5_WNW_SHIFT 24
-#define I2S_RCR5_WNW_WIDTH 5
-#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT 0
-#define I2S_RDR_RDR_WIDTH 32
-#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK 0xFu
-#define I2S_RFR_RFP_SHIFT 0
-#define I2S_RFR_RFP_WIDTH 4
-#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK 0xF0000u
-#define I2S_RFR_WFP_SHIFT 16
-#define I2S_RFR_WFP_WIDTH 4
-#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK 0xFFFFu
-#define I2S_RMR_RWM_SHIFT 0
-#define I2S_RMR_RWM_WIDTH 16
-#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK 0x3000000u
-#define I2S_MCR_MICS_SHIFT 24
-#define I2S_MCR_MICS_WIDTH 2
-#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK 0x40000000u
-#define I2S_MCR_MOE_SHIFT 30
-#define I2S_MCR_MOE_WIDTH 1
-#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
-#define I2S_MCR_DUF_MASK 0x80000000u
-#define I2S_MCR_DUF_SHIFT 31
-#define I2S_MCR_DUF_WIDTH 1
-#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK 0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT 0
-#define I2S_MDR_DIVIDE_WIDTH 12
-#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK 0xFF000u
-#define I2S_MDR_FRACT_SHIFT 12
-#define I2S_MDR_FRACT_WIDTH 8
-#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FRDE_MASK (0x1U)
+#define I2S_TCSR_FRDE_SHIFT (0U)
+#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK (0x2U)
+#define I2S_TCSR_FWDE_SHIFT (1U)
+#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK (0x100U)
+#define I2S_TCSR_FRIE_SHIFT (8U)
+#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK (0x200U)
+#define I2S_TCSR_FWIE_SHIFT (9U)
+#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK (0x400U)
+#define I2S_TCSR_FEIE_SHIFT (10U)
+#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK (0x800U)
+#define I2S_TCSR_SEIE_SHIFT (11U)
+#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT (12U)
+#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK (0x10000U)
+#define I2S_TCSR_FRF_SHIFT (16U)
+#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK (0x20000U)
+#define I2S_TCSR_FWF_SHIFT (17U)
+#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK (0x40000U)
+#define I2S_TCSR_FEF_SHIFT (18U)
+#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK (0x80000U)
+#define I2S_TCSR_SEF_SHIFT (19U)
+#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK (0x100000U)
+#define I2S_TCSR_WSF_SHIFT (20U)
+#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK (0x1000000U)
+#define I2S_TCSR_SR_SHIFT (24U)
+#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK (0x2000000U)
+#define I2S_TCSR_FR_SHIFT (25U)
+#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT (28U)
+#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT (29U)
+#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT (30U)
+#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK (0x80000000U)
+#define I2S_TCSR_TE_SHIFT (31U)
+#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+#define I2S_TCR1_TFW_MASK (0x7U)
+#define I2S_TCR1_TFW_SHIFT (0U)
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK (0xFFU)
+#define I2S_TCR2_DIV_SHIFT (0U)
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT (24U)
+#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT (25U)
+#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT (26U)
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT (28U)
+#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT (29U)
+#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT (30U)
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK (0xFU)
+#define I2S_TCR3_WDFL_SHIFT (0U)
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK (0x10000U)
+#define I2S_TCR3_TCE_SHIFT (16U)
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK (0x1U)
+#define I2S_TCR4_FSD_SHIFT (0U)
+#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK (0x2U)
+#define I2S_TCR4_FSP_SHIFT (1U)
+#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_ONDEM_MASK (0x4U)
+#define I2S_TCR4_ONDEM_SHIFT (2U)
+#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_FSE_MASK (0x8U)
+#define I2S_TCR4_FSE_SHIFT (3U)
+#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK (0x10U)
+#define I2S_TCR4_MF_SHIFT (4U)
+#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT (8U)
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK (0xF0000U)
+#define I2S_TCR4_FRSZ_SHIFT (16U)
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK (0x3000000U)
+#define I2S_TCR4_FPACK_SHIFT (24U)
+#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCONT_MASK (0x10000000U)
+#define I2S_TCR4_FCONT_SHIFT (28U)
+#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT (8U)
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT (16U)
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT (24U)
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT (0U)
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT (1U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+#define I2S_TFR_RFP_MASK (0xFU)
+#define I2S_TFR_RFP_SHIFT (0U)
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK (0xF0000U)
+#define I2S_TFR_WFP_SHIFT (16U)
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT (1U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK (0xFFFFU)
+#define I2S_TMR_TWM_SHIFT (0U)
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FRDE_MASK (0x1U)
+#define I2S_RCSR_FRDE_SHIFT (0U)
+#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK (0x2U)
+#define I2S_RCSR_FWDE_SHIFT (1U)
+#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK (0x100U)
+#define I2S_RCSR_FRIE_SHIFT (8U)
+#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK (0x200U)
+#define I2S_RCSR_FWIE_SHIFT (9U)
+#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK (0x400U)
+#define I2S_RCSR_FEIE_SHIFT (10U)
+#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK (0x800U)
+#define I2S_RCSR_SEIE_SHIFT (11U)
+#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT (12U)
+#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK (0x10000U)
+#define I2S_RCSR_FRF_SHIFT (16U)
+#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK (0x20000U)
+#define I2S_RCSR_FWF_SHIFT (17U)
+#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK (0x40000U)
+#define I2S_RCSR_FEF_SHIFT (18U)
+#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK (0x80000U)
+#define I2S_RCSR_SEF_SHIFT (19U)
+#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK (0x100000U)
+#define I2S_RCSR_WSF_SHIFT (20U)
+#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK (0x1000000U)
+#define I2S_RCSR_SR_SHIFT (24U)
+#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK (0x2000000U)
+#define I2S_RCSR_FR_SHIFT (25U)
+#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT (28U)
+#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT (29U)
+#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT (30U)
+#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK (0x80000000U)
+#define I2S_RCSR_RE_SHIFT (31U)
+#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+#define I2S_RCR1_RFW_MASK (0x7U)
+#define I2S_RCR1_RFW_SHIFT (0U)
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK (0xFFU)
+#define I2S_RCR2_DIV_SHIFT (0U)
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT (24U)
+#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT (25U)
+#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT (26U)
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT (28U)
+#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT (29U)
+#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT (30U)
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK (0xFU)
+#define I2S_RCR3_WDFL_SHIFT (0U)
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK (0x10000U)
+#define I2S_RCR3_RCE_SHIFT (16U)
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK (0x1U)
+#define I2S_RCR4_FSD_SHIFT (0U)
+#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK (0x2U)
+#define I2S_RCR4_FSP_SHIFT (1U)
+#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_ONDEM_MASK (0x4U)
+#define I2S_RCR4_ONDEM_SHIFT (2U)
+#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_FSE_MASK (0x8U)
+#define I2S_RCR4_FSE_SHIFT (3U)
+#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK (0x10U)
+#define I2S_RCR4_MF_SHIFT (4U)
+#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT (8U)
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK (0xF0000U)
+#define I2S_RCR4_FRSZ_SHIFT (16U)
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK (0x3000000U)
+#define I2S_RCR4_FPACK_SHIFT (24U)
+#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCONT_MASK (0x10000000U)
+#define I2S_RCR4_FCONT_SHIFT (28U)
+#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT (8U)
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT (16U)
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT (24U)
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT (0U)
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT (1U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+#define I2S_RFR_RFP_MASK (0xFU)
+#define I2S_RFR_RFP_SHIFT (0U)
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK (0xF0000U)
+#define I2S_RFR_WFP_SHIFT (16U)
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT (1U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK (0xFFFFU)
+#define I2S_RMR_RWM_SHIFT (0U)
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK (0x3000000U)
+#define I2S_MCR_MICS_SHIFT (24U)
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK (0x40000000U)
+#define I2S_MCR_MOE_SHIFT (30U)
+#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK (0x80000000U)
+#define I2S_MCR_DUF_SHIFT (31U)
+#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT (0U)
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT (12U)
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
/*!
* @}
@@ -5925,7 +4111,6 @@ typedef struct {
#define I2S0_BASE (0x4002F000u)
/** Peripheral I2S0 base pointer */
#define I2S0 ((I2S_Type *)I2S0_BASE)
-#define I2S0_BASE_PTR (I2S0)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { I2S0_BASE }
/** Array initializer of I2S peripheral base pointers */
@@ -5934,50 +4119,6 @@ typedef struct {
#define I2S_RX_IRQS { I2S0_Rx_IRQn }
#define I2S_TX_IRQS { I2S0_Tx_IRQn }
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register instance definitions */
-/* I2S0 */
-#define I2S0_TCSR I2S_TCSR_REG(I2S0)
-#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
-#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
-#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
-#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
-#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
-#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
-#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
-#define I2S0_TMR I2S_TMR_REG(I2S0)
-#define I2S0_RCSR I2S_RCSR_REG(I2S0)
-#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
-#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
-#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
-#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
-#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
-#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
-#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
-#define I2S0_RMR I2S_RMR_REG(I2S0)
-#define I2S0_MCR I2S_MCR_REG(I2S0)
-#define I2S0_MDR I2S_MDR_REG(I2S0)
-
-/* I2S - Register array accessors */
-#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
-#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
-#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
-#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
@@ -6004,34 +4145,7 @@ typedef struct {
__I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
__IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
__IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
-} LLWU_Type, *LLWU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register accessors */
-#define LLWU_PE1_REG(base) ((base)->PE1)
-#define LLWU_PE2_REG(base) ((base)->PE2)
-#define LLWU_PE3_REG(base) ((base)->PE3)
-#define LLWU_PE4_REG(base) ((base)->PE4)
-#define LLWU_ME_REG(base) ((base)->ME)
-#define LLWU_F1_REG(base) ((base)->F1)
-#define LLWU_F2_REG(base) ((base)->F2)
-#define LLWU_F3_REG(base) ((base)->F3)
-#define LLWU_FILT1_REG(base) ((base)->FILT1)
-#define LLWU_FILT2_REG(base) ((base)->FILT2)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
+} LLWU_Type;
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
@@ -6042,232 +4156,188 @@ typedef struct {
* @{
*/
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0_WIDTH 2
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1_WIDTH 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2_WIDTH 2
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3_WIDTH 2
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4_WIDTH 2
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5_WIDTH 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6_WIDTH 2
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7_WIDTH 2
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8_WIDTH 2
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9_WIDTH 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10_WIDTH 2
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11_WIDTH 2
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12_WIDTH 2
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13_WIDTH 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14_WIDTH 2
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15_WIDTH 2
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME0_WIDTH 1
-#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME1_WIDTH 1
-#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME2_WIDTH 1
-#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME3_WIDTH 1
-#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME4_WIDTH 1
-#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME5_WIDTH 1
-#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME6_WIDTH 1
-#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-#define LLWU_ME_WUME7_WIDTH 1
-#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF0_WIDTH 1
-#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF1_WIDTH 1
-#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF2_WIDTH 1
-#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF3_WIDTH 1
-#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF4_WIDTH 1
-#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF5_WIDTH 1
-#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF6_WIDTH 1
-#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-#define LLWU_F1_WUF7_WIDTH 1
-#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF8_WIDTH 1
-#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF9_WIDTH 1
-#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF10_WIDTH 1
-#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF11_WIDTH 1
-#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF12_WIDTH 1
-#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF13_WIDTH 1
-#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF14_WIDTH 1
-#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-#define LLWU_F2_WUF15_WIDTH 1
-#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF0_WIDTH 1
-#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF1_WIDTH 1
-#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF2_WIDTH 1
-#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF3_WIDTH 1
-#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF4_WIDTH 1
-#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF5_WIDTH 1
-#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF6_WIDTH 1
-#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-#define LLWU_F3_MWUF7_WIDTH 1
-#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL_WIDTH 4
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE_WIDTH 2
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-#define LLWU_FILT1_FILTF_WIDTH 1
-#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL_WIDTH 4
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE_WIDTH 2
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-#define LLWU_FILT2_FILTF_WIDTH 1
-#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT (0U)
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT (2U)
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT (4U)
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT (6U)
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT (0U)
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT (2U)
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT (4U)
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT (6U)
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT (0U)
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT (2U)
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT (4U)
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT (6U)
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT (0U)
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT (2U)
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT (4U)
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT (6U)
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK (0x1U)
+#define LLWU_ME_WUME0_SHIFT (0U)
+#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK (0x2U)
+#define LLWU_ME_WUME1_SHIFT (1U)
+#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK (0x4U)
+#define LLWU_ME_WUME2_SHIFT (2U)
+#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK (0x8U)
+#define LLWU_ME_WUME3_SHIFT (3U)
+#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK (0x10U)
+#define LLWU_ME_WUME4_SHIFT (4U)
+#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK (0x20U)
+#define LLWU_ME_WUME5_SHIFT (5U)
+#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK (0x40U)
+#define LLWU_ME_WUME6_SHIFT (6U)
+#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK (0x80U)
+#define LLWU_ME_WUME7_SHIFT (7U)
+#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name F1 - LLWU Flag 1 register */
+#define LLWU_F1_WUF0_MASK (0x1U)
+#define LLWU_F1_WUF0_SHIFT (0U)
+#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK (0x2U)
+#define LLWU_F1_WUF1_SHIFT (1U)
+#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK (0x4U)
+#define LLWU_F1_WUF2_SHIFT (2U)
+#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK (0x8U)
+#define LLWU_F1_WUF3_SHIFT (3U)
+#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK (0x10U)
+#define LLWU_F1_WUF4_SHIFT (4U)
+#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK (0x20U)
+#define LLWU_F1_WUF5_SHIFT (5U)
+#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK (0x40U)
+#define LLWU_F1_WUF6_SHIFT (6U)
+#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK (0x80U)
+#define LLWU_F1_WUF7_SHIFT (7U)
+#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+
+/*! @name F2 - LLWU Flag 2 register */
+#define LLWU_F2_WUF8_MASK (0x1U)
+#define LLWU_F2_WUF8_SHIFT (0U)
+#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK (0x2U)
+#define LLWU_F2_WUF9_SHIFT (1U)
+#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK (0x4U)
+#define LLWU_F2_WUF10_SHIFT (2U)
+#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK (0x8U)
+#define LLWU_F2_WUF11_SHIFT (3U)
+#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK (0x10U)
+#define LLWU_F2_WUF12_SHIFT (4U)
+#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK (0x20U)
+#define LLWU_F2_WUF13_SHIFT (5U)
+#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK (0x40U)
+#define LLWU_F2_WUF14_SHIFT (6U)
+#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK (0x80U)
+#define LLWU_F2_WUF15_SHIFT (7U)
+#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+
+/*! @name F3 - LLWU Flag 3 register */
+#define LLWU_F3_MWUF0_MASK (0x1U)
+#define LLWU_F3_MWUF0_SHIFT (0U)
+#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK (0x2U)
+#define LLWU_F3_MWUF1_SHIFT (1U)
+#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK (0x4U)
+#define LLWU_F3_MWUF2_SHIFT (2U)
+#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK (0x8U)
+#define LLWU_F3_MWUF3_SHIFT (3U)
+#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK (0x10U)
+#define LLWU_F3_MWUF4_SHIFT (4U)
+#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK (0x20U)
+#define LLWU_F3_MWUF5_SHIFT (5U)
+#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK (0x40U)
+#define LLWU_F3_MWUF6_SHIFT (6U)
+#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK (0x80U)
+#define LLWU_F3_MWUF7_SHIFT (7U)
+#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT (0U)
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT (5U)
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT (7U)
+#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT (0U)
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT (5U)
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT (7U)
+#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
/*!
* @}
@@ -6279,7 +4349,6 @@ typedef struct {
#define LLWU_BASE (0x4007C000u)
/** Peripheral LLWU base pointer */
#define LLWU ((LLWU_Type *)LLWU_BASE)
-#define LLWU_BASE_PTR (LLWU)
/** Array initializer of LLWU peripheral base addresses */
#define LLWU_BASE_ADDRS { LLWU_BASE }
/** Array initializer of LLWU peripheral base pointers */
@@ -6287,34 +4356,6 @@ typedef struct {
/** Interrupt vectors for the LLWU peripheral type */
#define LLWU_IRQS { LLWU_IRQn }
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register instance definitions */
-/* LLWU */
-#define LLWU_PE1 LLWU_PE1_REG(LLWU)
-#define LLWU_PE2 LLWU_PE2_REG(LLWU)
-#define LLWU_PE3 LLWU_PE3_REG(LLWU)
-#define LLWU_PE4 LLWU_PE4_REG(LLWU)
-#define LLWU_ME LLWU_ME_REG(LLWU)
-#define LLWU_F1 LLWU_F1_REG(LLWU)
-#define LLWU_F2 LLWU_F2_REG(LLWU)
-#define LLWU_F3 LLWU_F3_REG(LLWU)
-#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
-#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
@@ -6335,28 +4376,7 @@ typedef struct {
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type, *LPTMR_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register accessors */
-#define LPTMR_CSR_REG(base) ((base)->CSR)
-#define LPTMR_PSR_REG(base) ((base)->PSR)
-#define LPTMR_CMR_REG(base) ((base)->CMR)
-#define LPTMR_CNR_REG(base) ((base)->CNR)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
+} LPTMR_Type;
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
@@ -6367,58 +4387,50 @@ typedef struct {
* @{
*/
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TEN_WIDTH 1
-#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TMS_WIDTH 1
-#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TFC_WIDTH 1
-#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPP_WIDTH 1
-#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS_WIDTH 2
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TIE_WIDTH 1
-#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-#define LPTMR_CSR_TCF_WIDTH 1
-#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS_WIDTH 2
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PBYP_WIDTH 1
-#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE_WIDTH 4
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE_WIDTH 16
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER_WIDTH 16
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK (0x1U)
+#define LPTMR_CSR_TEN_SHIFT (0U)
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK (0x2U)
+#define LPTMR_CSR_TMS_SHIFT (1U)
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK (0x4U)
+#define LPTMR_CSR_TFC_SHIFT (2U)
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK (0x8U)
+#define LPTMR_CSR_TPP_SHIFT (3U)
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK (0x30U)
+#define LPTMR_CSR_TPS_SHIFT (4U)
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK (0x40U)
+#define LPTMR_CSR_TIE_SHIFT (6U)
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK (0x80U)
+#define LPTMR_CSR_TCF_SHIFT (7U)
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK (0x3U)
+#define LPTMR_PSR_PCS_SHIFT (0U)
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT (2U)
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT (3U)
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT (0U)
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT (0U)
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
/*!
* @}
@@ -6430,7 +4442,6 @@ typedef struct {
#define LPTMR0_BASE (0x40040000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-#define LPTMR0_BASE_PTR (LPTMR0)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
/** Array initializer of LPTMR peripheral base pointers */
@@ -6438,28 +4449,6 @@ typedef struct {
/** Interrupt vectors for the LPTMR peripheral type */
#define LPTMR_IRQS { LPTMR0_IRQn }
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register instance definitions */
-/* LPTMR0 */
-#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
-#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
-#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
-#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
@@ -6482,30 +4471,7 @@ typedef struct {
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
-} LPUART_Type, *LPUART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPUART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
- * @{
- */
-
-
-/* LPUART - Register accessors */
-#define LPUART_BAUD_REG(base) ((base)->BAUD)
-#define LPUART_STAT_REG(base) ((base)->STAT)
-#define LPUART_CTRL_REG(base) ((base)->CTRL)
-#define LPUART_DATA_REG(base) ((base)->DATA)
-#define LPUART_MATCH_REG(base) ((base)->MATCH)
-#define LPUART_MODIR_REG(base) ((base)->MODIR)
-
-/*!
- * @}
- */ /* end of group LPUART_Register_Accessor_Macros */
-
+} LPUART_Type;
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
@@ -6516,344 +4482,267 @@ typedef struct {
* @{
*/
-/* BAUD Bit Fields */
-#define LPUART_BAUD_SBR_MASK 0x1FFFu
-#define LPUART_BAUD_SBR_SHIFT 0
-#define LPUART_BAUD_SBR_WIDTH 13
-#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
-#define LPUART_BAUD_SBNS_MASK 0x2000u
-#define LPUART_BAUD_SBNS_SHIFT 13
-#define LPUART_BAUD_SBNS_WIDTH 1
-#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
-#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
-#define LPUART_BAUD_RXEDGIE_SHIFT 14
-#define LPUART_BAUD_RXEDGIE_WIDTH 1
-#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
-#define LPUART_BAUD_LBKDIE_MASK 0x8000u
-#define LPUART_BAUD_LBKDIE_SHIFT 15
-#define LPUART_BAUD_LBKDIE_WIDTH 1
-#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
-#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
-#define LPUART_BAUD_RESYNCDIS_SHIFT 16
-#define LPUART_BAUD_RESYNCDIS_WIDTH 1
-#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
-#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
-#define LPUART_BAUD_BOTHEDGE_SHIFT 17
-#define LPUART_BAUD_BOTHEDGE_WIDTH 1
-#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
-#define LPUART_BAUD_MATCFG_MASK 0xC0000u
-#define LPUART_BAUD_MATCFG_SHIFT 18
-#define LPUART_BAUD_MATCFG_WIDTH 2
-#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
-#define LPUART_BAUD_RDMAE_MASK 0x200000u
-#define LPUART_BAUD_RDMAE_SHIFT 21
-#define LPUART_BAUD_RDMAE_WIDTH 1
-#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
-#define LPUART_BAUD_TDMAE_MASK 0x800000u
-#define LPUART_BAUD_TDMAE_SHIFT 23
-#define LPUART_BAUD_TDMAE_WIDTH 1
-#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
-#define LPUART_BAUD_OSR_MASK 0x1F000000u
-#define LPUART_BAUD_OSR_SHIFT 24
-#define LPUART_BAUD_OSR_WIDTH 5
-#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
-#define LPUART_BAUD_M10_MASK 0x20000000u
-#define LPUART_BAUD_M10_SHIFT 29
-#define LPUART_BAUD_M10_WIDTH 1
-#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
-#define LPUART_BAUD_MAEN2_MASK 0x40000000u
-#define LPUART_BAUD_MAEN2_SHIFT 30
-#define LPUART_BAUD_MAEN2_WIDTH 1
-#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
-#define LPUART_BAUD_MAEN1_MASK 0x80000000u
-#define LPUART_BAUD_MAEN1_SHIFT 31
-#define LPUART_BAUD_MAEN1_WIDTH 1
-#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
-/* STAT Bit Fields */
-#define LPUART_STAT_MA2F_MASK 0x4000u
-#define LPUART_STAT_MA2F_SHIFT 14
-#define LPUART_STAT_MA2F_WIDTH 1
-#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
-#define LPUART_STAT_MA1F_MASK 0x8000u
-#define LPUART_STAT_MA1F_SHIFT 15
-#define LPUART_STAT_MA1F_WIDTH 1
-#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
-#define LPUART_STAT_PF_MASK 0x10000u
-#define LPUART_STAT_PF_SHIFT 16
-#define LPUART_STAT_PF_WIDTH 1
-#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
-#define LPUART_STAT_FE_MASK 0x20000u
-#define LPUART_STAT_FE_SHIFT 17
-#define LPUART_STAT_FE_WIDTH 1
-#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
-#define LPUART_STAT_NF_MASK 0x40000u
-#define LPUART_STAT_NF_SHIFT 18
-#define LPUART_STAT_NF_WIDTH 1
-#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
-#define LPUART_STAT_OR_MASK 0x80000u
-#define LPUART_STAT_OR_SHIFT 19
-#define LPUART_STAT_OR_WIDTH 1
-#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
-#define LPUART_STAT_IDLE_MASK 0x100000u
-#define LPUART_STAT_IDLE_SHIFT 20
-#define LPUART_STAT_IDLE_WIDTH 1
-#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
-#define LPUART_STAT_RDRF_MASK 0x200000u
-#define LPUART_STAT_RDRF_SHIFT 21
-#define LPUART_STAT_RDRF_WIDTH 1
-#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
-#define LPUART_STAT_TC_MASK 0x400000u
-#define LPUART_STAT_TC_SHIFT 22
-#define LPUART_STAT_TC_WIDTH 1
-#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
-#define LPUART_STAT_TDRE_MASK 0x800000u
-#define LPUART_STAT_TDRE_SHIFT 23
-#define LPUART_STAT_TDRE_WIDTH 1
-#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
-#define LPUART_STAT_RAF_MASK 0x1000000u
-#define LPUART_STAT_RAF_SHIFT 24
-#define LPUART_STAT_RAF_WIDTH 1
-#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
-#define LPUART_STAT_LBKDE_MASK 0x2000000u
-#define LPUART_STAT_LBKDE_SHIFT 25
-#define LPUART_STAT_LBKDE_WIDTH 1
-#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
-#define LPUART_STAT_BRK13_MASK 0x4000000u
-#define LPUART_STAT_BRK13_SHIFT 26
-#define LPUART_STAT_BRK13_WIDTH 1
-#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
-#define LPUART_STAT_RWUID_MASK 0x8000000u
-#define LPUART_STAT_RWUID_SHIFT 27
-#define LPUART_STAT_RWUID_WIDTH 1
-#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
-#define LPUART_STAT_RXINV_MASK 0x10000000u
-#define LPUART_STAT_RXINV_SHIFT 28
-#define LPUART_STAT_RXINV_WIDTH 1
-#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
-#define LPUART_STAT_MSBF_MASK 0x20000000u
-#define LPUART_STAT_MSBF_SHIFT 29
-#define LPUART_STAT_MSBF_WIDTH 1
-#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
-#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
-#define LPUART_STAT_RXEDGIF_SHIFT 30
-#define LPUART_STAT_RXEDGIF_WIDTH 1
-#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
-#define LPUART_STAT_LBKDIF_MASK 0x80000000u
-#define LPUART_STAT_LBKDIF_SHIFT 31
-#define LPUART_STAT_LBKDIF_WIDTH 1
-#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
-/* CTRL Bit Fields */
-#define LPUART_CTRL_PT_MASK 0x1u
-#define LPUART_CTRL_PT_SHIFT 0
-#define LPUART_CTRL_PT_WIDTH 1
-#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
-#define LPUART_CTRL_PE_MASK 0x2u
-#define LPUART_CTRL_PE_SHIFT 1
-#define LPUART_CTRL_PE_WIDTH 1
-#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
-#define LPUART_CTRL_ILT_MASK 0x4u
-#define LPUART_CTRL_ILT_SHIFT 2
-#define LPUART_CTRL_ILT_WIDTH 1
-#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
-#define LPUART_CTRL_WAKE_MASK 0x8u
-#define LPUART_CTRL_WAKE_SHIFT 3
-#define LPUART_CTRL_WAKE_WIDTH 1
-#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
-#define LPUART_CTRL_M_MASK 0x10u
-#define LPUART_CTRL_M_SHIFT 4
-#define LPUART_CTRL_M_WIDTH 1
-#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
-#define LPUART_CTRL_RSRC_MASK 0x20u
-#define LPUART_CTRL_RSRC_SHIFT 5
-#define LPUART_CTRL_RSRC_WIDTH 1
-#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
-#define LPUART_CTRL_DOZEEN_MASK 0x40u
-#define LPUART_CTRL_DOZEEN_SHIFT 6
-#define LPUART_CTRL_DOZEEN_WIDTH 1
-#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
-#define LPUART_CTRL_LOOPS_MASK 0x80u
-#define LPUART_CTRL_LOOPS_SHIFT 7
-#define LPUART_CTRL_LOOPS_WIDTH 1
-#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
-#define LPUART_CTRL_IDLECFG_MASK 0x700u
-#define LPUART_CTRL_IDLECFG_SHIFT 8
-#define LPUART_CTRL_IDLECFG_WIDTH 3
-#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
-#define LPUART_CTRL_MA2IE_MASK 0x4000u
-#define LPUART_CTRL_MA2IE_SHIFT 14
-#define LPUART_CTRL_MA2IE_WIDTH 1
-#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
-#define LPUART_CTRL_MA1IE_MASK 0x8000u
-#define LPUART_CTRL_MA1IE_SHIFT 15
-#define LPUART_CTRL_MA1IE_WIDTH 1
-#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
-#define LPUART_CTRL_SBK_MASK 0x10000u
-#define LPUART_CTRL_SBK_SHIFT 16
-#define LPUART_CTRL_SBK_WIDTH 1
-#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
-#define LPUART_CTRL_RWU_MASK 0x20000u
-#define LPUART_CTRL_RWU_SHIFT 17
-#define LPUART_CTRL_RWU_WIDTH 1
-#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
-#define LPUART_CTRL_RE_MASK 0x40000u
-#define LPUART_CTRL_RE_SHIFT 18
-#define LPUART_CTRL_RE_WIDTH 1
-#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
-#define LPUART_CTRL_TE_MASK 0x80000u
-#define LPUART_CTRL_TE_SHIFT 19
-#define LPUART_CTRL_TE_WIDTH 1
-#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
-#define LPUART_CTRL_ILIE_MASK 0x100000u
-#define LPUART_CTRL_ILIE_SHIFT 20
-#define LPUART_CTRL_ILIE_WIDTH 1
-#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
-#define LPUART_CTRL_RIE_MASK 0x200000u
-#define LPUART_CTRL_RIE_SHIFT 21
-#define LPUART_CTRL_RIE_WIDTH 1
-#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
-#define LPUART_CTRL_TCIE_MASK 0x400000u
-#define LPUART_CTRL_TCIE_SHIFT 22
-#define LPUART_CTRL_TCIE_WIDTH 1
-#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
-#define LPUART_CTRL_TIE_MASK 0x800000u
-#define LPUART_CTRL_TIE_SHIFT 23
-#define LPUART_CTRL_TIE_WIDTH 1
-#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
-#define LPUART_CTRL_PEIE_MASK 0x1000000u
-#define LPUART_CTRL_PEIE_SHIFT 24
-#define LPUART_CTRL_PEIE_WIDTH 1
-#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
-#define LPUART_CTRL_FEIE_MASK 0x2000000u
-#define LPUART_CTRL_FEIE_SHIFT 25
-#define LPUART_CTRL_FEIE_WIDTH 1
-#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
-#define LPUART_CTRL_NEIE_MASK 0x4000000u
-#define LPUART_CTRL_NEIE_SHIFT 26
-#define LPUART_CTRL_NEIE_WIDTH 1
-#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
-#define LPUART_CTRL_ORIE_MASK 0x8000000u
-#define LPUART_CTRL_ORIE_SHIFT 27
-#define LPUART_CTRL_ORIE_WIDTH 1
-#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
-#define LPUART_CTRL_TXINV_MASK 0x10000000u
-#define LPUART_CTRL_TXINV_SHIFT 28
-#define LPUART_CTRL_TXINV_WIDTH 1
-#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
-#define LPUART_CTRL_TXDIR_MASK 0x20000000u
-#define LPUART_CTRL_TXDIR_SHIFT 29
-#define LPUART_CTRL_TXDIR_WIDTH 1
-#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
-#define LPUART_CTRL_R9T8_MASK 0x40000000u
-#define LPUART_CTRL_R9T8_SHIFT 30
-#define LPUART_CTRL_R9T8_WIDTH 1
-#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
-#define LPUART_CTRL_R8T9_MASK 0x80000000u
-#define LPUART_CTRL_R8T9_SHIFT 31
-#define LPUART_CTRL_R8T9_WIDTH 1
-#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
-/* DATA Bit Fields */
-#define LPUART_DATA_R0T0_MASK 0x1u
-#define LPUART_DATA_R0T0_SHIFT 0
-#define LPUART_DATA_R0T0_WIDTH 1
-#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
-#define LPUART_DATA_R1T1_MASK 0x2u
-#define LPUART_DATA_R1T1_SHIFT 1
-#define LPUART_DATA_R1T1_WIDTH 1
-#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
-#define LPUART_DATA_R2T2_MASK 0x4u
-#define LPUART_DATA_R2T2_SHIFT 2
-#define LPUART_DATA_R2T2_WIDTH 1
-#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
-#define LPUART_DATA_R3T3_MASK 0x8u
-#define LPUART_DATA_R3T3_SHIFT 3
-#define LPUART_DATA_R3T3_WIDTH 1
-#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
-#define LPUART_DATA_R4T4_MASK 0x10u
-#define LPUART_DATA_R4T4_SHIFT 4
-#define LPUART_DATA_R4T4_WIDTH 1
-#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
-#define LPUART_DATA_R5T5_MASK 0x20u
-#define LPUART_DATA_R5T5_SHIFT 5
-#define LPUART_DATA_R5T5_WIDTH 1
-#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
-#define LPUART_DATA_R6T6_MASK 0x40u
-#define LPUART_DATA_R6T6_SHIFT 6
-#define LPUART_DATA_R6T6_WIDTH 1
-#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
-#define LPUART_DATA_R7T7_MASK 0x80u
-#define LPUART_DATA_R7T7_SHIFT 7
-#define LPUART_DATA_R7T7_WIDTH 1
-#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
-#define LPUART_DATA_R8T8_MASK 0x100u
-#define LPUART_DATA_R8T8_SHIFT 8
-#define LPUART_DATA_R8T8_WIDTH 1
-#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
-#define LPUART_DATA_R9T9_MASK 0x200u
-#define LPUART_DATA_R9T9_SHIFT 9
-#define LPUART_DATA_R9T9_WIDTH 1
-#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
-#define LPUART_DATA_IDLINE_MASK 0x800u
-#define LPUART_DATA_IDLINE_SHIFT 11
-#define LPUART_DATA_IDLINE_WIDTH 1
-#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
-#define LPUART_DATA_RXEMPT_MASK 0x1000u
-#define LPUART_DATA_RXEMPT_SHIFT 12
-#define LPUART_DATA_RXEMPT_WIDTH 1
-#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
-#define LPUART_DATA_FRETSC_MASK 0x2000u
-#define LPUART_DATA_FRETSC_SHIFT 13
-#define LPUART_DATA_FRETSC_WIDTH 1
-#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
-#define LPUART_DATA_PARITYE_MASK 0x4000u
-#define LPUART_DATA_PARITYE_SHIFT 14
-#define LPUART_DATA_PARITYE_WIDTH 1
-#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
-#define LPUART_DATA_NOISY_MASK 0x8000u
-#define LPUART_DATA_NOISY_SHIFT 15
-#define LPUART_DATA_NOISY_WIDTH 1
-#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
-/* MATCH Bit Fields */
-#define LPUART_MATCH_MA1_MASK 0x3FFu
-#define LPUART_MATCH_MA1_SHIFT 0
-#define LPUART_MATCH_MA1_WIDTH 10
-#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
-#define LPUART_MATCH_MA2_MASK 0x3FF0000u
-#define LPUART_MATCH_MA2_SHIFT 16
-#define LPUART_MATCH_MA2_WIDTH 10
-#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
-/* MODIR Bit Fields */
-#define LPUART_MODIR_TXCTSE_MASK 0x1u
-#define LPUART_MODIR_TXCTSE_SHIFT 0
-#define LPUART_MODIR_TXCTSE_WIDTH 1
-#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
-#define LPUART_MODIR_TXRTSE_MASK 0x2u
-#define LPUART_MODIR_TXRTSE_SHIFT 1
-#define LPUART_MODIR_TXRTSE_WIDTH 1
-#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
-#define LPUART_MODIR_TXRTSPOL_MASK 0x4u
-#define LPUART_MODIR_TXRTSPOL_SHIFT 2
-#define LPUART_MODIR_TXRTSPOL_WIDTH 1
-#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
-#define LPUART_MODIR_RXRTSE_MASK 0x8u
-#define LPUART_MODIR_RXRTSE_SHIFT 3
-#define LPUART_MODIR_RXRTSE_WIDTH 1
-#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
-#define LPUART_MODIR_TXCTSC_MASK 0x10u
-#define LPUART_MODIR_TXCTSC_SHIFT 4
-#define LPUART_MODIR_TXCTSC_WIDTH 1
-#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
-#define LPUART_MODIR_TXCTSSRC_MASK 0x20u
-#define LPUART_MODIR_TXCTSSRC_SHIFT 5
-#define LPUART_MODIR_TXCTSSRC_WIDTH 1
-#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
-#define LPUART_MODIR_TNP_MASK 0x30000u
-#define LPUART_MODIR_TNP_SHIFT 16
-#define LPUART_MODIR_TNP_WIDTH 2
-#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
-#define LPUART_MODIR_IREN_MASK 0x40000u
-#define LPUART_MODIR_IREN_SHIFT 18
-#define LPUART_MODIR_IREN_WIDTH 1
-#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
+/*! @name BAUD - LPUART Baud Rate Register */
+#define LPUART_BAUD_SBR_MASK (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT (0U)
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT (13U)
+#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
+#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT (15U)
+#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
+#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
+#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT (18U)
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT (21U)
+#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT (23U)
+#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT (24U)
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT (29U)
+#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT (30U)
+#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT (31U)
+#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+
+/*! @name STAT - LPUART Status Register */
+#define LPUART_STAT_MA2F_MASK (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT (14U)
+#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT (15U)
+#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK (0x10000U)
+#define LPUART_STAT_PF_SHIFT (16U)
+#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK (0x20000U)
+#define LPUART_STAT_FE_SHIFT (17U)
+#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK (0x40000U)
+#define LPUART_STAT_NF_SHIFT (18U)
+#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK (0x80000U)
+#define LPUART_STAT_OR_SHIFT (19U)
+#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT (20U)
+#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT (21U)
+#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK (0x400000U)
+#define LPUART_STAT_TC_SHIFT (22U)
+#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT (23U)
+#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT (24U)
+#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT (25U)
+#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT (26U)
+#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT (27U)
+#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT (28U)
+#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT (29U)
+#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT (30U)
+#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT (31U)
+#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+
+/*! @name CTRL - LPUART Control Register */
+#define LPUART_CTRL_PT_MASK (0x1U)
+#define LPUART_CTRL_PT_SHIFT (0U)
+#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK (0x2U)
+#define LPUART_CTRL_PE_SHIFT (1U)
+#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK (0x4U)
+#define LPUART_CTRL_ILT_SHIFT (2U)
+#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT (3U)
+#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK (0x10U)
+#define LPUART_CTRL_M_SHIFT (4U)
+#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT (5U)
+#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT (6U)
+#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT (7U)
+#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT (8U)
+#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT (14U)
+#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT (15U)
+#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT (16U)
+#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT (17U)
+#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK (0x40000U)
+#define LPUART_CTRL_RE_SHIFT (18U)
+#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK (0x80000U)
+#define LPUART_CTRL_TE_SHIFT (19U)
+#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT (20U)
+#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT (21U)
+#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT (22U)
+#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT (23U)
+#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT (24U)
+#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT (25U)
+#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT (26U)
+#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT (27U)
+#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT (28U)
+#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT (29U)
+#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT (30U)
+#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT (31U)
+#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+
+/*! @name DATA - LPUART Data Register */
+#define LPUART_DATA_R0T0_MASK (0x1U)
+#define LPUART_DATA_R0T0_SHIFT (0U)
+#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK (0x2U)
+#define LPUART_DATA_R1T1_SHIFT (1U)
+#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK (0x4U)
+#define LPUART_DATA_R2T2_SHIFT (2U)
+#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK (0x8U)
+#define LPUART_DATA_R3T3_SHIFT (3U)
+#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK (0x10U)
+#define LPUART_DATA_R4T4_SHIFT (4U)
+#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK (0x20U)
+#define LPUART_DATA_R5T5_SHIFT (5U)
+#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK (0x40U)
+#define LPUART_DATA_R6T6_SHIFT (6U)
+#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK (0x80U)
+#define LPUART_DATA_R7T7_SHIFT (7U)
+#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK (0x100U)
+#define LPUART_DATA_R8T8_SHIFT (8U)
+#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK (0x200U)
+#define LPUART_DATA_R9T9_SHIFT (9U)
+#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT (11U)
+#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT (12U)
+#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT (13U)
+#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT (14U)
+#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT (15U)
+#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+
+/*! @name MATCH - LPUART Match Address Register */
+#define LPUART_MATCH_MA1_MASK (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT (0U)
+#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT (16U)
+#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+
+/*! @name MODIR - LPUART Modem IrDA Register */
+#define LPUART_MODIR_TXCTSE_MASK (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT (0U)
+#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+#define LPUART_MODIR_TXRTSE_MASK (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT (1U)
+#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
+#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+#define LPUART_MODIR_RXRTSE_MASK (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT (3U)
+#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+#define LPUART_MODIR_TXCTSC_MASK (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT (4U)
+#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
+#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+#define LPUART_MODIR_TNP_MASK (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT (16U)
+#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT (18U)
+#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+
/*!
* @}
@@ -6865,7 +4754,6 @@ typedef struct {
#define LPUART0_BASE (0x4002A000u)
/** Peripheral LPUART0 base pointer */
#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
-#define LPUART0_BASE_PTR (LPUART0)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { LPUART0_BASE }
/** Array initializer of LPUART peripheral base pointers */
@@ -6874,30 +4762,6 @@ typedef struct {
#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
#define LPUART_ERR_IRQS { LPUART0_IRQn }
-/* ----------------------------------------------------------------------------
- -- LPUART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
- * @{
- */
-
-
-/* LPUART - Register instance definitions */
-/* LPUART0 */
-#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
-#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
-#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
-#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
-#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
-#define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
-
-/*!
- * @}
- */ /* end of group LPUART_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
@@ -6928,36 +4792,7 @@ typedef struct {
__IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
__IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
__IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
-} MCG_Type, *MCG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register accessors */
-#define MCG_C1_REG(base) ((base)->C1)
-#define MCG_C2_REG(base) ((base)->C2)
-#define MCG_C3_REG(base) ((base)->C3)
-#define MCG_C4_REG(base) ((base)->C4)
-#define MCG_C5_REG(base) ((base)->C5)
-#define MCG_C6_REG(base) ((base)->C6)
-#define MCG_S_REG(base) ((base)->S)
-#define MCG_SC_REG(base) ((base)->SC)
-#define MCG_ATCVH_REG(base) ((base)->ATCVH)
-#define MCG_ATCVL_REG(base) ((base)->ATCVL)
-#define MCG_C7_REG(base) ((base)->C7)
-#define MCG_C8_REG(base) ((base)->C8)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
+} MCG_Type;
/* ----------------------------------------------------------------------------
-- MCG Register Masks
@@ -6968,194 +4803,162 @@ typedef struct {
* @{
*/
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IREFSTEN_WIDTH 1
-#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IRCLKEN_WIDTH 1
-#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_IREFS_WIDTH 1
-#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV_WIDTH 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS_WIDTH 2
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_IRCS_WIDTH 1
-#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_LP_WIDTH 1
-#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
-#define MCG_C2_EREFS_MASK 0x4u
-#define MCG_C2_EREFS_SHIFT 2
-#define MCG_C2_EREFS_WIDTH 1
-#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
-#define MCG_C2_HGO_MASK 0x8u
-#define MCG_C2_HGO_SHIFT 3
-#define MCG_C2_HGO_WIDTH 1
-#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
-#define MCG_C2_RANGE_MASK 0x30u
-#define MCG_C2_RANGE_SHIFT 4
-#define MCG_C2_RANGE_WIDTH 2
-#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
-#define MCG_C2_FCFTRIM_MASK 0x40u
-#define MCG_C2_FCFTRIM_SHIFT 6
-#define MCG_C2_FCFTRIM_WIDTH 1
-#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-#define MCG_C2_LOCRE0_WIDTH 1
-#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM_WIDTH 8
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_SCFTRIM_WIDTH 1
-#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM_WIDTH 4
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS_WIDTH 2
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-#define MCG_C4_DMX32_WIDTH 1
-#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK 0x1Fu
-#define MCG_C5_PRDIV0_SHIFT 0
-#define MCG_C5_PRDIV0_WIDTH 5
-#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK 0x20u
-#define MCG_C5_PLLSTEN0_SHIFT 5
-#define MCG_C5_PLLSTEN0_WIDTH 1
-#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
-#define MCG_C5_PLLCLKEN0_MASK 0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT 6
-#define MCG_C5_PLLCLKEN0_WIDTH 1
-#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK 0x1Fu
-#define MCG_C6_VDIV0_SHIFT 0
-#define MCG_C6_VDIV0_WIDTH 5
-#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK 0x20u
-#define MCG_C6_CME0_SHIFT 5
-#define MCG_C6_CME0_WIDTH 1
-#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
-#define MCG_C6_PLLS_MASK 0x40u
-#define MCG_C6_PLLS_SHIFT 6
-#define MCG_C6_PLLS_WIDTH 1
-#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
-#define MCG_C6_LOLIE0_MASK 0x80u
-#define MCG_C6_LOLIE0_SHIFT 7
-#define MCG_C6_LOLIE0_WIDTH 1
-#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_IRCST_WIDTH 1
-#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_OSCINIT0_WIDTH 1
-#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST_WIDTH 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_IREFST_WIDTH 1
-#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
-#define MCG_S_PLLST_MASK 0x20u
-#define MCG_S_PLLST_SHIFT 5
-#define MCG_S_PLLST_WIDTH 1
-#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
-#define MCG_S_LOCK0_MASK 0x40u
-#define MCG_S_LOCK0_SHIFT 6
-#define MCG_S_LOCK0_WIDTH 1
-#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
-#define MCG_S_LOLS0_MASK 0x80u
-#define MCG_S_LOLS0_SHIFT 7
-#define MCG_S_LOLS0_WIDTH 1
-#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_LOCS0_WIDTH 1
-#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV_WIDTH 3
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_FLTPRSRV_WIDTH 1
-#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMF_WIDTH 1
-#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATMS_WIDTH 1
-#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-#define MCG_SC_ATME_WIDTH 1
-#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH_WIDTH 8
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL_WIDTH 8
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK 0x3u
-#define MCG_C7_OSCSEL_SHIFT 0
-#define MCG_C7_OSCSEL_WIDTH 2
-#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK 0x1u
-#define MCG_C8_LOCS1_SHIFT 0
-#define MCG_C8_LOCS1_WIDTH 1
-#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
-#define MCG_C8_CME1_MASK 0x20u
-#define MCG_C8_CME1_SHIFT 5
-#define MCG_C8_CME1_WIDTH 1
-#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
-#define MCG_C8_LOLRE_MASK 0x40u
-#define MCG_C8_LOLRE_SHIFT 6
-#define MCG_C8_LOLRE_WIDTH 1
-#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
-#define MCG_C8_LOCRE1_MASK 0x80u
-#define MCG_C8_LOCRE1_SHIFT 7
-#define MCG_C8_LOCRE1_WIDTH 1
-#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT (0U)
+#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT (1U)
+#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK (0x4U)
+#define MCG_C1_IREFS_SHIFT (2U)
+#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK (0x38U)
+#define MCG_C1_FRDIV_SHIFT (3U)
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK (0xC0U)
+#define MCG_C1_CLKS_SHIFT (6U)
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK (0x1U)
+#define MCG_C2_IRCS_SHIFT (0U)
+#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK (0x2U)
+#define MCG_C2_LP_SHIFT (1U)
+#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK (0x4U)
+#define MCG_C2_EREFS_SHIFT (2U)
+#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK (0x8U)
+#define MCG_C2_HGO_SHIFT (3U)
+#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK (0x30U)
+#define MCG_C2_RANGE_SHIFT (4U)
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK (0x40U)
+#define MCG_C2_FCFTRIM_SHIFT (6U)
+#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK (0x80U)
+#define MCG_C2_LOCRE0_SHIFT (7U)
+#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT (0U)
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT (0U)
+#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT (1U)
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT (5U)
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK (0x80U)
+#define MCG_C4_DMX32_SHIFT (7U)
+#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV0_MASK (0x1FU)
+#define MCG_C5_PRDIV0_SHIFT (0U)
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK (0x20U)
+#define MCG_C5_PLLSTEN0_SHIFT (5U)
+#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK (0x40U)
+#define MCG_C5_PLLCLKEN0_SHIFT (6U)
+#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV0_MASK (0x1FU)
+#define MCG_C6_VDIV0_SHIFT (0U)
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK (0x20U)
+#define MCG_C6_CME0_SHIFT (5U)
+#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK (0x40U)
+#define MCG_C6_PLLS_SHIFT (6U)
+#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK (0x80U)
+#define MCG_C6_LOLIE0_SHIFT (7U)
+#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK (0x1U)
+#define MCG_S_IRCST_SHIFT (0U)
+#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK (0x2U)
+#define MCG_S_OSCINIT0_SHIFT (1U)
+#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK (0xCU)
+#define MCG_S_CLKST_SHIFT (2U)
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK (0x10U)
+#define MCG_S_IREFST_SHIFT (4U)
+#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK (0x20U)
+#define MCG_S_PLLST_SHIFT (5U)
+#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK (0x40U)
+#define MCG_S_LOCK0_SHIFT (6U)
+#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK (0x80U)
+#define MCG_S_LOLS0_SHIFT (7U)
+#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK (0x1U)
+#define MCG_SC_LOCS0_SHIFT (0U)
+#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK (0xEU)
+#define MCG_SC_FCRDIV_SHIFT (1U)
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT (4U)
+#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK (0x20U)
+#define MCG_SC_ATMF_SHIFT (5U)
+#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK (0x40U)
+#define MCG_SC_ATMS_SHIFT (6U)
+#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK (0x80U)
+#define MCG_SC_ATME_SHIFT (7U)
+#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT (0U)
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT (0U)
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK (0x3U)
+#define MCG_C7_OSCSEL_SHIFT (0U)
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1_MASK (0x1U)
+#define MCG_C8_LOCS1_SHIFT (0U)
+#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK (0x20U)
+#define MCG_C8_CME1_SHIFT (5U)
+#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK (0x40U)
+#define MCG_C8_LOLRE_SHIFT (6U)
+#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK (0x80U)
+#define MCG_C8_LOCRE1_SHIFT (7U)
+#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+
/*!
* @}
@@ -7167,42 +4970,11 @@ typedef struct {
#define MCG_BASE (0x40064000u)
/** Peripheral MCG base pointer */
#define MCG ((MCG_Type *)MCG_BASE)
-#define MCG_BASE_PTR (MCG)
/** Array initializer of MCG peripheral base addresses */
#define MCG_BASE_ADDRS { MCG_BASE }
/** Array initializer of MCG peripheral base pointers */
#define MCG_BASE_PTRS { MCG }
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register instance definitions */
-/* MCG */
-#define MCG_C1 MCG_C1_REG(MCG)
-#define MCG_C2 MCG_C2_REG(MCG)
-#define MCG_C3 MCG_C3_REG(MCG)
-#define MCG_C4 MCG_C4_REG(MCG)
-#define MCG_C5 MCG_C5_REG(MCG)
-#define MCG_C6 MCG_C6_REG(MCG)
-#define MCG_S MCG_S_REG(MCG)
-#define MCG_SC MCG_SC_REG(MCG)
-#define MCG_ATCVH MCG_ATCVH_REG(MCG)
-#define MCG_ATCVL MCG_ATCVL_REG(MCG)
-#define MCG_C7 MCG_C7_REG(MCG)
-#define MCG_C8 MCG_C8_REG(MCG)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group MCG_Peripheral_Access_Layer */
@@ -7226,29 +4998,7 @@ typedef struct {
__IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
uint8_t RESERVED_1[44];
__IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
-} MCM_Type, *MCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register accessors */
-#define MCM_PLASC_REG(base) ((base)->PLASC)
-#define MCM_PLAMC_REG(base) ((base)->PLAMC)
-#define MCM_PLACR_REG(base) ((base)->PLACR)
-#define MCM_ISCR_REG(base) ((base)->ISCR)
-#define MCM_CPO_REG(base) ((base)->CPO)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
+} MCM_Type;
/* ----------------------------------------------------------------------------
-- MCM Register Masks
@@ -7259,83 +5009,70 @@ typedef struct {
* @{
*/
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK 0xFFu
-#define MCM_PLASC_ASC_SHIFT 0
-#define MCM_PLASC_ASC_WIDTH 8
-#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK 0xFFu
-#define MCM_PLAMC_AMC_SHIFT 0
-#define MCM_PLAMC_AMC_WIDTH 8
-#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* PLACR Bit Fields */
-#define MCM_PLACR_ARB_MASK 0x200u
-#define MCM_PLACR_ARB_SHIFT 9
-#define MCM_PLACR_ARB_WIDTH 1
-#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ARB_SHIFT))&MCM_PLACR_ARB_MASK)
-/* ISCR Bit Fields */
-#define MCM_ISCR_FIOC_MASK 0x100u
-#define MCM_ISCR_FIOC_SHIFT 8
-#define MCM_ISCR_FIOC_WIDTH 1
-#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
-#define MCM_ISCR_FDZC_MASK 0x200u
-#define MCM_ISCR_FDZC_SHIFT 9
-#define MCM_ISCR_FDZC_WIDTH 1
-#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
-#define MCM_ISCR_FOFC_MASK 0x400u
-#define MCM_ISCR_FOFC_SHIFT 10
-#define MCM_ISCR_FOFC_WIDTH 1
-#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
-#define MCM_ISCR_FUFC_MASK 0x800u
-#define MCM_ISCR_FUFC_SHIFT 11
-#define MCM_ISCR_FUFC_WIDTH 1
-#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
-#define MCM_ISCR_FIXC_MASK 0x1000u
-#define MCM_ISCR_FIXC_SHIFT 12
-#define MCM_ISCR_FIXC_WIDTH 1
-#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
-#define MCM_ISCR_FIDC_MASK 0x8000u
-#define MCM_ISCR_FIDC_SHIFT 15
-#define MCM_ISCR_FIDC_WIDTH 1
-#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
-#define MCM_ISCR_FIOCE_MASK 0x1000000u
-#define MCM_ISCR_FIOCE_SHIFT 24
-#define MCM_ISCR_FIOCE_WIDTH 1
-#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
-#define MCM_ISCR_FDZCE_MASK 0x2000000u
-#define MCM_ISCR_FDZCE_SHIFT 25
-#define MCM_ISCR_FDZCE_WIDTH 1
-#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
-#define MCM_ISCR_FOFCE_MASK 0x4000000u
-#define MCM_ISCR_FOFCE_SHIFT 26
-#define MCM_ISCR_FOFCE_WIDTH 1
-#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
-#define MCM_ISCR_FUFCE_MASK 0x8000000u
-#define MCM_ISCR_FUFCE_SHIFT 27
-#define MCM_ISCR_FUFCE_WIDTH 1
-#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
-#define MCM_ISCR_FIXCE_MASK 0x10000000u
-#define MCM_ISCR_FIXCE_SHIFT 28
-#define MCM_ISCR_FIXCE_WIDTH 1
-#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
-#define MCM_ISCR_FIDCE_MASK 0x80000000u
-#define MCM_ISCR_FIDCE_SHIFT 31
-#define MCM_ISCR_FIDCE_WIDTH 1
-#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
-/* CPO Bit Fields */
-#define MCM_CPO_CPOREQ_MASK 0x1u
-#define MCM_CPO_CPOREQ_SHIFT 0
-#define MCM_CPO_CPOREQ_WIDTH 1
-#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
-#define MCM_CPO_CPOACK_MASK 0x2u
-#define MCM_CPO_CPOACK_SHIFT 1
-#define MCM_CPO_CPOACK_WIDTH 1
-#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
-#define MCM_CPO_CPOWOI_MASK 0x4u
-#define MCM_CPO_CPOWOI_SHIFT 2
-#define MCM_CPO_CPOWOI_WIDTH 1
-#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK (0xFFU)
+#define MCM_PLASC_ASC_SHIFT (0U)
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT (0U)
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name PLACR - Crossbar Switch (AXBS) Control Register */
+#define MCM_PLACR_ARB_MASK (0x200U)
+#define MCM_PLACR_ARB_SHIFT (9U)
+#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
+
+/*! @name ISCR - Interrupt Status and Control Register */
+#define MCM_ISCR_FIOC_MASK (0x100U)
+#define MCM_ISCR_FIOC_SHIFT (8U)
+#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK (0x200U)
+#define MCM_ISCR_FDZC_SHIFT (9U)
+#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK (0x400U)
+#define MCM_ISCR_FOFC_SHIFT (10U)
+#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK (0x800U)
+#define MCM_ISCR_FUFC_SHIFT (11U)
+#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK (0x1000U)
+#define MCM_ISCR_FIXC_SHIFT (12U)
+#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK (0x8000U)
+#define MCM_ISCR_FIDC_SHIFT (15U)
+#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK (0x1000000U)
+#define MCM_ISCR_FIOCE_SHIFT (24U)
+#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK (0x2000000U)
+#define MCM_ISCR_FDZCE_SHIFT (25U)
+#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK (0x4000000U)
+#define MCM_ISCR_FOFCE_SHIFT (26U)
+#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK (0x8000000U)
+#define MCM_ISCR_FUFCE_SHIFT (27U)
+#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK (0x10000000U)
+#define MCM_ISCR_FIXCE_SHIFT (28U)
+#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK (0x80000000U)
+#define MCM_ISCR_FIDCE_SHIFT (31U)
+#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+
+/*! @name CPO - Compute Operation Control Register */
+#define MCM_CPO_CPOREQ_MASK (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT (0U)
+#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK (0x2U)
+#define MCM_CPO_CPOACK_SHIFT (1U)
+#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT (2U)
+#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+
/*!
* @}
@@ -7347,7 +5084,6 @@ typedef struct {
#define MCM_BASE (0xE0080000u)
/** Peripheral MCM base pointer */
#define MCM ((MCM_Type *)MCM_BASE)
-#define MCM_BASE_PTR (MCM)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
@@ -7355,29 +5091,6 @@ typedef struct {
/** Interrupt vectors for the MCM peripheral type */
#define MCM_IRQS { MCM_IRQn }
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register instance definitions */
-/* MCM */
-#define MCM_PLASC MCM_PLASC_REG(MCM)
-#define MCM_PLAMC MCM_PLAMC_REG(MCM)
-#define MCM_PLACR MCM_PLACR_REG(MCM)
-#define MCM_ISCR MCM_ISCR_REG(MCM)
-#define MCM_CPO MCM_CPO_REG(MCM)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
@@ -7408,38 +5121,7 @@ typedef struct {
__I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
__I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
-} NV_Type, *NV_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register accessors */
-#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
-#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
-#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
-#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
-#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
-#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
-#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
-#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
-#define NV_FPROT3_REG(base) ((base)->FPROT3)
-#define NV_FPROT2_REG(base) ((base)->FPROT2)
-#define NV_FPROT1_REG(base) ((base)->FPROT1)
-#define NV_FPROT0_REG(base) ((base)->FPROT0)
-#define NV_FSEC_REG(base) ((base)->FSEC)
-#define NV_FOPT_REG(base) ((base)->FOPT)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
+} NV_Type;
/* ----------------------------------------------------------------------------
-- NV Register Masks
@@ -7450,100 +5132,94 @@ typedef struct {
* @{
*/
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY_WIDTH 8
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY_WIDTH 8
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY_WIDTH 8
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY_WIDTH 8
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY_WIDTH 8
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY_WIDTH 8
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY_WIDTH 8
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY_WIDTH 8
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT_WIDTH 8
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT_WIDTH 8
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT_WIDTH 8
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT_WIDTH 8
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC_WIDTH 2
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC_WIDTH 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN_WIDTH 2
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN_WIDTH 2
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK 0x1u
-#define NV_FOPT_LPBOOT_SHIFT 0
-#define NV_FOPT_LPBOOT_WIDTH 1
-#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-#define NV_FOPT_EZPORT_DIS_WIDTH 1
-#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
-#define NV_FOPT_NMI_DIS_MASK 0x4u
-#define NV_FOPT_NMI_DIS_SHIFT 2
-#define NV_FOPT_NMI_DIS_WIDTH 1
-#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
-#define NV_FOPT_FAST_INIT_MASK 0x20u
-#define NV_FOPT_FAST_INIT_SHIFT 5
-#define NV_FOPT_FAST_INIT_WIDTH 1
-#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_FAST_INIT_SHIFT))&NV_FOPT_FAST_INIT_MASK)
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT (0U)
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT (0U)
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT (0U)
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT (0U)
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT (0U)
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT (0U)
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT (0U)
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT (0U)
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK (0xFFU)
+#define NV_FPROT3_PROT_SHIFT (0U)
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK (0xFFU)
+#define NV_FPROT2_PROT_SHIFT (0U)
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK (0xFFU)
+#define NV_FPROT1_PROT_SHIFT (0U)
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK (0xFFU)
+#define NV_FPROT0_PROT_SHIFT (0U)
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK (0x3U)
+#define NV_FSEC_SEC_SHIFT (0U)
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK (0xCU)
+#define NV_FSEC_FSLACC_SHIFT (2U)
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK (0x30U)
+#define NV_FSEC_MEEN_SHIFT (4U)
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT (6U)
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT_MASK (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT (0U)
+#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
+#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
+#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_NMI_DIS_MASK (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT (2U)
+#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_FAST_INIT_MASK (0x20U)
+#define NV_FOPT_FAST_INIT_SHIFT (5U)
+#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
+
/*!
* @}
@@ -7555,44 +5231,11 @@ typedef struct {
#define FTFA_FlashConfig_BASE (0x400u)
/** Peripheral FTFA_FlashConfig base pointer */
#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
-#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
/** Array initializer of NV peripheral base addresses */
#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
/** Array initializer of NV peripheral base pointers */
#define NV_BASE_PTRS { FTFA_FlashConfig }
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register instance definitions */
-/* FTFA_FlashConfig */
-#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
-#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
-#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
-#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
-#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
-#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
-#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
-#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
-#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
-#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
-#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
-#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
-#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
-#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
@@ -7612,26 +5255,7 @@ typedef struct {
__IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
uint8_t RESERVED_0[1];
__IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
-} OSC_Type, *OSC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register accessors */
-#define OSC_CR_REG(base) ((base)->CR)
-#define OSC_DIV_REG(base) ((base)->DIV)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
+} OSC_Type;
/* ----------------------------------------------------------------------------
-- OSC Register Masks
@@ -7642,36 +5266,31 @@ typedef struct {
* @{
*/
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC16P_WIDTH 1
-#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC8P_WIDTH 1
-#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC4P_WIDTH 1
-#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_SC2P_WIDTH 1
-#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_EREFSTEN_WIDTH 1
-#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-#define OSC_CR_ERCLKEN_WIDTH 1
-#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
-/* DIV Bit Fields */
-#define OSC_DIV_ERPS_MASK 0xC0u
-#define OSC_DIV_ERPS_SHIFT 6
-#define OSC_DIV_ERPS_WIDTH 2
-#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK (0x1U)
+#define OSC_CR_SC16P_SHIFT (0U)
+#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK (0x2U)
+#define OSC_CR_SC8P_SHIFT (1U)
+#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK (0x4U)
+#define OSC_CR_SC4P_SHIFT (2U)
+#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK (0x8U)
+#define OSC_CR_SC2P_SHIFT (3U)
+#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT (5U)
+#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT (7U)
+#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
+/*! @name DIV - OSC_DIV */
+#define OSC_DIV_ERPS_MASK (0xC0U)
+#define OSC_DIV_ERPS_SHIFT (6U)
+#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
+
/*!
* @}
@@ -7683,32 +5302,11 @@ typedef struct {
#define OSC_BASE (0x40065000u)
/** Peripheral OSC base pointer */
#define OSC ((OSC_Type *)OSC_BASE)
-#define OSC_BASE_PTR (OSC)
/** Array initializer of OSC peripheral base addresses */
#define OSC_BASE_ADDRS { OSC_BASE }
/** Array initializer of OSC peripheral base pointers */
#define OSC_BASE_PTRS { OSC }
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register instance definitions */
-/* OSC */
-#define OSC_CR OSC_CR_REG(OSC)
-#define OSC_DIV OSC_DIV_REG(OSC)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group OSC_Peripheral_Access_Layer */
@@ -7743,42 +5341,7 @@ typedef struct {
uint8_t RESERVED_1[56];
__IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
__IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
-} PDB_Type, *PDB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register accessors */
-#define PDB_SC_REG(base) ((base)->SC)
-#define PDB_MOD_REG(base) ((base)->MOD)
-#define PDB_CNT_REG(base) ((base)->CNT)
-#define PDB_IDLY_REG(base) ((base)->IDLY)
-#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
-#define PDB_C1_COUNT 2
-#define PDB_S_REG(base,index) ((base)->CH[index].S)
-#define PDB_S_COUNT 2
-#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
-#define PDB_DLY_COUNT 2
-#define PDB_DLY_COUNT2 2
-#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
-#define PDB_INTC_COUNT 1
-#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
-#define PDB_INT_COUNT 1
-#define PDB_POEN_REG(base) ((base)->POEN)
-#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
-#define PDB_PODLY_COUNT 2
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
+} PDB_Type;
/* ----------------------------------------------------------------------------
-- PDB Register Masks
@@ -7789,125 +5352,130 @@ typedef struct {
* @{
*/
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK 0x1u
-#define PDB_SC_LDOK_SHIFT 0
-#define PDB_SC_LDOK_WIDTH 1
-#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
-#define PDB_SC_CONT_MASK 0x2u
-#define PDB_SC_CONT_SHIFT 1
-#define PDB_SC_CONT_WIDTH 1
-#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
-#define PDB_SC_MULT_MASK 0xCu
-#define PDB_SC_MULT_SHIFT 2
-#define PDB_SC_MULT_WIDTH 2
-#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK 0x20u
-#define PDB_SC_PDBIE_SHIFT 5
-#define PDB_SC_PDBIE_WIDTH 1
-#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
-#define PDB_SC_PDBIF_MASK 0x40u
-#define PDB_SC_PDBIF_SHIFT 6
-#define PDB_SC_PDBIF_WIDTH 1
-#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
-#define PDB_SC_PDBEN_MASK 0x80u
-#define PDB_SC_PDBEN_SHIFT 7
-#define PDB_SC_PDBEN_WIDTH 1
-#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
-#define PDB_SC_TRGSEL_MASK 0xF00u
-#define PDB_SC_TRGSEL_SHIFT 8
-#define PDB_SC_TRGSEL_WIDTH 4
-#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK 0x7000u
-#define PDB_SC_PRESCALER_SHIFT 12
-#define PDB_SC_PRESCALER_WIDTH 3
-#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK 0x8000u
-#define PDB_SC_DMAEN_SHIFT 15
-#define PDB_SC_DMAEN_WIDTH 1
-#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
-#define PDB_SC_SWTRIG_MASK 0x10000u
-#define PDB_SC_SWTRIG_SHIFT 16
-#define PDB_SC_SWTRIG_WIDTH 1
-#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
-#define PDB_SC_PDBEIE_MASK 0x20000u
-#define PDB_SC_PDBEIE_SHIFT 17
-#define PDB_SC_PDBEIE_WIDTH 1
-#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
-#define PDB_SC_LDMOD_MASK 0xC0000u
-#define PDB_SC_LDMOD_SHIFT 18
-#define PDB_SC_LDMOD_WIDTH 2
-#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK 0xFFFFu
-#define PDB_MOD_MOD_SHIFT 0
-#define PDB_MOD_MOD_WIDTH 16
-#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK 0xFFFFu
-#define PDB_CNT_CNT_SHIFT 0
-#define PDB_CNT_CNT_WIDTH 16
-#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK 0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT 0
-#define PDB_IDLY_IDLY_WIDTH 16
-#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK 0xFFu
-#define PDB_C1_EN_SHIFT 0
-#define PDB_C1_EN_WIDTH 8
-#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK 0xFF00u
-#define PDB_C1_TOS_SHIFT 8
-#define PDB_C1_TOS_WIDTH 8
-#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK 0xFF0000u
-#define PDB_C1_BB_SHIFT 16
-#define PDB_C1_BB_WIDTH 8
-#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK 0xFFu
-#define PDB_S_ERR_SHIFT 0
-#define PDB_S_ERR_WIDTH 8
-#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK 0xFF0000u
-#define PDB_S_CF_SHIFT 16
-#define PDB_S_CF_WIDTH 8
-#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK 0xFFFFu
-#define PDB_DLY_DLY_SHIFT 0
-#define PDB_DLY_DLY_WIDTH 16
-#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* INTC Bit Fields */
-#define PDB_INTC_TOE_MASK 0x1u
-#define PDB_INTC_TOE_SHIFT 0
-#define PDB_INTC_TOE_WIDTH 1
-#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
-#define PDB_INTC_EXT_MASK 0x2u
-#define PDB_INTC_EXT_SHIFT 1
-#define PDB_INTC_EXT_WIDTH 1
-#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
-/* INT Bit Fields */
-#define PDB_INT_INT_MASK 0xFFFFu
-#define PDB_INT_INT_SHIFT 0
-#define PDB_INT_INT_WIDTH 16
-#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK 0xFFu
-#define PDB_POEN_POEN_SHIFT 0
-#define PDB_POEN_POEN_WIDTH 8
-#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK 0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT 0
-#define PDB_PODLY_DLY2_WIDTH 16
-#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT 16
-#define PDB_PODLY_DLY1_WIDTH 16
-#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+/*! @name SC - Status and Control register */
+#define PDB_SC_LDOK_MASK (0x1U)
+#define PDB_SC_LDOK_SHIFT (0U)
+#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK (0x2U)
+#define PDB_SC_CONT_SHIFT (1U)
+#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK (0xCU)
+#define PDB_SC_MULT_SHIFT (2U)
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK (0x20U)
+#define PDB_SC_PDBIE_SHIFT (5U)
+#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK (0x40U)
+#define PDB_SC_PDBIF_SHIFT (6U)
+#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK (0x80U)
+#define PDB_SC_PDBEN_SHIFT (7U)
+#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT (8U)
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT (12U)
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK (0x8000U)
+#define PDB_SC_DMAEN_SHIFT (15U)
+#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK (0x10000U)
+#define PDB_SC_SWTRIG_SHIFT (16U)
+#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK (0x20000U)
+#define PDB_SC_PDBEIE_SHIFT (17U)
+#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT (18U)
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+
+/*! @name MOD - Modulus register */
+#define PDB_MOD_MOD_MASK (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT (0U)
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+
+/*! @name CNT - Counter register */
+#define PDB_CNT_CNT_MASK (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT (0U)
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+
+/*! @name IDLY - Interrupt Delay register */
+#define PDB_IDLY_IDLY_MASK (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT (0U)
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+
+/*! @name C1 - Channel n Control register 1 */
+#define PDB_C1_EN_MASK (0xFFU)
+#define PDB_C1_EN_SHIFT (0U)
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK (0xFF00U)
+#define PDB_C1_TOS_SHIFT (8U)
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK (0xFF0000U)
+#define PDB_C1_BB_SHIFT (16U)
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT (2U)
+
+/*! @name S - Channel n Status register */
+#define PDB_S_ERR_MASK (0xFFU)
+#define PDB_S_ERR_SHIFT (0U)
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK (0xFF0000U)
+#define PDB_S_CF_SHIFT (16U)
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+
+/* The count of PDB_S */
+#define PDB_S_COUNT (2U)
+
+/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
+#define PDB_DLY_DLY_MASK (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT (0U)
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT (2U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2 (2U)
+
+/*! @name INTC - DAC Interval Trigger n Control register */
+#define PDB_INTC_TOE_MASK (0x1U)
+#define PDB_INTC_TOE_SHIFT (0U)
+#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK (0x2U)
+#define PDB_INTC_EXT_SHIFT (1U)
+#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+
+/* The count of PDB_INTC */
+#define PDB_INTC_COUNT (1U)
+
+/*! @name INT - DAC Interval n register */
+#define PDB_INT_INT_MASK (0xFFFFU)
+#define PDB_INT_INT_SHIFT (0U)
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+
+/* The count of PDB_INT */
+#define PDB_INT_COUNT (1U)
+
+/*! @name POEN - Pulse-Out n Enable register */
+#define PDB_POEN_POEN_MASK (0xFFU)
+#define PDB_POEN_POEN_SHIFT (0U)
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+
+/*! @name PODLY - Pulse-Out n Delay register */
+#define PDB_PODLY_DLY2_MASK (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT (0U)
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT (16U)
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT (2U)
+
/*!
* @}
@@ -7919,7 +5487,6 @@ typedef struct {
#define PDB0_BASE (0x40036000u)
/** Peripheral PDB0 base pointer */
#define PDB0 ((PDB_Type *)PDB0_BASE)
-#define PDB0_BASE_PTR (PDB0)
/** Array initializer of PDB peripheral base addresses */
#define PDB_BASE_ADDRS { PDB0_BASE }
/** Array initializer of PDB peripheral base pointers */
@@ -7927,49 +5494,6 @@ typedef struct {
/** Interrupt vectors for the PDB peripheral type */
#define PDB_IRQS { PDB0_IRQn }
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register instance definitions */
-/* PDB0 */
-#define PDB0_SC PDB_SC_REG(PDB0)
-#define PDB0_MOD PDB_MOD_REG(PDB0)
-#define PDB0_CNT PDB_CNT_REG(PDB0)
-#define PDB0_IDLY PDB_IDLY_REG(PDB0)
-#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
-#define PDB0_CH0S PDB_S_REG(PDB0,0)
-#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
-#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
-#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
-#define PDB0_CH1S PDB_S_REG(PDB0,1)
-#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
-#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
-#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
-#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
-#define PDB0_POEN PDB_POEN_REG(PDB0)
-#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
-#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
-
-/* PDB - Register array accessors */
-#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
-#define PDB0_S(index) PDB_S_REG(PDB0,index)
-#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
-#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
-#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
-#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PDB_Peripheral_Access_Layer */
@@ -7994,80 +5518,63 @@ typedef struct {
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[4];
-} PIT_Type, *PIT_MemMapPtr;
+} PIT_Type;
/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
+ -- PIT Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK (0x1U)
+#define PIT_MCR_FRZ_SHIFT (0U)
+#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK (0x2U)
+#define PIT_MCR_MDIS_SHIFT (1U)
+#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
-/* PIT - Register accessors */
-#define PIT_MCR_REG(base) ((base)->MCR)
-#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
-#define PIT_LDVAL_COUNT 4
-#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
-#define PIT_CVAL_COUNT 4
-#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
-#define PIT_TCTRL_COUNT 4
-#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
-#define PIT_TFLG_COUNT 4
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT (0U)
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT (4U)
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT (0U)
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT (4U)
-/*!
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK (0x1U)
+#define PIT_TCTRL_TEN_SHIFT (0U)
+#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK (0x2U)
+#define PIT_TCTRL_TIE_SHIFT (1U)
+#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK (0x4U)
+#define PIT_TCTRL_CHN_SHIFT (2U)
+#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK (0x1U)
+#define PIT_TFLG_TIF_SHIFT (0U)
+#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT (4U)
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_FRZ_WIDTH 1
-#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-#define PIT_MCR_MDIS_WIDTH 1
-#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV_WIDTH 32
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL_WIDTH 32
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TEN_WIDTH 1
-#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-#define PIT_TCTRL_TIE_WIDTH 1
-#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
-#define PIT_TCTRL_CHN_MASK 0x4u
-#define PIT_TCTRL_CHN_SHIFT 2
-#define PIT_TCTRL_CHN_WIDTH 1
-#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-#define PIT_TFLG_TIF_WIDTH 1
-#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
/*!
* @}
@@ -8079,54 +5586,12 @@ typedef struct {
#define PIT_BASE (0x40037000u)
/** Peripheral PIT base pointer */
#define PIT ((PIT_Type *)PIT_BASE)
-#define PIT_BASE_PTR (PIT)
/** Array initializer of PIT peripheral base addresses */
#define PIT_BASE_ADDRS { PIT_BASE }
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASE_PTRS { PIT }
/** Interrupt vectors for the PIT peripheral type */
-#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register instance definitions */
-/* PIT */
-#define PIT_MCR PIT_MCR_REG(PIT)
-#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
-#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
-#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
-#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
-#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
-#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
-#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
-#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
-#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
-#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
-#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
-#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
-#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
-#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
-#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
-#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
-
-/* PIT - Register array accessors */
-#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
-#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
-#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
-#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
+#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
/*!
* @}
@@ -8147,27 +5612,7 @@ typedef struct {
__IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
__IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
__IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type, *PMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register accessors */
-#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
-#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
-#define PMC_REGSC_REG(base) ((base)->REGSC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
+} PMC_Type;
/* ----------------------------------------------------------------------------
-- PMC Register Masks
@@ -8178,61 +5623,51 @@ typedef struct {
* @{
*/
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV_WIDTH 2
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDRE_WIDTH 1
-#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDIE_WIDTH 1
-#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDACK_WIDTH 1
-#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-#define PMC_LVDSC1_LVDF_WIDTH 1
-#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV_WIDTH 2
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWIE_WIDTH 1
-#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWACK_WIDTH 1
-#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-#define PMC_LVDSC2_LVWF_WIDTH 1
-#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_BGBE_WIDTH 1
-#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_REGONS_WIDTH 1
-#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-#define PMC_REGSC_ACKISO_WIDTH 1
-#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
-#define PMC_REGSC_BGEN_MASK 0x10u
-#define PMC_REGSC_BGEN_SHIFT 4
-#define PMC_REGSC_BGEN_WIDTH 1
-#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT (0U)
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT (4U)
+#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT (5U)
+#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT (6U)
+#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT (7U)
+#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT (0U)
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT (5U)
+#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT (6U)
+#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT (7U)
+#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK (0x1U)
+#define PMC_REGSC_BGBE_SHIFT (0U)
+#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK (0x4U)
+#define PMC_REGSC_REGONS_SHIFT (2U)
+#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT (3U)
+#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK (0x10U)
+#define PMC_REGSC_BGEN_SHIFT (4U)
+#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+
/*!
* @}
@@ -8244,7 +5679,6 @@ typedef struct {
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
-#define PMC_BASE_PTR (PMC)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS { PMC_BASE }
/** Array initializer of PMC peripheral base pointers */
@@ -8252,27 +5686,6 @@ typedef struct {
/** Interrupt vectors for the PMC peripheral type */
#define PMC_IRQS { LVD_LVW_IRQn }
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register instance definitions */
-/* PMC */
-#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
-#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
-#define PMC_REGSC PMC_REGSC_REG(PMC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
@@ -8298,32 +5711,7 @@ typedef struct {
__IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type, *PORT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register accessors */
-#define PORT_PCR_REG(base,index) ((base)->PCR[index])
-#define PORT_PCR_COUNT 32
-#define PORT_GPCLR_REG(base) ((base)->GPCLR)
-#define PORT_GPCHR_REG(base) ((base)->GPCHR)
-#define PORT_ISFR_REG(base) ((base)->ISFR)
-#define PORT_DFER_REG(base) ((base)->DFER)
-#define PORT_DFCR_REG(base) ((base)->DFCR)
-#define PORT_DFWR_REG(base) ((base)->DFWR)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
+} PORT_Type;
/* ----------------------------------------------------------------------------
-- PORT Register Masks
@@ -8334,85 +5722,77 @@ typedef struct {
* @{
*/
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PS_WIDTH 1
-#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_PE_WIDTH 1
-#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_SRE_WIDTH 1
-#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_PFE_WIDTH 1
-#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
-#define PORT_PCR_ODE_MASK 0x20u
-#define PORT_PCR_ODE_SHIFT 5
-#define PORT_PCR_ODE_WIDTH 1
-#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_DSE_WIDTH 1
-#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX_WIDTH 3
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK 0x8000u
-#define PORT_PCR_LK_SHIFT 15
-#define PORT_PCR_LK_WIDTH 1
-#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC_WIDTH 4
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-#define PORT_PCR_ISF_WIDTH 1
-#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD_WIDTH 16
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE_WIDTH 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD_WIDTH 16
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE_WIDTH 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF_WIDTH 32
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT 0
-#define PORT_DFER_DFE_WIDTH 32
-#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK 0x1u
-#define PORT_DFCR_CS_SHIFT 0
-#define PORT_DFCR_CS_WIDTH 1
-#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK 0x1Fu
-#define PORT_DFWR_FILT_SHIFT 0
-#define PORT_DFWR_FILT_WIDTH 5
-#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK (0x1U)
+#define PORT_PCR_PS_SHIFT (0U)
+#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK (0x2U)
+#define PORT_PCR_PE_SHIFT (1U)
+#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK (0x4U)
+#define PORT_PCR_SRE_SHIFT (2U)
+#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK (0x10U)
+#define PORT_PCR_PFE_SHIFT (4U)
+#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK (0x20U)
+#define PORT_PCR_ODE_SHIFT (5U)
+#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK (0x40U)
+#define PORT_PCR_DSE_SHIFT (6U)
+#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK (0x700U)
+#define PORT_PCR_MUX_SHIFT (8U)
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK (0x8000U)
+#define PORT_PCR_LK_SHIFT (15U)
+#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT (16U)
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK (0x1000000U)
+#define PORT_PCR_ISF_SHIFT (24U)
+#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT (0U)
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT (16U)
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT (0U)
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT (16U)
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT (0U)
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+/*! @name DFER - Digital Filter Enable Register */
+#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT (0U)
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+
+/*! @name DFCR - Digital Filter Clock Register */
+#define PORT_DFCR_CS_MASK (0x1U)
+#define PORT_DFCR_CS_SHIFT (0U)
+#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+
+/*! @name DFWR - Digital Filter Width Register */
+#define PORT_DFWR_FILT_MASK (0x1FU)
+#define PORT_DFWR_FILT_SHIFT (0U)
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+
/*!
* @}
@@ -8424,27 +5804,22 @@ typedef struct {
#define PORTA_BASE (0x40049000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
-#define PORTA_BASE_PTR (PORTA)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4004A000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
-#define PORTB_BASE_PTR (PORTB)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x4004B000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
-#define PORTC_BASE_PTR (PORTC)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4004C000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
-#define PORTD_BASE_PTR (PORTD)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4004D000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
-#define PORTE_BASE_PTR (PORTE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
/** Array initializer of PORT peripheral base pointers */
@@ -8452,213 +5827,6 @@ typedef struct {
/** Interrupt vectors for the PORT peripheral type */
#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register instance definitions */
-/* PORTA */
-#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
-#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
-#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
-#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
-#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
-#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
-#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
-#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
-#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
-#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
-#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
-#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
-#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
-#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
-#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
-#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
-#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
-#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
-#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
-#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
-#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
-#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
-#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
-#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
-#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
-#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
-#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
-#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
-#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
-#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
-#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
-#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
-#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
-#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
-#define PORTA_ISFR PORT_ISFR_REG(PORTA)
-/* PORTB */
-#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
-#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
-#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
-#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
-#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
-#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
-#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
-#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
-#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
-#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
-#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
-#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
-#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
-#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
-#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
-#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
-#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
-#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
-#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
-#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
-#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
-#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
-#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
-#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
-#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
-#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
-#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
-#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
-#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
-#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
-#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
-#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
-#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
-#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
-#define PORTB_ISFR PORT_ISFR_REG(PORTB)
-/* PORTC */
-#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
-#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
-#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
-#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
-#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
-#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
-#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
-#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
-#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
-#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
-#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
-#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
-#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
-#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
-#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
-#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
-#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
-#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
-#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
-#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
-#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
-#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
-#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
-#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
-#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
-#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
-#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
-#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
-#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
-#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
-#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
-#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
-#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
-#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
-#define PORTC_ISFR PORT_ISFR_REG(PORTC)
-/* PORTD */
-#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
-#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
-#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
-#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
-#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
-#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
-#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
-#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
-#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
-#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
-#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
-#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
-#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
-#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
-#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
-#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
-#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
-#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
-#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
-#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
-#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
-#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
-#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
-#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
-#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
-#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
-#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
-#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
-#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
-#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
-#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
-#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
-#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
-#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
-#define PORTD_ISFR PORT_ISFR_REG(PORTD)
-#define PORTD_DFER PORT_DFER_REG(PORTD)
-#define PORTD_DFCR PORT_DFCR_REG(PORTD)
-#define PORTD_DFWR PORT_DFWR_REG(PORTD)
-/* PORTE */
-#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
-#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
-#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
-#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
-#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
-#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
-#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
-#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
-#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
-#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
-#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
-#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
-#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
-#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
-#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
-#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
-#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
-#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
-#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
-#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
-#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
-#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
-#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
-#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
-#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
-#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
-#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
-#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
-#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
-#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
-#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
-#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
-#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
-#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
-#define PORTE_ISFR PORT_ISFR_REG(PORTE)
-
-/* PORT - Register array accessors */
-#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
-#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
-#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
-#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
-#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
@@ -8684,31 +5852,7 @@ typedef struct {
__I uint8_t MR; /**< Mode Register, offset: 0x7 */
__IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
__IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
-} RCM_Type, *RCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register accessors */
-#define RCM_SRS0_REG(base) ((base)->SRS0)
-#define RCM_SRS1_REG(base) ((base)->SRS1)
-#define RCM_RPFC_REG(base) ((base)->RPFC)
-#define RCM_RPFW_REG(base) ((base)->RPFW)
-#define RCM_MR_REG(base) ((base)->MR)
-#define RCM_SSRS0_REG(base) ((base)->SSRS0)
-#define RCM_SSRS1_REG(base) ((base)->SSRS1)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
+} RCM_Type;
/* ----------------------------------------------------------------------------
-- RCM Register Masks
@@ -8719,133 +5863,110 @@ typedef struct {
* @{
*/
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_WAKEUP_WIDTH 1
-#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LVD_WIDTH 1
-#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOC_WIDTH 1
-#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
-#define RCM_SRS0_LOL_MASK 0x8u
-#define RCM_SRS0_LOL_SHIFT 3
-#define RCM_SRS0_LOL_WIDTH 1
-#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_WDOG_WIDTH 1
-#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_PIN_WIDTH 1
-#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-#define RCM_SRS0_POR_WIDTH 1
-#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK 0x1u
-#define RCM_SRS1_JTAG_SHIFT 0
-#define RCM_SRS1_JTAG_WIDTH 1
-#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_LOCKUP_WIDTH 1
-#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_SW_WIDTH 1
-#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_MDM_AP_WIDTH 1
-#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
-#define RCM_SRS1_EZPT_MASK 0x10u
-#define RCM_SRS1_EZPT_SHIFT 4
-#define RCM_SRS1_EZPT_WIDTH 1
-#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-#define RCM_SRS1_SACKERR_WIDTH 1
-#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW_WIDTH 2
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-#define RCM_RPFC_RSTFLTSS_WIDTH 1
-#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL_WIDTH 5
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK 0x2u
-#define RCM_MR_EZP_MS_SHIFT 1
-#define RCM_MR_EZP_MS_WIDTH 1
-#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
-/* SSRS0 Bit Fields */
-#define RCM_SSRS0_SWAKEUP_MASK 0x1u
-#define RCM_SSRS0_SWAKEUP_SHIFT 0
-#define RCM_SSRS0_SWAKEUP_WIDTH 1
-#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWAKEUP_SHIFT))&RCM_SSRS0_SWAKEUP_MASK)
-#define RCM_SSRS0_SLVD_MASK 0x2u
-#define RCM_SSRS0_SLVD_SHIFT 1
-#define RCM_SSRS0_SLVD_WIDTH 1
-#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLVD_SHIFT))&RCM_SSRS0_SLVD_MASK)
-#define RCM_SSRS0_SLOC_MASK 0x4u
-#define RCM_SSRS0_SLOC_SHIFT 2
-#define RCM_SSRS0_SLOC_WIDTH 1
-#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLOC_SHIFT))&RCM_SSRS0_SLOC_MASK)
-#define RCM_SSRS0_SLOL_MASK 0x8u
-#define RCM_SSRS0_SLOL_SHIFT 3
-#define RCM_SSRS0_SLOL_WIDTH 1
-#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLOL_SHIFT))&RCM_SSRS0_SLOL_MASK)
-#define RCM_SSRS0_SWDOG_MASK 0x20u
-#define RCM_SSRS0_SWDOG_SHIFT 5
-#define RCM_SSRS0_SWDOG_WIDTH 1
-#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWDOG_SHIFT))&RCM_SSRS0_SWDOG_MASK)
-#define RCM_SSRS0_SPIN_MASK 0x40u
-#define RCM_SSRS0_SPIN_SHIFT 6
-#define RCM_SSRS0_SPIN_WIDTH 1
-#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPIN_SHIFT))&RCM_SSRS0_SPIN_MASK)
-#define RCM_SSRS0_SPOR_MASK 0x80u
-#define RCM_SSRS0_SPOR_SHIFT 7
-#define RCM_SSRS0_SPOR_WIDTH 1
-#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPOR_SHIFT))&RCM_SSRS0_SPOR_MASK)
-/* SSRS1 Bit Fields */
-#define RCM_SSRS1_SJTAG_MASK 0x1u
-#define RCM_SSRS1_SJTAG_SHIFT 0
-#define RCM_SSRS1_SJTAG_WIDTH 1
-#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SJTAG_SHIFT))&RCM_SSRS1_SJTAG_MASK)
-#define RCM_SSRS1_SLOCKUP_MASK 0x2u
-#define RCM_SSRS1_SLOCKUP_SHIFT 1
-#define RCM_SSRS1_SLOCKUP_WIDTH 1
-#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SLOCKUP_SHIFT))&RCM_SSRS1_SLOCKUP_MASK)
-#define RCM_SSRS1_SSW_MASK 0x4u
-#define RCM_SSRS1_SSW_SHIFT 2
-#define RCM_SSRS1_SSW_WIDTH 1
-#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSW_SHIFT))&RCM_SSRS1_SSW_MASK)
-#define RCM_SSRS1_SMDM_AP_MASK 0x8u
-#define RCM_SSRS1_SMDM_AP_SHIFT 3
-#define RCM_SSRS1_SMDM_AP_WIDTH 1
-#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SMDM_AP_SHIFT))&RCM_SSRS1_SMDM_AP_MASK)
-#define RCM_SSRS1_SEZPT_MASK 0x10u
-#define RCM_SSRS1_SEZPT_SHIFT 4
-#define RCM_SSRS1_SEZPT_WIDTH 1
-#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SEZPT_SHIFT))&RCM_SSRS1_SEZPT_MASK)
-#define RCM_SSRS1_SSACKERR_MASK 0x20u
-#define RCM_SSRS1_SSACKERR_SHIFT 5
-#define RCM_SSRS1_SSACKERR_WIDTH 1
-#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSACKERR_SHIFT))&RCM_SSRS1_SSACKERR_MASK)
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT (0U)
+#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK (0x2U)
+#define RCM_SRS0_LVD_SHIFT (1U)
+#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK (0x4U)
+#define RCM_SRS0_LOC_SHIFT (2U)
+#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK (0x8U)
+#define RCM_SRS0_LOL_SHIFT (3U)
+#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK (0x20U)
+#define RCM_SRS0_WDOG_SHIFT (5U)
+#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK (0x40U)
+#define RCM_SRS0_PIN_SHIFT (6U)
+#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK (0x80U)
+#define RCM_SRS0_POR_SHIFT (7U)
+#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_JTAG_MASK (0x1U)
+#define RCM_SRS1_JTAG_SHIFT (0U)
+#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT (1U)
+#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK (0x4U)
+#define RCM_SRS1_SW_SHIFT (2U)
+#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT (3U)
+#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK (0x10U)
+#define RCM_SRS1_EZPT_SHIFT (4U)
+#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT (5U)
+#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
+#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_EZP_MS_MASK (0x2U)
+#define RCM_MR_EZP_MS_SHIFT (1U)
+#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+
+/*! @name SSRS0 - Sticky System Reset Status Register 0 */
+#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
+#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
+#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SLVD_MASK (0x2U)
+#define RCM_SSRS0_SLVD_SHIFT (1U)
+#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SLOC_MASK (0x4U)
+#define RCM_SSRS0_SLOC_SHIFT (2U)
+#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
+#define RCM_SSRS0_SLOL_MASK (0x8U)
+#define RCM_SSRS0_SLOL_SHIFT (3U)
+#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
+#define RCM_SSRS0_SWDOG_MASK (0x20U)
+#define RCM_SSRS0_SWDOG_SHIFT (5U)
+#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SPIN_MASK (0x40U)
+#define RCM_SSRS0_SPIN_SHIFT (6U)
+#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPOR_MASK (0x80U)
+#define RCM_SSRS0_SPOR_SHIFT (7U)
+#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+
+/*! @name SSRS1 - Sticky System Reset Status Register 1 */
+#define RCM_SSRS1_SJTAG_MASK (0x1U)
+#define RCM_SSRS1_SJTAG_SHIFT (0U)
+#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
+#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
+#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
+#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SSW_MASK (0x4U)
+#define RCM_SSRS1_SSW_SHIFT (2U)
+#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
+#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
+#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SEZPT_MASK (0x10U)
+#define RCM_SSRS1_SEZPT_SHIFT (4U)
+#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
+#define RCM_SSRS1_SSACKERR_MASK (0x20U)
+#define RCM_SSRS1_SSACKERR_SHIFT (5U)
+#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+
/*!
* @}
@@ -8857,37 +5978,11 @@ typedef struct {
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
-#define RCM_BASE_PTR (RCM)
/** Array initializer of RCM peripheral base addresses */
#define RCM_BASE_ADDRS { RCM_BASE }
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASE_PTRS { RCM }
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register instance definitions */
-/* RCM */
-#define RCM_SRS0 RCM_SRS0_REG(RCM)
-#define RCM_SRS1 RCM_SRS1_REG(RCM)
-#define RCM_RPFC RCM_RPFC_REG(RCM)
-#define RCM_RPFW RCM_RPFW_REG(RCM)
-#define RCM_MR RCM_MR_REG(RCM)
-#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
-#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
@@ -8905,26 +6000,7 @@ typedef struct {
/** RFSYS - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type, *RFSYS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register accessors */
-#define RFSYS_REG_REG(base,index) ((base)->REG[index])
-#define RFSYS_REG_COUNT 8
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
+} RFSYS_Type;
/* ----------------------------------------------------------------------------
-- RFSYS Register Masks
@@ -8935,23 +6011,23 @@ typedef struct {
* @{
*/
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK 0xFFu
-#define RFSYS_REG_LL_SHIFT 0
-#define RFSYS_REG_LL_WIDTH 8
-#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK 0xFF00u
-#define RFSYS_REG_LH_SHIFT 8
-#define RFSYS_REG_LH_WIDTH 8
-#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK 0xFF0000u
-#define RFSYS_REG_HL_SHIFT 16
-#define RFSYS_REG_HL_WIDTH 8
-#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK 0xFF000000u
-#define RFSYS_REG_HH_SHIFT 24
-#define RFSYS_REG_HH_WIDTH 8
-#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK (0xFFU)
+#define RFSYS_REG_LL_SHIFT (0U)
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK (0xFF00U)
+#define RFSYS_REG_LH_SHIFT (8U)
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT (16U)
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT (24U)
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT (8U)
+
/*!
* @}
@@ -8963,41 +6039,11 @@ typedef struct {
#define RFSYS_BASE (0x40041000u)
/** Peripheral RFSYS base pointer */
#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
-#define RFSYS_BASE_PTR (RFSYS)
/** Array initializer of RFSYS peripheral base addresses */
#define RFSYS_BASE_ADDRS { RFSYS_BASE }
/** Array initializer of RFSYS peripheral base pointers */
#define RFSYS_BASE_PTRS { RFSYS }
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register instance definitions */
-/* RFSYS */
-#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
-#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
-#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
-#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
-#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
-#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
-#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
-#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
-
-/* RFSYS - Register array accessors */
-#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RFSYS_Peripheral_Access_Layer */
@@ -9015,26 +6061,7 @@ typedef struct {
/** RFVBAT - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type, *RFVBAT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register accessors */
-#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
-#define RFVBAT_REG_COUNT 8
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
+} RFVBAT_Type;
/* ----------------------------------------------------------------------------
-- RFVBAT Register Masks
@@ -9045,23 +6072,23 @@ typedef struct {
* @{
*/
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK 0xFFu
-#define RFVBAT_REG_LL_SHIFT 0
-#define RFVBAT_REG_LL_WIDTH 8
-#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK 0xFF00u
-#define RFVBAT_REG_LH_SHIFT 8
-#define RFVBAT_REG_LH_WIDTH 8
-#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK 0xFF0000u
-#define RFVBAT_REG_HL_SHIFT 16
-#define RFVBAT_REG_HL_WIDTH 8
-#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK 0xFF000000u
-#define RFVBAT_REG_HH_SHIFT 24
-#define RFVBAT_REG_HH_WIDTH 8
-#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK (0xFFU)
+#define RFVBAT_REG_LL_SHIFT (0U)
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT (8U)
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT (16U)
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT (24U)
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT (8U)
+
/*!
* @}
@@ -9073,41 +6100,11 @@ typedef struct {
#define RFVBAT_BASE (0x4003E000u)
/** Peripheral RFVBAT base pointer */
#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
-#define RFVBAT_BASE_PTR (RFVBAT)
/** Array initializer of RFVBAT peripheral base addresses */
#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
/** Array initializer of RFVBAT peripheral base pointers */
#define RFVBAT_BASE_PTRS { RFVBAT }
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register instance definitions */
-/* RFVBAT */
-#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
-#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
-#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
-#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
-#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
-#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
-#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
-#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
-
-/* RFVBAT - Register array accessors */
-#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RFVBAT_Peripheral_Access_Layer */
@@ -9127,29 +6124,8 @@ typedef struct {
__IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
__I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
__O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
- __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
-} RNG_Type, *RNG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RNG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register accessors */
-#define RNG_CR_REG(base) ((base)->CR)
-#define RNG_SR_REG(base) ((base)->SR)
-#define RNG_ER_REG(base) ((base)->ER)
-#define RNG_OR_REG(base) ((base)->OR)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
+ __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
+} RNG_Type;
/* ----------------------------------------------------------------------------
-- RNG Register Masks
@@ -9160,66 +6136,56 @@ typedef struct {
* @{
*/
-/* CR Bit Fields */
-#define RNG_CR_GO_MASK 0x1u
-#define RNG_CR_GO_SHIFT 0
-#define RNG_CR_GO_WIDTH 1
-#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
-#define RNG_CR_HA_MASK 0x2u
-#define RNG_CR_HA_SHIFT 1
-#define RNG_CR_HA_WIDTH 1
-#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
-#define RNG_CR_INTM_MASK 0x4u
-#define RNG_CR_INTM_SHIFT 2
-#define RNG_CR_INTM_WIDTH 1
-#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
-#define RNG_CR_CLRI_MASK 0x8u
-#define RNG_CR_CLRI_SHIFT 3
-#define RNG_CR_CLRI_WIDTH 1
-#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
-#define RNG_CR_SLP_MASK 0x10u
-#define RNG_CR_SLP_SHIFT 4
-#define RNG_CR_SLP_WIDTH 1
-#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
-/* SR Bit Fields */
-#define RNG_SR_SECV_MASK 0x1u
-#define RNG_SR_SECV_SHIFT 0
-#define RNG_SR_SECV_WIDTH 1
-#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
-#define RNG_SR_LRS_MASK 0x2u
-#define RNG_SR_LRS_SHIFT 1
-#define RNG_SR_LRS_WIDTH 1
-#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
-#define RNG_SR_ORU_MASK 0x4u
-#define RNG_SR_ORU_SHIFT 2
-#define RNG_SR_ORU_WIDTH 1
-#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
-#define RNG_SR_ERRI_MASK 0x8u
-#define RNG_SR_ERRI_SHIFT 3
-#define RNG_SR_ERRI_WIDTH 1
-#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
-#define RNG_SR_SLP_MASK 0x10u
-#define RNG_SR_SLP_SHIFT 4
-#define RNG_SR_SLP_WIDTH 1
-#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
-#define RNG_SR_OREG_LVL_MASK 0xFF00u
-#define RNG_SR_OREG_LVL_SHIFT 8
-#define RNG_SR_OREG_LVL_WIDTH 8
-#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
-#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
-#define RNG_SR_OREG_SIZE_SHIFT 16
-#define RNG_SR_OREG_SIZE_WIDTH 8
-#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
-/* ER Bit Fields */
-#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
-#define RNG_ER_EXT_ENT_SHIFT 0
-#define RNG_ER_EXT_ENT_WIDTH 32
-#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
-/* OR Bit Fields */
-#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
-#define RNG_OR_RANDOUT_SHIFT 0
-#define RNG_OR_RANDOUT_WIDTH 32
-#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+/*! @name CR - RNGA Control Register */
+#define RNG_CR_GO_MASK (0x1U)
+#define RNG_CR_GO_SHIFT (0U)
+#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK (0x2U)
+#define RNG_CR_HA_SHIFT (1U)
+#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK (0x4U)
+#define RNG_CR_INTM_SHIFT (2U)
+#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK (0x8U)
+#define RNG_CR_CLRI_SHIFT (3U)
+#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK (0x10U)
+#define RNG_CR_SLP_SHIFT (4U)
+#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
+
+/*! @name SR - RNGA Status Register */
+#define RNG_SR_SECV_MASK (0x1U)
+#define RNG_SR_SECV_SHIFT (0U)
+#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK (0x2U)
+#define RNG_SR_LRS_SHIFT (1U)
+#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK (0x4U)
+#define RNG_SR_ORU_SHIFT (2U)
+#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK (0x8U)
+#define RNG_SR_ERRI_SHIFT (3U)
+#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK (0x10U)
+#define RNG_SR_SLP_SHIFT (4U)
+#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK (0xFF00U)
+#define RNG_SR_OREG_LVL_SHIFT (8U)
+#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
+#define RNG_SR_OREG_SIZE_SHIFT (16U)
+#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
+
+/*! @name ER - RNGA Entropy Register */
+#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
+#define RNG_ER_EXT_ENT_SHIFT (0U)
+#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
+
+/*! @name OR - RNGA Output Register */
+#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
+#define RNG_OR_RANDOUT_SHIFT (0U)
+#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
+
/*!
* @}
@@ -9231,7 +6197,6 @@ typedef struct {
#define RNG_BASE (0x40029000u)
/** Peripheral RNG base pointer */
#define RNG ((RNG_Type *)RNG_BASE)
-#define RNG_BASE_PTR (RNG)
/** Array initializer of RNG peripheral base addresses */
#define RNG_BASE_ADDRS { RNG_BASE }
/** Array initializer of RNG peripheral base pointers */
@@ -9239,28 +6204,6 @@ typedef struct {
/** Interrupt vectors for the RNG peripheral type */
#define RNG_IRQS { RNG_IRQn }
-/* ----------------------------------------------------------------------------
- -- RNG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
- * @{
- */
-
-
-/* RNG - Register instance definitions */
-/* RNG */
-#define RNG_CR RNG_CR_REG(RNG)
-#define RNG_SR RNG_SR_REG(RNG)
-#define RNG_ER RNG_ER_REG(RNG)
-#define RNG_OR RNG_OR_REG(RNG)
-
-/*!
- * @}
- */ /* end of group RNG_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RNG_Peripheral_Access_Layer */
@@ -9288,34 +6231,7 @@ typedef struct {
uint8_t RESERVED_0[2016];
__IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
__IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type, *RTC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register accessors */
-#define RTC_TSR_REG(base) ((base)->TSR)
-#define RTC_TPR_REG(base) ((base)->TPR)
-#define RTC_TAR_REG(base) ((base)->TAR)
-#define RTC_TCR_REG(base) ((base)->TCR)
-#define RTC_CR_REG(base) ((base)->CR)
-#define RTC_SR_REG(base) ((base)->SR)
-#define RTC_LR_REG(base) ((base)->LR)
-#define RTC_IER_REG(base) ((base)->IER)
-#define RTC_WAR_REG(base) ((base)->WAR)
-#define RTC_RAR_REG(base) ((base)->RAR)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
+} RTC_Type;
/* ----------------------------------------------------------------------------
-- RTC Register Masks
@@ -9326,204 +6242,167 @@ typedef struct {
* @{
*/
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR_WIDTH 32
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR_WIDTH 16
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR_WIDTH 32
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR_WIDTH 8
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR_WIDTH 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV_WIDTH 8
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC_WIDTH 8
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_SWR_WIDTH 1
-#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_WPE_WIDTH 1
-#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_SUP_WIDTH 1
-#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_UM_WIDTH 1
-#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
-#define RTC_CR_WPS_MASK 0x10u
-#define RTC_CR_WPS_SHIFT 4
-#define RTC_CR_WPS_WIDTH 1
-#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_OSCE_WIDTH 1
-#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_CLKO_WIDTH 1
-#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC16P_WIDTH 1
-#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC8P_WIDTH 1
-#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC4P_WIDTH 1
-#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-#define RTC_CR_SC2P_WIDTH 1
-#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TIF_WIDTH 1
-#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TOF_WIDTH 1
-#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TAF_WIDTH 1
-#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-#define RTC_SR_TCE_WIDTH 1
-#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_TCL_WIDTH 1
-#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_CRL_WIDTH 1
-#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_SRL_WIDTH 1
-#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-#define RTC_LR_LRL_WIDTH 1
-#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TIIE_WIDTH 1
-#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TOIE_WIDTH 1
-#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TAIE_WIDTH 1
-#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-#define RTC_IER_TSIE_WIDTH 1
-#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
-#define RTC_IER_WPON_MASK 0x80u
-#define RTC_IER_WPON_SHIFT 7
-#define RTC_IER_WPON_WIDTH 1
-#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK 0x1u
-#define RTC_WAR_TSRW_SHIFT 0
-#define RTC_WAR_TSRW_WIDTH 1
-#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
-#define RTC_WAR_TPRW_MASK 0x2u
-#define RTC_WAR_TPRW_SHIFT 1
-#define RTC_WAR_TPRW_WIDTH 1
-#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
-#define RTC_WAR_TARW_MASK 0x4u
-#define RTC_WAR_TARW_SHIFT 2
-#define RTC_WAR_TARW_WIDTH 1
-#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
-#define RTC_WAR_TCRW_MASK 0x8u
-#define RTC_WAR_TCRW_SHIFT 3
-#define RTC_WAR_TCRW_WIDTH 1
-#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
-#define RTC_WAR_CRW_MASK 0x10u
-#define RTC_WAR_CRW_SHIFT 4
-#define RTC_WAR_CRW_WIDTH 1
-#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
-#define RTC_WAR_SRW_MASK 0x20u
-#define RTC_WAR_SRW_SHIFT 5
-#define RTC_WAR_SRW_WIDTH 1
-#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
-#define RTC_WAR_LRW_MASK 0x40u
-#define RTC_WAR_LRW_SHIFT 6
-#define RTC_WAR_LRW_WIDTH 1
-#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
-#define RTC_WAR_IERW_MASK 0x80u
-#define RTC_WAR_IERW_SHIFT 7
-#define RTC_WAR_IERW_WIDTH 1
-#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK 0x1u
-#define RTC_RAR_TSRR_SHIFT 0
-#define RTC_RAR_TSRR_WIDTH 1
-#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
-#define RTC_RAR_TPRR_MASK 0x2u
-#define RTC_RAR_TPRR_SHIFT 1
-#define RTC_RAR_TPRR_WIDTH 1
-#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
-#define RTC_RAR_TARR_MASK 0x4u
-#define RTC_RAR_TARR_SHIFT 2
-#define RTC_RAR_TARR_WIDTH 1
-#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
-#define RTC_RAR_TCRR_MASK 0x8u
-#define RTC_RAR_TCRR_SHIFT 3
-#define RTC_RAR_TCRR_WIDTH 1
-#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
-#define RTC_RAR_CRR_MASK 0x10u
-#define RTC_RAR_CRR_SHIFT 4
-#define RTC_RAR_CRR_WIDTH 1
-#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
-#define RTC_RAR_SRR_MASK 0x20u
-#define RTC_RAR_SRR_SHIFT 5
-#define RTC_RAR_SRR_WIDTH 1
-#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
-#define RTC_RAR_LRR_MASK 0x40u
-#define RTC_RAR_LRR_SHIFT 6
-#define RTC_RAR_LRR_WIDTH 1
-#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
-#define RTC_RAR_IERR_MASK 0x80u
-#define RTC_RAR_IERR_SHIFT 7
-#define RTC_RAR_IERR_WIDTH 1
-#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT (0U)
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT (0U)
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT (0U)
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK (0xFFU)
+#define RTC_TCR_TCR_SHIFT (0U)
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK (0xFF00U)
+#define RTC_TCR_CIR_SHIFT (8U)
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT (16U)
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT (24U)
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK (0x1U)
+#define RTC_CR_SWR_SHIFT (0U)
+#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK (0x2U)
+#define RTC_CR_WPE_SHIFT (1U)
+#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK (0x4U)
+#define RTC_CR_SUP_SHIFT (2U)
+#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK (0x8U)
+#define RTC_CR_UM_SHIFT (3U)
+#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK (0x10U)
+#define RTC_CR_WPS_SHIFT (4U)
+#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK (0x100U)
+#define RTC_CR_OSCE_SHIFT (8U)
+#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK (0x200U)
+#define RTC_CR_CLKO_SHIFT (9U)
+#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK (0x400U)
+#define RTC_CR_SC16P_SHIFT (10U)
+#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK (0x800U)
+#define RTC_CR_SC8P_SHIFT (11U)
+#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK (0x1000U)
+#define RTC_CR_SC4P_SHIFT (12U)
+#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK (0x2000U)
+#define RTC_CR_SC2P_SHIFT (13U)
+#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK (0x1U)
+#define RTC_SR_TIF_SHIFT (0U)
+#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK (0x2U)
+#define RTC_SR_TOF_SHIFT (1U)
+#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK (0x4U)
+#define RTC_SR_TAF_SHIFT (2U)
+#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TCE_MASK (0x10U)
+#define RTC_SR_TCE_SHIFT (4U)
+#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK (0x8U)
+#define RTC_LR_TCL_SHIFT (3U)
+#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK (0x10U)
+#define RTC_LR_CRL_SHIFT (4U)
+#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK (0x20U)
+#define RTC_LR_SRL_SHIFT (5U)
+#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK (0x40U)
+#define RTC_LR_LRL_SHIFT (6U)
+#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK (0x1U)
+#define RTC_IER_TIIE_SHIFT (0U)
+#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK (0x2U)
+#define RTC_IER_TOIE_SHIFT (1U)
+#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK (0x4U)
+#define RTC_IER_TAIE_SHIFT (2U)
+#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TSIE_MASK (0x10U)
+#define RTC_IER_TSIE_SHIFT (4U)
+#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK (0x80U)
+#define RTC_IER_WPON_SHIFT (7U)
+#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW_MASK (0x1U)
+#define RTC_WAR_TSRW_SHIFT (0U)
+#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK (0x2U)
+#define RTC_WAR_TPRW_SHIFT (1U)
+#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK (0x4U)
+#define RTC_WAR_TARW_SHIFT (2U)
+#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK (0x8U)
+#define RTC_WAR_TCRW_SHIFT (3U)
+#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK (0x10U)
+#define RTC_WAR_CRW_SHIFT (4U)
+#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK (0x20U)
+#define RTC_WAR_SRW_SHIFT (5U)
+#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK (0x40U)
+#define RTC_WAR_LRW_SHIFT (6U)
+#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK (0x80U)
+#define RTC_WAR_IERW_SHIFT (7U)
+#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR_MASK (0x1U)
+#define RTC_RAR_TSRR_SHIFT (0U)
+#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK (0x2U)
+#define RTC_RAR_TPRR_SHIFT (1U)
+#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK (0x4U)
+#define RTC_RAR_TARR_SHIFT (2U)
+#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK (0x8U)
+#define RTC_RAR_TCRR_SHIFT (3U)
+#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK (0x10U)
+#define RTC_RAR_CRR_SHIFT (4U)
+#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK (0x20U)
+#define RTC_RAR_SRR_SHIFT (5U)
+#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK (0x40U)
+#define RTC_RAR_LRR_SHIFT (6U)
+#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK (0x80U)
+#define RTC_RAR_IERR_SHIFT (7U)
+#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+
/*!
* @}
@@ -9535,7 +6414,6 @@ typedef struct {
#define RTC_BASE (0x4003D000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
-#define RTC_BASE_PTR (RTC)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
@@ -9544,34 +6422,6 @@ typedef struct {
#define RTC_IRQS { RTC_IRQn }
#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register instance definitions */
-/* RTC */
-#define RTC_TSR RTC_TSR_REG(RTC)
-#define RTC_TPR RTC_TPR_REG(RTC)
-#define RTC_TAR RTC_TAR_REG(RTC)
-#define RTC_TCR RTC_TCR_REG(RTC)
-#define RTC_CR RTC_CR_REG(RTC)
-#define RTC_SR RTC_SR_REG(RTC)
-#define RTC_LR RTC_LR_REG(RTC)
-#define RTC_IER RTC_IER_REG(RTC)
-#define RTC_WAR RTC_WAR_REG(RTC)
-#define RTC_RAR RTC_RAR_REG(RTC)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
@@ -9613,44 +6463,7 @@ typedef struct {
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type, *SIM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register accessors */
-#define SIM_SOPT1_REG(base) ((base)->SOPT1)
-#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
-#define SIM_SOPT2_REG(base) ((base)->SOPT2)
-#define SIM_SOPT4_REG(base) ((base)->SOPT4)
-#define SIM_SOPT5_REG(base) ((base)->SOPT5)
-#define SIM_SOPT7_REG(base) ((base)->SOPT7)
-#define SIM_SOPT8_REG(base) ((base)->SOPT8)
-#define SIM_SDID_REG(base) ((base)->SDID)
-#define SIM_SCGC4_REG(base) ((base)->SCGC4)
-#define SIM_SCGC5_REG(base) ((base)->SCGC5)
-#define SIM_SCGC6_REG(base) ((base)->SCGC6)
-#define SIM_SCGC7_REG(base) ((base)->SCGC7)
-#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
-#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
-#define SIM_FCFG1_REG(base) ((base)->FCFG1)
-#define SIM_FCFG2_REG(base) ((base)->FCFG2)
-#define SIM_UIDH_REG(base) ((base)->UIDH)
-#define SIM_UIDMH_REG(base) ((base)->UIDMH)
-#define SIM_UIDML_REG(base) ((base)->UIDML)
-#define SIM_UIDL_REG(base) ((base)->UIDL)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
+} SIM_Type;
/* ----------------------------------------------------------------------------
-- SIM Register Masks
@@ -9661,438 +6474,355 @@ typedef struct {
* @{
*/
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT 12
-#define SIM_SOPT1_RAMSIZE_WIDTH 4
-#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
-#define SIM_SOPT1_OSC32KOUT_SHIFT 16
-#define SIM_SOPT1_OSC32KOUT_WIDTH 2
-#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL_WIDTH 2
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT 29
-#define SIM_SOPT1_USBVSTBY_WIDTH 1
-#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
-#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT 30
-#define SIM_SOPT1_USBSSTBY_WIDTH 1
-#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
-#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT 31
-#define SIM_SOPT1_USBREGEN_WIDTH 1
-#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT 24
-#define SIM_SOPT1CFG_URWE_WIDTH 1
-#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
-#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT 25
-#define SIM_SOPT1CFG_UVSWE_WIDTH 1
-#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
-#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT 26
-#define SIM_SOPT1CFG_USSWE_WIDTH 1
-#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH 1
-#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL_WIDTH 3
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
-#define SIM_SOPT2_TRACECLKSEL_WIDTH 1
-#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_PLLFLLSEL_WIDTH 2
-#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-#define SIM_SOPT2_USBSRC_WIDTH 1
-#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
-#define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
-#define SIM_SOPT2_LPUARTSRC_SHIFT 26
-#define SIM_SOPT2_LPUARTSRC_WIDTH 2
-#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT 0
-#define SIM_SOPT4_FTM0FLT0_WIDTH 1
-#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
-#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT 1
-#define SIM_SOPT4_FTM0FLT1_WIDTH 1
-#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
-#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT 4
-#define SIM_SOPT4_FTM1FLT0_WIDTH 1
-#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
-#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
-#define SIM_SOPT4_FTM2FLT0_SHIFT 8
-#define SIM_SOPT4_FTM2FLT0_WIDTH 1
-#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
-#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_FTM1CH0SRC_WIDTH 2
-#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
-#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
-#define SIM_SOPT4_FTM2CH0SRC_WIDTH 2
-#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH1SRC_MASK 0x400000u
-#define SIM_SOPT4_FTM2CH1SRC_SHIFT 22
-#define SIM_SOPT4_FTM2CH1SRC_WIDTH 1
-#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH1SRC_SHIFT))&SIM_SOPT4_FTM2CH1SRC_MASK)
-#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_FTM0CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
-#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_FTM1CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
-#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
-#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
-#define SIM_SOPT4_FTM2CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
-#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
-#define SIM_SOPT4_FTM0TRG0SRC_WIDTH 1
-#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
-#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
-#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
-#define SIM_SOPT4_FTM0TRG1SRC_WIDTH 1
-#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0TXSRC_WIDTH 2
-#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART0RXSRC_WIDTH 2
-#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1TXSRC_WIDTH 2
-#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART1RXSRC_WIDTH 2
-#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-#define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
-#define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
-#define SIM_SOPT5_LPUART0RXSRC_WIDTH 2
-#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL_WIDTH 4
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH 1
-#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH 1
-#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
-#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
-#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
-#define SIM_SOPT7_ADC1TRGSEL_WIDTH 4
-#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
-#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
-#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
-#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH 1
-#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
-#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
-#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
-#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH 1
-#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
-/* SOPT8 Bit Fields */
-#define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
-#define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
-#define SIM_SOPT8_FTM0SYNCBIT_WIDTH 1
-#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0SYNCBIT_SHIFT))&SIM_SOPT8_FTM0SYNCBIT_MASK)
-#define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
-#define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
-#define SIM_SOPT8_FTM1SYNCBIT_WIDTH 1
-#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM1SYNCBIT_SHIFT))&SIM_SOPT8_FTM1SYNCBIT_MASK)
-#define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
-#define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
-#define SIM_SOPT8_FTM2SYNCBIT_WIDTH 1
-#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM2SYNCBIT_SHIFT))&SIM_SOPT8_FTM2SYNCBIT_MASK)
-#define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
-#define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
-#define SIM_SOPT8_FTM0OCH0SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH0SRC_SHIFT))&SIM_SOPT8_FTM0OCH0SRC_MASK)
-#define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
-#define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
-#define SIM_SOPT8_FTM0OCH1SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH1SRC_SHIFT))&SIM_SOPT8_FTM0OCH1SRC_MASK)
-#define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
-#define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
-#define SIM_SOPT8_FTM0OCH2SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH2SRC_SHIFT))&SIM_SOPT8_FTM0OCH2SRC_MASK)
-#define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
-#define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
-#define SIM_SOPT8_FTM0OCH3SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH3SRC_SHIFT))&SIM_SOPT8_FTM0OCH3SRC_MASK)
-#define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
-#define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
-#define SIM_SOPT8_FTM0OCH4SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH4SRC_SHIFT))&SIM_SOPT8_FTM0OCH4SRC_MASK)
-#define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
-#define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
-#define SIM_SOPT8_FTM0OCH5SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH5SRC_SHIFT))&SIM_SOPT8_FTM0OCH5SRC_MASK)
-#define SIM_SOPT8_FTM0OCH6SRC_MASK 0x400000u
-#define SIM_SOPT8_FTM0OCH6SRC_SHIFT 22
-#define SIM_SOPT8_FTM0OCH6SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH6SRC_SHIFT))&SIM_SOPT8_FTM0OCH6SRC_MASK)
-#define SIM_SOPT8_FTM0OCH7SRC_MASK 0x800000u
-#define SIM_SOPT8_FTM0OCH7SRC_SHIFT 23
-#define SIM_SOPT8_FTM0OCH7SRC_WIDTH 1
-#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT8_FTM0OCH7SRC_SHIFT))&SIM_SOPT8_FTM0OCH7SRC_MASK)
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID_WIDTH 4
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK 0x70u
-#define SIM_SDID_FAMID_SHIFT 4
-#define SIM_SDID_FAMID_WIDTH 3
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_DIEID_MASK 0xF80u
-#define SIM_SDID_DIEID_SHIFT 7
-#define SIM_SDID_DIEID_WIDTH 5
-#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID_WIDTH 4
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-#define SIM_SDID_SERIESID_MASK 0xF00000u
-#define SIM_SDID_SERIESID_SHIFT 20
-#define SIM_SDID_SERIESID_WIDTH 4
-#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
-#define SIM_SDID_SUBFAMID_MASK 0xF000000u
-#define SIM_SDID_SUBFAMID_SHIFT 24
-#define SIM_SDID_SUBFAMID_WIDTH 4
-#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
-#define SIM_SDID_FAMILYID_MASK 0xF0000000u
-#define SIM_SDID_FAMILYID_SHIFT 28
-#define SIM_SDID_FAMILYID_WIDTH 4
-#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK 0x2u
-#define SIM_SCGC4_EWM_SHIFT 1
-#define SIM_SCGC4_EWM_WIDTH 1
-#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_I2C0_WIDTH 1
-#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
-#define SIM_SCGC4_I2C1_MASK 0x80u
-#define SIM_SCGC4_I2C1_SHIFT 7
-#define SIM_SCGC4_I2C1_WIDTH 1
-#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART0_WIDTH 1
-#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART1_WIDTH 1
-#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_UART2_WIDTH 1
-#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_USBOTG_WIDTH 1
-#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_CMP_WIDTH 1
-#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
-#define SIM_SCGC4_VREF_MASK 0x100000u
-#define SIM_SCGC4_VREF_SHIFT 20
-#define SIM_SCGC4_VREF_WIDTH 1
-#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTMR_MASK 0x1u
-#define SIM_SCGC5_LPTMR_SHIFT 0
-#define SIM_SCGC5_LPTMR_WIDTH 1
-#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTA_WIDTH 1
-#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTB_WIDTH 1
-#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTC_WIDTH 1
-#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTD_WIDTH 1
-#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-#define SIM_SCGC5_PORTE_WIDTH 1
-#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTF_MASK 0x1u
-#define SIM_SCGC6_FTF_SHIFT 0
-#define SIM_SCGC6_FTF_WIDTH 1
-#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_DMAMUX_WIDTH 1
-#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
-#define SIM_SCGC6_ADC1_MASK 0x80u
-#define SIM_SCGC6_ADC1_SHIFT 7
-#define SIM_SCGC6_ADC1_WIDTH 1
-#define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC1_SHIFT))&SIM_SCGC6_ADC1_MASK)
-#define SIM_SCGC6_RNGA_MASK 0x200u
-#define SIM_SCGC6_RNGA_SHIFT 9
-#define SIM_SCGC6_RNGA_WIDTH 1
-#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
-#define SIM_SCGC6_LPUART0_MASK 0x400u
-#define SIM_SCGC6_LPUART0_SHIFT 10
-#define SIM_SCGC6_LPUART0_WIDTH 1
-#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_LPUART0_SHIFT))&SIM_SCGC6_LPUART0_MASK)
-#define SIM_SCGC6_SPI0_MASK 0x1000u
-#define SIM_SCGC6_SPI0_SHIFT 12
-#define SIM_SCGC6_SPI0_WIDTH 1
-#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
-#define SIM_SCGC6_SPI1_MASK 0x2000u
-#define SIM_SCGC6_SPI1_SHIFT 13
-#define SIM_SCGC6_SPI1_WIDTH 1
-#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
-#define SIM_SCGC6_I2S_MASK 0x8000u
-#define SIM_SCGC6_I2S_SHIFT 15
-#define SIM_SCGC6_I2S_WIDTH 1
-#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
-#define SIM_SCGC6_CRC_MASK 0x40000u
-#define SIM_SCGC6_CRC_SHIFT 18
-#define SIM_SCGC6_CRC_WIDTH 1
-#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
-#define SIM_SCGC6_PDB_MASK 0x400000u
-#define SIM_SCGC6_PDB_SHIFT 22
-#define SIM_SCGC6_PDB_WIDTH 1
-#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_PIT_WIDTH 1
-#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
-#define SIM_SCGC6_FTM0_MASK 0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT 24
-#define SIM_SCGC6_FTM0_WIDTH 1
-#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
-#define SIM_SCGC6_FTM1_MASK 0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT 25
-#define SIM_SCGC6_FTM1_WIDTH 1
-#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
-#define SIM_SCGC6_FTM2_MASK 0x4000000u
-#define SIM_SCGC6_FTM2_SHIFT 26
-#define SIM_SCGC6_FTM2_WIDTH 1
-#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_ADC0_WIDTH 1
-#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-#define SIM_SCGC6_RTC_WIDTH 1
-#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
-#define SIM_SCGC6_DAC0_MASK 0x80000000u
-#define SIM_SCGC6_DAC0_SHIFT 31
-#define SIM_SCGC6_DAC0_WIDTH 1
-#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_DMA_MASK 0x2u
-#define SIM_SCGC7_DMA_SHIFT 1
-#define SIM_SCGC7_DMA_WIDTH 1
-#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
-#define SIM_CLKDIV1_OUTDIV2_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT 0
-#define SIM_CLKDIV2_USBFRAC_WIDTH 1
-#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
-#define SIM_CLKDIV2_USBDIV_MASK 0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT 1
-#define SIM_CLKDIV2_USBDIV_WIDTH 3
-#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDIS_WIDTH 1
-#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_FLASHDOZE_WIDTH 1
-#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE_WIDTH 4
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT 16
-#define SIM_FCFG2_MAXADDR1_WIDTH 7
-#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT 24
-#define SIM_FCFG2_MAXADDR0_WIDTH 7
-#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT 0
-#define SIM_UIDH_UID_WIDTH 32
-#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID_WIDTH 32
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID_WIDTH 32
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID_WIDTH 32
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
+#define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
+#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
+#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
+#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT (31U)
+#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT (24U)
+#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
+#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
+#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
+#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
+#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT (18U)
+#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
+#define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
+#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
+#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
+#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
+#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
+#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
+#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
+#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
+#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
+#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
+#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
+#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
+#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
+#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
+#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
+#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
+#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
+#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
+#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
+#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+
+/*! @name SOPT8 - System Options Register 8 */
+#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
+#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
+#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
+#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
+#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
+#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
+#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
+#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
+#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
+#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
+#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
+#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
+#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
+#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
+#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
+#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
+#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
+#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
+#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
+#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
+#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
+#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
+#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
+#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
+#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
+#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
+#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
+#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
+#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
+#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
+#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
+#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
+#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK (0xFU)
+#define SIM_SDID_PINID_SHIFT (0U)
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK (0x70U)
+#define SIM_SDID_FAMID_SHIFT (4U)
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK (0xF80U)
+#define SIM_SDID_DIEID_SHIFT (7U)
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK (0xF000U)
+#define SIM_SDID_REVID_SHIFT (12U)
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT (20U)
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT (24U)
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
+#define SIM_SDID_FAMILYID_SHIFT (28U)
+#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM_MASK (0x2U)
+#define SIM_SCGC4_EWM_SHIFT (1U)
+#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_I2C0_MASK (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT (6U)
+#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT (7U)
+#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK (0x400U)
+#define SIM_SCGC4_UART0_SHIFT (10U)
+#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK (0x800U)
+#define SIM_SCGC4_UART1_SHIFT (11U)
+#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT (12U)
+#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_USBOTG_MASK (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT (18U)
+#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT (19U)
+#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT (20U)
+#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR_MASK (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT (0U)
+#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT (9U)
+#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT (10U)
+#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT (11U)
+#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT (12U)
+#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT (13U)
+#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTF_MASK (0x1U)
+#define SIM_SCGC6_FTF_SHIFT (0U)
+#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT (1U)
+#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_ADC1_MASK (0x80U)
+#define SIM_SCGC6_ADC1_SHIFT (7U)
+#define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC1_SHIFT)) & SIM_SCGC6_ADC1_MASK)
+#define SIM_SCGC6_RNGA_MASK (0x200U)
+#define SIM_SCGC6_RNGA_SHIFT (9U)
+#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_LPUART0_MASK (0x400U)
+#define SIM_SCGC6_LPUART0_SHIFT (10U)
+#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_LPUART0_SHIFT)) & SIM_SCGC6_LPUART0_MASK)
+#define SIM_SCGC6_SPI0_MASK (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT (12U)
+#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK (0x2000U)
+#define SIM_SCGC6_SPI1_SHIFT (13U)
+#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT (15U)
+#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT (18U)
+#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_PDB_MASK (0x400000U)
+#define SIM_SCGC6_PDB_SHIFT (22U)
+#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT (23U)
+#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK (0x1000000U)
+#define SIM_SCGC6_FTM0_SHIFT (24U)
+#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK (0x2000000U)
+#define SIM_SCGC6_FTM1_SHIFT (25U)
+#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK (0x4000000U)
+#define SIM_SCGC6_FTM2_SHIFT (26U)
+#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT (27U)
+#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT (29U)
+#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT (31U)
+#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_DMA_MASK (0x2U)
+#define SIM_SCGC7_DMA_SHIFT (1U)
+#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
+#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
+#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
+#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT (24U)
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+
+/*! @name UIDH - Unique Identification Register High */
+#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT (0U)
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT (0U)
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT (0U)
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT (0U)
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
/*!
* @}
@@ -10104,50 +6834,11 @@ typedef struct {
#define SIM_BASE (0x40047000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
-#define SIM_BASE_PTR (SIM)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register instance definitions */
-/* SIM */
-#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
-#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
-#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
-#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
-#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
-#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
-#define SIM_SOPT8 SIM_SOPT8_REG(SIM)
-#define SIM_SDID SIM_SDID_REG(SIM)
-#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
-#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
-#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
-#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
-#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
-#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
-#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
-#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
-#define SIM_UIDH SIM_UIDH_REG(SIM)
-#define SIM_UIDMH SIM_UIDMH_REG(SIM)
-#define SIM_UIDML SIM_UIDML_REG(SIM)
-#define SIM_UIDL SIM_UIDL_REG(SIM)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
@@ -10168,28 +6859,7 @@ typedef struct {
__IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
__IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
__I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type, *SMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register accessors */
-#define SMC_PMPROT_REG(base) ((base)->PMPROT)
-#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
-#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
-#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
+} SMC_Type;
/* ----------------------------------------------------------------------------
-- SMC Register Masks
@@ -10200,54 +6870,47 @@ typedef struct {
* @{
*/
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_AVLLS_WIDTH 1
-#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_ALLS_WIDTH 1
-#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-#define SMC_PMPROT_AVLP_WIDTH 1
-#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
-#define SMC_PMPROT_AHSRUN_MASK 0x80u
-#define SMC_PMPROT_AHSRUN_SHIFT 7
-#define SMC_PMPROT_AHSRUN_WIDTH 1
-#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM_WIDTH 3
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_STOPA_WIDTH 1
-#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM_WIDTH 2
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-/* STOPCTRL Bit Fields */
-#define SMC_STOPCTRL_LLSM_MASK 0x7u
-#define SMC_STOPCTRL_LLSM_SHIFT 0
-#define SMC_STOPCTRL_LLSM_WIDTH 3
-#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
-#define SMC_STOPCTRL_PORPO_MASK 0x20u
-#define SMC_STOPCTRL_PORPO_SHIFT 5
-#define SMC_STOPCTRL_PORPO_WIDTH 1
-#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PORPO_SHIFT))&SMC_STOPCTRL_PORPO_MASK)
-#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
-#define SMC_STOPCTRL_PSTOPO_SHIFT 6
-#define SMC_STOPCTRL_PSTOPO_WIDTH 2
-#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT_WIDTH 8
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT (1U)
+#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT (3U)
+#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT (5U)
+#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AHSRUN_MASK (0x80U)
+#define SMC_PMPROT_AHSRUN_SHIFT (7U)
+#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT (0U)
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT (3U)
+#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT (5U)
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+
+/*! @name STOPCTRL - Stop Control Register */
+#define SMC_STOPCTRL_LLSM_MASK (0x7U)
+#define SMC_STOPCTRL_LLSM_SHIFT (0U)
+#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT (5U)
+#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
/*!
* @}
@@ -10259,34 +6922,11 @@ typedef struct {
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
-#define SMC_BASE_PTR (SMC)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS { SMC_BASE }
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS { SMC }
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register instance definitions */
-/* SMC */
-#define SMC_PMPROT SMC_PMPROT_REG(SMC)
-#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
-#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
-#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
@@ -10327,43 +6967,7 @@ typedef struct {
__I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
__I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
__I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
-} SPI_Type, *SPI_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register accessors */
-#define SPI_MCR_REG(base) ((base)->MCR)
-#define SPI_TCR_REG(base) ((base)->TCR)
-#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
-#define SPI_CTAR_COUNT 2
-#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
-#define SPI_CTAR_SLAVE_COUNT 1
-#define SPI_SR_REG(base) ((base)->SR)
-#define SPI_RSER_REG(base) ((base)->RSER)
-#define SPI_PUSHR_REG(base) ((base)->PUSHR)
-#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
-#define SPI_POPR_REG(base) ((base)->POPR)
-#define SPI_TXFR0_REG(base) ((base)->TXFR0)
-#define SPI_TXFR1_REG(base) ((base)->TXFR1)
-#define SPI_TXFR2_REG(base) ((base)->TXFR2)
-#define SPI_TXFR3_REG(base) ((base)->TXFR3)
-#define SPI_RXFR0_REG(base) ((base)->RXFR0)
-#define SPI_RXFR1_REG(base) ((base)->RXFR1)
-#define SPI_RXFR2_REG(base) ((base)->RXFR2)
-#define SPI_RXFR3_REG(base) ((base)->RXFR3)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
+} SPI_Type;
/* ----------------------------------------------------------------------------
-- SPI Register Masks
@@ -10374,311 +6978,262 @@ typedef struct {
* @{
*/
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK 0x1u
-#define SPI_MCR_HALT_SHIFT 0
-#define SPI_MCR_HALT_WIDTH 1
-#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
-#define SPI_MCR_SMPL_PT_MASK 0x300u
-#define SPI_MCR_SMPL_PT_SHIFT 8
-#define SPI_MCR_SMPL_PT_WIDTH 2
-#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK 0x400u
-#define SPI_MCR_CLR_RXF_SHIFT 10
-#define SPI_MCR_CLR_RXF_WIDTH 1
-#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
-#define SPI_MCR_CLR_TXF_MASK 0x800u
-#define SPI_MCR_CLR_TXF_SHIFT 11
-#define SPI_MCR_CLR_TXF_WIDTH 1
-#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
-#define SPI_MCR_DIS_RXF_MASK 0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT 12
-#define SPI_MCR_DIS_RXF_WIDTH 1
-#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
-#define SPI_MCR_DIS_TXF_MASK 0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT 13
-#define SPI_MCR_DIS_TXF_WIDTH 1
-#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
-#define SPI_MCR_MDIS_MASK 0x4000u
-#define SPI_MCR_MDIS_SHIFT 14
-#define SPI_MCR_MDIS_WIDTH 1
-#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
-#define SPI_MCR_DOZE_MASK 0x8000u
-#define SPI_MCR_DOZE_SHIFT 15
-#define SPI_MCR_DOZE_WIDTH 1
-#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
-#define SPI_MCR_PCSIS_MASK 0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT 16
-#define SPI_MCR_PCSIS_WIDTH 6
-#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK 0x1000000u
-#define SPI_MCR_ROOE_SHIFT 24
-#define SPI_MCR_ROOE_WIDTH 1
-#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
-#define SPI_MCR_PCSSE_MASK 0x2000000u
-#define SPI_MCR_PCSSE_SHIFT 25
-#define SPI_MCR_PCSSE_WIDTH 1
-#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
-#define SPI_MCR_MTFE_MASK 0x4000000u
-#define SPI_MCR_MTFE_SHIFT 26
-#define SPI_MCR_MTFE_WIDTH 1
-#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
-#define SPI_MCR_FRZ_MASK 0x8000000u
-#define SPI_MCR_FRZ_SHIFT 27
-#define SPI_MCR_FRZ_WIDTH 1
-#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
-#define SPI_MCR_DCONF_MASK 0x30000000u
-#define SPI_MCR_DCONF_SHIFT 28
-#define SPI_MCR_DCONF_WIDTH 2
-#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT 30
-#define SPI_MCR_CONT_SCKE_WIDTH 1
-#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
-#define SPI_MCR_MSTR_MASK 0x80000000u
-#define SPI_MCR_MSTR_SHIFT 31
-#define SPI_MCR_MSTR_WIDTH 1
-#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT 16
-#define SPI_TCR_SPI_TCNT_WIDTH 16
-#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK 0xFu
-#define SPI_CTAR_BR_SHIFT 0
-#define SPI_CTAR_BR_WIDTH 4
-#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK 0xF0u
-#define SPI_CTAR_DT_SHIFT 4
-#define SPI_CTAR_DT_WIDTH 4
-#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK 0xF00u
-#define SPI_CTAR_ASC_SHIFT 8
-#define SPI_CTAR_ASC_WIDTH 4
-#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK 0xF000u
-#define SPI_CTAR_CSSCK_SHIFT 12
-#define SPI_CTAR_CSSCK_WIDTH 4
-#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK 0x30000u
-#define SPI_CTAR_PBR_SHIFT 16
-#define SPI_CTAR_PBR_WIDTH 2
-#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK 0xC0000u
-#define SPI_CTAR_PDT_SHIFT 18
-#define SPI_CTAR_PDT_WIDTH 2
-#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK 0x300000u
-#define SPI_CTAR_PASC_SHIFT 20
-#define SPI_CTAR_PASC_WIDTH 2
-#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK 0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT 22
-#define SPI_CTAR_PCSSCK_WIDTH 2
-#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK 0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT 24
-#define SPI_CTAR_LSBFE_WIDTH 1
-#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
-#define SPI_CTAR_CPHA_MASK 0x2000000u
-#define SPI_CTAR_CPHA_SHIFT 25
-#define SPI_CTAR_CPHA_WIDTH 1
-#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
-#define SPI_CTAR_CPOL_MASK 0x4000000u
-#define SPI_CTAR_CPOL_SHIFT 26
-#define SPI_CTAR_CPOL_WIDTH 1
-#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
-#define SPI_CTAR_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT 27
-#define SPI_CTAR_FMSZ_WIDTH 4
-#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK 0x80000000u
-#define SPI_CTAR_DBR_SHIFT 31
-#define SPI_CTAR_DBR_WIDTH 1
-#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
-#define SPI_CTAR_SLAVE_CPHA_WIDTH 1
-#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
-#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
-#define SPI_CTAR_SLAVE_CPOL_WIDTH 1
-#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
-#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
-#define SPI_CTAR_SLAVE_FMSZ_WIDTH 5
-#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK 0xFu
-#define SPI_SR_POPNXTPTR_SHIFT 0
-#define SPI_SR_POPNXTPTR_WIDTH 4
-#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK 0xF0u
-#define SPI_SR_RXCTR_SHIFT 4
-#define SPI_SR_RXCTR_WIDTH 4
-#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK 0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT 8
-#define SPI_SR_TXNXTPTR_WIDTH 4
-#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK 0xF000u
-#define SPI_SR_TXCTR_SHIFT 12
-#define SPI_SR_TXCTR_WIDTH 4
-#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK 0x20000u
-#define SPI_SR_RFDF_SHIFT 17
-#define SPI_SR_RFDF_WIDTH 1
-#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
-#define SPI_SR_RFOF_MASK 0x80000u
-#define SPI_SR_RFOF_SHIFT 19
-#define SPI_SR_RFOF_WIDTH 1
-#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
-#define SPI_SR_TFFF_MASK 0x2000000u
-#define SPI_SR_TFFF_SHIFT 25
-#define SPI_SR_TFFF_WIDTH 1
-#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
-#define SPI_SR_TFUF_MASK 0x8000000u
-#define SPI_SR_TFUF_SHIFT 27
-#define SPI_SR_TFUF_WIDTH 1
-#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
-#define SPI_SR_EOQF_MASK 0x10000000u
-#define SPI_SR_EOQF_SHIFT 28
-#define SPI_SR_EOQF_WIDTH 1
-#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
-#define SPI_SR_TXRXS_MASK 0x40000000u
-#define SPI_SR_TXRXS_SHIFT 30
-#define SPI_SR_TXRXS_WIDTH 1
-#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
-#define SPI_SR_TCF_MASK 0x80000000u
-#define SPI_SR_TCF_SHIFT 31
-#define SPI_SR_TCF_WIDTH 1
-#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT 16
-#define SPI_RSER_RFDF_DIRS_WIDTH 1
-#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
-#define SPI_RSER_RFDF_RE_MASK 0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT 17
-#define SPI_RSER_RFDF_RE_WIDTH 1
-#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
-#define SPI_RSER_RFOF_RE_MASK 0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT 19
-#define SPI_RSER_RFOF_RE_WIDTH 1
-#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
-#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT 24
-#define SPI_RSER_TFFF_DIRS_WIDTH 1
-#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
-#define SPI_RSER_TFFF_RE_MASK 0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT 25
-#define SPI_RSER_TFFF_RE_WIDTH 1
-#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
-#define SPI_RSER_TFUF_RE_MASK 0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT 27
-#define SPI_RSER_TFUF_RE_WIDTH 1
-#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
-#define SPI_RSER_EOQF_RE_MASK 0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT 28
-#define SPI_RSER_EOQF_RE_WIDTH 1
-#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
-#define SPI_RSER_TCF_RE_MASK 0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT 31
-#define SPI_RSER_TCF_RE_WIDTH 1
-#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT 0
-#define SPI_PUSHR_TXDATA_WIDTH 16
-#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK 0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT 16
-#define SPI_PUSHR_PCS_WIDTH 6
-#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK 0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT 26
-#define SPI_PUSHR_CTCNT_WIDTH 1
-#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
-#define SPI_PUSHR_EOQ_MASK 0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT 27
-#define SPI_PUSHR_EOQ_WIDTH 1
-#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
-#define SPI_PUSHR_CTAS_MASK 0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT 28
-#define SPI_PUSHR_CTAS_WIDTH 3
-#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK 0x80000000u
-#define SPI_PUSHR_CONT_SHIFT 31
-#define SPI_PUSHR_CONT_WIDTH 1
-#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
-#define SPI_PUSHR_SLAVE_TXDATA_WIDTH 32
-#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT 0
-#define SPI_POPR_RXDATA_WIDTH 32
-#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT 0
-#define SPI_TXFR0_TXDATA_WIDTH 16
-#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR0_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT 0
-#define SPI_TXFR1_TXDATA_WIDTH 16
-#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR1_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT 0
-#define SPI_TXFR2_TXDATA_WIDTH 16
-#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR2_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT 0
-#define SPI_TXFR3_TXDATA_WIDTH 16
-#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR3_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT 0
-#define SPI_RXFR0_RXDATA_WIDTH 32
-#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT 0
-#define SPI_RXFR1_RXDATA_WIDTH 32
-#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT 0
-#define SPI_RXFR2_RXDATA_WIDTH 32
-#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT 0
-#define SPI_RXFR3_RXDATA_WIDTH 32
-#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+/*! @name MCR - Module Configuration Register */
+#define SPI_MCR_HALT_MASK (0x1U)
+#define SPI_MCR_HALT_SHIFT (0U)
+#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT (8U)
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT (10U)
+#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT (11U)
+#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT (12U)
+#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT (13U)
+#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK (0x4000U)
+#define SPI_MCR_MDIS_SHIFT (14U)
+#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK (0x8000U)
+#define SPI_MCR_DOZE_SHIFT (15U)
+#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT (16U)
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT (24U)
+#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT (25U)
+#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT (26U)
+#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT (27U)
+#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT (28U)
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT (30U)
+#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT (31U)
+#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+
+/*! @name TCR - Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT (16U)
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK (0xFU)
+#define SPI_CTAR_BR_SHIFT (0U)
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK (0xF0U)
+#define SPI_CTAR_DT_SHIFT (4U)
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK (0xF00U)
+#define SPI_CTAR_ASC_SHIFT (8U)
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT (12U)
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK (0x30000U)
+#define SPI_CTAR_PBR_SHIFT (16U)
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT (18U)
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK (0x300000U)
+#define SPI_CTAR_PASC_SHIFT (20U)
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT (22U)
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT (24U)
+#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT (25U)
+#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT (26U)
+#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT (27U)
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT (31U)
+#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
+#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
+#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT (1U)
+
+/*! @name SR - Status Register */
+#define SPI_SR_POPNXTPTR_MASK (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT (0U)
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK (0xF0U)
+#define SPI_SR_RXCTR_SHIFT (4U)
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT (8U)
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK (0xF000U)
+#define SPI_SR_TXCTR_SHIFT (12U)
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK (0x20000U)
+#define SPI_SR_RFDF_SHIFT (17U)
+#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK (0x80000U)
+#define SPI_SR_RFOF_SHIFT (19U)
+#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK (0x2000000U)
+#define SPI_SR_TFFF_SHIFT (25U)
+#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK (0x8000000U)
+#define SPI_SR_TFUF_SHIFT (27U)
+#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK (0x10000000U)
+#define SPI_SR_EOQF_SHIFT (28U)
+#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT (30U)
+#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK (0x80000000U)
+#define SPI_SR_TCF_SHIFT (31U)
+#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
+#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT (17U)
+#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT (19U)
+#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
+#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT (25U)
+#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT (27U)
+#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT (28U)
+#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT (31U)
+#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT (16U)
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT (26U)
+#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT (27U)
+#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT (28U)
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT (31U)
+#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+
+/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+
+/*! @name POPR - POP RX FIFO Register */
+#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT (0U)
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+
+/*! @name TXFR0 - Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT (0U)
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT (0U)
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT (0U)
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT (0U)
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*! @name RXFR0 - Receive FIFO Registers */
+#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT (0U)
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+
+/*! @name RXFR1 - Receive FIFO Registers */
+#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT (0U)
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+
+/*! @name RXFR2 - Receive FIFO Registers */
+#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT (0U)
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+
+/*! @name RXFR3 - Receive FIFO Registers */
+#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT (0U)
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+
/*!
* @}
@@ -10690,12 +7245,10 @@ typedef struct {
#define SPI0_BASE (0x4002C000u)
/** Peripheral SPI0 base pointer */
#define SPI0 ((SPI_Type *)SPI0_BASE)
-#define SPI0_BASE_PTR (SPI0)
/** Peripheral SPI1 base address */
#define SPI1_BASE (0x4002D000u)
/** Peripheral SPI1 base pointer */
#define SPI1 ((SPI_Type *)SPI1_BASE)
-#define SPI1_BASE_PTR (SPI1)
/** Array initializer of SPI peripheral base addresses */
#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
/** Array initializer of SPI peripheral base pointers */
@@ -10703,67 +7256,6 @@ typedef struct {
/** Interrupt vectors for the SPI peripheral type */
#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register instance definitions */
-/* SPI0 */
-#define SPI0_MCR SPI_MCR_REG(SPI0)
-#define SPI0_TCR SPI_TCR_REG(SPI0)
-#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
-#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
-#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
-#define SPI0_SR SPI_SR_REG(SPI0)
-#define SPI0_RSER SPI_RSER_REG(SPI0)
-#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
-#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
-#define SPI0_POPR SPI_POPR_REG(SPI0)
-#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
-#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
-#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
-#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
-#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
-#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
-#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
-#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
-/* SPI1 */
-#define SPI1_MCR SPI_MCR_REG(SPI1)
-#define SPI1_TCR SPI_TCR_REG(SPI1)
-#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
-#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
-#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
-#define SPI1_SR SPI_SR_REG(SPI1)
-#define SPI1_RSER SPI_RSER_REG(SPI1)
-#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
-#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
-#define SPI1_POPR SPI_POPR_REG(SPI1)
-#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
-#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
-#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
-#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
-#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
-#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
-#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
-#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
-
-/* SPI - Register array accessors */
-#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
-#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
-#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
-#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SPI_Peripheral_Access_Layer */
@@ -10827,62 +7319,7 @@ typedef struct {
};
__IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
__IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
-} UART_Type, *UART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register accessors */
-#define UART_BDH_REG(base) ((base)->BDH)
-#define UART_BDL_REG(base) ((base)->BDL)
-#define UART_C1_REG(base) ((base)->C1)
-#define UART_C2_REG(base) ((base)->C2)
-#define UART_S1_REG(base) ((base)->S1)
-#define UART_S2_REG(base) ((base)->S2)
-#define UART_C3_REG(base) ((base)->C3)
-#define UART_D_REG(base) ((base)->D)
-#define UART_MA1_REG(base) ((base)->MA1)
-#define UART_MA2_REG(base) ((base)->MA2)
-#define UART_C4_REG(base) ((base)->C4)
-#define UART_C5_REG(base) ((base)->C5)
-#define UART_ED_REG(base) ((base)->ED)
-#define UART_MODEM_REG(base) ((base)->MODEM)
-#define UART_IR_REG(base) ((base)->IR)
-#define UART_PFIFO_REG(base) ((base)->PFIFO)
-#define UART_CFIFO_REG(base) ((base)->CFIFO)
-#define UART_SFIFO_REG(base) ((base)->SFIFO)
-#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
-#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
-#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
-#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
-#define UART_C7816_REG(base) ((base)->C7816)
-#define UART_IE7816_REG(base) ((base)->IE7816)
-#define UART_IS7816_REG(base) ((base)->IS7816)
-#define UART_WP7816_REG(base) ((base)->WP7816)
-#define UART_WN7816_REG(base) ((base)->WN7816)
-#define UART_WF7816_REG(base) ((base)->WF7816)
-#define UART_ET7816_REG(base) ((base)->ET7816)
-#define UART_TL7816_REG(base) ((base)->TL7816)
-#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
-#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
-#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
-#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
-#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
-#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
-#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
-#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
+} UART_Type;
/* ----------------------------------------------------------------------------
-- UART Register Masks
@@ -10893,504 +7330,427 @@ typedef struct {
* @{
*/
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR_WIDTH 5
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_RXEDGIE_WIDTH 1
-#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-#define UART_BDH_LBKDIE_WIDTH 1
-#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR_WIDTH 8
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PT_WIDTH 1
-#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_PE_WIDTH 1
-#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_ILT_WIDTH 1
-#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_WAKE_WIDTH 1
-#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_M_WIDTH 1
-#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_RSRC_WIDTH 1
-#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_UARTSWAI_WIDTH 1
-#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-#define UART_C1_LOOPS_WIDTH 1
-#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_SBK_WIDTH 1
-#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RWU_WIDTH 1
-#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_RE_WIDTH 1
-#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_TE_WIDTH 1
-#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_ILIE_WIDTH 1
-#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_RIE_WIDTH 1
-#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TCIE_WIDTH 1
-#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-#define UART_C2_TIE_WIDTH 1
-#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_PF_WIDTH 1
-#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_FE_WIDTH 1
-#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_NF_WIDTH 1
-#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_OR_WIDTH 1
-#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_IDLE_WIDTH 1
-#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_RDRF_WIDTH 1
-#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TC_WIDTH 1
-#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-#define UART_S1_TDRE_WIDTH 1
-#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_RAF_WIDTH 1
-#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_LBKDE_WIDTH 1
-#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_BRK13_WIDTH 1
-#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RWUID_WIDTH 1
-#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_RXINV_WIDTH 1
-#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
-#define UART_S2_MSBF_MASK 0x20u
-#define UART_S2_MSBF_SHIFT 5
-#define UART_S2_MSBF_WIDTH 1
-#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_RXEDGIF_WIDTH 1
-#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-#define UART_S2_LBKDIF_WIDTH 1
-#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_PEIE_WIDTH 1
-#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_FEIE_WIDTH 1
-#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_NEIE_WIDTH 1
-#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_ORIE_WIDTH 1
-#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXINV_WIDTH 1
-#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_TXDIR_WIDTH 1
-#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_T8_WIDTH 1
-#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-#define UART_C3_R8_WIDTH 1
-#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
-/* D Bit Fields */
-#define UART_D_RT_MASK 0xFFu
-#define UART_D_RT_SHIFT 0
-#define UART_D_RT_WIDTH 8
-#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK 0xFFu
-#define UART_MA1_MA_SHIFT 0
-#define UART_MA1_MA_WIDTH 8
-#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK 0xFFu
-#define UART_MA2_MA_SHIFT 0
-#define UART_MA2_MA_WIDTH 8
-#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK 0x1Fu
-#define UART_C4_BRFA_SHIFT 0
-#define UART_C4_BRFA_WIDTH 5
-#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK 0x20u
-#define UART_C4_M10_SHIFT 5
-#define UART_C4_M10_WIDTH 1
-#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
-#define UART_C4_MAEN2_MASK 0x40u
-#define UART_C4_MAEN2_SHIFT 6
-#define UART_C4_MAEN2_WIDTH 1
-#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
-#define UART_C4_MAEN1_MASK 0x80u
-#define UART_C4_MAEN1_SHIFT 7
-#define UART_C4_MAEN1_WIDTH 1
-#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
-/* C5 Bit Fields */
-#define UART_C5_RDMAS_MASK 0x20u
-#define UART_C5_RDMAS_SHIFT 5
-#define UART_C5_RDMAS_WIDTH 1
-#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
-#define UART_C5_TDMAS_MASK 0x80u
-#define UART_C5_TDMAS_SHIFT 7
-#define UART_C5_TDMAS_WIDTH 1
-#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK 0x40u
-#define UART_ED_PARITYE_SHIFT 6
-#define UART_ED_PARITYE_WIDTH 1
-#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
-#define UART_ED_NOISY_MASK 0x80u
-#define UART_ED_NOISY_SHIFT 7
-#define UART_ED_NOISY_WIDTH 1
-#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK 0x1u
-#define UART_MODEM_TXCTSE_SHIFT 0
-#define UART_MODEM_TXCTSE_WIDTH 1
-#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
-#define UART_MODEM_TXRTSE_MASK 0x2u
-#define UART_MODEM_TXRTSE_SHIFT 1
-#define UART_MODEM_TXRTSE_WIDTH 1
-#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
-#define UART_MODEM_TXRTSPOL_MASK 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT 2
-#define UART_MODEM_TXRTSPOL_WIDTH 1
-#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
-#define UART_MODEM_RXRTSE_MASK 0x8u
-#define UART_MODEM_RXRTSE_SHIFT 3
-#define UART_MODEM_RXRTSE_WIDTH 1
-#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK 0x3u
-#define UART_IR_TNP_SHIFT 0
-#define UART_IR_TNP_WIDTH 2
-#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK 0x4u
-#define UART_IR_IREN_SHIFT 2
-#define UART_IR_IREN_WIDTH 1
-#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
-#define UART_PFIFO_RXFIFOSIZE_WIDTH 3
-#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK 0x8u
-#define UART_PFIFO_RXFE_SHIFT 3
-#define UART_PFIFO_RXFE_WIDTH 1
-#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
-#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
-#define UART_PFIFO_TXFIFOSIZE_WIDTH 3
-#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK 0x80u
-#define UART_PFIFO_TXFE_SHIFT 7
-#define UART_PFIFO_TXFE_WIDTH 1
-#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK 0x1u
-#define UART_CFIFO_RXUFE_SHIFT 0
-#define UART_CFIFO_RXUFE_WIDTH 1
-#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
-#define UART_CFIFO_TXOFE_MASK 0x2u
-#define UART_CFIFO_TXOFE_SHIFT 1
-#define UART_CFIFO_TXOFE_WIDTH 1
-#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
-#define UART_CFIFO_RXOFE_MASK 0x4u
-#define UART_CFIFO_RXOFE_SHIFT 2
-#define UART_CFIFO_RXOFE_WIDTH 1
-#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
-#define UART_CFIFO_RXFLUSH_MASK 0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT 6
-#define UART_CFIFO_RXFLUSH_WIDTH 1
-#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
-#define UART_CFIFO_TXFLUSH_MASK 0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT 7
-#define UART_CFIFO_TXFLUSH_WIDTH 1
-#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK 0x1u
-#define UART_SFIFO_RXUF_SHIFT 0
-#define UART_SFIFO_RXUF_WIDTH 1
-#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
-#define UART_SFIFO_TXOF_MASK 0x2u
-#define UART_SFIFO_TXOF_SHIFT 1
-#define UART_SFIFO_TXOF_WIDTH 1
-#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
-#define UART_SFIFO_RXOF_MASK 0x4u
-#define UART_SFIFO_RXOF_SHIFT 2
-#define UART_SFIFO_RXOF_WIDTH 1
-#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
-#define UART_SFIFO_RXEMPT_MASK 0x40u
-#define UART_SFIFO_RXEMPT_SHIFT 6
-#define UART_SFIFO_RXEMPT_WIDTH 1
-#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
-#define UART_SFIFO_TXEMPT_MASK 0x80u
-#define UART_SFIFO_TXEMPT_SHIFT 7
-#define UART_SFIFO_TXEMPT_WIDTH 1
-#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT 0
-#define UART_TWFIFO_TXWATER_WIDTH 8
-#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT 0
-#define UART_TCFIFO_TXCOUNT_WIDTH 8
-#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT 0
-#define UART_RWFIFO_RXWATER_WIDTH 8
-#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT 0
-#define UART_RCFIFO_RXCOUNT_WIDTH 8
-#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK 0x1u
-#define UART_C7816_ISO_7816E_SHIFT 0
-#define UART_C7816_ISO_7816E_WIDTH 1
-#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
-#define UART_C7816_TTYPE_MASK 0x2u
-#define UART_C7816_TTYPE_SHIFT 1
-#define UART_C7816_TTYPE_WIDTH 1
-#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
-#define UART_C7816_INIT_MASK 0x4u
-#define UART_C7816_INIT_SHIFT 2
-#define UART_C7816_INIT_WIDTH 1
-#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
-#define UART_C7816_ANACK_MASK 0x8u
-#define UART_C7816_ANACK_SHIFT 3
-#define UART_C7816_ANACK_WIDTH 1
-#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
-#define UART_C7816_ONACK_MASK 0x10u
-#define UART_C7816_ONACK_SHIFT 4
-#define UART_C7816_ONACK_WIDTH 1
-#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK 0x1u
-#define UART_IE7816_RXTE_SHIFT 0
-#define UART_IE7816_RXTE_WIDTH 1
-#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
-#define UART_IE7816_TXTE_MASK 0x2u
-#define UART_IE7816_TXTE_SHIFT 1
-#define UART_IE7816_TXTE_WIDTH 1
-#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
-#define UART_IE7816_GTVE_MASK 0x4u
-#define UART_IE7816_GTVE_SHIFT 2
-#define UART_IE7816_GTVE_WIDTH 1
-#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
-#define UART_IE7816_ADTE_MASK 0x8u
-#define UART_IE7816_ADTE_SHIFT 3
-#define UART_IE7816_ADTE_WIDTH 1
-#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_ADTE_SHIFT))&UART_IE7816_ADTE_MASK)
-#define UART_IE7816_INITDE_MASK 0x10u
-#define UART_IE7816_INITDE_SHIFT 4
-#define UART_IE7816_INITDE_WIDTH 1
-#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
-#define UART_IE7816_BWTE_MASK 0x20u
-#define UART_IE7816_BWTE_SHIFT 5
-#define UART_IE7816_BWTE_WIDTH 1
-#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
-#define UART_IE7816_CWTE_MASK 0x40u
-#define UART_IE7816_CWTE_SHIFT 6
-#define UART_IE7816_CWTE_WIDTH 1
-#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
-#define UART_IE7816_WTE_MASK 0x80u
-#define UART_IE7816_WTE_SHIFT 7
-#define UART_IE7816_WTE_WIDTH 1
-#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK 0x1u
-#define UART_IS7816_RXT_SHIFT 0
-#define UART_IS7816_RXT_WIDTH 1
-#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
-#define UART_IS7816_TXT_MASK 0x2u
-#define UART_IS7816_TXT_SHIFT 1
-#define UART_IS7816_TXT_WIDTH 1
-#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
-#define UART_IS7816_GTV_MASK 0x4u
-#define UART_IS7816_GTV_SHIFT 2
-#define UART_IS7816_GTV_WIDTH 1
-#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
-#define UART_IS7816_ADT_MASK 0x8u
-#define UART_IS7816_ADT_SHIFT 3
-#define UART_IS7816_ADT_WIDTH 1
-#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_ADT_SHIFT))&UART_IS7816_ADT_MASK)
-#define UART_IS7816_INITD_MASK 0x10u
-#define UART_IS7816_INITD_SHIFT 4
-#define UART_IS7816_INITD_WIDTH 1
-#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
-#define UART_IS7816_BWT_MASK 0x20u
-#define UART_IS7816_BWT_SHIFT 5
-#define UART_IS7816_BWT_WIDTH 1
-#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
-#define UART_IS7816_CWT_MASK 0x40u
-#define UART_IS7816_CWT_SHIFT 6
-#define UART_IS7816_CWT_WIDTH 1
-#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
-#define UART_IS7816_WT_MASK 0x80u
-#define UART_IS7816_WT_SHIFT 7
-#define UART_IS7816_WT_WIDTH 1
-#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
-/* WP7816 Bit Fields */
-#define UART_WP7816_WTX_MASK 0xFFu
-#define UART_WP7816_WTX_SHIFT 0
-#define UART_WP7816_WTX_WIDTH 8
-#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK 0xFFu
-#define UART_WN7816_GTN_SHIFT 0
-#define UART_WN7816_GTN_WIDTH 8
-#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK 0xFFu
-#define UART_WF7816_GTFD_SHIFT 0
-#define UART_WF7816_GTFD_WIDTH 8
-#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT 0
-#define UART_ET7816_RXTHRESHOLD_WIDTH 4
-#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT 4
-#define UART_ET7816_TXTHRESHOLD_WIDTH 4
-#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK 0xFFu
-#define UART_TL7816_TLEN_SHIFT 0
-#define UART_TL7816_TLEN_WIDTH 8
-#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-/* AP7816A_T0 Bit Fields */
-#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
-#define UART_AP7816A_T0_ADTI_H_SHIFT 0
-#define UART_AP7816A_T0_ADTI_H_WIDTH 8
-#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
-/* AP7816B_T0 Bit Fields */
-#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
-#define UART_AP7816B_T0_ADTI_L_SHIFT 0
-#define UART_AP7816B_T0_ADTI_L_WIDTH 8
-#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
-/* WP7816A_T0 Bit Fields */
-#define UART_WP7816A_T0_WI_H_MASK 0xFFu
-#define UART_WP7816A_T0_WI_H_SHIFT 0
-#define UART_WP7816A_T0_WI_H_WIDTH 8
-#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
-/* WP7816B_T0 Bit Fields */
-#define UART_WP7816B_T0_WI_L_MASK 0xFFu
-#define UART_WP7816B_T0_WI_L_SHIFT 0
-#define UART_WP7816B_T0_WI_L_WIDTH 8
-#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
-/* WP7816A_T1 Bit Fields */
-#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
-#define UART_WP7816A_T1_BWI_H_SHIFT 0
-#define UART_WP7816A_T1_BWI_H_WIDTH 8
-#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
-/* WP7816B_T1 Bit Fields */
-#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
-#define UART_WP7816B_T1_BWI_L_SHIFT 0
-#define UART_WP7816B_T1_BWI_L_WIDTH 8
-#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
-/* WGP7816_T1 Bit Fields */
-#define UART_WGP7816_T1_BGI_MASK 0xFu
-#define UART_WGP7816_T1_BGI_SHIFT 0
-#define UART_WGP7816_T1_BGI_WIDTH 4
-#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
-#define UART_WGP7816_T1_CWI1_MASK 0xF0u
-#define UART_WGP7816_T1_CWI1_SHIFT 4
-#define UART_WGP7816_T1_CWI1_WIDTH 4
-#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
-/* WP7816C_T1 Bit Fields */
-#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
-#define UART_WP7816C_T1_CWI2_SHIFT 0
-#define UART_WP7816C_T1_CWI2_WIDTH 5
-#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+/*! @name BDH - UART Baud Rate Registers: High */
+#define UART_BDH_SBR_MASK (0x1FU)
+#define UART_BDH_SBR_SHIFT (0U)
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT (6U)
+#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK (0x80U)
+#define UART_BDH_LBKDIE_SHIFT (7U)
+#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+#define UART_BDL_SBR_MASK (0xFFU)
+#define UART_BDL_SBR_SHIFT (0U)
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK (0x1U)
+#define UART_C1_PT_SHIFT (0U)
+#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK (0x2U)
+#define UART_C1_PE_SHIFT (1U)
+#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK (0x4U)
+#define UART_C1_ILT_SHIFT (2U)
+#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK (0x8U)
+#define UART_C1_WAKE_SHIFT (3U)
+#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK (0x10U)
+#define UART_C1_M_SHIFT (4U)
+#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK (0x20U)
+#define UART_C1_RSRC_SHIFT (5U)
+#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK (0x40U)
+#define UART_C1_UARTSWAI_SHIFT (6U)
+#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK (0x80U)
+#define UART_C1_LOOPS_SHIFT (7U)
+#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK (0x1U)
+#define UART_C2_SBK_SHIFT (0U)
+#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK (0x2U)
+#define UART_C2_RWU_SHIFT (1U)
+#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK (0x4U)
+#define UART_C2_RE_SHIFT (2U)
+#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK (0x8U)
+#define UART_C2_TE_SHIFT (3U)
+#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK (0x10U)
+#define UART_C2_ILIE_SHIFT (4U)
+#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK (0x20U)
+#define UART_C2_RIE_SHIFT (5U)
+#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK (0x40U)
+#define UART_C2_TCIE_SHIFT (6U)
+#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK (0x80U)
+#define UART_C2_TIE_SHIFT (7U)
+#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK (0x1U)
+#define UART_S1_PF_SHIFT (0U)
+#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK (0x2U)
+#define UART_S1_FE_SHIFT (1U)
+#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK (0x4U)
+#define UART_S1_NF_SHIFT (2U)
+#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK (0x8U)
+#define UART_S1_OR_SHIFT (3U)
+#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK (0x10U)
+#define UART_S1_IDLE_SHIFT (4U)
+#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK (0x20U)
+#define UART_S1_RDRF_SHIFT (5U)
+#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK (0x40U)
+#define UART_S1_TC_SHIFT (6U)
+#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK (0x80U)
+#define UART_S1_TDRE_SHIFT (7U)
+#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK (0x1U)
+#define UART_S2_RAF_SHIFT (0U)
+#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK (0x2U)
+#define UART_S2_LBKDE_SHIFT (1U)
+#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK (0x4U)
+#define UART_S2_BRK13_SHIFT (2U)
+#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK (0x8U)
+#define UART_S2_RWUID_SHIFT (3U)
+#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK (0x10U)
+#define UART_S2_RXINV_SHIFT (4U)
+#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK (0x20U)
+#define UART_S2_MSBF_SHIFT (5U)
+#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK (0x40U)
+#define UART_S2_RXEDGIF_SHIFT (6U)
+#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK (0x80U)
+#define UART_S2_LBKDIF_SHIFT (7U)
+#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK (0x1U)
+#define UART_C3_PEIE_SHIFT (0U)
+#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK (0x2U)
+#define UART_C3_FEIE_SHIFT (1U)
+#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK (0x4U)
+#define UART_C3_NEIE_SHIFT (2U)
+#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK (0x8U)
+#define UART_C3_ORIE_SHIFT (3U)
+#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK (0x10U)
+#define UART_C3_TXINV_SHIFT (4U)
+#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK (0x20U)
+#define UART_C3_TXDIR_SHIFT (5U)
+#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK (0x40U)
+#define UART_C3_T8_SHIFT (6U)
+#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK (0x80U)
+#define UART_C3_R8_SHIFT (7U)
+#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_RT_MASK (0xFFU)
+#define UART_D_RT_SHIFT (0U)
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART_MA1_MA_MASK (0xFFU)
+#define UART_MA1_MA_SHIFT (0U)
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART_MA2_MA_MASK (0xFFU)
+#define UART_MA2_MA_SHIFT (0U)
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_BRFA_MASK (0x1FU)
+#define UART_C4_BRFA_SHIFT (0U)
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK (0x20U)
+#define UART_C4_M10_SHIFT (5U)
+#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK (0x40U)
+#define UART_C4_MAEN2_SHIFT (6U)
+#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK (0x80U)
+#define UART_C4_MAEN1_SHIFT (7U)
+#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART_C5_RDMAS_MASK (0x20U)
+#define UART_C5_RDMAS_SHIFT (5U)
+#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK (0x80U)
+#define UART_C5_TDMAS_SHIFT (7U)
+#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+
+/*! @name ED - UART Extended Data Register */
+#define UART_ED_PARITYE_MASK (0x40U)
+#define UART_ED_PARITYE_SHIFT (6U)
+#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK (0x80U)
+#define UART_ED_NOISY_SHIFT (7U)
+#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+
+/*! @name MODEM - UART Modem Register */
+#define UART_MODEM_TXCTSE_MASK (0x1U)
+#define UART_MODEM_TXCTSE_SHIFT (0U)
+#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK (0x2U)
+#define UART_MODEM_TXRTSE_SHIFT (1U)
+#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK (0x4U)
+#define UART_MODEM_TXRTSPOL_SHIFT (2U)
+#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK (0x8U)
+#define UART_MODEM_RXRTSE_SHIFT (3U)
+#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+
+/*! @name IR - UART Infrared Register */
+#define UART_IR_TNP_MASK (0x3U)
+#define UART_IR_TNP_SHIFT (0U)
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK (0x4U)
+#define UART_IR_IREN_SHIFT (2U)
+#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+
+/*! @name PFIFO - UART FIFO Parameters */
+#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK (0x8U)
+#define UART_PFIFO_RXFE_SHIFT (3U)
+#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK (0x80U)
+#define UART_PFIFO_TXFE_SHIFT (7U)
+#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+
+/*! @name CFIFO - UART FIFO Control Register */
+#define UART_CFIFO_RXUFE_MASK (0x1U)
+#define UART_CFIFO_RXUFE_SHIFT (0U)
+#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK (0x2U)
+#define UART_CFIFO_TXOFE_SHIFT (1U)
+#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK (0x4U)
+#define UART_CFIFO_RXOFE_SHIFT (2U)
+#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK (0x40U)
+#define UART_CFIFO_RXFLUSH_SHIFT (6U)
+#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK (0x80U)
+#define UART_CFIFO_TXFLUSH_SHIFT (7U)
+#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+
+/*! @name SFIFO - UART FIFO Status Register */
+#define UART_SFIFO_RXUF_MASK (0x1U)
+#define UART_SFIFO_RXUF_SHIFT (0U)
+#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK (0x2U)
+#define UART_SFIFO_TXOF_SHIFT (1U)
+#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK (0x4U)
+#define UART_SFIFO_RXOF_SHIFT (2U)
+#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK (0x40U)
+#define UART_SFIFO_RXEMPT_SHIFT (6U)
+#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK (0x80U)
+#define UART_SFIFO_TXEMPT_SHIFT (7U)
+#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+#define UART_TWFIFO_TXWATER_MASK (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT (0U)
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+#define UART_RWFIFO_RXWATER_MASK (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT (0U)
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+
+/*! @name C7816 - UART 7816 Control Register */
+#define UART_C7816_ISO_7816E_MASK (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT (0U)
+#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK (0x2U)
+#define UART_C7816_TTYPE_SHIFT (1U)
+#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK (0x4U)
+#define UART_C7816_INIT_SHIFT (2U)
+#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK (0x8U)
+#define UART_C7816_ANACK_SHIFT (3U)
+#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK (0x10U)
+#define UART_C7816_ONACK_SHIFT (4U)
+#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+#define UART_IE7816_RXTE_MASK (0x1U)
+#define UART_IE7816_RXTE_SHIFT (0U)
+#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK (0x2U)
+#define UART_IE7816_TXTE_SHIFT (1U)
+#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK (0x4U)
+#define UART_IE7816_GTVE_SHIFT (2U)
+#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+#define UART_IE7816_ADTE_MASK (0x8U)
+#define UART_IE7816_ADTE_SHIFT (3U)
+#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
+#define UART_IE7816_INITDE_MASK (0x10U)
+#define UART_IE7816_INITDE_SHIFT (4U)
+#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK (0x20U)
+#define UART_IE7816_BWTE_SHIFT (5U)
+#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK (0x40U)
+#define UART_IE7816_CWTE_SHIFT (6U)
+#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK (0x80U)
+#define UART_IE7816_WTE_SHIFT (7U)
+#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+#define UART_IS7816_RXT_MASK (0x1U)
+#define UART_IS7816_RXT_SHIFT (0U)
+#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK (0x2U)
+#define UART_IS7816_TXT_SHIFT (1U)
+#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK (0x4U)
+#define UART_IS7816_GTV_SHIFT (2U)
+#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+#define UART_IS7816_ADT_MASK (0x8U)
+#define UART_IS7816_ADT_SHIFT (3U)
+#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
+#define UART_IS7816_INITD_MASK (0x10U)
+#define UART_IS7816_INITD_SHIFT (4U)
+#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK (0x20U)
+#define UART_IS7816_BWT_SHIFT (5U)
+#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK (0x40U)
+#define UART_IS7816_CWT_SHIFT (6U)
+#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK (0x80U)
+#define UART_IS7816_WT_SHIFT (7U)
+#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+
+/*! @name WP7816 - UART 7816 Wait Parameter Register */
+#define UART_WP7816_WTX_MASK (0xFFU)
+#define UART_WP7816_WTX_SHIFT (0U)
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+#define UART_WN7816_GTN_MASK (0xFFU)
+#define UART_WN7816_GTN_SHIFT (0U)
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+#define UART_WF7816_GTFD_MASK (0xFFU)
+#define UART_WF7816_GTFD_SHIFT (0U)
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+#define UART_TL7816_TLEN_MASK (0xFFU)
+#define UART_TL7816_TLEN_SHIFT (0U)
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+
+/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
+#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
+#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
+
+/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
+#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
+#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
+
+/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
+#define UART_WP7816A_T0_WI_H_SHIFT (0U)
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
+
+/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
+#define UART_WP7816B_T0_WI_L_SHIFT (0U)
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
+
+/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
+#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
+
+/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
+#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
+
+/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
+#define UART_WGP7816_T1_BGI_MASK (0xFU)
+#define UART_WGP7816_T1_BGI_SHIFT (0U)
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
+#define UART_WGP7816_T1_CWI1_SHIFT (4U)
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
+
+/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
+#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
+#define UART_WP7816C_T1_CWI2_SHIFT (0U)
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
+
/*!
* @}
@@ -11402,17 +7762,14 @@ typedef struct {
#define UART0_BASE (0x4006A000u)
/** Peripheral UART0 base pointer */
#define UART0 ((UART_Type *)UART0_BASE)
-#define UART0_BASE_PTR (UART0)
/** Peripheral UART1 base address */
#define UART1_BASE (0x4006B000u)
/** Peripheral UART1 base pointer */
#define UART1 ((UART_Type *)UART1_BASE)
-#define UART1_BASE_PTR (UART1)
/** Peripheral UART2 base address */
#define UART2_BASE (0x4006C000u)
/** Peripheral UART2 base pointer */
#define UART2 ((UART_Type *)UART2_BASE)
-#define UART2_BASE_PTR (UART2)
/** Array initializer of UART peripheral base addresses */
#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
/** Array initializer of UART peripheral base pointers */
@@ -11421,108 +7778,6 @@ typedef struct {
#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register instance definitions */
-/* UART0 */
-#define UART0_BDH UART_BDH_REG(UART0)
-#define UART0_BDL UART_BDL_REG(UART0)
-#define UART0_C1 UART_C1_REG(UART0)
-#define UART0_C2 UART_C2_REG(UART0)
-#define UART0_S1 UART_S1_REG(UART0)
-#define UART0_S2 UART_S2_REG(UART0)
-#define UART0_C3 UART_C3_REG(UART0)
-#define UART0_D UART_D_REG(UART0)
-#define UART0_MA1 UART_MA1_REG(UART0)
-#define UART0_MA2 UART_MA2_REG(UART0)
-#define UART0_C4 UART_C4_REG(UART0)
-#define UART0_C5 UART_C5_REG(UART0)
-#define UART0_ED UART_ED_REG(UART0)
-#define UART0_MODEM UART_MODEM_REG(UART0)
-#define UART0_IR UART_IR_REG(UART0)
-#define UART0_PFIFO UART_PFIFO_REG(UART0)
-#define UART0_CFIFO UART_CFIFO_REG(UART0)
-#define UART0_SFIFO UART_SFIFO_REG(UART0)
-#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
-#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
-#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
-#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
-#define UART0_C7816 UART_C7816_REG(UART0)
-#define UART0_IE7816 UART_IE7816_REG(UART0)
-#define UART0_IS7816 UART_IS7816_REG(UART0)
-#define UART0_WP7816 UART_WP7816_REG(UART0)
-#define UART0_WN7816 UART_WN7816_REG(UART0)
-#define UART0_WF7816 UART_WF7816_REG(UART0)
-#define UART0_ET7816 UART_ET7816_REG(UART0)
-#define UART0_TL7816 UART_TL7816_REG(UART0)
-#define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
-#define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
-#define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
-#define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
-#define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
-#define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
-#define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
-#define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
-/* UART1 */
-#define UART1_BDH UART_BDH_REG(UART1)
-#define UART1_BDL UART_BDL_REG(UART1)
-#define UART1_C1 UART_C1_REG(UART1)
-#define UART1_C2 UART_C2_REG(UART1)
-#define UART1_S1 UART_S1_REG(UART1)
-#define UART1_S2 UART_S2_REG(UART1)
-#define UART1_C3 UART_C3_REG(UART1)
-#define UART1_D UART_D_REG(UART1)
-#define UART1_MA1 UART_MA1_REG(UART1)
-#define UART1_MA2 UART_MA2_REG(UART1)
-#define UART1_C4 UART_C4_REG(UART1)
-#define UART1_C5 UART_C5_REG(UART1)
-#define UART1_ED UART_ED_REG(UART1)
-#define UART1_MODEM UART_MODEM_REG(UART1)
-#define UART1_IR UART_IR_REG(UART1)
-#define UART1_PFIFO UART_PFIFO_REG(UART1)
-#define UART1_CFIFO UART_CFIFO_REG(UART1)
-#define UART1_SFIFO UART_SFIFO_REG(UART1)
-#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
-#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
-#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
-#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
-/* UART2 */
-#define UART2_BDH UART_BDH_REG(UART2)
-#define UART2_BDL UART_BDL_REG(UART2)
-#define UART2_C1 UART_C1_REG(UART2)
-#define UART2_C2 UART_C2_REG(UART2)
-#define UART2_S1 UART_S1_REG(UART2)
-#define UART2_S2 UART_S2_REG(UART2)
-#define UART2_C3 UART_C3_REG(UART2)
-#define UART2_D UART_D_REG(UART2)
-#define UART2_MA1 UART_MA1_REG(UART2)
-#define UART2_MA2 UART_MA2_REG(UART2)
-#define UART2_C4 UART_C4_REG(UART2)
-#define UART2_C5 UART_C5_REG(UART2)
-#define UART2_ED UART_ED_REG(UART2)
-#define UART2_MODEM UART_MODEM_REG(UART2)
-#define UART2_IR UART_IR_REG(UART2)
-#define UART2_PFIFO UART_PFIFO_REG(UART2)
-#define UART2_CFIFO UART_CFIFO_REG(UART2)
-#define UART2_SFIFO UART_SFIFO_REG(UART2)
-#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
-#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
-#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
-#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group UART_Peripheral_Access_Layer */
@@ -11602,56 +7857,7 @@ typedef struct {
__IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
uint8_t RESERVED_28[23];
__IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
-} USB_Type, *USB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register accessors */
-#define USB_PERID_REG(base) ((base)->PERID)
-#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
-#define USB_REV_REG(base) ((base)->REV)
-#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
-#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
-#define USB_OTGICR_REG(base) ((base)->OTGICR)
-#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
-#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
-#define USB_ISTAT_REG(base) ((base)->ISTAT)
-#define USB_INTEN_REG(base) ((base)->INTEN)
-#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
-#define USB_ERREN_REG(base) ((base)->ERREN)
-#define USB_STAT_REG(base) ((base)->STAT)
-#define USB_CTL_REG(base) ((base)->CTL)
-#define USB_ADDR_REG(base) ((base)->ADDR)
-#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
-#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
-#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
-#define USB_TOKEN_REG(base) ((base)->TOKEN)
-#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
-#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
-#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
-#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
-#define USB_ENDPT_COUNT 16
-#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
-#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
-#define USB_CONTROL_REG(base) ((base)->CONTROL)
-#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
-#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
-#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
-#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
-#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
+} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
@@ -11662,445 +7868,377 @@ typedef struct {
* @{
*/
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID_WIDTH 6
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID_WIDTH 6
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV_WIDTH 8
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-#define USB_ADDINFO_IEHOST_WIDTH 1
-#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_AVBUSCHG_WIDTH 1
-#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_B_SESS_CHG_WIDTH 1
-#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_SESSVLDCHG_WIDTH 1
-#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH 1
-#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_ONEMSEC_WIDTH 1
-#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-#define USB_OTGISTAT_IDCHG_WIDTH 1
-#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_AVBUSEN_WIDTH 1
-#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_BSESSEN_WIDTH 1
-#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_SESSVLDEN_WIDTH 1
-#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_LINESTATEEN_WIDTH 1
-#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_ONEMSECEN_WIDTH 1
-#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-#define USB_OTGICR_IDEN_WIDTH 1
-#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_AVBUSVLD_WIDTH 1
-#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_BSESSEND_WIDTH 1
-#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_SESS_VLD_WIDTH 1
-#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_LINESTATESTABLE_WIDTH 1
-#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ONEMSECEN_WIDTH 1
-#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-#define USB_OTGSTAT_ID_WIDTH 1
-#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_OTGEN_WIDTH 1
-#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DMLOW_WIDTH 1
-#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPLOW_WIDTH 1
-#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-#define USB_OTGCTL_DPHIGH_WIDTH 1
-#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_USBRST_WIDTH 1
-#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_ERROR_WIDTH 1
-#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_SOFTOK_WIDTH 1
-#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_TOKDNE_WIDTH 1
-#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_SLEEP_WIDTH 1
-#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_RESUME_WIDTH 1
-#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_ATTACH_WIDTH 1
-#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-#define USB_ISTAT_STALL_WIDTH 1
-#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_USBRSTEN_WIDTH 1
-#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_ERROREN_WIDTH 1
-#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_SOFTOKEN_WIDTH 1
-#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_TOKDNEEN_WIDTH 1
-#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_SLEEPEN_WIDTH 1
-#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_RESUMEEN_WIDTH 1
-#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_ATTACHEN_WIDTH 1
-#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-#define USB_INTEN_STALLEN_WIDTH 1
-#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_PIDERR_WIDTH 1
-#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC5EOF_WIDTH 1
-#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_CRC16_WIDTH 1
-#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_DFN8_WIDTH 1
-#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_BTOERR_WIDTH 1
-#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_DMAERR_WIDTH 1
-#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-#define USB_ERRSTAT_BTSERR_WIDTH 1
-#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_PIDERREN_WIDTH 1
-#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC5EOFEN_WIDTH 1
-#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_CRC16EN_WIDTH 1
-#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_DFN8EN_WIDTH 1
-#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_BTOERREN_WIDTH 1
-#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_DMAERREN_WIDTH 1
-#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-#define USB_ERREN_BTSERREN_WIDTH 1
-#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_ODD_WIDTH 1
-#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_TX_WIDTH 1
-#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP_WIDTH 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_USBENSOFEN_WIDTH 1
-#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_ODDRST_WIDTH 1
-#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_RESUME_WIDTH 1
-#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_HOSTMODEEN_WIDTH 1
-#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_RESET_WIDTH 1
-#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH 1
-#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_SE0_WIDTH 1
-#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-#define USB_CTL_JSTATE_WIDTH 1
-#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR_WIDTH 7
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-#define USB_ADDR_LSEN_WIDTH 1
-#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA_WIDTH 7
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM_WIDTH 8
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM_WIDTH 3
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT_WIDTH 4
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID_WIDTH 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT_WIDTH 8
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA_WIDTH 8
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA_WIDTH 8
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPHSHK_WIDTH 1
-#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPSTALL_WIDTH 1
-#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPTXEN_WIDTH 1
-#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPRXEN_WIDTH 1
-#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_EPCTLDIS_WIDTH 1
-#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_RETRYDIS_WIDTH 1
-#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-#define USB_ENDPT_HOSTWOHUB_WIDTH 1
-#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_PDE_WIDTH 1
-#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-#define USB_USBCTRL_SUSP_WIDTH 1
-#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DMPD_WIDTH 1
-#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPD_WIDTH 1
-#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-#define USB_OBSERVE_DPPU_WIDTH 1
-#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-#define USB_CONTROL_DPPULLUPNONOTG_WIDTH 1
-#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_USB_RESUME_INT_WIDTH 1
-#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_SYNC_DET_WIDTH 1
-#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH 1
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESMEN_WIDTH 1
-#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-#define USB_USBTRC0_USBRESET_WIDTH 1
-#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT 0
-#define USB_USBFRMADJUST_ADJ_WIDTH 8
-#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
-/* CLK_RECOVER_CTRL Bit Fields */
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
-/* CLK_RECOVER_IRC_EN Bit Fields */
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH 1
-#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH 1
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
-/* CLK_RECOVER_INT_STATUS Bit Fields */
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
+#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT (7U)
+#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_AVBUSEN_MASK (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT (0U)
+#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT (2U)
+#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
+#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK (0x80U)
+#define USB_OTGICR_IDEN_SHIFT (7U)
+#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
+#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
+#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
+#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK (0x80U)
+#define USB_OTGSTAT_ID_SHIFT (7U)
+#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
/*!
* @}
@@ -12112,7 +8250,6 @@ typedef struct {
#define USB0_BASE (0x40072000u)
/** Peripheral USB0 base pointer */
#define USB0 ((USB_Type *)USB0_BASE)
-#define USB0_BASE_PTR (USB0)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { USB0_BASE }
/** Array initializer of USB peripheral base pointers */
@@ -12120,73 +8257,6 @@ typedef struct {
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS { USB0_IRQn }
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register instance definitions */
-/* USB0 */
-#define USB0_PERID USB_PERID_REG(USB0)
-#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
-#define USB0_REV USB_REV_REG(USB0)
-#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
-#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
-#define USB0_OTGICR USB_OTGICR_REG(USB0)
-#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
-#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
-#define USB0_ISTAT USB_ISTAT_REG(USB0)
-#define USB0_INTEN USB_INTEN_REG(USB0)
-#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
-#define USB0_ERREN USB_ERREN_REG(USB0)
-#define USB0_STAT USB_STAT_REG(USB0)
-#define USB0_CTL USB_CTL_REG(USB0)
-#define USB0_ADDR USB_ADDR_REG(USB0)
-#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
-#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
-#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
-#define USB0_TOKEN USB_TOKEN_REG(USB0)
-#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
-#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
-#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
-#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
-#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
-#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
-#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
-#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
-#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
-#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
-#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
-#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
-#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
-#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
-#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
-#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
-#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
-#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
-#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
-#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
-#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
-#define USB0_CONTROL USB_CONTROL_REG(USB0)
-#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
-#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
-#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
-#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
-#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
-
-/* USB - Register array accessors */
-#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
@@ -12205,26 +8275,7 @@ typedef struct {
typedef struct {
__IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
__IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type, *VREF_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register accessors */
-#define VREF_TRM_REG(base) ((base)->TRM)
-#define VREF_SC_REG(base) ((base)->SC)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
+} VREF_Type;
/* ----------------------------------------------------------------------------
-- VREF Register Masks
@@ -12235,36 +8286,31 @@ typedef struct {
* @{
*/
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK 0x3Fu
-#define VREF_TRM_TRIM_SHIFT 0
-#define VREF_TRM_TRIM_WIDTH 6
-#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK 0x40u
-#define VREF_TRM_CHOPEN_SHIFT 6
-#define VREF_TRM_CHOPEN_WIDTH 1
-#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK 0x3u
-#define VREF_SC_MODE_LV_SHIFT 0
-#define VREF_SC_MODE_LV_WIDTH 2
-#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK 0x4u
-#define VREF_SC_VREFST_SHIFT 2
-#define VREF_SC_VREFST_WIDTH 1
-#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
-#define VREF_SC_ICOMPEN_MASK 0x20u
-#define VREF_SC_ICOMPEN_SHIFT 5
-#define VREF_SC_ICOMPEN_WIDTH 1
-#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
-#define VREF_SC_REGEN_MASK 0x40u
-#define VREF_SC_REGEN_SHIFT 6
-#define VREF_SC_REGEN_WIDTH 1
-#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
-#define VREF_SC_VREFEN_MASK 0x80u
-#define VREF_SC_VREFEN_SHIFT 7
-#define VREF_SC_VREFEN_WIDTH 1
-#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK (0x3FU)
+#define VREF_TRM_TRIM_SHIFT (0U)
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT (6U)
+#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK (0x3U)
+#define VREF_SC_MODE_LV_SHIFT (0U)
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK (0x4U)
+#define VREF_SC_VREFST_SHIFT (2U)
+#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT (5U)
+#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK (0x40U)
+#define VREF_SC_REGEN_SHIFT (6U)
+#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK (0x80U)
+#define VREF_SC_VREFEN_SHIFT (7U)
+#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+
/*!
* @}
@@ -12276,32 +8322,11 @@ typedef struct {
#define VREF_BASE (0x40074000u)
/** Peripheral VREF base pointer */
#define VREF ((VREF_Type *)VREF_BASE)
-#define VREF_BASE_PTR (VREF)
/** Array initializer of VREF peripheral base addresses */
#define VREF_BASE_ADDRS { VREF_BASE }
/** Array initializer of VREF peripheral base pointers */
#define VREF_BASE_PTRS { VREF }
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register instance definitions */
-/* VREF */
-#define VREF_TRM VREF_TRM_REG(VREF)
-#define VREF_SC VREF_SC_REG(VREF)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group VREF_Peripheral_Access_Layer */
@@ -12330,36 +8355,7 @@ typedef struct {
__IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
__IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
__IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
-} WDOG_Type, *WDOG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register accessors */
-#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
-#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
-#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
-#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
-#define WDOG_WINH_REG(base) ((base)->WINH)
-#define WDOG_WINL_REG(base) ((base)->WINL)
-#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
-#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
-#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
-#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
-#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
-#define WDOG_PRESC_REG(base) ((base)->PRESC)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
+} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
@@ -12370,110 +8366,99 @@ typedef struct {
* @{
*/
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT 0
-#define WDOG_STCTRLH_WDOGEN_WIDTH 1
-#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
-#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT 1
-#define WDOG_STCTRLH_CLKSRC_WIDTH 1
-#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
-#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
-#define WDOG_STCTRLH_IRQRSTEN_WIDTH 1
-#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
-#define WDOG_STCTRLH_WINEN_MASK 0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT 3
-#define WDOG_STCTRLH_WINEN_WIDTH 1
-#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
-#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH 1
-#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
-#define WDOG_STCTRLH_DBGEN_MASK 0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT 5
-#define WDOG_STCTRLH_DBGEN_WIDTH 1
-#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
-#define WDOG_STCTRLH_STOPEN_MASK 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT 6
-#define WDOG_STCTRLH_STOPEN_WIDTH 1
-#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
-#define WDOG_STCTRLH_WAITEN_MASK 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT 7
-#define WDOG_STCTRLH_WAITEN_WIDTH 1
-#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
-#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
-#define WDOG_STCTRLH_TESTWDOG_WIDTH 1
-#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
-#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT 11
-#define WDOG_STCTRLH_TESTSEL_WIDTH 1
-#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
-#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT 12
-#define WDOG_STCTRLH_BYTESEL_WIDTH 2
-#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
-#define WDOG_STCTRLH_DISTESTWDOG_WIDTH 1
-#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT 15
-#define WDOG_STCTRLL_INTFLG_WIDTH 1
-#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
-#define WDOG_TOVALH_TOVALHIGH_WIDTH 16
-#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT 0
-#define WDOG_TOVALL_TOVALLOW_WIDTH 16
-#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT 0
-#define WDOG_WINH_WINHIGH_WIDTH 16
-#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK 0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT 0
-#define WDOG_WINL_WINLOW_WIDTH 16
-#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
-#define WDOG_REFRESH_WDOGREFRESH_WIDTH 16
-#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
-#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH 16
-#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
-#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH 16
-#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
-#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH 16
-#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT 0
-#define WDOG_RSTCNT_RSTCNT_WIDTH 16
-#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT 8
-#define WDOG_PRESC_PRESCVAL_WIDTH 3
-#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
+#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
+#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
+#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT (3U)
+#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
+#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
+#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
+#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
+#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
+#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
+#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
+#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
+#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+
+/*! @name WINH - Watchdog Window Register High */
+#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT (0U)
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+
+/*! @name WINL - Watchdog Window Register Low */
+#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT (0U)
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+
+/*! @name REFRESH - Watchdog Refresh register */
+#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+
+/*! @name UNLOCK - Watchdog Unlock register */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+
+/*! @name RSTCNT - Watchdog Reset Count register */
+#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+
+/*! @name PRESC - Watchdog Prescaler register */
+#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
/*!
* @}
@@ -12485,7 +8470,6 @@ typedef struct {
#define WDOG_BASE (0x40052000u)
/** Peripheral WDOG base pointer */
#define WDOG ((WDOG_Type *)WDOG_BASE)
-#define WDOG_BASE_PTR (WDOG)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { WDOG_BASE }
/** Array initializer of WDOG peripheral base pointers */
@@ -12493,36 +8477,6 @@ typedef struct {
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS { WDOG_EWM_IRQn }
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register instance definitions */
-/* WDOG */
-#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
-#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
-#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
-#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
-#define WDOG_WINH WDOG_WINH_REG(WDOG)
-#define WDOG_WINL WDOG_WINL_REG(WDOG)
-#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
-#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
-#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
-#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
-#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
-#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
@@ -12550,11 +8504,48 @@ typedef struct {
/* ----------------------------------------------------------------------------
- -- Backward Compatibility
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
@@ -12565,77 +8556,31 @@ typedef struct {
#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
-#define ADC_BASES ADC_BASE_PTRS
-#define CMP_BASES CMP_BASE_PTRS
-#define CRC_BASES CRC_BASE_PTRS
-#define DAC_BASES DAC_BASE_PTRS
-#define DMA_BASES DMA_BASE_PTRS
-#define DMAMUX_BASES DMAMUX_BASE_PTRS
-#define EWM_BASES EWM_BASE_PTRS
-#define FMC_BASES FMC_BASE_PTRS
-#define FTFA_BASES FTFA_BASE_PTRS
-#define FTM_BASES FTM_BASE_PTRS
-#define GPIO_BASES GPIO_BASE_PTRS
-#define I2C_BASES I2C_BASE_PTRS
-#define I2S_BASES I2S_BASE_PTRS
-#define LLWU_BASES LLWU_BASE_PTRS
-#define LPTMR_BASES LPTMR_BASE_PTRS
-#define LPUART_BASES LPUART_BASE_PTRS
-#define MCG_BASES MCG_BASE_PTRS
-#define MCM_BASES MCM_BASE_PTRS
-#define NV_BASES NV_BASE_PTRS
-#define OSC_BASES OSC_BASE_PTRS
-#define PDB_BASES PDB_BASE_PTRS
-#define PIT_BASES PIT_BASE_PTRS
-#define PMC_BASES PMC_BASE_PTRS
-#define PORT_BASES PORT_BASE_PTRS
-#define RCM_BASES RCM_BASE_PTRS
-#define RFSYS_BASES RFSYS_BASE_PTRS
-#define RFVBAT_BASES RFVBAT_BASE_PTRS
-#define RNG_BASES RNG_BASE_PTRS
-#define RTC_BASES RTC_BASE_PTRS
-#define SIM_BASES SIM_BASE_PTRS
-#define SMC_BASES SMC_BASE_PTRS
-#define SPI_BASES SPI_BASE_PTRS
-#define UART_BASES UART_BASE_PTRS
-#define USB_BASES USB_BASE_PTRS
-#define VREF_BASES VREF_BASE_PTRS
-#define WDOG_BASES WDOG_BASE_PTRS
-#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
-#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
-#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
-#define Watchdog_IRQn WDOG_EWM_IRQn
-#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
-#define LPTimer_IRQn LPTMR0_IRQn
-#define LPTimer_IRQHandler LPTMR0_IRQHandler
-#define LLW_IRQn LLWU_IRQn
-#define LLW_IRQHandler LLWU_IRQHandler
-
-#define GPIOA_BASE PTA_BASE
-#define GPIOB_BASE PTB_BASE
-#define GPIOC_BASE PTC_BASE
-#define GPIOD_BASE PTD_BASE
-#define GPIOE_BASE PTE_BASE
-#define GPIOF_BASE PTF_BASE
-#define GPIOG_BASE PTG_BASE
-#define GPIOA PTA
-#define GPIOB PTB
-#define GPIOC PTC
-#define GPIOD PTD
-#define GPIOE PTE
-#define GPIOF PTF
-#define GPIOG PTG
-#define OSC0 OSC
-/*!
- * @}
- */ /* end of group Backward_Compatibility_Symbols */
-
-
-#else /* #if !defined(MK22F25612_H_) */
- /* There is already included the same memory map. Check if it is compatible (has the same major version) */
- #if (MCU_MEM_MAP_VERSION != 0x0100u)
- #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
- #warning There are included two not compatible versions of memory maps. Please check possible differences.
- #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
- #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
-#endif /* #if !defined(MK22F25612_H_) */
+#define DSPI0 SPI0
+#define DSPI1 SPI1
+#define PTA_BASE GPIOA_BASE
+#define PTA GPIOA
+#define PTB_BASE GPIOB_BASE
+#define PTB GPIOB
+#define PTC_BASE GPIOC_BASE
+#define PTC GPIOC
+#define PTD_BASE GPIOD_BASE
+#define PTD GPIOD
+#define PTE_BASE GPIOE_BASE
+#define PTE GPIOE
+#define DMAMUX0 DMAMUX
+#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
+#define Watchdog_IRQn WDOG_EWM_IRQn
+#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
+#define LPTimer_IRQn LPTMR0_IRQn
+#define LPTimer_IRQHandler LPTMR0_IRQHandler
+#define LLW_IRQn LLWU_IRQn
+#define LLW_IRQHandler LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+#endif /* _MK22F25612_H_ */
diff --git a/cpu/k22f/include/vendor/MK22FA12.h b/cpu/k22f/include/vendor/MK22FA12.h
index 15ef9fe636..786b09b4be 100644
--- a/cpu/k22f/include/vendor/MK22FA12.h
+++ b/cpu/k22f/include/vendor/MK22FA12.h
@@ -1,38 +1,38 @@
/*
** ###################################################################
** Processors: MK22FN1M0AVLH12
-** MK22FX512AVLH12
** MK22FN1M0AVLK12
-** MK22FX512AVLK12
** MK22FN1M0AVLL12
-** MK22FX512AVLL12
** MK22FN1M0AVLQ12
-** MK22FX512AVLQ12
** MK22FN1M0AVMC12
-** MK22FX512AVMC12
** MK22FN1M0AVMD12
+** MK22FX512AVLH12
+** MK22FX512AVLK12
+** MK22FX512AVLL12
+** MK22FX512AVLQ12
+** MK22FX512AVMC12
** MK22FX512AVMD12
**
** Compilers: Keil ARM C/C++ Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
-** GNU C Compiler - CodeSourcery Sourcery G++
** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
**
-** Reference manuals: K22P64M120SF5V2RM, Rev.5, March 2015
-** K22P80M120SF5V2RM, Rev.5, March 2015
-** K22P100M120SF5V2RM, Rev.5, March 2015
+** Reference manuals: K22P100M120SF5V2RM, Rev.5, March 2015
+** K22P121M120SF5V2RM, Rev.5, March 2015
** K22P144M120SF5V2RM, Rev.5, March 2015
+** K22P64M120SF5V2RM, Rev.5, March 2015
+** K22P80M120SF5V2RM, Rev.5, March 2015
**
** Version: rev. 1.0, 2015-04-07
-** Build: b150408
+** Build: b170112
**
** Abstract:
** CMSIS Peripheral Access Layer for MK22FA12
**
-** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
-** All rights reserved.
-**
+** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+** Copyright 2016 - 2017 NXP
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
**
@@ -43,7 +43,7 @@
** list of conditions and the following disclaimer in the documentation and/or
** other materials provided with the distribution.
**
-** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** o Neither the name of the copyright holder nor the names of its
** contributors may be used to endorse or promote products derived from this
** software without specific prior written permission.
**
@@ -58,8 +58,8 @@
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
-** http: www.freescale.com
-** mail: support@freescale.com
+** http: www.nxp.com
+** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2015-04-07)
@@ -77,29 +77,14 @@
* CMSIS Peripheral Access Layer for MK22FA12
*/
-
-/* ----------------------------------------------------------------------------
- -- MCU activation
- ---------------------------------------------------------------------------- */
-
-/* Prevention from multiple including the same memory map */
-#if !defined(MK22FA12_H_) /* Check if memory map has not been already included */
-#define MK22FA12_H_
-#define MCU_MK22FA12
-
-/* Check if another memory map has not been also included */
-#if (defined(MCU_ACTIVE))
- #error MK22FA12 memory map: There is already included another memory map. Only one memory map can be included.
-#endif /* (defined(MCU_ACTIVE)) */
-#define MCU_ACTIVE
-
-#include <stdint.h>
+#ifndef _MK22FA12_H_
+#define _MK22FA12_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
+#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
/**
* @brief Macro to calculate address of an aliased word in the peripheral
@@ -118,8 +103,8 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
-#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -128,7 +113,7 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
@@ -137,7 +122,7 @@
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
-#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
@@ -277,6 +262,110 @@ typedef enum IRQn {
*/ /* end of group Cortex_Core_Configuration */
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
+ kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
+ kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
+ kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
+ kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
+ kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
+ kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
+ kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
+ kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
+ kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
+ kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
+ kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */
+ kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
+ kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
+ kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
+ kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
+ kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
+ kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */
+ kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
+ kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
+ kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
+ kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
+ kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
+ kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
+ kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
+ kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
+ kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
+ kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
+ kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
+ kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
+ kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
+ kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
+ kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
+ kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
+ kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
+ kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
+ kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
+ kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
+ kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
+ kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
+ kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
+ kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
+ kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
+ kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
+ kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
+ kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
+ kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */
+ kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
+ kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
+ kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
+ kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
+ kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
+ kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
+ kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
+ kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
+ kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
+ kDmaRequestMux0AlwaysOn54 = 54|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn55 = 55|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn56 = 56|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn57 = 57|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
+ kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -342,51 +431,7 @@ typedef struct {
__IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
__IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
__IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type, *ADC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register accessors */
-#define ADC_SC1_REG(base,index) ((base)->SC1[index])
-#define ADC_SC1_COUNT 2
-#define ADC_CFG1_REG(base) ((base)->CFG1)
-#define ADC_CFG2_REG(base) ((base)->CFG2)
-#define ADC_R_REG(base,index) ((base)->R[index])
-#define ADC_R_COUNT 2
-#define ADC_CV1_REG(base) ((base)->CV1)
-#define ADC_CV2_REG(base) ((base)->CV2)
-#define ADC_SC2_REG(base) ((base)->SC2)
-#define ADC_SC3_REG(base) ((base)->SC3)
-#define ADC_OFS_REG(base) ((base)->OFS)
-#define ADC_PG_REG(base) ((base)->PG)
-#define ADC_MG_REG(base) ((base)->MG)
-#define ADC_CLPD_REG(base) ((base)->CLPD)
-#define ADC_CLPS_REG(base) ((base)->CLPS)
-#define ADC_CLP4_REG(base) ((base)->CLP4)
-#define ADC_CLP3_REG(base) ((base)->CLP3)
-#define ADC_CLP2_REG(base) ((base)->CLP2)
-#define ADC_CLP1_REG(base) ((base)->CLP1)
-#define ADC_CLP0_REG(base) ((base)->CLP0)
-#define ADC_CLMD_REG(base) ((base)->CLMD)
-#define ADC_CLMS_REG(base) ((base)->CLMS)
-#define ADC_CLM4_REG(base) ((base)->CLM4)
-#define ADC_CLM3_REG(base) ((base)->CLM3)
-#define ADC_CLM2_REG(base) ((base)->CLM2)
-#define ADC_CLM1_REG(base) ((base)->CLM1)
-#define ADC_CLM0_REG(base) ((base)->CLM0)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
+} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
@@ -397,211 +442,197 @@ typedef struct {
* @{
*/
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH_WIDTH 5
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_DIFF_WIDTH 1
-#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_AIEN_WIDTH 1
-#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-#define ADC_SC1_COCO_WIDTH 1
-#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK_WIDTH 2
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE_WIDTH 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADLSMP_WIDTH 1
-#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV_WIDTH 2
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-#define ADC_CFG1_ADLPC_WIDTH 1
-#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS_WIDTH 2
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADHSC_WIDTH 1
-#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_ADACKEN_WIDTH 1
-#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-#define ADC_CFG2_MUXSEL_WIDTH 1
-#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D_WIDTH 16
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV_WIDTH 16
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV_WIDTH 16
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL_WIDTH 2
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_DMAEN_WIDTH 1
-#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACREN_WIDTH 1
-#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFGT_WIDTH 1
-#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ACFE_WIDTH 1
-#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADTRG_WIDTH 1
-#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-#define ADC_SC2_ADACT_WIDTH 1
-#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS_WIDTH 2
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_AVGE_WIDTH 1
-#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_ADCO_WIDTH 1
-#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CALF_WIDTH 1
-#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-#define ADC_SC3_CAL_WIDTH 1
-#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS_WIDTH 16
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG_WIDTH 16
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG_WIDTH 16
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD_WIDTH 6
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS_WIDTH 6
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4_WIDTH 10
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3_WIDTH 9
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2_WIDTH 8
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1_WIDTH 7
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0_WIDTH 6
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD_WIDTH 6
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS_WIDTH 6
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4_WIDTH 10
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3_WIDTH 9
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2_WIDTH 8
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1_WIDTH 7
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0_WIDTH 6
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK (0x1FU)
+#define ADC_SC1_ADCH_SHIFT (0U)
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK (0x20U)
+#define ADC_SC1_DIFF_SHIFT (5U)
+#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK (0x40U)
+#define ADC_SC1_AIEN_SHIFT (6U)
+#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK (0x80U)
+#define ADC_SC1_COCO_SHIFT (7U)
+#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT (0U)
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK (0xCU)
+#define ADC_CFG1_MODE_SHIFT (2U)
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT (4U)
+#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK (0x60U)
+#define ADC_CFG1_ADIV_SHIFT (5U)
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT (7U)
+#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT (0U)
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT (2U)
+#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT (3U)
+#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT (4U)
+#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK (0xFFFFU)
+#define ADC_R_D_SHIFT (0U)
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK (0xFFFFU)
+#define ADC_CV1_CV_SHIFT (0U)
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK (0xFFFFU)
+#define ADC_CV2_CV_SHIFT (0U)
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK (0x3U)
+#define ADC_SC2_REFSEL_SHIFT (0U)
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK (0x4U)
+#define ADC_SC2_DMAEN_SHIFT (2U)
+#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK (0x8U)
+#define ADC_SC2_ACREN_SHIFT (3U)
+#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK (0x10U)
+#define ADC_SC2_ACFGT_SHIFT (4U)
+#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK (0x20U)
+#define ADC_SC2_ACFE_SHIFT (5U)
+#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK (0x40U)
+#define ADC_SC2_ADTRG_SHIFT (6U)
+#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK (0x80U)
+#define ADC_SC2_ADACT_SHIFT (7U)
+#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK (0x3U)
+#define ADC_SC3_AVGS_SHIFT (0U)
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK (0x4U)
+#define ADC_SC3_AVGE_SHIFT (2U)
+#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK (0x8U)
+#define ADC_SC3_ADCO_SHIFT (3U)
+#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK (0x40U)
+#define ADC_SC3_CALF_SHIFT (6U)
+#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK (0x80U)
+#define ADC_SC3_CAL_SHIFT (7U)
+#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK (0xFFFFU)
+#define ADC_PG_PG_SHIFT (0U)
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK (0xFFFFU)
+#define ADC_MG_MG_SHIFT (0U)
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT (0U)
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT (0U)
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT (0U)
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT (0U)
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT (0U)
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT (0U)
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT (0U)
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT (0U)
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT (0U)
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT (0U)
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT (0U)
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT (0U)
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT (0U)
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT (0U)
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
/*!
* @}
@@ -613,12 +644,10 @@ typedef struct {
#define ADC0_BASE (0x4003B000u)
/** Peripheral ADC0 base pointer */
#define ADC0 ((ADC_Type *)ADC0_BASE)
-#define ADC0_BASE_PTR (ADC0)
/** Peripheral ADC1 base address */
#define ADC1_BASE (0x400BB000u)
/** Peripheral ADC1 base pointer */
#define ADC1 ((ADC_Type *)ADC1_BASE)
-#define ADC1_BASE_PTR (ADC1)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
/** Array initializer of ADC peripheral base pointers */
@@ -626,85 +655,6 @@ typedef struct {
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
-/* ----------------------------------------------------------------------------
- -- ADC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
- * @{
- */
-
-
-/* ADC - Register instance definitions */
-/* ADC0 */
-#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
-#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
-#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
-#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
-#define ADC0_RA ADC_R_REG(ADC0,0)
-#define ADC0_RB ADC_R_REG(ADC0,1)
-#define ADC0_CV1 ADC_CV1_REG(ADC0)
-#define ADC0_CV2 ADC_CV2_REG(ADC0)
-#define ADC0_SC2 ADC_SC2_REG(ADC0)
-#define ADC0_SC3 ADC_SC3_REG(ADC0)
-#define ADC0_OFS ADC_OFS_REG(ADC0)
-#define ADC0_PG ADC_PG_REG(ADC0)
-#define ADC0_MG ADC_MG_REG(ADC0)
-#define ADC0_CLPD ADC_CLPD_REG(ADC0)
-#define ADC0_CLPS ADC_CLPS_REG(ADC0)
-#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
-#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
-#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
-#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
-#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
-#define ADC0_CLMD ADC_CLMD_REG(ADC0)
-#define ADC0_CLMS ADC_CLMS_REG(ADC0)
-#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
-#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
-#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
-#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
-#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
-/* ADC1 */
-#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
-#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
-#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
-#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
-#define ADC1_RA ADC_R_REG(ADC1,0)
-#define ADC1_RB ADC_R_REG(ADC1,1)
-#define ADC1_CV1 ADC_CV1_REG(ADC1)
-#define ADC1_CV2 ADC_CV2_REG(ADC1)
-#define ADC1_SC2 ADC_SC2_REG(ADC1)
-#define ADC1_SC3 ADC_SC3_REG(ADC1)
-#define ADC1_OFS ADC_OFS_REG(ADC1)
-#define ADC1_PG ADC_PG_REG(ADC1)
-#define ADC1_MG ADC_MG_REG(ADC1)
-#define ADC1_CLPD ADC_CLPD_REG(ADC1)
-#define ADC1_CLPS ADC_CLPS_REG(ADC1)
-#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
-#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
-#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
-#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
-#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
-#define ADC1_CLMD ADC_CLMD_REG(ADC1)
-#define ADC1_CLMS ADC_CLMS_REG(ADC1)
-#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
-#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
-#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
-#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
-#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
-
-/* ADC - Register array accessors */
-#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
-#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
-#define ADC0_R(index) ADC_R_REG(ADC0,index)
-#define ADC1_R(index) ADC_R_REG(ADC1,index)
-
-/*!
- * @}
- */ /* end of group ADC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
@@ -740,41 +690,7 @@ typedef struct {
__IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
__IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
__IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
-} AIPS_Type, *AIPS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- AIPS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
- * @{
- */
-
-
-/* AIPS - Register accessors */
-#define AIPS_MPRA_REG(base) ((base)->MPRA)
-#define AIPS_PACRA_REG(base) ((base)->PACRA)
-#define AIPS_PACRB_REG(base) ((base)->PACRB)
-#define AIPS_PACRC_REG(base) ((base)->PACRC)
-#define AIPS_PACRD_REG(base) ((base)->PACRD)
-#define AIPS_PACRE_REG(base) ((base)->PACRE)
-#define AIPS_PACRF_REG(base) ((base)->PACRF)
-#define AIPS_PACRG_REG(base) ((base)->PACRG)
-#define AIPS_PACRH_REG(base) ((base)->PACRH)
-#define AIPS_PACRI_REG(base) ((base)->PACRI)
-#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
-#define AIPS_PACRK_REG(base) ((base)->PACRK)
-#define AIPS_PACRL_REG(base) ((base)->PACRL)
-#define AIPS_PACRM_REG(base) ((base)->PACRM)
-#define AIPS_PACRN_REG(base) ((base)->PACRN)
-#define AIPS_PACRO_REG(base) ((base)->PACRO)
-#define AIPS_PACRP_REG(base) ((base)->PACRP)
-
-/*!
- * @}
- */ /* end of group AIPS_Register_Accessor_Macros */
-
+} AIPS_Type;
/* ----------------------------------------------------------------------------
-- AIPS Register Masks
@@ -785,1558 +701,1190 @@ typedef struct {
* @{
*/
-/* PACRA Bit Fields */
-#define AIPS_PACRA_TP7_MASK 0x1u
-#define AIPS_PACRA_TP7_SHIFT 0
-#define AIPS_PACRA_TP7_WIDTH 1
-#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP7_SHIFT))&AIPS_PACRA_TP7_MASK)
-#define AIPS_PACRA_WP7_MASK 0x2u
-#define AIPS_PACRA_WP7_SHIFT 1
-#define AIPS_PACRA_WP7_WIDTH 1
-#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP7_SHIFT))&AIPS_PACRA_WP7_MASK)
-#define AIPS_PACRA_SP7_MASK 0x4u
-#define AIPS_PACRA_SP7_SHIFT 2
-#define AIPS_PACRA_SP7_WIDTH 1
-#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP7_SHIFT))&AIPS_PACRA_SP7_MASK)
-#define AIPS_PACRA_TP6_MASK 0x10u
-#define AIPS_PACRA_TP6_SHIFT 4
-#define AIPS_PACRA_TP6_WIDTH 1
-#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP6_SHIFT))&AIPS_PACRA_TP6_MASK)
-#define AIPS_PACRA_WP6_MASK 0x20u
-#define AIPS_PACRA_WP6_SHIFT 5
-#define AIPS_PACRA_WP6_WIDTH 1
-#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP6_SHIFT))&AIPS_PACRA_WP6_MASK)
-#define AIPS_PACRA_SP6_MASK 0x40u
-#define AIPS_PACRA_SP6_SHIFT 6
-#define AIPS_PACRA_SP6_WIDTH 1
-#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP6_SHIFT))&AIPS_PACRA_SP6_MASK)
-#define AIPS_PACRA_TP5_MASK 0x100u
-#define AIPS_PACRA_TP5_SHIFT 8
-#define AIPS_PACRA_TP5_WIDTH 1
-#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP5_SHIFT))&AIPS_PACRA_TP5_MASK)
-#define AIPS_PACRA_WP5_MASK 0x200u
-#define AIPS_PACRA_WP5_SHIFT 9
-#define AIPS_PACRA_WP5_WIDTH 1
-#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP5_SHIFT))&AIPS_PACRA_WP5_MASK)
-#define AIPS_PACRA_SP5_MASK 0x400u
-#define AIPS_PACRA_SP5_SHIFT 10
-#define AIPS_PACRA_SP5_WIDTH 1
-#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP5_SHIFT))&AIPS_PACRA_SP5_MASK)
-#define AIPS_PACRA_TP4_MASK 0x1000u
-#define AIPS_PACRA_TP4_SHIFT 12
-#define AIPS_PACRA_TP4_WIDTH 1
-#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP4_SHIFT))&AIPS_PACRA_TP4_MASK)
-#define AIPS_PACRA_WP4_MASK 0x2000u
-#define AIPS_PACRA_WP4_SHIFT 13
-#define AIPS_PACRA_WP4_WIDTH 1
-#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP4_SHIFT))&AIPS_PACRA_WP4_MASK)
-#define AIPS_PACRA_SP4_MASK 0x4000u
-#define AIPS_PACRA_SP4_SHIFT 14
-#define AIPS_PACRA_SP4_WIDTH 1
-#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP4_SHIFT))&AIPS_PACRA_SP4_MASK)
-#define AIPS_PACRA_TP3_MASK 0x10000u
-#define AIPS_PACRA_TP3_SHIFT 16
-#define AIPS_PACRA_TP3_WIDTH 1
-#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP3_SHIFT))&AIPS_PACRA_TP3_MASK)
-#define AIPS_PACRA_WP3_MASK 0x20000u
-#define AIPS_PACRA_WP3_SHIFT 17
-#define AIPS_PACRA_WP3_WIDTH 1
-#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP3_SHIFT))&AIPS_PACRA_WP3_MASK)
-#define AIPS_PACRA_SP3_MASK 0x40000u
-#define AIPS_PACRA_SP3_SHIFT 18
-#define AIPS_PACRA_SP3_WIDTH 1
-#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP3_SHIFT))&AIPS_PACRA_SP3_MASK)
-#define AIPS_PACRA_TP2_MASK 0x100000u
-#define AIPS_PACRA_TP2_SHIFT 20
-#define AIPS_PACRA_TP2_WIDTH 1
-#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP2_SHIFT))&AIPS_PACRA_TP2_MASK)
-#define AIPS_PACRA_WP2_MASK 0x200000u
-#define AIPS_PACRA_WP2_SHIFT 21
-#define AIPS_PACRA_WP2_WIDTH 1
-#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP2_SHIFT))&AIPS_PACRA_WP2_MASK)
-#define AIPS_PACRA_SP2_MASK 0x400000u
-#define AIPS_PACRA_SP2_SHIFT 22
-#define AIPS_PACRA_SP2_WIDTH 1
-#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP2_SHIFT))&AIPS_PACRA_SP2_MASK)
-#define AIPS_PACRA_TP1_MASK 0x1000000u
-#define AIPS_PACRA_TP1_SHIFT 24
-#define AIPS_PACRA_TP1_WIDTH 1
-#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP1_SHIFT))&AIPS_PACRA_TP1_MASK)
-#define AIPS_PACRA_WP1_MASK 0x2000000u
-#define AIPS_PACRA_WP1_SHIFT 25
-#define AIPS_PACRA_WP1_WIDTH 1
-#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP1_SHIFT))&AIPS_PACRA_WP1_MASK)
-#define AIPS_PACRA_SP1_MASK 0x4000000u
-#define AIPS_PACRA_SP1_SHIFT 26
-#define AIPS_PACRA_SP1_WIDTH 1
-#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP1_SHIFT))&AIPS_PACRA_SP1_MASK)
-#define AIPS_PACRA_TP0_MASK 0x10000000u
-#define AIPS_PACRA_TP0_SHIFT 28
-#define AIPS_PACRA_TP0_WIDTH 1
-#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_TP0_SHIFT))&AIPS_PACRA_TP0_MASK)
-#define AIPS_PACRA_WP0_MASK 0x20000000u
-#define AIPS_PACRA_WP0_SHIFT 29
-#define AIPS_PACRA_WP0_WIDTH 1
-#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_WP0_SHIFT))&AIPS_PACRA_WP0_MASK)
-#define AIPS_PACRA_SP0_MASK 0x40000000u
-#define AIPS_PACRA_SP0_SHIFT 30
-#define AIPS_PACRA_SP0_WIDTH 1
-#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRA_SP0_SHIFT))&AIPS_PACRA_SP0_MASK)
-/* PACRB Bit Fields */
-#define AIPS_PACRB_TP7_MASK 0x1u
-#define AIPS_PACRB_TP7_SHIFT 0
-#define AIPS_PACRB_TP7_WIDTH 1
-#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP7_SHIFT))&AIPS_PACRB_TP7_MASK)
-#define AIPS_PACRB_WP7_MASK 0x2u
-#define AIPS_PACRB_WP7_SHIFT 1
-#define AIPS_PACRB_WP7_WIDTH 1
-#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP7_SHIFT))&AIPS_PACRB_WP7_MASK)
-#define AIPS_PACRB_SP7_MASK 0x4u
-#define AIPS_PACRB_SP7_SHIFT 2
-#define AIPS_PACRB_SP7_WIDTH 1
-#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP7_SHIFT))&AIPS_PACRB_SP7_MASK)
-#define AIPS_PACRB_TP6_MASK 0x10u
-#define AIPS_PACRB_TP6_SHIFT 4
-#define AIPS_PACRB_TP6_WIDTH 1
-#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP6_SHIFT))&AIPS_PACRB_TP6_MASK)
-#define AIPS_PACRB_WP6_MASK 0x20u
-#define AIPS_PACRB_WP6_SHIFT 5
-#define AIPS_PACRB_WP6_WIDTH 1
-#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP6_SHIFT))&AIPS_PACRB_WP6_MASK)
-#define AIPS_PACRB_SP6_MASK 0x40u
-#define AIPS_PACRB_SP6_SHIFT 6
-#define AIPS_PACRB_SP6_WIDTH 1
-#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP6_SHIFT))&AIPS_PACRB_SP6_MASK)
-#define AIPS_PACRB_TP5_MASK 0x100u
-#define AIPS_PACRB_TP5_SHIFT 8
-#define AIPS_PACRB_TP5_WIDTH 1
-#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP5_SHIFT))&AIPS_PACRB_TP5_MASK)
-#define AIPS_PACRB_WP5_MASK 0x200u
-#define AIPS_PACRB_WP5_SHIFT 9
-#define AIPS_PACRB_WP5_WIDTH 1
-#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP5_SHIFT))&AIPS_PACRB_WP5_MASK)
-#define AIPS_PACRB_SP5_MASK 0x400u
-#define AIPS_PACRB_SP5_SHIFT 10
-#define AIPS_PACRB_SP5_WIDTH 1
-#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP5_SHIFT))&AIPS_PACRB_SP5_MASK)
-#define AIPS_PACRB_TP4_MASK 0x1000u
-#define AIPS_PACRB_TP4_SHIFT 12
-#define AIPS_PACRB_TP4_WIDTH 1
-#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP4_SHIFT))&AIPS_PACRB_TP4_MASK)
-#define AIPS_PACRB_WP4_MASK 0x2000u
-#define AIPS_PACRB_WP4_SHIFT 13
-#define AIPS_PACRB_WP4_WIDTH 1
-#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP4_SHIFT))&AIPS_PACRB_WP4_MASK)
-#define AIPS_PACRB_SP4_MASK 0x4000u
-#define AIPS_PACRB_SP4_SHIFT 14
-#define AIPS_PACRB_SP4_WIDTH 1
-#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP4_SHIFT))&AIPS_PACRB_SP4_MASK)
-#define AIPS_PACRB_TP3_MASK 0x10000u
-#define AIPS_PACRB_TP3_SHIFT 16
-#define AIPS_PACRB_TP3_WIDTH 1
-#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP3_SHIFT))&AIPS_PACRB_TP3_MASK)
-#define AIPS_PACRB_WP3_MASK 0x20000u
-#define AIPS_PACRB_WP3_SHIFT 17
-#define AIPS_PACRB_WP3_WIDTH 1
-#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP3_SHIFT))&AIPS_PACRB_WP3_MASK)
-#define AIPS_PACRB_SP3_MASK 0x40000u
-#define AIPS_PACRB_SP3_SHIFT 18
-#define AIPS_PACRB_SP3_WIDTH 1
-#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP3_SHIFT))&AIPS_PACRB_SP3_MASK)
-#define AIPS_PACRB_TP2_MASK 0x100000u
-#define AIPS_PACRB_TP2_SHIFT 20
-#define AIPS_PACRB_TP2_WIDTH 1
-#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP2_SHIFT))&AIPS_PACRB_TP2_MASK)
-#define AIPS_PACRB_WP2_MASK 0x200000u
-#define AIPS_PACRB_WP2_SHIFT 21
-#define AIPS_PACRB_WP2_WIDTH 1
-#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP2_SHIFT))&AIPS_PACRB_WP2_MASK)
-#define AIPS_PACRB_SP2_MASK 0x400000u
-#define AIPS_PACRB_SP2_SHIFT 22
-#define AIPS_PACRB_SP2_WIDTH 1
-#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP2_SHIFT))&AIPS_PACRB_SP2_MASK)
-#define AIPS_PACRB_TP1_MASK 0x1000000u
-#define AIPS_PACRB_TP1_SHIFT 24
-#define AIPS_PACRB_TP1_WIDTH 1
-#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP1_SHIFT))&AIPS_PACRB_TP1_MASK)
-#define AIPS_PACRB_WP1_MASK 0x2000000u
-#define AIPS_PACRB_WP1_SHIFT 25
-#define AIPS_PACRB_WP1_WIDTH 1
-#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP1_SHIFT))&AIPS_PACRB_WP1_MASK)
-#define AIPS_PACRB_SP1_MASK 0x4000000u
-#define AIPS_PACRB_SP1_SHIFT 26
-#define AIPS_PACRB_SP1_WIDTH 1
-#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP1_SHIFT))&AIPS_PACRB_SP1_MASK)
-#define AIPS_PACRB_TP0_MASK 0x10000000u
-#define AIPS_PACRB_TP0_SHIFT 28
-#define AIPS_PACRB_TP0_WIDTH 1
-#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_TP0_SHIFT))&AIPS_PACRB_TP0_MASK)
-#define AIPS_PACRB_WP0_MASK 0x20000000u
-#define AIPS_PACRB_WP0_SHIFT 29
-#define AIPS_PACRB_WP0_WIDTH 1
-#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_WP0_SHIFT))&AIPS_PACRB_WP0_MASK)
-#define AIPS_PACRB_SP0_MASK 0x40000000u
-#define AIPS_PACRB_SP0_SHIFT 30
-#define AIPS_PACRB_SP0_WIDTH 1
-#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRB_SP0_SHIFT))&AIPS_PACRB_SP0_MASK)
-/* PACRC Bit Fields */
-#define AIPS_PACRC_TP7_MASK 0x1u
-#define AIPS_PACRC_TP7_SHIFT 0
-#define AIPS_PACRC_TP7_WIDTH 1
-#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP7_SHIFT))&AIPS_PACRC_TP7_MASK)
-#define AIPS_PACRC_WP7_MASK 0x2u
-#define AIPS_PACRC_WP7_SHIFT 1
-#define AIPS_PACRC_WP7_WIDTH 1
-#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP7_SHIFT))&AIPS_PACRC_WP7_MASK)
-#define AIPS_PACRC_SP7_MASK 0x4u
-#define AIPS_PACRC_SP7_SHIFT 2
-#define AIPS_PACRC_SP7_WIDTH 1
-#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP7_SHIFT))&AIPS_PACRC_SP7_MASK)
-#define AIPS_PACRC_TP6_MASK 0x10u
-#define AIPS_PACRC_TP6_SHIFT 4
-#define AIPS_PACRC_TP6_WIDTH 1
-#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP6_SHIFT))&AIPS_PACRC_TP6_MASK)
-#define AIPS_PACRC_WP6_MASK 0x20u
-#define AIPS_PACRC_WP6_SHIFT 5
-#define AIPS_PACRC_WP6_WIDTH 1
-#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP6_SHIFT))&AIPS_PACRC_WP6_MASK)
-#define AIPS_PACRC_SP6_MASK 0x40u
-#define AIPS_PACRC_SP6_SHIFT 6
-#define AIPS_PACRC_SP6_WIDTH 1
-#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP6_SHIFT))&AIPS_PACRC_SP6_MASK)
-#define AIPS_PACRC_TP5_MASK 0x100u
-#define AIPS_PACRC_TP5_SHIFT 8
-#define AIPS_PACRC_TP5_WIDTH 1
-#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP5_SHIFT))&AIPS_PACRC_TP5_MASK)
-#define AIPS_PACRC_WP5_MASK 0x200u
-#define AIPS_PACRC_WP5_SHIFT 9
-#define AIPS_PACRC_WP5_WIDTH 1
-#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP5_SHIFT))&AIPS_PACRC_WP5_MASK)
-#define AIPS_PACRC_SP5_MASK 0x400u
-#define AIPS_PACRC_SP5_SHIFT 10
-#define AIPS_PACRC_SP5_WIDTH 1
-#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP5_SHIFT))&AIPS_PACRC_SP5_MASK)
-#define AIPS_PACRC_TP4_MASK 0x1000u
-#define AIPS_PACRC_TP4_SHIFT 12
-#define AIPS_PACRC_TP4_WIDTH 1
-#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP4_SHIFT))&AIPS_PACRC_TP4_MASK)
-#define AIPS_PACRC_WP4_MASK 0x2000u
-#define AIPS_PACRC_WP4_SHIFT 13
-#define AIPS_PACRC_WP4_WIDTH 1
-#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP4_SHIFT))&AIPS_PACRC_WP4_MASK)
-#define AIPS_PACRC_SP4_MASK 0x4000u
-#define AIPS_PACRC_SP4_SHIFT 14
-#define AIPS_PACRC_SP4_WIDTH 1
-#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP4_SHIFT))&AIPS_PACRC_SP4_MASK)
-#define AIPS_PACRC_TP3_MASK 0x10000u
-#define AIPS_PACRC_TP3_SHIFT 16
-#define AIPS_PACRC_TP3_WIDTH 1
-#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP3_SHIFT))&AIPS_PACRC_TP3_MASK)
-#define AIPS_PACRC_WP3_MASK 0x20000u
-#define AIPS_PACRC_WP3_SHIFT 17
-#define AIPS_PACRC_WP3_WIDTH 1
-#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP3_SHIFT))&AIPS_PACRC_WP3_MASK)
-#define AIPS_PACRC_SP3_MASK 0x40000u
-#define AIPS_PACRC_SP3_SHIFT 18
-#define AIPS_PACRC_SP3_WIDTH 1
-#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP3_SHIFT))&AIPS_PACRC_SP3_MASK)
-#define AIPS_PACRC_TP2_MASK 0x100000u
-#define AIPS_PACRC_TP2_SHIFT 20
-#define AIPS_PACRC_TP2_WIDTH 1
-#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP2_SHIFT))&AIPS_PACRC_TP2_MASK)
-#define AIPS_PACRC_WP2_MASK 0x200000u
-#define AIPS_PACRC_WP2_SHIFT 21
-#define AIPS_PACRC_WP2_WIDTH 1
-#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP2_SHIFT))&AIPS_PACRC_WP2_MASK)
-#define AIPS_PACRC_SP2_MASK 0x400000u
-#define AIPS_PACRC_SP2_SHIFT 22
-#define AIPS_PACRC_SP2_WIDTH 1
-#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP2_SHIFT))&AIPS_PACRC_SP2_MASK)
-#define AIPS_PACRC_TP1_MASK 0x1000000u
-#define AIPS_PACRC_TP1_SHIFT 24
-#define AIPS_PACRC_TP1_WIDTH 1
-#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP1_SHIFT))&AIPS_PACRC_TP1_MASK)
-#define AIPS_PACRC_WP1_MASK 0x2000000u
-#define AIPS_PACRC_WP1_SHIFT 25
-#define AIPS_PACRC_WP1_WIDTH 1
-#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP1_SHIFT))&AIPS_PACRC_WP1_MASK)
-#define AIPS_PACRC_SP1_MASK 0x4000000u
-#define AIPS_PACRC_SP1_SHIFT 26
-#define AIPS_PACRC_SP1_WIDTH 1
-#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP1_SHIFT))&AIPS_PACRC_SP1_MASK)
-#define AIPS_PACRC_TP0_MASK 0x10000000u
-#define AIPS_PACRC_TP0_SHIFT 28
-#define AIPS_PACRC_TP0_WIDTH 1
-#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_TP0_SHIFT))&AIPS_PACRC_TP0_MASK)
-#define AIPS_PACRC_WP0_MASK 0x20000000u
-#define AIPS_PACRC_WP0_SHIFT 29
-#define AIPS_PACRC_WP0_WIDTH 1
-#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_WP0_SHIFT))&AIPS_PACRC_WP0_MASK)
-#define AIPS_PACRC_SP0_MASK 0x40000000u
-#define AIPS_PACRC_SP0_SHIFT 30
-#define AIPS_PACRC_SP0_WIDTH 1
-#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRC_SP0_SHIFT))&AIPS_PACRC_SP0_MASK)
-/* PACRD Bit Fields */
-#define AIPS_PACRD_TP7_MASK 0x1u
-#define AIPS_PACRD_TP7_SHIFT 0
-#define AIPS_PACRD_TP7_WIDTH 1
-#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP7_SHIFT))&AIPS_PACRD_TP7_MASK)
-#define AIPS_PACRD_WP7_MASK 0x2u
-#define AIPS_PACRD_WP7_SHIFT 1
-#define AIPS_PACRD_WP7_WIDTH 1
-#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP7_SHIFT))&AIPS_PACRD_WP7_MASK)
-#define AIPS_PACRD_SP7_MASK 0x4u
-#define AIPS_PACRD_SP7_SHIFT 2
-#define AIPS_PACRD_SP7_WIDTH 1
-#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP7_SHIFT))&AIPS_PACRD_SP7_MASK)
-#define AIPS_PACRD_TP6_MASK 0x10u
-#define AIPS_PACRD_TP6_SHIFT 4
-#define AIPS_PACRD_TP6_WIDTH 1
-#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP6_SHIFT))&AIPS_PACRD_TP6_MASK)
-#define AIPS_PACRD_WP6_MASK 0x20u
-#define AIPS_PACRD_WP6_SHIFT 5
-#define AIPS_PACRD_WP6_WIDTH 1
-#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP6_SHIFT))&AIPS_PACRD_WP6_MASK)
-#define AIPS_PACRD_SP6_MASK 0x40u
-#define AIPS_PACRD_SP6_SHIFT 6
-#define AIPS_PACRD_SP6_WIDTH 1
-#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP6_SHIFT))&AIPS_PACRD_SP6_MASK)
-#define AIPS_PACRD_TP5_MASK 0x100u
-#define AIPS_PACRD_TP5_SHIFT 8
-#define AIPS_PACRD_TP5_WIDTH 1
-#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP5_SHIFT))&AIPS_PACRD_TP5_MASK)
-#define AIPS_PACRD_WP5_MASK 0x200u
-#define AIPS_PACRD_WP5_SHIFT 9
-#define AIPS_PACRD_WP5_WIDTH 1
-#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP5_SHIFT))&AIPS_PACRD_WP5_MASK)
-#define AIPS_PACRD_SP5_MASK 0x400u
-#define AIPS_PACRD_SP5_SHIFT 10
-#define AIPS_PACRD_SP5_WIDTH 1
-#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP5_SHIFT))&AIPS_PACRD_SP5_MASK)
-#define AIPS_PACRD_TP4_MASK 0x1000u
-#define AIPS_PACRD_TP4_SHIFT 12
-#define AIPS_PACRD_TP4_WIDTH 1
-#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP4_SHIFT))&AIPS_PACRD_TP4_MASK)
-#define AIPS_PACRD_WP4_MASK 0x2000u
-#define AIPS_PACRD_WP4_SHIFT 13
-#define AIPS_PACRD_WP4_WIDTH 1
-#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP4_SHIFT))&AIPS_PACRD_WP4_MASK)
-#define AIPS_PACRD_SP4_MASK 0x4000u
-#define AIPS_PACRD_SP4_SHIFT 14
-#define AIPS_PACRD_SP4_WIDTH 1
-#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP4_SHIFT))&AIPS_PACRD_SP4_MASK)
-#define AIPS_PACRD_TP3_MASK 0x10000u
-#define AIPS_PACRD_TP3_SHIFT 16
-#define AIPS_PACRD_TP3_WIDTH 1
-#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP3_SHIFT))&AIPS_PACRD_TP3_MASK)
-#define AIPS_PACRD_WP3_MASK 0x20000u
-#define AIPS_PACRD_WP3_SHIFT 17
-#define AIPS_PACRD_WP3_WIDTH 1
-#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP3_SHIFT))&AIPS_PACRD_WP3_MASK)
-#define AIPS_PACRD_SP3_MASK 0x40000u
-#define AIPS_PACRD_SP3_SHIFT 18
-#define AIPS_PACRD_SP3_WIDTH 1
-#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP3_SHIFT))&AIPS_PACRD_SP3_MASK)
-#define AIPS_PACRD_TP2_MASK 0x100000u
-#define AIPS_PACRD_TP2_SHIFT 20
-#define AIPS_PACRD_TP2_WIDTH 1
-#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP2_SHIFT))&AIPS_PACRD_TP2_MASK)
-#define AIPS_PACRD_WP2_MASK 0x200000u
-#define AIPS_PACRD_WP2_SHIFT 21
-#define AIPS_PACRD_WP2_WIDTH 1
-#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP2_SHIFT))&AIPS_PACRD_WP2_MASK)
-#define AIPS_PACRD_SP2_MASK 0x400000u
-#define AIPS_PACRD_SP2_SHIFT 22
-#define AIPS_PACRD_SP2_WIDTH 1
-#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP2_SHIFT))&AIPS_PACRD_SP2_MASK)
-#define AIPS_PACRD_TP1_MASK 0x1000000u
-#define AIPS_PACRD_TP1_SHIFT 24
-#define AIPS_PACRD_TP1_WIDTH 1
-#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP1_SHIFT))&AIPS_PACRD_TP1_MASK)
-#define AIPS_PACRD_WP1_MASK 0x2000000u
-#define AIPS_PACRD_WP1_SHIFT 25
-#define AIPS_PACRD_WP1_WIDTH 1
-#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP1_SHIFT))&AIPS_PACRD_WP1_MASK)
-#define AIPS_PACRD_SP1_MASK 0x4000000u
-#define AIPS_PACRD_SP1_SHIFT 26
-#define AIPS_PACRD_SP1_WIDTH 1
-#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP1_SHIFT))&AIPS_PACRD_SP1_MASK)
-#define AIPS_PACRD_TP0_MASK 0x10000000u
-#define AIPS_PACRD_TP0_SHIFT 28
-#define AIPS_PACRD_TP0_WIDTH 1
-#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_TP0_SHIFT))&AIPS_PACRD_TP0_MASK)
-#define AIPS_PACRD_WP0_MASK 0x20000000u
-#define AIPS_PACRD_WP0_SHIFT 29
-#define AIPS_PACRD_WP0_WIDTH 1
-#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_WP0_SHIFT))&AIPS_PACRD_WP0_MASK)
-#define AIPS_PACRD_SP0_MASK 0x40000000u
-#define AIPS_PACRD_SP0_SHIFT 30
-#define AIPS_PACRD_SP0_WIDTH 1
-#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRD_SP0_SHIFT))&AIPS_PACRD_SP0_MASK)
-/* PACRE Bit Fields */
-#define AIPS_PACRE_TP7_MASK 0x1u
-#define AIPS_PACRE_TP7_SHIFT 0
-#define AIPS_PACRE_TP7_WIDTH 1
-#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP7_SHIFT))&AIPS_PACRE_TP7_MASK)
-#define AIPS_PACRE_WP7_MASK 0x2u
-#define AIPS_PACRE_WP7_SHIFT 1
-#define AIPS_PACRE_WP7_WIDTH 1
-#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP7_SHIFT))&AIPS_PACRE_WP7_MASK)
-#define AIPS_PACRE_SP7_MASK 0x4u
-#define AIPS_PACRE_SP7_SHIFT 2
-#define AIPS_PACRE_SP7_WIDTH 1
-#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP7_SHIFT))&AIPS_PACRE_SP7_MASK)
-#define AIPS_PACRE_TP6_MASK 0x10u
-#define AIPS_PACRE_TP6_SHIFT 4
-#define AIPS_PACRE_TP6_WIDTH 1
-#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP6_SHIFT))&AIPS_PACRE_TP6_MASK)
-#define AIPS_PACRE_WP6_MASK 0x20u
-#define AIPS_PACRE_WP6_SHIFT 5
-#define AIPS_PACRE_WP6_WIDTH 1
-#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP6_SHIFT))&AIPS_PACRE_WP6_MASK)
-#define AIPS_PACRE_SP6_MASK 0x40u
-#define AIPS_PACRE_SP6_SHIFT 6
-#define AIPS_PACRE_SP6_WIDTH 1
-#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP6_SHIFT))&AIPS_PACRE_SP6_MASK)
-#define AIPS_PACRE_TP5_MASK 0x100u
-#define AIPS_PACRE_TP5_SHIFT 8
-#define AIPS_PACRE_TP5_WIDTH 1
-#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP5_SHIFT))&AIPS_PACRE_TP5_MASK)
-#define AIPS_PACRE_WP5_MASK 0x200u
-#define AIPS_PACRE_WP5_SHIFT 9
-#define AIPS_PACRE_WP5_WIDTH 1
-#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP5_SHIFT))&AIPS_PACRE_WP5_MASK)
-#define AIPS_PACRE_SP5_MASK 0x400u
-#define AIPS_PACRE_SP5_SHIFT 10
-#define AIPS_PACRE_SP5_WIDTH 1
-#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP5_SHIFT))&AIPS_PACRE_SP5_MASK)
-#define AIPS_PACRE_TP4_MASK 0x1000u
-#define AIPS_PACRE_TP4_SHIFT 12
-#define AIPS_PACRE_TP4_WIDTH 1
-#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP4_SHIFT))&AIPS_PACRE_TP4_MASK)
-#define AIPS_PACRE_WP4_MASK 0x2000u
-#define AIPS_PACRE_WP4_SHIFT 13
-#define AIPS_PACRE_WP4_WIDTH 1
-#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP4_SHIFT))&AIPS_PACRE_WP4_MASK)
-#define AIPS_PACRE_SP4_MASK 0x4000u
-#define AIPS_PACRE_SP4_SHIFT 14
-#define AIPS_PACRE_SP4_WIDTH 1
-#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP4_SHIFT))&AIPS_PACRE_SP4_MASK)
-#define AIPS_PACRE_TP3_MASK 0x10000u
-#define AIPS_PACRE_TP3_SHIFT 16
-#define AIPS_PACRE_TP3_WIDTH 1
-#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP3_SHIFT))&AIPS_PACRE_TP3_MASK)
-#define AIPS_PACRE_WP3_MASK 0x20000u
-#define AIPS_PACRE_WP3_SHIFT 17
-#define AIPS_PACRE_WP3_WIDTH 1
-#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP3_SHIFT))&AIPS_PACRE_WP3_MASK)
-#define AIPS_PACRE_SP3_MASK 0x40000u
-#define AIPS_PACRE_SP3_SHIFT 18
-#define AIPS_PACRE_SP3_WIDTH 1
-#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP3_SHIFT))&AIPS_PACRE_SP3_MASK)
-#define AIPS_PACRE_TP2_MASK 0x100000u
-#define AIPS_PACRE_TP2_SHIFT 20
-#define AIPS_PACRE_TP2_WIDTH 1
-#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP2_SHIFT))&AIPS_PACRE_TP2_MASK)
-#define AIPS_PACRE_WP2_MASK 0x200000u
-#define AIPS_PACRE_WP2_SHIFT 21
-#define AIPS_PACRE_WP2_WIDTH 1
-#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP2_SHIFT))&AIPS_PACRE_WP2_MASK)
-#define AIPS_PACRE_SP2_MASK 0x400000u
-#define AIPS_PACRE_SP2_SHIFT 22
-#define AIPS_PACRE_SP2_WIDTH 1
-#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP2_SHIFT))&AIPS_PACRE_SP2_MASK)
-#define AIPS_PACRE_TP1_MASK 0x1000000u
-#define AIPS_PACRE_TP1_SHIFT 24
-#define AIPS_PACRE_TP1_WIDTH 1
-#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP1_SHIFT))&AIPS_PACRE_TP1_MASK)
-#define AIPS_PACRE_WP1_MASK 0x2000000u
-#define AIPS_PACRE_WP1_SHIFT 25
-#define AIPS_PACRE_WP1_WIDTH 1
-#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP1_SHIFT))&AIPS_PACRE_WP1_MASK)
-#define AIPS_PACRE_SP1_MASK 0x4000000u
-#define AIPS_PACRE_SP1_SHIFT 26
-#define AIPS_PACRE_SP1_WIDTH 1
-#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP1_SHIFT))&AIPS_PACRE_SP1_MASK)
-#define AIPS_PACRE_TP0_MASK 0x10000000u
-#define AIPS_PACRE_TP0_SHIFT 28
-#define AIPS_PACRE_TP0_WIDTH 1
-#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_TP0_SHIFT))&AIPS_PACRE_TP0_MASK)
-#define AIPS_PACRE_WP0_MASK 0x20000000u
-#define AIPS_PACRE_WP0_SHIFT 29
-#define AIPS_PACRE_WP0_WIDTH 1
-#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_WP0_SHIFT))&AIPS_PACRE_WP0_MASK)
-#define AIPS_PACRE_SP0_MASK 0x40000000u
-#define AIPS_PACRE_SP0_SHIFT 30
-#define AIPS_PACRE_SP0_WIDTH 1
-#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRE_SP0_SHIFT))&AIPS_PACRE_SP0_MASK)
-/* PACRF Bit Fields */
-#define AIPS_PACRF_TP7_MASK 0x1u
-#define AIPS_PACRF_TP7_SHIFT 0
-#define AIPS_PACRF_TP7_WIDTH 1
-#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP7_SHIFT))&AIPS_PACRF_TP7_MASK)
-#define AIPS_PACRF_WP7_MASK 0x2u
-#define AIPS_PACRF_WP7_SHIFT 1
-#define AIPS_PACRF_WP7_WIDTH 1
-#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP7_SHIFT))&AIPS_PACRF_WP7_MASK)
-#define AIPS_PACRF_SP7_MASK 0x4u
-#define AIPS_PACRF_SP7_SHIFT 2
-#define AIPS_PACRF_SP7_WIDTH 1
-#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP7_SHIFT))&AIPS_PACRF_SP7_MASK)
-#define AIPS_PACRF_TP6_MASK 0x10u
-#define AIPS_PACRF_TP6_SHIFT 4
-#define AIPS_PACRF_TP6_WIDTH 1
-#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP6_SHIFT))&AIPS_PACRF_TP6_MASK)
-#define AIPS_PACRF_WP6_MASK 0x20u
-#define AIPS_PACRF_WP6_SHIFT 5
-#define AIPS_PACRF_WP6_WIDTH 1
-#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP6_SHIFT))&AIPS_PACRF_WP6_MASK)
-#define AIPS_PACRF_SP6_MASK 0x40u
-#define AIPS_PACRF_SP6_SHIFT 6
-#define AIPS_PACRF_SP6_WIDTH 1
-#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP6_SHIFT))&AIPS_PACRF_SP6_MASK)
-#define AIPS_PACRF_TP5_MASK 0x100u
-#define AIPS_PACRF_TP5_SHIFT 8
-#define AIPS_PACRF_TP5_WIDTH 1
-#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP5_SHIFT))&AIPS_PACRF_TP5_MASK)
-#define AIPS_PACRF_WP5_MASK 0x200u
-#define AIPS_PACRF_WP5_SHIFT 9
-#define AIPS_PACRF_WP5_WIDTH 1
-#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP5_SHIFT))&AIPS_PACRF_WP5_MASK)
-#define AIPS_PACRF_SP5_MASK 0x400u
-#define AIPS_PACRF_SP5_SHIFT 10
-#define AIPS_PACRF_SP5_WIDTH 1
-#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP5_SHIFT))&AIPS_PACRF_SP5_MASK)
-#define AIPS_PACRF_TP4_MASK 0x1000u
-#define AIPS_PACRF_TP4_SHIFT 12
-#define AIPS_PACRF_TP4_WIDTH 1
-#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP4_SHIFT))&AIPS_PACRF_TP4_MASK)
-#define AIPS_PACRF_WP4_MASK 0x2000u
-#define AIPS_PACRF_WP4_SHIFT 13
-#define AIPS_PACRF_WP4_WIDTH 1
-#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP4_SHIFT))&AIPS_PACRF_WP4_MASK)
-#define AIPS_PACRF_SP4_MASK 0x4000u
-#define AIPS_PACRF_SP4_SHIFT 14
-#define AIPS_PACRF_SP4_WIDTH 1
-#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP4_SHIFT))&AIPS_PACRF_SP4_MASK)
-#define AIPS_PACRF_TP3_MASK 0x10000u
-#define AIPS_PACRF_TP3_SHIFT 16
-#define AIPS_PACRF_TP3_WIDTH 1
-#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP3_SHIFT))&AIPS_PACRF_TP3_MASK)
-#define AIPS_PACRF_WP3_MASK 0x20000u
-#define AIPS_PACRF_WP3_SHIFT 17
-#define AIPS_PACRF_WP3_WIDTH 1
-#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP3_SHIFT))&AIPS_PACRF_WP3_MASK)
-#define AIPS_PACRF_SP3_MASK 0x40000u
-#define AIPS_PACRF_SP3_SHIFT 18
-#define AIPS_PACRF_SP3_WIDTH 1
-#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP3_SHIFT))&AIPS_PACRF_SP3_MASK)
-#define AIPS_PACRF_TP2_MASK 0x100000u
-#define AIPS_PACRF_TP2_SHIFT 20
-#define AIPS_PACRF_TP2_WIDTH 1
-#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP2_SHIFT))&AIPS_PACRF_TP2_MASK)
-#define AIPS_PACRF_WP2_MASK 0x200000u
-#define AIPS_PACRF_WP2_SHIFT 21
-#define AIPS_PACRF_WP2_WIDTH 1
-#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP2_SHIFT))&AIPS_PACRF_WP2_MASK)
-#define AIPS_PACRF_SP2_MASK 0x400000u
-#define AIPS_PACRF_SP2_SHIFT 22
-#define AIPS_PACRF_SP2_WIDTH 1
-#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP2_SHIFT))&AIPS_PACRF_SP2_MASK)
-#define AIPS_PACRF_TP1_MASK 0x1000000u
-#define AIPS_PACRF_TP1_SHIFT 24
-#define AIPS_PACRF_TP1_WIDTH 1
-#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP1_SHIFT))&AIPS_PACRF_TP1_MASK)
-#define AIPS_PACRF_WP1_MASK 0x2000000u
-#define AIPS_PACRF_WP1_SHIFT 25
-#define AIPS_PACRF_WP1_WIDTH 1
-#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP1_SHIFT))&AIPS_PACRF_WP1_MASK)
-#define AIPS_PACRF_SP1_MASK 0x4000000u
-#define AIPS_PACRF_SP1_SHIFT 26
-#define AIPS_PACRF_SP1_WIDTH 1
-#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP1_SHIFT))&AIPS_PACRF_SP1_MASK)
-#define AIPS_PACRF_TP0_MASK 0x10000000u
-#define AIPS_PACRF_TP0_SHIFT 28
-#define AIPS_PACRF_TP0_WIDTH 1
-#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_TP0_SHIFT))&AIPS_PACRF_TP0_MASK)
-#define AIPS_PACRF_WP0_MASK 0x20000000u
-#define AIPS_PACRF_WP0_SHIFT 29
-#define AIPS_PACRF_WP0_WIDTH 1
-#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_WP0_SHIFT))&AIPS_PACRF_WP0_MASK)
-#define AIPS_PACRF_SP0_MASK 0x40000000u
-#define AIPS_PACRF_SP0_SHIFT 30
-#define AIPS_PACRF_SP0_WIDTH 1
-#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRF_SP0_SHIFT))&AIPS_PACRF_SP0_MASK)
-/* PACRG Bit Fields */
-#define AIPS_PACRG_TP7_MASK 0x1u
-#define AIPS_PACRG_TP7_SHIFT 0
-#define AIPS_PACRG_TP7_WIDTH 1
-#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP7_SHIFT))&AIPS_PACRG_TP7_MASK)
-#define AIPS_PACRG_WP7_MASK 0x2u
-#define AIPS_PACRG_WP7_SHIFT 1
-#define AIPS_PACRG_WP7_WIDTH 1
-#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP7_SHIFT))&AIPS_PACRG_WP7_MASK)
-#define AIPS_PACRG_SP7_MASK 0x4u
-#define AIPS_PACRG_SP7_SHIFT 2
-#define AIPS_PACRG_SP7_WIDTH 1
-#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP7_SHIFT))&AIPS_PACRG_SP7_MASK)
-#define AIPS_PACRG_TP6_MASK 0x10u
-#define AIPS_PACRG_TP6_SHIFT 4
-#define AIPS_PACRG_TP6_WIDTH 1
-#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP6_SHIFT))&AIPS_PACRG_TP6_MASK)
-#define AIPS_PACRG_WP6_MASK 0x20u
-#define AIPS_PACRG_WP6_SHIFT 5
-#define AIPS_PACRG_WP6_WIDTH 1
-#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP6_SHIFT))&AIPS_PACRG_WP6_MASK)
-#define AIPS_PACRG_SP6_MASK 0x40u
-#define AIPS_PACRG_SP6_SHIFT 6
-#define AIPS_PACRG_SP6_WIDTH 1
-#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP6_SHIFT))&AIPS_PACRG_SP6_MASK)
-#define AIPS_PACRG_TP5_MASK 0x100u
-#define AIPS_PACRG_TP5_SHIFT 8
-#define AIPS_PACRG_TP5_WIDTH 1
-#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP5_SHIFT))&AIPS_PACRG_TP5_MASK)
-#define AIPS_PACRG_WP5_MASK 0x200u
-#define AIPS_PACRG_WP5_SHIFT 9
-#define AIPS_PACRG_WP5_WIDTH 1
-#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP5_SHIFT))&AIPS_PACRG_WP5_MASK)
-#define AIPS_PACRG_SP5_MASK 0x400u
-#define AIPS_PACRG_SP5_SHIFT 10
-#define AIPS_PACRG_SP5_WIDTH 1
-#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP5_SHIFT))&AIPS_PACRG_SP5_MASK)
-#define AIPS_PACRG_TP4_MASK 0x1000u
-#define AIPS_PACRG_TP4_SHIFT 12
-#define AIPS_PACRG_TP4_WIDTH 1
-#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP4_SHIFT))&AIPS_PACRG_TP4_MASK)
-#define AIPS_PACRG_WP4_MASK 0x2000u
-#define AIPS_PACRG_WP4_SHIFT 13
-#define AIPS_PACRG_WP4_WIDTH 1
-#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP4_SHIFT))&AIPS_PACRG_WP4_MASK)
-#define AIPS_PACRG_SP4_MASK 0x4000u
-#define AIPS_PACRG_SP4_SHIFT 14
-#define AIPS_PACRG_SP4_WIDTH 1
-#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP4_SHIFT))&AIPS_PACRG_SP4_MASK)
-#define AIPS_PACRG_TP3_MASK 0x10000u
-#define AIPS_PACRG_TP3_SHIFT 16
-#define AIPS_PACRG_TP3_WIDTH 1
-#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP3_SHIFT))&AIPS_PACRG_TP3_MASK)
-#define AIPS_PACRG_WP3_MASK 0x20000u
-#define AIPS_PACRG_WP3_SHIFT 17
-#define AIPS_PACRG_WP3_WIDTH 1
-#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP3_SHIFT))&AIPS_PACRG_WP3_MASK)
-#define AIPS_PACRG_SP3_MASK 0x40000u
-#define AIPS_PACRG_SP3_SHIFT 18
-#define AIPS_PACRG_SP3_WIDTH 1
-#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP3_SHIFT))&AIPS_PACRG_SP3_MASK)
-#define AIPS_PACRG_TP2_MASK 0x100000u
-#define AIPS_PACRG_TP2_SHIFT 20
-#define AIPS_PACRG_TP2_WIDTH 1
-#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP2_SHIFT))&AIPS_PACRG_TP2_MASK)
-#define AIPS_PACRG_WP2_MASK 0x200000u
-#define AIPS_PACRG_WP2_SHIFT 21
-#define AIPS_PACRG_WP2_WIDTH 1
-#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP2_SHIFT))&AIPS_PACRG_WP2_MASK)
-#define AIPS_PACRG_SP2_MASK 0x400000u
-#define AIPS_PACRG_SP2_SHIFT 22
-#define AIPS_PACRG_SP2_WIDTH 1
-#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP2_SHIFT))&AIPS_PACRG_SP2_MASK)
-#define AIPS_PACRG_TP1_MASK 0x1000000u
-#define AIPS_PACRG_TP1_SHIFT 24
-#define AIPS_PACRG_TP1_WIDTH 1
-#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP1_SHIFT))&AIPS_PACRG_TP1_MASK)
-#define AIPS_PACRG_WP1_MASK 0x2000000u
-#define AIPS_PACRG_WP1_SHIFT 25
-#define AIPS_PACRG_WP1_WIDTH 1
-#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP1_SHIFT))&AIPS_PACRG_WP1_MASK)
-#define AIPS_PACRG_SP1_MASK 0x4000000u
-#define AIPS_PACRG_SP1_SHIFT 26
-#define AIPS_PACRG_SP1_WIDTH 1
-#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP1_SHIFT))&AIPS_PACRG_SP1_MASK)
-#define AIPS_PACRG_TP0_MASK 0x10000000u
-#define AIPS_PACRG_TP0_SHIFT 28
-#define AIPS_PACRG_TP0_WIDTH 1
-#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_TP0_SHIFT))&AIPS_PACRG_TP0_MASK)
-#define AIPS_PACRG_WP0_MASK 0x20000000u
-#define AIPS_PACRG_WP0_SHIFT 29
-#define AIPS_PACRG_WP0_WIDTH 1
-#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_WP0_SHIFT))&AIPS_PACRG_WP0_MASK)
-#define AIPS_PACRG_SP0_MASK 0x40000000u
-#define AIPS_PACRG_SP0_SHIFT 30
-#define AIPS_PACRG_SP0_WIDTH 1
-#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRG_SP0_SHIFT))&AIPS_PACRG_SP0_MASK)
-/* PACRH Bit Fields */
-#define AIPS_PACRH_TP7_MASK 0x1u
-#define AIPS_PACRH_TP7_SHIFT 0
-#define AIPS_PACRH_TP7_WIDTH 1
-#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP7_SHIFT))&AIPS_PACRH_TP7_MASK)
-#define AIPS_PACRH_WP7_MASK 0x2u
-#define AIPS_PACRH_WP7_SHIFT 1
-#define AIPS_PACRH_WP7_WIDTH 1
-#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP7_SHIFT))&AIPS_PACRH_WP7_MASK)
-#define AIPS_PACRH_SP7_MASK 0x4u
-#define AIPS_PACRH_SP7_SHIFT 2
-#define AIPS_PACRH_SP7_WIDTH 1
-#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP7_SHIFT))&AIPS_PACRH_SP7_MASK)
-#define AIPS_PACRH_TP6_MASK 0x10u
-#define AIPS_PACRH_TP6_SHIFT 4
-#define AIPS_PACRH_TP6_WIDTH 1
-#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP6_SHIFT))&AIPS_PACRH_TP6_MASK)
-#define AIPS_PACRH_WP6_MASK 0x20u
-#define AIPS_PACRH_WP6_SHIFT 5
-#define AIPS_PACRH_WP6_WIDTH 1
-#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP6_SHIFT))&AIPS_PACRH_WP6_MASK)
-#define AIPS_PACRH_SP6_MASK 0x40u
-#define AIPS_PACRH_SP6_SHIFT 6
-#define AIPS_PACRH_SP6_WIDTH 1
-#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP6_SHIFT))&AIPS_PACRH_SP6_MASK)
-#define AIPS_PACRH_TP5_MASK 0x100u
-#define AIPS_PACRH_TP5_SHIFT 8
-#define AIPS_PACRH_TP5_WIDTH 1
-#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP5_SHIFT))&AIPS_PACRH_TP5_MASK)
-#define AIPS_PACRH_WP5_MASK 0x200u
-#define AIPS_PACRH_WP5_SHIFT 9
-#define AIPS_PACRH_WP5_WIDTH 1
-#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP5_SHIFT))&AIPS_PACRH_WP5_MASK)
-#define AIPS_PACRH_SP5_MASK 0x400u
-#define AIPS_PACRH_SP5_SHIFT 10
-#define AIPS_PACRH_SP5_WIDTH 1
-#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP5_SHIFT))&AIPS_PACRH_SP5_MASK)
-#define AIPS_PACRH_TP4_MASK 0x1000u
-#define AIPS_PACRH_TP4_SHIFT 12
-#define AIPS_PACRH_TP4_WIDTH 1
-#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP4_SHIFT))&AIPS_PACRH_TP4_MASK)
-#define AIPS_PACRH_WP4_MASK 0x2000u
-#define AIPS_PACRH_WP4_SHIFT 13
-#define AIPS_PACRH_WP4_WIDTH 1
-#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP4_SHIFT))&AIPS_PACRH_WP4_MASK)
-#define AIPS_PACRH_SP4_MASK 0x4000u
-#define AIPS_PACRH_SP4_SHIFT 14
-#define AIPS_PACRH_SP4_WIDTH 1
-#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP4_SHIFT))&AIPS_PACRH_SP4_MASK)
-#define AIPS_PACRH_TP3_MASK 0x10000u
-#define AIPS_PACRH_TP3_SHIFT 16
-#define AIPS_PACRH_TP3_WIDTH 1
-#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP3_SHIFT))&AIPS_PACRH_TP3_MASK)
-#define AIPS_PACRH_WP3_MASK 0x20000u
-#define AIPS_PACRH_WP3_SHIFT 17
-#define AIPS_PACRH_WP3_WIDTH 1
-#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP3_SHIFT))&AIPS_PACRH_WP3_MASK)
-#define AIPS_PACRH_SP3_MASK 0x40000u
-#define AIPS_PACRH_SP3_SHIFT 18
-#define AIPS_PACRH_SP3_WIDTH 1
-#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP3_SHIFT))&AIPS_PACRH_SP3_MASK)
-#define AIPS_PACRH_TP2_MASK 0x100000u
-#define AIPS_PACRH_TP2_SHIFT 20
-#define AIPS_PACRH_TP2_WIDTH 1
-#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP2_SHIFT))&AIPS_PACRH_TP2_MASK)
-#define AIPS_PACRH_WP2_MASK 0x200000u
-#define AIPS_PACRH_WP2_SHIFT 21
-#define AIPS_PACRH_WP2_WIDTH 1
-#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP2_SHIFT))&AIPS_PACRH_WP2_MASK)
-#define AIPS_PACRH_SP2_MASK 0x400000u
-#define AIPS_PACRH_SP2_SHIFT 22
-#define AIPS_PACRH_SP2_WIDTH 1
-#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP2_SHIFT))&AIPS_PACRH_SP2_MASK)
-#define AIPS_PACRH_TP1_MASK 0x1000000u
-#define AIPS_PACRH_TP1_SHIFT 24
-#define AIPS_PACRH_TP1_WIDTH 1
-#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP1_SHIFT))&AIPS_PACRH_TP1_MASK)
-#define AIPS_PACRH_WP1_MASK 0x2000000u
-#define AIPS_PACRH_WP1_SHIFT 25
-#define AIPS_PACRH_WP1_WIDTH 1
-#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP1_SHIFT))&AIPS_PACRH_WP1_MASK)
-#define AIPS_PACRH_SP1_MASK 0x4000000u
-#define AIPS_PACRH_SP1_SHIFT 26
-#define AIPS_PACRH_SP1_WIDTH 1
-#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP1_SHIFT))&AIPS_PACRH_SP1_MASK)
-#define AIPS_PACRH_TP0_MASK 0x10000000u
-#define AIPS_PACRH_TP0_SHIFT 28
-#define AIPS_PACRH_TP0_WIDTH 1
-#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_TP0_SHIFT))&AIPS_PACRH_TP0_MASK)
-#define AIPS_PACRH_WP0_MASK 0x20000000u
-#define AIPS_PACRH_WP0_SHIFT 29
-#define AIPS_PACRH_WP0_WIDTH 1
-#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_WP0_SHIFT))&AIPS_PACRH_WP0_MASK)
-#define AIPS_PACRH_SP0_MASK 0x40000000u
-#define AIPS_PACRH_SP0_SHIFT 30
-#define AIPS_PACRH_SP0_WIDTH 1
-#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRH_SP0_SHIFT))&AIPS_PACRH_SP0_MASK)
-/* PACRI Bit Fields */
-#define AIPS_PACRI_TP7_MASK 0x1u
-#define AIPS_PACRI_TP7_SHIFT 0
-#define AIPS_PACRI_TP7_WIDTH 1
-#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP7_SHIFT))&AIPS_PACRI_TP7_MASK)
-#define AIPS_PACRI_WP7_MASK 0x2u
-#define AIPS_PACRI_WP7_SHIFT 1
-#define AIPS_PACRI_WP7_WIDTH 1
-#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP7_SHIFT))&AIPS_PACRI_WP7_MASK)
-#define AIPS_PACRI_SP7_MASK 0x4u
-#define AIPS_PACRI_SP7_SHIFT 2
-#define AIPS_PACRI_SP7_WIDTH 1
-#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP7_SHIFT))&AIPS_PACRI_SP7_MASK)
-#define AIPS_PACRI_TP6_MASK 0x10u
-#define AIPS_PACRI_TP6_SHIFT 4
-#define AIPS_PACRI_TP6_WIDTH 1
-#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP6_SHIFT))&AIPS_PACRI_TP6_MASK)
-#define AIPS_PACRI_WP6_MASK 0x20u
-#define AIPS_PACRI_WP6_SHIFT 5
-#define AIPS_PACRI_WP6_WIDTH 1
-#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP6_SHIFT))&AIPS_PACRI_WP6_MASK)
-#define AIPS_PACRI_SP6_MASK 0x40u
-#define AIPS_PACRI_SP6_SHIFT 6
-#define AIPS_PACRI_SP6_WIDTH 1
-#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP6_SHIFT))&AIPS_PACRI_SP6_MASK)
-#define AIPS_PACRI_TP5_MASK 0x100u
-#define AIPS_PACRI_TP5_SHIFT 8
-#define AIPS_PACRI_TP5_WIDTH 1
-#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP5_SHIFT))&AIPS_PACRI_TP5_MASK)
-#define AIPS_PACRI_WP5_MASK 0x200u
-#define AIPS_PACRI_WP5_SHIFT 9
-#define AIPS_PACRI_WP5_WIDTH 1
-#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP5_SHIFT))&AIPS_PACRI_WP5_MASK)
-#define AIPS_PACRI_SP5_MASK 0x400u
-#define AIPS_PACRI_SP5_SHIFT 10
-#define AIPS_PACRI_SP5_WIDTH 1
-#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP5_SHIFT))&AIPS_PACRI_SP5_MASK)
-#define AIPS_PACRI_TP4_MASK 0x1000u
-#define AIPS_PACRI_TP4_SHIFT 12
-#define AIPS_PACRI_TP4_WIDTH 1
-#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP4_SHIFT))&AIPS_PACRI_TP4_MASK)
-#define AIPS_PACRI_WP4_MASK 0x2000u
-#define AIPS_PACRI_WP4_SHIFT 13
-#define AIPS_PACRI_WP4_WIDTH 1
-#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP4_SHIFT))&AIPS_PACRI_WP4_MASK)
-#define AIPS_PACRI_SP4_MASK 0x4000u
-#define AIPS_PACRI_SP4_SHIFT 14
-#define AIPS_PACRI_SP4_WIDTH 1
-#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP4_SHIFT))&AIPS_PACRI_SP4_MASK)
-#define AIPS_PACRI_TP3_MASK 0x10000u
-#define AIPS_PACRI_TP3_SHIFT 16
-#define AIPS_PACRI_TP3_WIDTH 1
-#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP3_SHIFT))&AIPS_PACRI_TP3_MASK)
-#define AIPS_PACRI_WP3_MASK 0x20000u
-#define AIPS_PACRI_WP3_SHIFT 17
-#define AIPS_PACRI_WP3_WIDTH 1
-#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP3_SHIFT))&AIPS_PACRI_WP3_MASK)
-#define AIPS_PACRI_SP3_MASK 0x40000u
-#define AIPS_PACRI_SP3_SHIFT 18
-#define AIPS_PACRI_SP3_WIDTH 1
-#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP3_SHIFT))&AIPS_PACRI_SP3_MASK)
-#define AIPS_PACRI_TP2_MASK 0x100000u
-#define AIPS_PACRI_TP2_SHIFT 20
-#define AIPS_PACRI_TP2_WIDTH 1
-#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP2_SHIFT))&AIPS_PACRI_TP2_MASK)
-#define AIPS_PACRI_WP2_MASK 0x200000u
-#define AIPS_PACRI_WP2_SHIFT 21
-#define AIPS_PACRI_WP2_WIDTH 1
-#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP2_SHIFT))&AIPS_PACRI_WP2_MASK)
-#define AIPS_PACRI_SP2_MASK 0x400000u
-#define AIPS_PACRI_SP2_SHIFT 22
-#define AIPS_PACRI_SP2_WIDTH 1
-#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP2_SHIFT))&AIPS_PACRI_SP2_MASK)
-#define AIPS_PACRI_TP1_MASK 0x1000000u
-#define AIPS_PACRI_TP1_SHIFT 24
-#define AIPS_PACRI_TP1_WIDTH 1
-#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP1_SHIFT))&AIPS_PACRI_TP1_MASK)
-#define AIPS_PACRI_WP1_MASK 0x2000000u
-#define AIPS_PACRI_WP1_SHIFT 25
-#define AIPS_PACRI_WP1_WIDTH 1
-#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP1_SHIFT))&AIPS_PACRI_WP1_MASK)
-#define AIPS_PACRI_SP1_MASK 0x4000000u
-#define AIPS_PACRI_SP1_SHIFT 26
-#define AIPS_PACRI_SP1_WIDTH 1
-#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP1_SHIFT))&AIPS_PACRI_SP1_MASK)
-#define AIPS_PACRI_TP0_MASK 0x10000000u
-#define AIPS_PACRI_TP0_SHIFT 28
-#define AIPS_PACRI_TP0_WIDTH 1
-#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_TP0_SHIFT))&AIPS_PACRI_TP0_MASK)
-#define AIPS_PACRI_WP0_MASK 0x20000000u
-#define AIPS_PACRI_WP0_SHIFT 29
-#define AIPS_PACRI_WP0_WIDTH 1
-#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_WP0_SHIFT))&AIPS_PACRI_WP0_MASK)
-#define AIPS_PACRI_SP0_MASK 0x40000000u
-#define AIPS_PACRI_SP0_SHIFT 30
-#define AIPS_PACRI_SP0_WIDTH 1
-#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRI_SP0_SHIFT))&AIPS_PACRI_SP0_MASK)
-/* PACRJ Bit Fields */
-#define AIPS_PACRJ_TP7_MASK 0x1u
-#define AIPS_PACRJ_TP7_SHIFT 0
-#define AIPS_PACRJ_TP7_WIDTH 1
-#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP7_SHIFT))&AIPS_PACRJ_TP7_MASK)
-#define AIPS_PACRJ_WP7_MASK 0x2u
-#define AIPS_PACRJ_WP7_SHIFT 1
-#define AIPS_PACRJ_WP7_WIDTH 1
-#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP7_SHIFT))&AIPS_PACRJ_WP7_MASK)
-#define AIPS_PACRJ_SP7_MASK 0x4u
-#define AIPS_PACRJ_SP7_SHIFT 2
-#define AIPS_PACRJ_SP7_WIDTH 1
-#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP7_SHIFT))&AIPS_PACRJ_SP7_MASK)
-#define AIPS_PACRJ_TP6_MASK 0x10u
-#define AIPS_PACRJ_TP6_SHIFT 4
-#define AIPS_PACRJ_TP6_WIDTH 1
-#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP6_SHIFT))&AIPS_PACRJ_TP6_MASK)
-#define AIPS_PACRJ_WP6_MASK 0x20u
-#define AIPS_PACRJ_WP6_SHIFT 5
-#define AIPS_PACRJ_WP6_WIDTH 1
-#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP6_SHIFT))&AIPS_PACRJ_WP6_MASK)
-#define AIPS_PACRJ_SP6_MASK 0x40u
-#define AIPS_PACRJ_SP6_SHIFT 6
-#define AIPS_PACRJ_SP6_WIDTH 1
-#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP6_SHIFT))&AIPS_PACRJ_SP6_MASK)
-#define AIPS_PACRJ_TP5_MASK 0x100u
-#define AIPS_PACRJ_TP5_SHIFT 8
-#define AIPS_PACRJ_TP5_WIDTH 1
-#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP5_SHIFT))&AIPS_PACRJ_TP5_MASK)
-#define AIPS_PACRJ_WP5_MASK 0x200u
-#define AIPS_PACRJ_WP5_SHIFT 9
-#define AIPS_PACRJ_WP5_WIDTH 1
-#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP5_SHIFT))&AIPS_PACRJ_WP5_MASK)
-#define AIPS_PACRJ_SP5_MASK 0x400u
-#define AIPS_PACRJ_SP5_SHIFT 10
-#define AIPS_PACRJ_SP5_WIDTH 1
-#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP5_SHIFT))&AIPS_PACRJ_SP5_MASK)
-#define AIPS_PACRJ_TP4_MASK 0x1000u
-#define AIPS_PACRJ_TP4_SHIFT 12
-#define AIPS_PACRJ_TP4_WIDTH 1
-#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP4_SHIFT))&AIPS_PACRJ_TP4_MASK)
-#define AIPS_PACRJ_WP4_MASK 0x2000u
-#define AIPS_PACRJ_WP4_SHIFT 13
-#define AIPS_PACRJ_WP4_WIDTH 1
-#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP4_SHIFT))&AIPS_PACRJ_WP4_MASK)
-#define AIPS_PACRJ_SP4_MASK 0x4000u
-#define AIPS_PACRJ_SP4_SHIFT 14
-#define AIPS_PACRJ_SP4_WIDTH 1
-#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP4_SHIFT))&AIPS_PACRJ_SP4_MASK)
-#define AIPS_PACRJ_TP3_MASK 0x10000u
-#define AIPS_PACRJ_TP3_SHIFT 16
-#define AIPS_PACRJ_TP3_WIDTH 1
-#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP3_SHIFT))&AIPS_PACRJ_TP3_MASK)
-#define AIPS_PACRJ_WP3_MASK 0x20000u
-#define AIPS_PACRJ_WP3_SHIFT 17
-#define AIPS_PACRJ_WP3_WIDTH 1
-#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP3_SHIFT))&AIPS_PACRJ_WP3_MASK)
-#define AIPS_PACRJ_SP3_MASK 0x40000u
-#define AIPS_PACRJ_SP3_SHIFT 18
-#define AIPS_PACRJ_SP3_WIDTH 1
-#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP3_SHIFT))&AIPS_PACRJ_SP3_MASK)
-#define AIPS_PACRJ_TP2_MASK 0x100000u
-#define AIPS_PACRJ_TP2_SHIFT 20
-#define AIPS_PACRJ_TP2_WIDTH 1
-#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP2_SHIFT))&AIPS_PACRJ_TP2_MASK)
-#define AIPS_PACRJ_WP2_MASK 0x200000u
-#define AIPS_PACRJ_WP2_SHIFT 21
-#define AIPS_PACRJ_WP2_WIDTH 1
-#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP2_SHIFT))&AIPS_PACRJ_WP2_MASK)
-#define AIPS_PACRJ_SP2_MASK 0x400000u
-#define AIPS_PACRJ_SP2_SHIFT 22
-#define AIPS_PACRJ_SP2_WIDTH 1
-#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP2_SHIFT))&AIPS_PACRJ_SP2_MASK)
-#define AIPS_PACRJ_TP1_MASK 0x1000000u
-#define AIPS_PACRJ_TP1_SHIFT 24
-#define AIPS_PACRJ_TP1_WIDTH 1
-#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP1_SHIFT))&AIPS_PACRJ_TP1_MASK)
-#define AIPS_PACRJ_WP1_MASK 0x2000000u
-#define AIPS_PACRJ_WP1_SHIFT 25
-#define AIPS_PACRJ_WP1_WIDTH 1
-#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP1_SHIFT))&AIPS_PACRJ_WP1_MASK)
-#define AIPS_PACRJ_SP1_MASK 0x4000000u
-#define AIPS_PACRJ_SP1_SHIFT 26
-#define AIPS_PACRJ_SP1_WIDTH 1
-#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP1_SHIFT))&AIPS_PACRJ_SP1_MASK)
-#define AIPS_PACRJ_TP0_MASK 0x10000000u
-#define AIPS_PACRJ_TP0_SHIFT 28
-#define AIPS_PACRJ_TP0_WIDTH 1
-#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_TP0_SHIFT))&AIPS_PACRJ_TP0_MASK)
-#define AIPS_PACRJ_WP0_MASK 0x20000000u
-#define AIPS_PACRJ_WP0_SHIFT 29
-#define AIPS_PACRJ_WP0_WIDTH 1
-#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_WP0_SHIFT))&AIPS_PACRJ_WP0_MASK)
-#define AIPS_PACRJ_SP0_MASK 0x40000000u
-#define AIPS_PACRJ_SP0_SHIFT 30
-#define AIPS_PACRJ_SP0_WIDTH 1
-#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRJ_SP0_SHIFT))&AIPS_PACRJ_SP0_MASK)
-/* PACRK Bit Fields */
-#define AIPS_PACRK_TP7_MASK 0x1u
-#define AIPS_PACRK_TP7_SHIFT 0
-#define AIPS_PACRK_TP7_WIDTH 1
-#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP7_SHIFT))&AIPS_PACRK_TP7_MASK)
-#define AIPS_PACRK_WP7_MASK 0x2u
-#define AIPS_PACRK_WP7_SHIFT 1
-#define AIPS_PACRK_WP7_WIDTH 1
-#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP7_SHIFT))&AIPS_PACRK_WP7_MASK)
-#define AIPS_PACRK_SP7_MASK 0x4u
-#define AIPS_PACRK_SP7_SHIFT 2
-#define AIPS_PACRK_SP7_WIDTH 1
-#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP7_SHIFT))&AIPS_PACRK_SP7_MASK)
-#define AIPS_PACRK_TP6_MASK 0x10u
-#define AIPS_PACRK_TP6_SHIFT 4
-#define AIPS_PACRK_TP6_WIDTH 1
-#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP6_SHIFT))&AIPS_PACRK_TP6_MASK)
-#define AIPS_PACRK_WP6_MASK 0x20u
-#define AIPS_PACRK_WP6_SHIFT 5
-#define AIPS_PACRK_WP6_WIDTH 1
-#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP6_SHIFT))&AIPS_PACRK_WP6_MASK)
-#define AIPS_PACRK_SP6_MASK 0x40u
-#define AIPS_PACRK_SP6_SHIFT 6
-#define AIPS_PACRK_SP6_WIDTH 1
-#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP6_SHIFT))&AIPS_PACRK_SP6_MASK)
-#define AIPS_PACRK_TP5_MASK 0x100u
-#define AIPS_PACRK_TP5_SHIFT 8
-#define AIPS_PACRK_TP5_WIDTH 1
-#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP5_SHIFT))&AIPS_PACRK_TP5_MASK)
-#define AIPS_PACRK_WP5_MASK 0x200u
-#define AIPS_PACRK_WP5_SHIFT 9
-#define AIPS_PACRK_WP5_WIDTH 1
-#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP5_SHIFT))&AIPS_PACRK_WP5_MASK)
-#define AIPS_PACRK_SP5_MASK 0x400u
-#define AIPS_PACRK_SP5_SHIFT 10
-#define AIPS_PACRK_SP5_WIDTH 1
-#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP5_SHIFT))&AIPS_PACRK_SP5_MASK)
-#define AIPS_PACRK_TP4_MASK 0x1000u
-#define AIPS_PACRK_TP4_SHIFT 12
-#define AIPS_PACRK_TP4_WIDTH 1
-#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP4_SHIFT))&AIPS_PACRK_TP4_MASK)
-#define AIPS_PACRK_WP4_MASK 0x2000u
-#define AIPS_PACRK_WP4_SHIFT 13
-#define AIPS_PACRK_WP4_WIDTH 1
-#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP4_SHIFT))&AIPS_PACRK_WP4_MASK)
-#define AIPS_PACRK_SP4_MASK 0x4000u
-#define AIPS_PACRK_SP4_SHIFT 14
-#define AIPS_PACRK_SP4_WIDTH 1
-#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP4_SHIFT))&AIPS_PACRK_SP4_MASK)
-#define AIPS_PACRK_TP3_MASK 0x10000u
-#define AIPS_PACRK_TP3_SHIFT 16
-#define AIPS_PACRK_TP3_WIDTH 1
-#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP3_SHIFT))&AIPS_PACRK_TP3_MASK)
-#define AIPS_PACRK_WP3_MASK 0x20000u
-#define AIPS_PACRK_WP3_SHIFT 17
-#define AIPS_PACRK_WP3_WIDTH 1
-#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP3_SHIFT))&AIPS_PACRK_WP3_MASK)
-#define AIPS_PACRK_SP3_MASK 0x40000u
-#define AIPS_PACRK_SP3_SHIFT 18
-#define AIPS_PACRK_SP3_WIDTH 1
-#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP3_SHIFT))&AIPS_PACRK_SP3_MASK)
-#define AIPS_PACRK_TP2_MASK 0x100000u
-#define AIPS_PACRK_TP2_SHIFT 20
-#define AIPS_PACRK_TP2_WIDTH 1
-#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP2_SHIFT))&AIPS_PACRK_TP2_MASK)
-#define AIPS_PACRK_WP2_MASK 0x200000u
-#define AIPS_PACRK_WP2_SHIFT 21
-#define AIPS_PACRK_WP2_WIDTH 1
-#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP2_SHIFT))&AIPS_PACRK_WP2_MASK)
-#define AIPS_PACRK_SP2_MASK 0x400000u
-#define AIPS_PACRK_SP2_SHIFT 22
-#define AIPS_PACRK_SP2_WIDTH 1
-#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP2_SHIFT))&AIPS_PACRK_SP2_MASK)
-#define AIPS_PACRK_TP1_MASK 0x1000000u
-#define AIPS_PACRK_TP1_SHIFT 24
-#define AIPS_PACRK_TP1_WIDTH 1
-#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP1_SHIFT))&AIPS_PACRK_TP1_MASK)
-#define AIPS_PACRK_WP1_MASK 0x2000000u
-#define AIPS_PACRK_WP1_SHIFT 25
-#define AIPS_PACRK_WP1_WIDTH 1
-#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP1_SHIFT))&AIPS_PACRK_WP1_MASK)
-#define AIPS_PACRK_SP1_MASK 0x4000000u
-#define AIPS_PACRK_SP1_SHIFT 26
-#define AIPS_PACRK_SP1_WIDTH 1
-#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP1_SHIFT))&AIPS_PACRK_SP1_MASK)
-#define AIPS_PACRK_TP0_MASK 0x10000000u
-#define AIPS_PACRK_TP0_SHIFT 28
-#define AIPS_PACRK_TP0_WIDTH 1
-#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_TP0_SHIFT))&AIPS_PACRK_TP0_MASK)
-#define AIPS_PACRK_WP0_MASK 0x20000000u
-#define AIPS_PACRK_WP0_SHIFT 29
-#define AIPS_PACRK_WP0_WIDTH 1
-#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_WP0_SHIFT))&AIPS_PACRK_WP0_MASK)
-#define AIPS_PACRK_SP0_MASK 0x40000000u
-#define AIPS_PACRK_SP0_SHIFT 30
-#define AIPS_PACRK_SP0_WIDTH 1
-#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRK_SP0_SHIFT))&AIPS_PACRK_SP0_MASK)
-/* PACRL Bit Fields */
-#define AIPS_PACRL_TP7_MASK 0x1u
-#define AIPS_PACRL_TP7_SHIFT 0
-#define AIPS_PACRL_TP7_WIDTH 1
-#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP7_SHIFT))&AIPS_PACRL_TP7_MASK)
-#define AIPS_PACRL_WP7_MASK 0x2u
-#define AIPS_PACRL_WP7_SHIFT 1
-#define AIPS_PACRL_WP7_WIDTH 1
-#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP7_SHIFT))&AIPS_PACRL_WP7_MASK)
-#define AIPS_PACRL_SP7_MASK 0x4u
-#define AIPS_PACRL_SP7_SHIFT 2
-#define AIPS_PACRL_SP7_WIDTH 1
-#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP7_SHIFT))&AIPS_PACRL_SP7_MASK)
-#define AIPS_PACRL_TP6_MASK 0x10u
-#define AIPS_PACRL_TP6_SHIFT 4
-#define AIPS_PACRL_TP6_WIDTH 1
-#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP6_SHIFT))&AIPS_PACRL_TP6_MASK)
-#define AIPS_PACRL_WP6_MASK 0x20u
-#define AIPS_PACRL_WP6_SHIFT 5
-#define AIPS_PACRL_WP6_WIDTH 1
-#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP6_SHIFT))&AIPS_PACRL_WP6_MASK)
-#define AIPS_PACRL_SP6_MASK 0x40u
-#define AIPS_PACRL_SP6_SHIFT 6
-#define AIPS_PACRL_SP6_WIDTH 1
-#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP6_SHIFT))&AIPS_PACRL_SP6_MASK)
-#define AIPS_PACRL_TP5_MASK 0x100u
-#define AIPS_PACRL_TP5_SHIFT 8
-#define AIPS_PACRL_TP5_WIDTH 1
-#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP5_SHIFT))&AIPS_PACRL_TP5_MASK)
-#define AIPS_PACRL_WP5_MASK 0x200u
-#define AIPS_PACRL_WP5_SHIFT 9
-#define AIPS_PACRL_WP5_WIDTH 1
-#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP5_SHIFT))&AIPS_PACRL_WP5_MASK)
-#define AIPS_PACRL_SP5_MASK 0x400u
-#define AIPS_PACRL_SP5_SHIFT 10
-#define AIPS_PACRL_SP5_WIDTH 1
-#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP5_SHIFT))&AIPS_PACRL_SP5_MASK)
-#define AIPS_PACRL_TP4_MASK 0x1000u
-#define AIPS_PACRL_TP4_SHIFT 12
-#define AIPS_PACRL_TP4_WIDTH 1
-#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP4_SHIFT))&AIPS_PACRL_TP4_MASK)
-#define AIPS_PACRL_WP4_MASK 0x2000u
-#define AIPS_PACRL_WP4_SHIFT 13
-#define AIPS_PACRL_WP4_WIDTH 1
-#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP4_SHIFT))&AIPS_PACRL_WP4_MASK)
-#define AIPS_PACRL_SP4_MASK 0x4000u
-#define AIPS_PACRL_SP4_SHIFT 14
-#define AIPS_PACRL_SP4_WIDTH 1
-#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP4_SHIFT))&AIPS_PACRL_SP4_MASK)
-#define AIPS_PACRL_TP3_MASK 0x10000u
-#define AIPS_PACRL_TP3_SHIFT 16
-#define AIPS_PACRL_TP3_WIDTH 1
-#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP3_SHIFT))&AIPS_PACRL_TP3_MASK)
-#define AIPS_PACRL_WP3_MASK 0x20000u
-#define AIPS_PACRL_WP3_SHIFT 17
-#define AIPS_PACRL_WP3_WIDTH 1
-#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP3_SHIFT))&AIPS_PACRL_WP3_MASK)
-#define AIPS_PACRL_SP3_MASK 0x40000u
-#define AIPS_PACRL_SP3_SHIFT 18
-#define AIPS_PACRL_SP3_WIDTH 1
-#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP3_SHIFT))&AIPS_PACRL_SP3_MASK)
-#define AIPS_PACRL_TP2_MASK 0x100000u
-#define AIPS_PACRL_TP2_SHIFT 20
-#define AIPS_PACRL_TP2_WIDTH 1
-#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP2_SHIFT))&AIPS_PACRL_TP2_MASK)
-#define AIPS_PACRL_WP2_MASK 0x200000u
-#define AIPS_PACRL_WP2_SHIFT 21
-#define AIPS_PACRL_WP2_WIDTH 1
-#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP2_SHIFT))&AIPS_PACRL_WP2_MASK)
-#define AIPS_PACRL_SP2_MASK 0x400000u
-#define AIPS_PACRL_SP2_SHIFT 22
-#define AIPS_PACRL_SP2_WIDTH 1
-#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP2_SHIFT))&AIPS_PACRL_SP2_MASK)
-#define AIPS_PACRL_TP1_MASK 0x1000000u
-#define AIPS_PACRL_TP1_SHIFT 24
-#define AIPS_PACRL_TP1_WIDTH 1
-#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP1_SHIFT))&AIPS_PACRL_TP1_MASK)
-#define AIPS_PACRL_WP1_MASK 0x2000000u
-#define AIPS_PACRL_WP1_SHIFT 25
-#define AIPS_PACRL_WP1_WIDTH 1
-#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP1_SHIFT))&AIPS_PACRL_WP1_MASK)
-#define AIPS_PACRL_SP1_MASK 0x4000000u
-#define AIPS_PACRL_SP1_SHIFT 26
-#define AIPS_PACRL_SP1_WIDTH 1
-#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP1_SHIFT))&AIPS_PACRL_SP1_MASK)
-#define AIPS_PACRL_TP0_MASK 0x10000000u
-#define AIPS_PACRL_TP0_SHIFT 28
-#define AIPS_PACRL_TP0_WIDTH 1
-#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_TP0_SHIFT))&AIPS_PACRL_TP0_MASK)
-#define AIPS_PACRL_WP0_MASK 0x20000000u
-#define AIPS_PACRL_WP0_SHIFT 29
-#define AIPS_PACRL_WP0_WIDTH 1
-#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_WP0_SHIFT))&AIPS_PACRL_WP0_MASK)
-#define AIPS_PACRL_SP0_MASK 0x40000000u
-#define AIPS_PACRL_SP0_SHIFT 30
-#define AIPS_PACRL_SP0_WIDTH 1
-#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRL_SP0_SHIFT))&AIPS_PACRL_SP0_MASK)
-/* PACRM Bit Fields */
-#define AIPS_PACRM_TP7_MASK 0x1u
-#define AIPS_PACRM_TP7_SHIFT 0
-#define AIPS_PACRM_TP7_WIDTH 1
-#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP7_SHIFT))&AIPS_PACRM_TP7_MASK)
-#define AIPS_PACRM_WP7_MASK 0x2u
-#define AIPS_PACRM_WP7_SHIFT 1
-#define AIPS_PACRM_WP7_WIDTH 1
-#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP7_SHIFT))&AIPS_PACRM_WP7_MASK)
-#define AIPS_PACRM_SP7_MASK 0x4u
-#define AIPS_PACRM_SP7_SHIFT 2
-#define AIPS_PACRM_SP7_WIDTH 1
-#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP7_SHIFT))&AIPS_PACRM_SP7_MASK)
-#define AIPS_PACRM_TP6_MASK 0x10u
-#define AIPS_PACRM_TP6_SHIFT 4
-#define AIPS_PACRM_TP6_WIDTH 1
-#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP6_SHIFT))&AIPS_PACRM_TP6_MASK)
-#define AIPS_PACRM_WP6_MASK 0x20u
-#define AIPS_PACRM_WP6_SHIFT 5
-#define AIPS_PACRM_WP6_WIDTH 1
-#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP6_SHIFT))&AIPS_PACRM_WP6_MASK)
-#define AIPS_PACRM_SP6_MASK 0x40u
-#define AIPS_PACRM_SP6_SHIFT 6
-#define AIPS_PACRM_SP6_WIDTH 1
-#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP6_SHIFT))&AIPS_PACRM_SP6_MASK)
-#define AIPS_PACRM_TP5_MASK 0x100u
-#define AIPS_PACRM_TP5_SHIFT 8
-#define AIPS_PACRM_TP5_WIDTH 1
-#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP5_SHIFT))&AIPS_PACRM_TP5_MASK)
-#define AIPS_PACRM_WP5_MASK 0x200u
-#define AIPS_PACRM_WP5_SHIFT 9
-#define AIPS_PACRM_WP5_WIDTH 1
-#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP5_SHIFT))&AIPS_PACRM_WP5_MASK)
-#define AIPS_PACRM_SP5_MASK 0x400u
-#define AIPS_PACRM_SP5_SHIFT 10
-#define AIPS_PACRM_SP5_WIDTH 1
-#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP5_SHIFT))&AIPS_PACRM_SP5_MASK)
-#define AIPS_PACRM_TP4_MASK 0x1000u
-#define AIPS_PACRM_TP4_SHIFT 12
-#define AIPS_PACRM_TP4_WIDTH 1
-#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP4_SHIFT))&AIPS_PACRM_TP4_MASK)
-#define AIPS_PACRM_WP4_MASK 0x2000u
-#define AIPS_PACRM_WP4_SHIFT 13
-#define AIPS_PACRM_WP4_WIDTH 1
-#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP4_SHIFT))&AIPS_PACRM_WP4_MASK)
-#define AIPS_PACRM_SP4_MASK 0x4000u
-#define AIPS_PACRM_SP4_SHIFT 14
-#define AIPS_PACRM_SP4_WIDTH 1
-#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP4_SHIFT))&AIPS_PACRM_SP4_MASK)
-#define AIPS_PACRM_TP3_MASK 0x10000u
-#define AIPS_PACRM_TP3_SHIFT 16
-#define AIPS_PACRM_TP3_WIDTH 1
-#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP3_SHIFT))&AIPS_PACRM_TP3_MASK)
-#define AIPS_PACRM_WP3_MASK 0x20000u
-#define AIPS_PACRM_WP3_SHIFT 17
-#define AIPS_PACRM_WP3_WIDTH 1
-#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP3_SHIFT))&AIPS_PACRM_WP3_MASK)
-#define AIPS_PACRM_SP3_MASK 0x40000u
-#define AIPS_PACRM_SP3_SHIFT 18
-#define AIPS_PACRM_SP3_WIDTH 1
-#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP3_SHIFT))&AIPS_PACRM_SP3_MASK)
-#define AIPS_PACRM_TP2_MASK 0x100000u
-#define AIPS_PACRM_TP2_SHIFT 20
-#define AIPS_PACRM_TP2_WIDTH 1
-#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP2_SHIFT))&AIPS_PACRM_TP2_MASK)
-#define AIPS_PACRM_WP2_MASK 0x200000u
-#define AIPS_PACRM_WP2_SHIFT 21
-#define AIPS_PACRM_WP2_WIDTH 1
-#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP2_SHIFT))&AIPS_PACRM_WP2_MASK)
-#define AIPS_PACRM_SP2_MASK 0x400000u
-#define AIPS_PACRM_SP2_SHIFT 22
-#define AIPS_PACRM_SP2_WIDTH 1
-#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP2_SHIFT))&AIPS_PACRM_SP2_MASK)
-#define AIPS_PACRM_TP1_MASK 0x1000000u
-#define AIPS_PACRM_TP1_SHIFT 24
-#define AIPS_PACRM_TP1_WIDTH 1
-#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP1_SHIFT))&AIPS_PACRM_TP1_MASK)
-#define AIPS_PACRM_WP1_MASK 0x2000000u
-#define AIPS_PACRM_WP1_SHIFT 25
-#define AIPS_PACRM_WP1_WIDTH 1
-#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP1_SHIFT))&AIPS_PACRM_WP1_MASK)
-#define AIPS_PACRM_SP1_MASK 0x4000000u
-#define AIPS_PACRM_SP1_SHIFT 26
-#define AIPS_PACRM_SP1_WIDTH 1
-#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP1_SHIFT))&AIPS_PACRM_SP1_MASK)
-#define AIPS_PACRM_TP0_MASK 0x10000000u
-#define AIPS_PACRM_TP0_SHIFT 28
-#define AIPS_PACRM_TP0_WIDTH 1
-#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_TP0_SHIFT))&AIPS_PACRM_TP0_MASK)
-#define AIPS_PACRM_WP0_MASK 0x20000000u
-#define AIPS_PACRM_WP0_SHIFT 29
-#define AIPS_PACRM_WP0_WIDTH 1
-#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_WP0_SHIFT))&AIPS_PACRM_WP0_MASK)
-#define AIPS_PACRM_SP0_MASK 0x40000000u
-#define AIPS_PACRM_SP0_SHIFT 30
-#define AIPS_PACRM_SP0_WIDTH 1
-#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRM_SP0_SHIFT))&AIPS_PACRM_SP0_MASK)
-/* PACRN Bit Fields */
-#define AIPS_PACRN_TP7_MASK 0x1u
-#define AIPS_PACRN_TP7_SHIFT 0
-#define AIPS_PACRN_TP7_WIDTH 1
-#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP7_SHIFT))&AIPS_PACRN_TP7_MASK)
-#define AIPS_PACRN_WP7_MASK 0x2u
-#define AIPS_PACRN_WP7_SHIFT 1
-#define AIPS_PACRN_WP7_WIDTH 1
-#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP7_SHIFT))&AIPS_PACRN_WP7_MASK)
-#define AIPS_PACRN_SP7_MASK 0x4u
-#define AIPS_PACRN_SP7_SHIFT 2
-#define AIPS_PACRN_SP7_WIDTH 1
-#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP7_SHIFT))&AIPS_PACRN_SP7_MASK)
-#define AIPS_PACRN_TP6_MASK 0x10u
-#define AIPS_PACRN_TP6_SHIFT 4
-#define AIPS_PACRN_TP6_WIDTH 1
-#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP6_SHIFT))&AIPS_PACRN_TP6_MASK)
-#define AIPS_PACRN_WP6_MASK 0x20u
-#define AIPS_PACRN_WP6_SHIFT 5
-#define AIPS_PACRN_WP6_WIDTH 1
-#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP6_SHIFT))&AIPS_PACRN_WP6_MASK)
-#define AIPS_PACRN_SP6_MASK 0x40u
-#define AIPS_PACRN_SP6_SHIFT 6
-#define AIPS_PACRN_SP6_WIDTH 1
-#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP6_SHIFT))&AIPS_PACRN_SP6_MASK)
-#define AIPS_PACRN_TP5_MASK 0x100u
-#define AIPS_PACRN_TP5_SHIFT 8
-#define AIPS_PACRN_TP5_WIDTH 1
-#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP5_SHIFT))&AIPS_PACRN_TP5_MASK)
-#define AIPS_PACRN_WP5_MASK 0x200u
-#define AIPS_PACRN_WP5_SHIFT 9
-#define AIPS_PACRN_WP5_WIDTH 1
-#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP5_SHIFT))&AIPS_PACRN_WP5_MASK)
-#define AIPS_PACRN_SP5_MASK 0x400u
-#define AIPS_PACRN_SP5_SHIFT 10
-#define AIPS_PACRN_SP5_WIDTH 1
-#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP5_SHIFT))&AIPS_PACRN_SP5_MASK)
-#define AIPS_PACRN_TP4_MASK 0x1000u
-#define AIPS_PACRN_TP4_SHIFT 12
-#define AIPS_PACRN_TP4_WIDTH 1
-#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP4_SHIFT))&AIPS_PACRN_TP4_MASK)
-#define AIPS_PACRN_WP4_MASK 0x2000u
-#define AIPS_PACRN_WP4_SHIFT 13
-#define AIPS_PACRN_WP4_WIDTH 1
-#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP4_SHIFT))&AIPS_PACRN_WP4_MASK)
-#define AIPS_PACRN_SP4_MASK 0x4000u
-#define AIPS_PACRN_SP4_SHIFT 14
-#define AIPS_PACRN_SP4_WIDTH 1
-#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP4_SHIFT))&AIPS_PACRN_SP4_MASK)
-#define AIPS_PACRN_TP3_MASK 0x10000u
-#define AIPS_PACRN_TP3_SHIFT 16
-#define AIPS_PACRN_TP3_WIDTH 1
-#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP3_SHIFT))&AIPS_PACRN_TP3_MASK)
-#define AIPS_PACRN_WP3_MASK 0x20000u
-#define AIPS_PACRN_WP3_SHIFT 17
-#define AIPS_PACRN_WP3_WIDTH 1
-#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP3_SHIFT))&AIPS_PACRN_WP3_MASK)
-#define AIPS_PACRN_SP3_MASK 0x40000u
-#define AIPS_PACRN_SP3_SHIFT 18
-#define AIPS_PACRN_SP3_WIDTH 1
-#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP3_SHIFT))&AIPS_PACRN_SP3_MASK)
-#define AIPS_PACRN_TP2_MASK 0x100000u
-#define AIPS_PACRN_TP2_SHIFT 20
-#define AIPS_PACRN_TP2_WIDTH 1
-#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP2_SHIFT))&AIPS_PACRN_TP2_MASK)
-#define AIPS_PACRN_WP2_MASK 0x200000u
-#define AIPS_PACRN_WP2_SHIFT 21
-#define AIPS_PACRN_WP2_WIDTH 1
-#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP2_SHIFT))&AIPS_PACRN_WP2_MASK)
-#define AIPS_PACRN_SP2_MASK 0x400000u
-#define AIPS_PACRN_SP2_SHIFT 22
-#define AIPS_PACRN_SP2_WIDTH 1
-#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP2_SHIFT))&AIPS_PACRN_SP2_MASK)
-#define AIPS_PACRN_TP1_MASK 0x1000000u
-#define AIPS_PACRN_TP1_SHIFT 24
-#define AIPS_PACRN_TP1_WIDTH 1
-#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP1_SHIFT))&AIPS_PACRN_TP1_MASK)
-#define AIPS_PACRN_WP1_MASK 0x2000000u
-#define AIPS_PACRN_WP1_SHIFT 25
-#define AIPS_PACRN_WP1_WIDTH 1
-#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP1_SHIFT))&AIPS_PACRN_WP1_MASK)
-#define AIPS_PACRN_SP1_MASK 0x4000000u
-#define AIPS_PACRN_SP1_SHIFT 26
-#define AIPS_PACRN_SP1_WIDTH 1
-#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP1_SHIFT))&AIPS_PACRN_SP1_MASK)
-#define AIPS_PACRN_TP0_MASK 0x10000000u
-#define AIPS_PACRN_TP0_SHIFT 28
-#define AIPS_PACRN_TP0_WIDTH 1
-#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_TP0_SHIFT))&AIPS_PACRN_TP0_MASK)
-#define AIPS_PACRN_WP0_MASK 0x20000000u
-#define AIPS_PACRN_WP0_SHIFT 29
-#define AIPS_PACRN_WP0_WIDTH 1
-#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_WP0_SHIFT))&AIPS_PACRN_WP0_MASK)
-#define AIPS_PACRN_SP0_MASK 0x40000000u
-#define AIPS_PACRN_SP0_SHIFT 30
-#define AIPS_PACRN_SP0_WIDTH 1
-#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRN_SP0_SHIFT))&AIPS_PACRN_SP0_MASK)
-/* PACRO Bit Fields */
-#define AIPS_PACRO_TP7_MASK 0x1u
-#define AIPS_PACRO_TP7_SHIFT 0
-#define AIPS_PACRO_TP7_WIDTH 1
-#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP7_SHIFT))&AIPS_PACRO_TP7_MASK)
-#define AIPS_PACRO_WP7_MASK 0x2u
-#define AIPS_PACRO_WP7_SHIFT 1
-#define AIPS_PACRO_WP7_WIDTH 1
-#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP7_SHIFT))&AIPS_PACRO_WP7_MASK)
-#define AIPS_PACRO_SP7_MASK 0x4u
-#define AIPS_PACRO_SP7_SHIFT 2
-#define AIPS_PACRO_SP7_WIDTH 1
-#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP7_SHIFT))&AIPS_PACRO_SP7_MASK)
-#define AIPS_PACRO_TP6_MASK 0x10u
-#define AIPS_PACRO_TP6_SHIFT 4
-#define AIPS_PACRO_TP6_WIDTH 1
-#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP6_SHIFT))&AIPS_PACRO_TP6_MASK)
-#define AIPS_PACRO_WP6_MASK 0x20u
-#define AIPS_PACRO_WP6_SHIFT 5
-#define AIPS_PACRO_WP6_WIDTH 1
-#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP6_SHIFT))&AIPS_PACRO_WP6_MASK)
-#define AIPS_PACRO_SP6_MASK 0x40u
-#define AIPS_PACRO_SP6_SHIFT 6
-#define AIPS_PACRO_SP6_WIDTH 1
-#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP6_SHIFT))&AIPS_PACRO_SP6_MASK)
-#define AIPS_PACRO_TP5_MASK 0x100u
-#define AIPS_PACRO_TP5_SHIFT 8
-#define AIPS_PACRO_TP5_WIDTH 1
-#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP5_SHIFT))&AIPS_PACRO_TP5_MASK)
-#define AIPS_PACRO_WP5_MASK 0x200u
-#define AIPS_PACRO_WP5_SHIFT 9
-#define AIPS_PACRO_WP5_WIDTH 1
-#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP5_SHIFT))&AIPS_PACRO_WP5_MASK)
-#define AIPS_PACRO_SP5_MASK 0x400u
-#define AIPS_PACRO_SP5_SHIFT 10
-#define AIPS_PACRO_SP5_WIDTH 1
-#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP5_SHIFT))&AIPS_PACRO_SP5_MASK)
-#define AIPS_PACRO_TP4_MASK 0x1000u
-#define AIPS_PACRO_TP4_SHIFT 12
-#define AIPS_PACRO_TP4_WIDTH 1
-#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP4_SHIFT))&AIPS_PACRO_TP4_MASK)
-#define AIPS_PACRO_WP4_MASK 0x2000u
-#define AIPS_PACRO_WP4_SHIFT 13
-#define AIPS_PACRO_WP4_WIDTH 1
-#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP4_SHIFT))&AIPS_PACRO_WP4_MASK)
-#define AIPS_PACRO_SP4_MASK 0x4000u
-#define AIPS_PACRO_SP4_SHIFT 14
-#define AIPS_PACRO_SP4_WIDTH 1
-#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP4_SHIFT))&AIPS_PACRO_SP4_MASK)
-#define AIPS_PACRO_TP3_MASK 0x10000u
-#define AIPS_PACRO_TP3_SHIFT 16
-#define AIPS_PACRO_TP3_WIDTH 1
-#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP3_SHIFT))&AIPS_PACRO_TP3_MASK)
-#define AIPS_PACRO_WP3_MASK 0x20000u
-#define AIPS_PACRO_WP3_SHIFT 17
-#define AIPS_PACRO_WP3_WIDTH 1
-#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP3_SHIFT))&AIPS_PACRO_WP3_MASK)
-#define AIPS_PACRO_SP3_MASK 0x40000u
-#define AIPS_PACRO_SP3_SHIFT 18
-#define AIPS_PACRO_SP3_WIDTH 1
-#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP3_SHIFT))&AIPS_PACRO_SP3_MASK)
-#define AIPS_PACRO_TP2_MASK 0x100000u
-#define AIPS_PACRO_TP2_SHIFT 20
-#define AIPS_PACRO_TP2_WIDTH 1
-#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP2_SHIFT))&AIPS_PACRO_TP2_MASK)
-#define AIPS_PACRO_WP2_MASK 0x200000u
-#define AIPS_PACRO_WP2_SHIFT 21
-#define AIPS_PACRO_WP2_WIDTH 1
-#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP2_SHIFT))&AIPS_PACRO_WP2_MASK)
-#define AIPS_PACRO_SP2_MASK 0x400000u
-#define AIPS_PACRO_SP2_SHIFT 22
-#define AIPS_PACRO_SP2_WIDTH 1
-#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP2_SHIFT))&AIPS_PACRO_SP2_MASK)
-#define AIPS_PACRO_TP1_MASK 0x1000000u
-#define AIPS_PACRO_TP1_SHIFT 24
-#define AIPS_PACRO_TP1_WIDTH 1
-#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP1_SHIFT))&AIPS_PACRO_TP1_MASK)
-#define AIPS_PACRO_WP1_MASK 0x2000000u
-#define AIPS_PACRO_WP1_SHIFT 25
-#define AIPS_PACRO_WP1_WIDTH 1
-#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP1_SHIFT))&AIPS_PACRO_WP1_MASK)
-#define AIPS_PACRO_SP1_MASK 0x4000000u
-#define AIPS_PACRO_SP1_SHIFT 26
-#define AIPS_PACRO_SP1_WIDTH 1
-#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP1_SHIFT))&AIPS_PACRO_SP1_MASK)
-#define AIPS_PACRO_TP0_MASK 0x10000000u
-#define AIPS_PACRO_TP0_SHIFT 28
-#define AIPS_PACRO_TP0_WIDTH 1
-#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_TP0_SHIFT))&AIPS_PACRO_TP0_MASK)
-#define AIPS_PACRO_WP0_MASK 0x20000000u
-#define AIPS_PACRO_WP0_SHIFT 29
-#define AIPS_PACRO_WP0_WIDTH 1
-#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_WP0_SHIFT))&AIPS_PACRO_WP0_MASK)
-#define AIPS_PACRO_SP0_MASK 0x40000000u
-#define AIPS_PACRO_SP0_SHIFT 30
-#define AIPS_PACRO_SP0_WIDTH 1
-#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRO_SP0_SHIFT))&AIPS_PACRO_SP0_MASK)
-/* PACRP Bit Fields */
-#define AIPS_PACRP_TP7_MASK 0x1u
-#define AIPS_PACRP_TP7_SHIFT 0
-#define AIPS_PACRP_TP7_WIDTH 1
-#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP7_SHIFT))&AIPS_PACRP_TP7_MASK)
-#define AIPS_PACRP_WP7_MASK 0x2u
-#define AIPS_PACRP_WP7_SHIFT 1
-#define AIPS_PACRP_WP7_WIDTH 1
-#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP7_SHIFT))&AIPS_PACRP_WP7_MASK)
-#define AIPS_PACRP_SP7_MASK 0x4u
-#define AIPS_PACRP_SP7_SHIFT 2
-#define AIPS_PACRP_SP7_WIDTH 1
-#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP7_SHIFT))&AIPS_PACRP_SP7_MASK)
-#define AIPS_PACRP_TP6_MASK 0x10u
-#define AIPS_PACRP_TP6_SHIFT 4
-#define AIPS_PACRP_TP6_WIDTH 1
-#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP6_SHIFT))&AIPS_PACRP_TP6_MASK)
-#define AIPS_PACRP_WP6_MASK 0x20u
-#define AIPS_PACRP_WP6_SHIFT 5
-#define AIPS_PACRP_WP6_WIDTH 1
-#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP6_SHIFT))&AIPS_PACRP_WP6_MASK)
-#define AIPS_PACRP_SP6_MASK 0x40u
-#define AIPS_PACRP_SP6_SHIFT 6
-#define AIPS_PACRP_SP6_WIDTH 1
-#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP6_SHIFT))&AIPS_PACRP_SP6_MASK)
-#define AIPS_PACRP_TP5_MASK 0x100u
-#define AIPS_PACRP_TP5_SHIFT 8
-#define AIPS_PACRP_TP5_WIDTH 1
-#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP5_SHIFT))&AIPS_PACRP_TP5_MASK)
-#define AIPS_PACRP_WP5_MASK 0x200u
-#define AIPS_PACRP_WP5_SHIFT 9
-#define AIPS_PACRP_WP5_WIDTH 1
-#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP5_SHIFT))&AIPS_PACRP_WP5_MASK)
-#define AIPS_PACRP_SP5_MASK 0x400u
-#define AIPS_PACRP_SP5_SHIFT 10
-#define AIPS_PACRP_SP5_WIDTH 1
-#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP5_SHIFT))&AIPS_PACRP_SP5_MASK)
-#define AIPS_PACRP_TP4_MASK 0x1000u
-#define AIPS_PACRP_TP4_SHIFT 12
-#define AIPS_PACRP_TP4_WIDTH 1
-#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP4_SHIFT))&AIPS_PACRP_TP4_MASK)
-#define AIPS_PACRP_WP4_MASK 0x2000u
-#define AIPS_PACRP_WP4_SHIFT 13
-#define AIPS_PACRP_WP4_WIDTH 1
-#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP4_SHIFT))&AIPS_PACRP_WP4_MASK)
-#define AIPS_PACRP_SP4_MASK 0x4000u
-#define AIPS_PACRP_SP4_SHIFT 14
-#define AIPS_PACRP_SP4_WIDTH 1
-#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP4_SHIFT))&AIPS_PACRP_SP4_MASK)
-#define AIPS_PACRP_TP3_MASK 0x10000u
-#define AIPS_PACRP_TP3_SHIFT 16
-#define AIPS_PACRP_TP3_WIDTH 1
-#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP3_SHIFT))&AIPS_PACRP_TP3_MASK)
-#define AIPS_PACRP_WP3_MASK 0x20000u
-#define AIPS_PACRP_WP3_SHIFT 17
-#define AIPS_PACRP_WP3_WIDTH 1
-#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP3_SHIFT))&AIPS_PACRP_WP3_MASK)
-#define AIPS_PACRP_SP3_MASK 0x40000u
-#define AIPS_PACRP_SP3_SHIFT 18
-#define AIPS_PACRP_SP3_WIDTH 1
-#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP3_SHIFT))&AIPS_PACRP_SP3_MASK)
-#define AIPS_PACRP_TP2_MASK 0x100000u
-#define AIPS_PACRP_TP2_SHIFT 20
-#define AIPS_PACRP_TP2_WIDTH 1
-#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP2_SHIFT))&AIPS_PACRP_TP2_MASK)
-#define AIPS_PACRP_WP2_MASK 0x200000u
-#define AIPS_PACRP_WP2_SHIFT 21
-#define AIPS_PACRP_WP2_WIDTH 1
-#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP2_SHIFT))&AIPS_PACRP_WP2_MASK)
-#define AIPS_PACRP_SP2_MASK 0x400000u
-#define AIPS_PACRP_SP2_SHIFT 22
-#define AIPS_PACRP_SP2_WIDTH 1
-#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP2_SHIFT))&AIPS_PACRP_SP2_MASK)
-#define AIPS_PACRP_TP1_MASK 0x1000000u
-#define AIPS_PACRP_TP1_SHIFT 24
-#define AIPS_PACRP_TP1_WIDTH 1
-#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP1_SHIFT))&AIPS_PACRP_TP1_MASK)
-#define AIPS_PACRP_WP1_MASK 0x2000000u
-#define AIPS_PACRP_WP1_SHIFT 25
-#define AIPS_PACRP_WP1_WIDTH 1
-#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP1_SHIFT))&AIPS_PACRP_WP1_MASK)
-#define AIPS_PACRP_SP1_MASK 0x4000000u
-#define AIPS_PACRP_SP1_SHIFT 26
-#define AIPS_PACRP_SP1_WIDTH 1
-#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP1_SHIFT))&AIPS_PACRP_SP1_MASK)
-#define AIPS_PACRP_TP0_MASK 0x10000000u
-#define AIPS_PACRP_TP0_SHIFT 28
-#define AIPS_PACRP_TP0_WIDTH 1
-#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_TP0_SHIFT))&AIPS_PACRP_TP0_MASK)
-#define AIPS_PACRP_WP0_MASK 0x20000000u
-#define AIPS_PACRP_WP0_SHIFT 29
-#define AIPS_PACRP_WP0_WIDTH 1
-#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_WP0_SHIFT))&AIPS_PACRP_WP0_MASK)
-#define AIPS_PACRP_SP0_MASK 0x40000000u
-#define AIPS_PACRP_SP0_SHIFT 30
-#define AIPS_PACRP_SP0_WIDTH 1
-#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACRP_SP0_SHIFT))&AIPS_PACRP_SP0_MASK)
+/*! @name PACRA - Peripheral Access Control Register */
+#define AIPS_PACRA_TP7_MASK (0x1U)
+#define AIPS_PACRA_TP7_SHIFT (0U)
+#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK (0x2U)
+#define AIPS_PACRA_WP7_SHIFT (1U)
+#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK (0x4U)
+#define AIPS_PACRA_SP7_SHIFT (2U)
+#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK (0x10U)
+#define AIPS_PACRA_TP6_SHIFT (4U)
+#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK (0x20U)
+#define AIPS_PACRA_WP6_SHIFT (5U)
+#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK (0x40U)
+#define AIPS_PACRA_SP6_SHIFT (6U)
+#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK (0x100U)
+#define AIPS_PACRA_TP5_SHIFT (8U)
+#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK (0x200U)
+#define AIPS_PACRA_WP5_SHIFT (9U)
+#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK (0x400U)
+#define AIPS_PACRA_SP5_SHIFT (10U)
+#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK (0x1000U)
+#define AIPS_PACRA_TP4_SHIFT (12U)
+#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK (0x2000U)
+#define AIPS_PACRA_WP4_SHIFT (13U)
+#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK (0x4000U)
+#define AIPS_PACRA_SP4_SHIFT (14U)
+#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK (0x10000U)
+#define AIPS_PACRA_TP3_SHIFT (16U)
+#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK (0x20000U)
+#define AIPS_PACRA_WP3_SHIFT (17U)
+#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK (0x40000U)
+#define AIPS_PACRA_SP3_SHIFT (18U)
+#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK (0x100000U)
+#define AIPS_PACRA_TP2_SHIFT (20U)
+#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK (0x200000U)
+#define AIPS_PACRA_WP2_SHIFT (21U)
+#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK (0x400000U)
+#define AIPS_PACRA_SP2_SHIFT (22U)
+#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK (0x1000000U)
+#define AIPS_PACRA_TP1_SHIFT (24U)
+#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK (0x2000000U)
+#define AIPS_PACRA_WP1_SHIFT (25U)
+#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK (0x4000000U)
+#define AIPS_PACRA_SP1_SHIFT (26U)
+#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK (0x10000000U)
+#define AIPS_PACRA_TP0_SHIFT (28U)
+#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK (0x20000000U)
+#define AIPS_PACRA_WP0_SHIFT (29U)
+#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK (0x40000000U)
+#define AIPS_PACRA_SP0_SHIFT (30U)
+#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+
+/*! @name PACRB - Peripheral Access Control Register */
+#define AIPS_PACRB_TP7_MASK (0x1U)
+#define AIPS_PACRB_TP7_SHIFT (0U)
+#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK (0x2U)
+#define AIPS_PACRB_WP7_SHIFT (1U)
+#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK (0x4U)
+#define AIPS_PACRB_SP7_SHIFT (2U)
+#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK (0x10U)
+#define AIPS_PACRB_TP6_SHIFT (4U)
+#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK (0x20U)
+#define AIPS_PACRB_WP6_SHIFT (5U)
+#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK (0x40U)
+#define AIPS_PACRB_SP6_SHIFT (6U)
+#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK (0x100U)
+#define AIPS_PACRB_TP5_SHIFT (8U)
+#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK (0x200U)
+#define AIPS_PACRB_WP5_SHIFT (9U)
+#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK (0x400U)
+#define AIPS_PACRB_SP5_SHIFT (10U)
+#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK (0x1000U)
+#define AIPS_PACRB_TP4_SHIFT (12U)
+#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK (0x2000U)
+#define AIPS_PACRB_WP4_SHIFT (13U)
+#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK (0x4000U)
+#define AIPS_PACRB_SP4_SHIFT (14U)
+#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK (0x10000U)
+#define AIPS_PACRB_TP3_SHIFT (16U)
+#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK (0x20000U)
+#define AIPS_PACRB_WP3_SHIFT (17U)
+#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK (0x40000U)
+#define AIPS_PACRB_SP3_SHIFT (18U)
+#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK (0x100000U)
+#define AIPS_PACRB_TP2_SHIFT (20U)
+#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK (0x200000U)
+#define AIPS_PACRB_WP2_SHIFT (21U)
+#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK (0x400000U)
+#define AIPS_PACRB_SP2_SHIFT (22U)
+#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK (0x1000000U)
+#define AIPS_PACRB_TP1_SHIFT (24U)
+#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK (0x2000000U)
+#define AIPS_PACRB_WP1_SHIFT (25U)
+#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK (0x4000000U)
+#define AIPS_PACRB_SP1_SHIFT (26U)
+#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK (0x10000000U)
+#define AIPS_PACRB_TP0_SHIFT (28U)
+#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK (0x20000000U)
+#define AIPS_PACRB_WP0_SHIFT (29U)
+#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK (0x40000000U)
+#define AIPS_PACRB_SP0_SHIFT (30U)
+#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
+
+/*! @name PACRC - Peripheral Access Control Register */
+#define AIPS_PACRC_TP7_MASK (0x1U)
+#define AIPS_PACRC_TP7_SHIFT (0U)
+#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK (0x2U)
+#define AIPS_PACRC_WP7_SHIFT (1U)
+#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK (0x4U)
+#define AIPS_PACRC_SP7_SHIFT (2U)
+#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK (0x10U)
+#define AIPS_PACRC_TP6_SHIFT (4U)
+#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK (0x20U)
+#define AIPS_PACRC_WP6_SHIFT (5U)
+#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK (0x40U)
+#define AIPS_PACRC_SP6_SHIFT (6U)
+#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK (0x100U)
+#define AIPS_PACRC_TP5_SHIFT (8U)
+#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK (0x200U)
+#define AIPS_PACRC_WP5_SHIFT (9U)
+#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK (0x400U)
+#define AIPS_PACRC_SP5_SHIFT (10U)
+#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK (0x1000U)
+#define AIPS_PACRC_TP4_SHIFT (12U)
+#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK (0x2000U)
+#define AIPS_PACRC_WP4_SHIFT (13U)
+#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK (0x4000U)
+#define AIPS_PACRC_SP4_SHIFT (14U)
+#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK (0x10000U)
+#define AIPS_PACRC_TP3_SHIFT (16U)
+#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK (0x20000U)
+#define AIPS_PACRC_WP3_SHIFT (17U)
+#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK (0x40000U)
+#define AIPS_PACRC_SP3_SHIFT (18U)
+#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK (0x100000U)
+#define AIPS_PACRC_TP2_SHIFT (20U)
+#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK (0x200000U)
+#define AIPS_PACRC_WP2_SHIFT (21U)
+#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK (0x400000U)
+#define AIPS_PACRC_SP2_SHIFT (22U)
+#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK (0x1000000U)
+#define AIPS_PACRC_TP1_SHIFT (24U)
+#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK (0x2000000U)
+#define AIPS_PACRC_WP1_SHIFT (25U)
+#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK (0x4000000U)
+#define AIPS_PACRC_SP1_SHIFT (26U)
+#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK (0x10000000U)
+#define AIPS_PACRC_TP0_SHIFT (28U)
+#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK (0x20000000U)
+#define AIPS_PACRC_WP0_SHIFT (29U)
+#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK (0x40000000U)
+#define AIPS_PACRC_SP0_SHIFT (30U)
+#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
+
+/*! @name PACRD - Peripheral Access Control Register */
+#define AIPS_PACRD_TP7_MASK (0x1U)
+#define AIPS_PACRD_TP7_SHIFT (0U)
+#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK (0x2U)
+#define AIPS_PACRD_WP7_SHIFT (1U)
+#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK (0x4U)
+#define AIPS_PACRD_SP7_SHIFT (2U)
+#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK (0x10U)
+#define AIPS_PACRD_TP6_SHIFT (4U)
+#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK (0x20U)
+#define AIPS_PACRD_WP6_SHIFT (5U)
+#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK (0x40U)
+#define AIPS_PACRD_SP6_SHIFT (6U)
+#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK (0x100U)
+#define AIPS_PACRD_TP5_SHIFT (8U)
+#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK (0x200U)
+#define AIPS_PACRD_WP5_SHIFT (9U)
+#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK (0x400U)
+#define AIPS_PACRD_SP5_SHIFT (10U)
+#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK (0x1000U)
+#define AIPS_PACRD_TP4_SHIFT (12U)
+#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK (0x2000U)
+#define AIPS_PACRD_WP4_SHIFT (13U)
+#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK (0x4000U)
+#define AIPS_PACRD_SP4_SHIFT (14U)
+#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK (0x10000U)
+#define AIPS_PACRD_TP3_SHIFT (16U)
+#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK (0x20000U)
+#define AIPS_PACRD_WP3_SHIFT (17U)
+#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK (0x40000U)
+#define AIPS_PACRD_SP3_SHIFT (18U)
+#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK (0x100000U)
+#define AIPS_PACRD_TP2_SHIFT (20U)
+#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK (0x200000U)
+#define AIPS_PACRD_WP2_SHIFT (21U)
+#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK (0x400000U)
+#define AIPS_PACRD_SP2_SHIFT (22U)
+#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK (0x1000000U)
+#define AIPS_PACRD_TP1_SHIFT (24U)
+#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK (0x2000000U)
+#define AIPS_PACRD_WP1_SHIFT (25U)
+#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK (0x4000000U)
+#define AIPS_PACRD_SP1_SHIFT (26U)
+#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK (0x10000000U)
+#define AIPS_PACRD_TP0_SHIFT (28U)
+#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK (0x20000000U)
+#define AIPS_PACRD_WP0_SHIFT (29U)
+#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK (0x40000000U)
+#define AIPS_PACRD_SP0_SHIFT (30U)
+#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
+
+/*! @name PACRE - Peripheral Access Control Register */
+#define AIPS_PACRE_TP7_MASK (0x1U)
+#define AIPS_PACRE_TP7_SHIFT (0U)
+#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK (0x2U)
+#define AIPS_PACRE_WP7_SHIFT (1U)
+#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK (0x4U)
+#define AIPS_PACRE_SP7_SHIFT (2U)
+#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK (0x10U)
+#define AIPS_PACRE_TP6_SHIFT (4U)
+#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK (0x20U)
+#define AIPS_PACRE_WP6_SHIFT (5U)
+#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK (0x40U)
+#define AIPS_PACRE_SP6_SHIFT (6U)
+#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK (0x100U)
+#define AIPS_PACRE_TP5_SHIFT (8U)
+#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK (0x200U)
+#define AIPS_PACRE_WP5_SHIFT (9U)
+#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK (0x400U)
+#define AIPS_PACRE_SP5_SHIFT (10U)
+#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK (0x1000U)
+#define AIPS_PACRE_TP4_SHIFT (12U)
+#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK (0x2000U)
+#define AIPS_PACRE_WP4_SHIFT (13U)
+#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK (0x4000U)
+#define AIPS_PACRE_SP4_SHIFT (14U)
+#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK (0x10000U)
+#define AIPS_PACRE_TP3_SHIFT (16U)
+#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK (0x20000U)
+#define AIPS_PACRE_WP3_SHIFT (17U)
+#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK (0x40000U)
+#define AIPS_PACRE_SP3_SHIFT (18U)
+#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK (0x100000U)
+#define AIPS_PACRE_TP2_SHIFT (20U)
+#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK (0x200000U)
+#define AIPS_PACRE_WP2_SHIFT (21U)
+#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK (0x400000U)
+#define AIPS_PACRE_SP2_SHIFT (22U)
+#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK (0x1000000U)
+#define AIPS_PACRE_TP1_SHIFT (24U)
+#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK (0x2000000U)
+#define AIPS_PACRE_WP1_SHIFT (25U)
+#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK (0x4000000U)
+#define AIPS_PACRE_SP1_SHIFT (26U)
+#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK (0x10000000U)
+#define AIPS_PACRE_TP0_SHIFT (28U)
+#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK (0x20000000U)
+#define AIPS_PACRE_WP0_SHIFT (29U)
+#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK (0x40000000U)
+#define AIPS_PACRE_SP0_SHIFT (30U)
+#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
+
+/*! @name PACRF - Peripheral Access Control Register */
+#define AIPS_PACRF_TP7_MASK (0x1U)
+#define AIPS_PACRF_TP7_SHIFT (0U)
+#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK (0x2U)
+#define AIPS_PACRF_WP7_SHIFT (1U)
+#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK (0x4U)
+#define AIPS_PACRF_SP7_SHIFT (2U)
+#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK (0x10U)
+#define AIPS_PACRF_TP6_SHIFT (4U)
+#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK (0x20U)
+#define AIPS_PACRF_WP6_SHIFT (5U)
+#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK (0x40U)
+#define AIPS_PACRF_SP6_SHIFT (6U)
+#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK (0x100U)
+#define AIPS_PACRF_TP5_SHIFT (8U)
+#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK (0x200U)
+#define AIPS_PACRF_WP5_SHIFT (9U)
+#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK (0x400U)
+#define AIPS_PACRF_SP5_SHIFT (10U)
+#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK (0x1000U)
+#define AIPS_PACRF_TP4_SHIFT (12U)
+#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK (0x2000U)
+#define AIPS_PACRF_WP4_SHIFT (13U)
+#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK (0x4000U)
+#define AIPS_PACRF_SP4_SHIFT (14U)
+#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK (0x10000U)
+#define AIPS_PACRF_TP3_SHIFT (16U)
+#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK (0x20000U)
+#define AIPS_PACRF_WP3_SHIFT (17U)
+#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK (0x40000U)
+#define AIPS_PACRF_SP3_SHIFT (18U)
+#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK (0x100000U)
+#define AIPS_PACRF_TP2_SHIFT (20U)
+#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK (0x200000U)
+#define AIPS_PACRF_WP2_SHIFT (21U)
+#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK (0x400000U)
+#define AIPS_PACRF_SP2_SHIFT (22U)
+#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK (0x1000000U)
+#define AIPS_PACRF_TP1_SHIFT (24U)
+#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK (0x2000000U)
+#define AIPS_PACRF_WP1_SHIFT (25U)
+#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK (0x4000000U)
+#define AIPS_PACRF_SP1_SHIFT (26U)
+#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK (0x10000000U)
+#define AIPS_PACRF_TP0_SHIFT (28U)
+#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK (0x20000000U)
+#define AIPS_PACRF_WP0_SHIFT (29U)
+#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK (0x40000000U)
+#define AIPS_PACRF_SP0_SHIFT (30U)
+#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
+
+/*! @name PACRG - Peripheral Access Control Register */
+#define AIPS_PACRG_TP7_MASK (0x1U)
+#define AIPS_PACRG_TP7_SHIFT (0U)
+#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK (0x2U)
+#define AIPS_PACRG_WP7_SHIFT (1U)
+#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK (0x4U)
+#define AIPS_PACRG_SP7_SHIFT (2U)
+#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK (0x10U)
+#define AIPS_PACRG_TP6_SHIFT (4U)
+#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK (0x20U)
+#define AIPS_PACRG_WP6_SHIFT (5U)
+#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK (0x40U)
+#define AIPS_PACRG_SP6_SHIFT (6U)
+#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK (0x100U)
+#define AIPS_PACRG_TP5_SHIFT (8U)
+#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK (0x200U)
+#define AIPS_PACRG_WP5_SHIFT (9U)
+#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK (0x400U)
+#define AIPS_PACRG_SP5_SHIFT (10U)
+#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK (0x1000U)
+#define AIPS_PACRG_TP4_SHIFT (12U)
+#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK (0x2000U)
+#define AIPS_PACRG_WP4_SHIFT (13U)
+#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK (0x4000U)
+#define AIPS_PACRG_SP4_SHIFT (14U)
+#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK (0x10000U)
+#define AIPS_PACRG_TP3_SHIFT (16U)
+#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK (0x20000U)
+#define AIPS_PACRG_WP3_SHIFT (17U)
+#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK (0x40000U)
+#define AIPS_PACRG_SP3_SHIFT (18U)
+#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK (0x100000U)
+#define AIPS_PACRG_TP2_SHIFT (20U)
+#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK (0x200000U)
+#define AIPS_PACRG_WP2_SHIFT (21U)
+#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK (0x400000U)
+#define AIPS_PACRG_SP2_SHIFT (22U)
+#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK (0x1000000U)
+#define AIPS_PACRG_TP1_SHIFT (24U)
+#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK (0x2000000U)
+#define AIPS_PACRG_WP1_SHIFT (25U)
+#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK (0x4000000U)
+#define AIPS_PACRG_SP1_SHIFT (26U)
+#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK (0x10000000U)
+#define AIPS_PACRG_TP0_SHIFT (28U)
+#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK (0x20000000U)
+#define AIPS_PACRG_WP0_SHIFT (29U)
+#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK (0x40000000U)
+#define AIPS_PACRG_SP0_SHIFT (30U)
+#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
+
+/*! @name PACRH - Peripheral Access Control Register */
+#define AIPS_PACRH_TP7_MASK (0x1U)
+#define AIPS_PACRH_TP7_SHIFT (0U)
+#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK (0x2U)
+#define AIPS_PACRH_WP7_SHIFT (1U)
+#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK (0x4U)
+#define AIPS_PACRH_SP7_SHIFT (2U)
+#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK (0x10U)
+#define AIPS_PACRH_TP6_SHIFT (4U)
+#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK (0x20U)
+#define AIPS_PACRH_WP6_SHIFT (5U)
+#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK (0x40U)
+#define AIPS_PACRH_SP6_SHIFT (6U)
+#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK (0x100U)
+#define AIPS_PACRH_TP5_SHIFT (8U)
+#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK (0x200U)
+#define AIPS_PACRH_WP5_SHIFT (9U)
+#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK (0x400U)
+#define AIPS_PACRH_SP5_SHIFT (10U)
+#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK (0x1000U)
+#define AIPS_PACRH_TP4_SHIFT (12U)
+#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK (0x2000U)
+#define AIPS_PACRH_WP4_SHIFT (13U)
+#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK (0x4000U)
+#define AIPS_PACRH_SP4_SHIFT (14U)
+#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK (0x10000U)
+#define AIPS_PACRH_TP3_SHIFT (16U)
+#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK (0x20000U)
+#define AIPS_PACRH_WP3_SHIFT (17U)
+#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK (0x40000U)
+#define AIPS_PACRH_SP3_SHIFT (18U)
+#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK (0x100000U)
+#define AIPS_PACRH_TP2_SHIFT (20U)
+#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK (0x200000U)
+#define AIPS_PACRH_WP2_SHIFT (21U)
+#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK (0x400000U)
+#define AIPS_PACRH_SP2_SHIFT (22U)
+#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK (0x1000000U)
+#define AIPS_PACRH_TP1_SHIFT (24U)
+#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK (0x2000000U)
+#define AIPS_PACRH_WP1_SHIFT (25U)
+#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK (0x4000000U)
+#define AIPS_PACRH_SP1_SHIFT (26U)
+#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK (0x10000000U)
+#define AIPS_PACRH_TP0_SHIFT (28U)
+#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK (0x20000000U)
+#define AIPS_PACRH_WP0_SHIFT (29U)
+#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK (0x40000000U)
+#define AIPS_PACRH_SP0_SHIFT (30U)
+#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
+
+/*! @name PACRI - Peripheral Access Control Register */
+#define AIPS_PACRI_TP7_MASK (0x1U)
+#define AIPS_PACRI_TP7_SHIFT (0U)
+#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK (0x2U)
+#define AIPS_PACRI_WP7_SHIFT (1U)
+#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK (0x4U)
+#define AIPS_PACRI_SP7_SHIFT (2U)
+#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK (0x10U)
+#define AIPS_PACRI_TP6_SHIFT (4U)
+#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK (0x20U)
+#define AIPS_PACRI_WP6_SHIFT (5U)
+#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK (0x40U)
+#define AIPS_PACRI_SP6_SHIFT (6U)
+#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK (0x100U)
+#define AIPS_PACRI_TP5_SHIFT (8U)
+#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK (0x200U)
+#define AIPS_PACRI_WP5_SHIFT (9U)
+#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK (0x400U)
+#define AIPS_PACRI_SP5_SHIFT (10U)
+#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK (0x1000U)
+#define AIPS_PACRI_TP4_SHIFT (12U)
+#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK (0x2000U)
+#define AIPS_PACRI_WP4_SHIFT (13U)
+#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK (0x4000U)
+#define AIPS_PACRI_SP4_SHIFT (14U)
+#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK (0x10000U)
+#define AIPS_PACRI_TP3_SHIFT (16U)
+#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK (0x20000U)
+#define AIPS_PACRI_WP3_SHIFT (17U)
+#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK (0x40000U)
+#define AIPS_PACRI_SP3_SHIFT (18U)
+#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK (0x100000U)
+#define AIPS_PACRI_TP2_SHIFT (20U)
+#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK (0x200000U)
+#define AIPS_PACRI_WP2_SHIFT (21U)
+#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK (0x400000U)
+#define AIPS_PACRI_SP2_SHIFT (22U)
+#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK (0x1000000U)
+#define AIPS_PACRI_TP1_SHIFT (24U)
+#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK (0x2000000U)
+#define AIPS_PACRI_WP1_SHIFT (25U)
+#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK (0x4000000U)
+#define AIPS_PACRI_SP1_SHIFT (26U)
+#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK (0x10000000U)
+#define AIPS_PACRI_TP0_SHIFT (28U)
+#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK (0x20000000U)
+#define AIPS_PACRI_WP0_SHIFT (29U)
+#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK (0x40000000U)
+#define AIPS_PACRI_SP0_SHIFT (30U)
+#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
+
+/*! @name PACRJ - Peripheral Access Control Register */
+#define AIPS_PACRJ_TP7_MASK (0x1U)
+#define AIPS_PACRJ_TP7_SHIFT (0U)
+#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK (0x2U)
+#define AIPS_PACRJ_WP7_SHIFT (1U)
+#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK (0x4U)
+#define AIPS_PACRJ_SP7_SHIFT (2U)
+#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK (0x10U)
+#define AIPS_PACRJ_TP6_SHIFT (4U)
+#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK (0x20U)
+#define AIPS_PACRJ_WP6_SHIFT (5U)
+#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK (0x40U)
+#define AIPS_PACRJ_SP6_SHIFT (6U)
+#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK (0x100U)
+#define AIPS_PACRJ_TP5_SHIFT (8U)
+#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK (0x200U)
+#define AIPS_PACRJ_WP5_SHIFT (9U)
+#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK (0x400U)
+#define AIPS_PACRJ_SP5_SHIFT (10U)
+#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK (0x1000U)
+#define AIPS_PACRJ_TP4_SHIFT (12U)
+#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK (0x2000U)
+#define AIPS_PACRJ_WP4_SHIFT (13U)
+#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK (0x4000U)
+#define AIPS_PACRJ_SP4_SHIFT (14U)
+#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK (0x10000U)
+#define AIPS_PACRJ_TP3_SHIFT (16U)
+#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK (0x20000U)
+#define AIPS_PACRJ_WP3_SHIFT (17U)
+#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK (0x40000U)
+#define AIPS_PACRJ_SP3_SHIFT (18U)
+#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK (0x100000U)
+#define AIPS_PACRJ_TP2_SHIFT (20U)
+#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK (0x200000U)
+#define AIPS_PACRJ_WP2_SHIFT (21U)
+#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK (0x400000U)
+#define AIPS_PACRJ_SP2_SHIFT (22U)
+#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK (0x1000000U)
+#define AIPS_PACRJ_TP1_SHIFT (24U)
+#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK (0x2000000U)
+#define AIPS_PACRJ_WP1_SHIFT (25U)
+#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK (0x4000000U)
+#define AIPS_PACRJ_SP1_SHIFT (26U)
+#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK (0x10000000U)
+#define AIPS_PACRJ_TP0_SHIFT (28U)
+#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK (0x20000000U)
+#define AIPS_PACRJ_WP0_SHIFT (29U)
+#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK (0x40000000U)
+#define AIPS_PACRJ_SP0_SHIFT (30U)
+#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
+
+/*! @name PACRK - Peripheral Access Control Register */
+#define AIPS_PACRK_TP7_MASK (0x1U)
+#define AIPS_PACRK_TP7_SHIFT (0U)
+#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK (0x2U)
+#define AIPS_PACRK_WP7_SHIFT (1U)
+#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK (0x4U)
+#define AIPS_PACRK_SP7_SHIFT (2U)
+#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK (0x10U)
+#define AIPS_PACRK_TP6_SHIFT (4U)
+#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK (0x20U)
+#define AIPS_PACRK_WP6_SHIFT (5U)
+#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK (0x40U)
+#define AIPS_PACRK_SP6_SHIFT (6U)
+#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK (0x100U)
+#define AIPS_PACRK_TP5_SHIFT (8U)
+#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK (0x200U)
+#define AIPS_PACRK_WP5_SHIFT (9U)
+#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK (0x400U)
+#define AIPS_PACRK_SP5_SHIFT (10U)
+#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK (0x1000U)
+#define AIPS_PACRK_TP4_SHIFT (12U)
+#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK (0x2000U)
+#define AIPS_PACRK_WP4_SHIFT (13U)
+#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK (0x4000U)
+#define AIPS_PACRK_SP4_SHIFT (14U)
+#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK (0x10000U)
+#define AIPS_PACRK_TP3_SHIFT (16U)
+#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK (0x20000U)
+#define AIPS_PACRK_WP3_SHIFT (17U)
+#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK (0x40000U)
+#define AIPS_PACRK_SP3_SHIFT (18U)
+#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK (0x100000U)
+#define AIPS_PACRK_TP2_SHIFT (20U)
+#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK (0x200000U)
+#define AIPS_PACRK_WP2_SHIFT (21U)
+#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK (0x400000U)
+#define AIPS_PACRK_SP2_SHIFT (22U)
+#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK (0x1000000U)
+#define AIPS_PACRK_TP1_SHIFT (24U)
+#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK (0x2000000U)
+#define AIPS_PACRK_WP1_SHIFT (25U)
+#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK (0x4000000U)
+#define AIPS_PACRK_SP1_SHIFT (26U)
+#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK (0x10000000U)
+#define AIPS_PACRK_TP0_SHIFT (28U)
+#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK (0x20000000U)
+#define AIPS_PACRK_WP0_SHIFT (29U)
+#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK (0x40000000U)
+#define AIPS_PACRK_SP0_SHIFT (30U)
+#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
+
+/*! @name PACRL - Peripheral Access Control Register */
+#define AIPS_PACRL_TP7_MASK (0x1U)
+#define AIPS_PACRL_TP7_SHIFT (0U)
+#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK (0x2U)
+#define AIPS_PACRL_WP7_SHIFT (1U)
+#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK (0x4U)
+#define AIPS_PACRL_SP7_SHIFT (2U)
+#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK (0x10U)
+#define AIPS_PACRL_TP6_SHIFT (4U)
+#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK (0x20U)
+#define AIPS_PACRL_WP6_SHIFT (5U)
+#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK (0x40U)
+#define AIPS_PACRL_SP6_SHIFT (6U)
+#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK (0x100U)
+#define AIPS_PACRL_TP5_SHIFT (8U)
+#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK (0x200U)
+#define AIPS_PACRL_WP5_SHIFT (9U)
+#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK (0x400U)
+#define AIPS_PACRL_SP5_SHIFT (10U)
+#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK (0x1000U)
+#define AIPS_PACRL_TP4_SHIFT (12U)
+#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK (0x2000U)
+#define AIPS_PACRL_WP4_SHIFT (13U)
+#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK (0x4000U)
+#define AIPS_PACRL_SP4_SHIFT (14U)
+#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK (0x10000U)
+#define AIPS_PACRL_TP3_SHIFT (16U)
+#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK (0x20000U)
+#define AIPS_PACRL_WP3_SHIFT (17U)
+#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK (0x40000U)
+#define AIPS_PACRL_SP3_SHIFT (18U)
+#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK (0x100000U)
+#define AIPS_PACRL_TP2_SHIFT (20U)
+#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK (0x200000U)
+#define AIPS_PACRL_WP2_SHIFT (21U)
+#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK (0x400000U)
+#define AIPS_PACRL_SP2_SHIFT (22U)
+#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK (0x1000000U)
+#define AIPS_PACRL_TP1_SHIFT (24U)
+#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK (0x2000000U)
+#define AIPS_PACRL_WP1_SHIFT (25U)
+#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK (0x4000000U)
+#define AIPS_PACRL_SP1_SHIFT (26U)
+#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK (0x10000000U)
+#define AIPS_PACRL_TP0_SHIFT (28U)
+#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK (0x20000000U)
+#define AIPS_PACRL_WP0_SHIFT (29U)
+#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK (0x40000000U)
+#define AIPS_PACRL_SP0_SHIFT (30U)
+#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
+
+/*! @name PACRM - Peripheral Access Control Register */
+#define AIPS_PACRM_TP7_MASK (0x1U)
+#define AIPS_PACRM_TP7_SHIFT (0U)
+#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK (0x2U)
+#define AIPS_PACRM_WP7_SHIFT (1U)
+#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK (0x4U)
+#define AIPS_PACRM_SP7_SHIFT (2U)
+#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK (0x10U)
+#define AIPS_PACRM_TP6_SHIFT (4U)
+#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK (0x20U)
+#define AIPS_PACRM_WP6_SHIFT (5U)
+#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK (0x40U)
+#define AIPS_PACRM_SP6_SHIFT (6U)
+#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK (0x100U)
+#define AIPS_PACRM_TP5_SHIFT (8U)
+#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK (0x200U)
+#define AIPS_PACRM_WP5_SHIFT (9U)
+#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK (0x400U)
+#define AIPS_PACRM_SP5_SHIFT (10U)
+#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK (0x1000U)
+#define AIPS_PACRM_TP4_SHIFT (12U)
+#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK (0x2000U)
+#define AIPS_PACRM_WP4_SHIFT (13U)
+#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK (0x4000U)
+#define AIPS_PACRM_SP4_SHIFT (14U)
+#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK (0x10000U)
+#define AIPS_PACRM_TP3_SHIFT (16U)
+#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK (0x20000U)
+#define AIPS_PACRM_WP3_SHIFT (17U)
+#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK (0x40000U)
+#define AIPS_PACRM_SP3_SHIFT (18U)
+#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK (0x100000U)
+#define AIPS_PACRM_TP2_SHIFT (20U)
+#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK (0x200000U)
+#define AIPS_PACRM_WP2_SHIFT (21U)
+#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK (0x400000U)
+#define AIPS_PACRM_SP2_SHIFT (22U)
+#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK (0x1000000U)
+#define AIPS_PACRM_TP1_SHIFT (24U)
+#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK (0x2000000U)
+#define AIPS_PACRM_WP1_SHIFT (25U)
+#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK (0x4000000U)
+#define AIPS_PACRM_SP1_SHIFT (26U)
+#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK (0x10000000U)
+#define AIPS_PACRM_TP0_SHIFT (28U)
+#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK (0x20000000U)
+#define AIPS_PACRM_WP0_SHIFT (29U)
+#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK (0x40000000U)
+#define AIPS_PACRM_SP0_SHIFT (30U)
+#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
+
+/*! @name PACRN - Peripheral Access Control Register */
+#define AIPS_PACRN_TP7_MASK (0x1U)
+#define AIPS_PACRN_TP7_SHIFT (0U)
+#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK (0x2U)
+#define AIPS_PACRN_WP7_SHIFT (1U)
+#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK (0x4U)
+#define AIPS_PACRN_SP7_SHIFT (2U)
+#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK (0x10U)
+#define AIPS_PACRN_TP6_SHIFT (4U)
+#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK (0x20U)
+#define AIPS_PACRN_WP6_SHIFT (5U)
+#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK (0x40U)
+#define AIPS_PACRN_SP6_SHIFT (6U)
+#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK (0x100U)
+#define AIPS_PACRN_TP5_SHIFT (8U)
+#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK (0x200U)
+#define AIPS_PACRN_WP5_SHIFT (9U)
+#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK (0x400U)
+#define AIPS_PACRN_SP5_SHIFT (10U)
+#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK (0x1000U)
+#define AIPS_PACRN_TP4_SHIFT (12U)
+#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK (0x2000U)
+#define AIPS_PACRN_WP4_SHIFT (13U)
+#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK (0x4000U)
+#define AIPS_PACRN_SP4_SHIFT (14U)
+#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK (0x10000U)
+#define AIPS_PACRN_TP3_SHIFT (16U)
+#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK (0x20000U)
+#define AIPS_PACRN_WP3_SHIFT (17U)
+#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK (0x40000U)
+#define AIPS_PACRN_SP3_SHIFT (18U)
+#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK (0x100000U)
+#define AIPS_PACRN_TP2_SHIFT (20U)
+#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK (0x200000U)
+#define AIPS_PACRN_WP2_SHIFT (21U)
+#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK (0x400000U)
+#define AIPS_PACRN_SP2_SHIFT (22U)
+#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK (0x1000000U)
+#define AIPS_PACRN_TP1_SHIFT (24U)
+#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK (0x2000000U)
+#define AIPS_PACRN_WP1_SHIFT (25U)
+#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK (0x4000000U)
+#define AIPS_PACRN_SP1_SHIFT (26U)
+#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK (0x10000000U)
+#define AIPS_PACRN_TP0_SHIFT (28U)
+#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK (0x20000000U)
+#define AIPS_PACRN_WP0_SHIFT (29U)
+#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK (0x40000000U)
+#define AIPS_PACRN_SP0_SHIFT (30U)
+#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
+
+/*! @name PACRO - Peripheral Access Control Register */
+#define AIPS_PACRO_TP7_MASK (0x1U)
+#define AIPS_PACRO_TP7_SHIFT (0U)
+#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK (0x2U)
+#define AIPS_PACRO_WP7_SHIFT (1U)
+#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK (0x4U)
+#define AIPS_PACRO_SP7_SHIFT (2U)
+#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK (0x10U)
+#define AIPS_PACRO_TP6_SHIFT (4U)
+#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK (0x20U)
+#define AIPS_PACRO_WP6_SHIFT (5U)
+#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK (0x40U)
+#define AIPS_PACRO_SP6_SHIFT (6U)
+#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK (0x100U)
+#define AIPS_PACRO_TP5_SHIFT (8U)
+#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK (0x200U)
+#define AIPS_PACRO_WP5_SHIFT (9U)
+#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK (0x400U)
+#define AIPS_PACRO_SP5_SHIFT (10U)
+#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK (0x1000U)
+#define AIPS_PACRO_TP4_SHIFT (12U)
+#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK (0x2000U)
+#define AIPS_PACRO_WP4_SHIFT (13U)
+#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK (0x4000U)
+#define AIPS_PACRO_SP4_SHIFT (14U)
+#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK (0x10000U)
+#define AIPS_PACRO_TP3_SHIFT (16U)
+#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK (0x20000U)
+#define AIPS_PACRO_WP3_SHIFT (17U)
+#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK (0x40000U)
+#define AIPS_PACRO_SP3_SHIFT (18U)
+#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK (0x100000U)
+#define AIPS_PACRO_TP2_SHIFT (20U)
+#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK (0x200000U)
+#define AIPS_PACRO_WP2_SHIFT (21U)
+#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK (0x400000U)
+#define AIPS_PACRO_SP2_SHIFT (22U)
+#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK (0x1000000U)
+#define AIPS_PACRO_TP1_SHIFT (24U)
+#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK (0x2000000U)
+#define AIPS_PACRO_WP1_SHIFT (25U)
+#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK (0x4000000U)
+#define AIPS_PACRO_SP1_SHIFT (26U)
+#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK (0x10000000U)
+#define AIPS_PACRO_TP0_SHIFT (28U)
+#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK (0x20000000U)
+#define AIPS_PACRO_WP0_SHIFT (29U)
+#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK (0x40000000U)
+#define AIPS_PACRO_SP0_SHIFT (30U)
+#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
+
+/*! @name PACRP - Peripheral Access Control Register */
+#define AIPS_PACRP_TP7_MASK (0x1U)
+#define AIPS_PACRP_TP7_SHIFT (0U)
+#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK (0x2U)
+#define AIPS_PACRP_WP7_SHIFT (1U)
+#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK (0x4U)
+#define AIPS_PACRP_SP7_SHIFT (2U)
+#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK (0x10U)
+#define AIPS_PACRP_TP6_SHIFT (4U)
+#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK (0x20U)
+#define AIPS_PACRP_WP6_SHIFT (5U)
+#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK (0x40U)
+#define AIPS_PACRP_SP6_SHIFT (6U)
+#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK (0x100U)
+#define AIPS_PACRP_TP5_SHIFT (8U)
+#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK (0x200U)
+#define AIPS_PACRP_WP5_SHIFT (9U)
+#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK (0x400U)
+#define AIPS_PACRP_SP5_SHIFT (10U)
+#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK (0x1000U)
+#define AIPS_PACRP_TP4_SHIFT (12U)
+#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK (0x2000U)
+#define AIPS_PACRP_WP4_SHIFT (13U)
+#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK (0x4000U)
+#define AIPS_PACRP_SP4_SHIFT (14U)
+#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK (0x10000U)
+#define AIPS_PACRP_TP3_SHIFT (16U)
+#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK (0x20000U)
+#define AIPS_PACRP_WP3_SHIFT (17U)
+#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK (0x40000U)
+#define AIPS_PACRP_SP3_SHIFT (18U)
+#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK (0x100000U)
+#define AIPS_PACRP_TP2_SHIFT (20U)
+#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK (0x200000U)
+#define AIPS_PACRP_WP2_SHIFT (21U)
+#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK (0x400000U)
+#define AIPS_PACRP_SP2_SHIFT (22U)
+#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK (0x1000000U)
+#define AIPS_PACRP_TP1_SHIFT (24U)
+#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK (0x2000000U)
+#define AIPS_PACRP_WP1_SHIFT (25U)
+#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK (0x4000000U)
+#define AIPS_PACRP_SP1_SHIFT (26U)
+#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK (0x10000000U)
+#define AIPS_PACRP_TP0_SHIFT (28U)
+#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK (0x20000000U)
+#define AIPS_PACRP_WP0_SHIFT (29U)
+#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK (0x40000000U)
+#define AIPS_PACRP_SP0_SHIFT (30U)
+#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
+
/*!
* @}
@@ -2348,70 +1896,15 @@ typedef struct {
#define AIPS0_BASE (0x40000000u)
/** Peripheral AIPS0 base pointer */
#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
-#define AIPS0_BASE_PTR (AIPS0)
/** Peripheral AIPS1 base address */
#define AIPS1_BASE (0x40080000u)
/** Peripheral AIPS1 base pointer */
#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
-#define AIPS1_BASE_PTR (AIPS1)
/** Array initializer of AIPS peripheral base addresses */
#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
/** Array initializer of AIPS peripheral base pointers */
#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
-/* ----------------------------------------------------------------------------
- -- AIPS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
- * @{
- */
-
-
-/* AIPS - Register instance definitions */
-/* AIPS0 */
-#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
-#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
-#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
-#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
-#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
-#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
-#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
-#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
-#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
-#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
-#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
-#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
-#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
-#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
-#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
-#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
-#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
-/* AIPS1 */
-#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
-#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
-#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
-#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
-#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
-#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
-#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
-#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
-#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
-#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
-#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
-#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
-#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
-#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
-#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
-#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
-#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
-
-/*!
- * @}
- */ /* end of group AIPS_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group AIPS_Peripheral_Access_Layer */
@@ -2444,33 +1937,7 @@ typedef struct {
__IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
uint8_t RESERVED_4[252];
__IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
-} AXBS_Type, *AXBS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- AXBS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
- * @{
- */
-
-
-/* AXBS - Register accessors */
-#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
-#define AXBS_PRS_COUNT 5
-#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
-#define AXBS_CRS_COUNT 5
-#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
-#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
-#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
-#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
-#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
-
-/*!
- * @}
- */ /* end of group AXBS_Register_Accessor_Macros */
-
+} AXBS_Type;
/* ----------------------------------------------------------------------------
-- AXBS Register Masks
@@ -2481,73 +1948,71 @@ typedef struct {
* @{
*/
-/* PRS Bit Fields */
-#define AXBS_PRS_M0_MASK 0x7u
-#define AXBS_PRS_M0_SHIFT 0
-#define AXBS_PRS_M0_WIDTH 3
-#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
-#define AXBS_PRS_M1_MASK 0x70u
-#define AXBS_PRS_M1_SHIFT 4
-#define AXBS_PRS_M1_WIDTH 3
-#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
-#define AXBS_PRS_M2_MASK 0x700u
-#define AXBS_PRS_M2_SHIFT 8
-#define AXBS_PRS_M2_WIDTH 3
-#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
-#define AXBS_PRS_M4_MASK 0x70000u
-#define AXBS_PRS_M4_SHIFT 16
-#define AXBS_PRS_M4_WIDTH 3
-#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
-#define AXBS_PRS_M5_MASK 0x700000u
-#define AXBS_PRS_M5_SHIFT 20
-#define AXBS_PRS_M5_WIDTH 3
-#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
-/* CRS Bit Fields */
-#define AXBS_CRS_PARK_MASK 0x7u
-#define AXBS_CRS_PARK_SHIFT 0
-#define AXBS_CRS_PARK_WIDTH 3
-#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
-#define AXBS_CRS_PCTL_MASK 0x30u
-#define AXBS_CRS_PCTL_SHIFT 4
-#define AXBS_CRS_PCTL_WIDTH 2
-#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
-#define AXBS_CRS_ARB_MASK 0x300u
-#define AXBS_CRS_ARB_SHIFT 8
-#define AXBS_CRS_ARB_WIDTH 2
-#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
-#define AXBS_CRS_HLP_MASK 0x40000000u
-#define AXBS_CRS_HLP_SHIFT 30
-#define AXBS_CRS_HLP_WIDTH 1
-#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_HLP_SHIFT))&AXBS_CRS_HLP_MASK)
-#define AXBS_CRS_RO_MASK 0x80000000u
-#define AXBS_CRS_RO_SHIFT 31
-#define AXBS_CRS_RO_WIDTH 1
-#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_RO_SHIFT))&AXBS_CRS_RO_MASK)
-/* MGPCR0 Bit Fields */
-#define AXBS_MGPCR0_AULB_MASK 0x7u
-#define AXBS_MGPCR0_AULB_SHIFT 0
-#define AXBS_MGPCR0_AULB_WIDTH 3
-#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
-/* MGPCR1 Bit Fields */
-#define AXBS_MGPCR1_AULB_MASK 0x7u
-#define AXBS_MGPCR1_AULB_SHIFT 0
-#define AXBS_MGPCR1_AULB_WIDTH 3
-#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
-/* MGPCR2 Bit Fields */
-#define AXBS_MGPCR2_AULB_MASK 0x7u
-#define AXBS_MGPCR2_AULB_SHIFT 0
-#define AXBS_MGPCR2_AULB_WIDTH 3
-#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
-/* MGPCR4 Bit Fields */
-#define AXBS_MGPCR4_AULB_MASK 0x7u
-#define AXBS_MGPCR4_AULB_SHIFT 0
-#define AXBS_MGPCR4_AULB_WIDTH 3
-#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
-/* MGPCR5 Bit Fields */
-#define AXBS_MGPCR5_AULB_MASK 0x7u
-#define AXBS_MGPCR5_AULB_SHIFT 0
-#define AXBS_MGPCR5_AULB_WIDTH 3
-#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+/*! @name PRS - Priority Registers Slave */
+#define AXBS_PRS_M0_MASK (0x7U)
+#define AXBS_PRS_M0_SHIFT (0U)
+#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK (0x70U)
+#define AXBS_PRS_M1_SHIFT (4U)
+#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK (0x700U)
+#define AXBS_PRS_M2_SHIFT (8U)
+#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M4_MASK (0x70000U)
+#define AXBS_PRS_M4_SHIFT (16U)
+#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK (0x700000U)
+#define AXBS_PRS_M5_SHIFT (20U)
+#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+
+/* The count of AXBS_PRS */
+#define AXBS_PRS_COUNT (5U)
+
+/*! @name CRS - Control Register */
+#define AXBS_CRS_PARK_MASK (0x7U)
+#define AXBS_CRS_PARK_SHIFT (0U)
+#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK (0x30U)
+#define AXBS_CRS_PCTL_SHIFT (4U)
+#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK (0x300U)
+#define AXBS_CRS_ARB_SHIFT (8U)
+#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK (0x40000000U)
+#define AXBS_CRS_HLP_SHIFT (30U)
+#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK (0x80000000U)
+#define AXBS_CRS_RO_SHIFT (31U)
+#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
+
+/* The count of AXBS_CRS */
+#define AXBS_CRS_COUNT (5U)
+
+/*! @name MGPCR0 - Master General Purpose Control Register */
+#define AXBS_MGPCR0_AULB_MASK (0x7U)
+#define AXBS_MGPCR0_AULB_SHIFT (0U)
+#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+
+/*! @name MGPCR1 - Master General Purpose Control Register */
+#define AXBS_MGPCR1_AULB_MASK (0x7U)
+#define AXBS_MGPCR1_AULB_SHIFT (0U)
+#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+
+/*! @name MGPCR2 - Master General Purpose Control Register */
+#define AXBS_MGPCR2_AULB_MASK (0x7U)
+#define AXBS_MGPCR2_AULB_SHIFT (0U)
+#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+
+/*! @name MGPCR4 - Master General Purpose Control Register */
+#define AXBS_MGPCR4_AULB_MASK (0x7U)
+#define AXBS_MGPCR4_AULB_SHIFT (0U)
+#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+
+/*! @name MGPCR5 - Master General Purpose Control Register */
+#define AXBS_MGPCR5_AULB_MASK (0x7U)
+#define AXBS_MGPCR5_AULB_SHIFT (0U)
+#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+
/*!
* @}
@@ -2559,49 +2024,11 @@ typedef struct {
#define AXBS_BASE (0x40004000u)
/** Peripheral AXBS base pointer */
#define AXBS ((AXBS_Type *)AXBS_BASE)
-#define AXBS_BASE_PTR (AXBS)
/** Array initializer of AXBS peripheral base addresses */
#define AXBS_BASE_ADDRS { AXBS_BASE }
/** Array initializer of AXBS peripheral base pointers */
#define AXBS_BASE_PTRS { AXBS }
-/* ----------------------------------------------------------------------------
- -- AXBS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
- * @{
- */
-
-
-/* AXBS - Register instance definitions */
-/* AXBS */
-#define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
-#define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
-#define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
-#define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
-#define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
-#define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
-#define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
-#define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
-#define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
-#define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
-#define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
-#define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
-#define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
-#define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
-#define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
-
-/* AXBS - Register array accessors */
-#define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
-#define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
-
-/*!
- * @}
- */ /* end of group AXBS_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group AXBS_Peripheral_Access_Layer */
@@ -2646,49 +2073,7 @@ typedef struct {
} MB[16];
uint8_t RESERVED_5[1792];
__IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
-} CAN_Type, *CAN_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CAN - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
- * @{
- */
-
-
-/* CAN - Register accessors */
-#define CAN_MCR_REG(base) ((base)->MCR)
-#define CAN_CTRL1_REG(base) ((base)->CTRL1)
-#define CAN_TIMER_REG(base) ((base)->TIMER)
-#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
-#define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
-#define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
-#define CAN_ECR_REG(base) ((base)->ECR)
-#define CAN_ESR1_REG(base) ((base)->ESR1)
-#define CAN_IMASK1_REG(base) ((base)->IMASK1)
-#define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
-#define CAN_CTRL2_REG(base) ((base)->CTRL2)
-#define CAN_ESR2_REG(base) ((base)->ESR2)
-#define CAN_CRCR_REG(base) ((base)->CRCR)
-#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
-#define CAN_RXFIR_REG(base) ((base)->RXFIR)
-#define CAN_CS_REG(base,index) ((base)->MB[index].CS)
-#define CAN_CS_COUNT 16
-#define CAN_ID_REG(base,index) ((base)->MB[index].ID)
-#define CAN_ID_COUNT 16
-#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
-#define CAN_WORD0_COUNT 16
-#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
-#define CAN_WORD1_COUNT 16
-#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
-#define CAN_RXIMR_COUNT 16
-
-/*!
- * @}
- */ /* end of group CAN_Register_Accessor_Macros */
-
+} CAN_Type;
/* ----------------------------------------------------------------------------
-- CAN Register Masks
@@ -2699,414 +2084,352 @@ typedef struct {
* @{
*/
-/* MCR Bit Fields */
-#define CAN_MCR_MAXMB_MASK 0x7Fu
-#define CAN_MCR_MAXMB_SHIFT 0
-#define CAN_MCR_MAXMB_WIDTH 7
-#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
-#define CAN_MCR_IDAM_MASK 0x300u
-#define CAN_MCR_IDAM_SHIFT 8
-#define CAN_MCR_IDAM_WIDTH 2
-#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
-#define CAN_MCR_AEN_MASK 0x1000u
-#define CAN_MCR_AEN_SHIFT 12
-#define CAN_MCR_AEN_WIDTH 1
-#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
-#define CAN_MCR_LPRIOEN_MASK 0x2000u
-#define CAN_MCR_LPRIOEN_SHIFT 13
-#define CAN_MCR_LPRIOEN_WIDTH 1
-#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
-#define CAN_MCR_IRMQ_MASK 0x10000u
-#define CAN_MCR_IRMQ_SHIFT 16
-#define CAN_MCR_IRMQ_WIDTH 1
-#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
-#define CAN_MCR_SRXDIS_MASK 0x20000u
-#define CAN_MCR_SRXDIS_SHIFT 17
-#define CAN_MCR_SRXDIS_WIDTH 1
-#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
-#define CAN_MCR_WAKSRC_MASK 0x80000u
-#define CAN_MCR_WAKSRC_SHIFT 19
-#define CAN_MCR_WAKSRC_WIDTH 1
-#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
-#define CAN_MCR_LPMACK_MASK 0x100000u
-#define CAN_MCR_LPMACK_SHIFT 20
-#define CAN_MCR_LPMACK_WIDTH 1
-#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
-#define CAN_MCR_WRNEN_MASK 0x200000u
-#define CAN_MCR_WRNEN_SHIFT 21
-#define CAN_MCR_WRNEN_WIDTH 1
-#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
-#define CAN_MCR_SLFWAK_MASK 0x400000u
-#define CAN_MCR_SLFWAK_SHIFT 22
-#define CAN_MCR_SLFWAK_WIDTH 1
-#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
-#define CAN_MCR_SUPV_MASK 0x800000u
-#define CAN_MCR_SUPV_SHIFT 23
-#define CAN_MCR_SUPV_WIDTH 1
-#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
-#define CAN_MCR_FRZACK_MASK 0x1000000u
-#define CAN_MCR_FRZACK_SHIFT 24
-#define CAN_MCR_FRZACK_WIDTH 1
-#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
-#define CAN_MCR_SOFTRST_MASK 0x2000000u
-#define CAN_MCR_SOFTRST_SHIFT 25
-#define CAN_MCR_SOFTRST_WIDTH 1
-#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
-#define CAN_MCR_WAKMSK_MASK 0x4000000u
-#define CAN_MCR_WAKMSK_SHIFT 26
-#define CAN_MCR_WAKMSK_WIDTH 1
-#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
-#define CAN_MCR_NOTRDY_MASK 0x8000000u
-#define CAN_MCR_NOTRDY_SHIFT 27
-#define CAN_MCR_NOTRDY_WIDTH 1
-#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
-#define CAN_MCR_HALT_MASK 0x10000000u
-#define CAN_MCR_HALT_SHIFT 28
-#define CAN_MCR_HALT_WIDTH 1
-#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
-#define CAN_MCR_RFEN_MASK 0x20000000u
-#define CAN_MCR_RFEN_SHIFT 29
-#define CAN_MCR_RFEN_WIDTH 1
-#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
-#define CAN_MCR_FRZ_MASK 0x40000000u
-#define CAN_MCR_FRZ_SHIFT 30
-#define CAN_MCR_FRZ_WIDTH 1
-#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
-#define CAN_MCR_MDIS_MASK 0x80000000u
-#define CAN_MCR_MDIS_SHIFT 31
-#define CAN_MCR_MDIS_WIDTH 1
-#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
-/* CTRL1 Bit Fields */
-#define CAN_CTRL1_PROPSEG_MASK 0x7u
-#define CAN_CTRL1_PROPSEG_SHIFT 0
-#define CAN_CTRL1_PROPSEG_WIDTH 3
-#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
-#define CAN_CTRL1_LOM_MASK 0x8u
-#define CAN_CTRL1_LOM_SHIFT 3
-#define CAN_CTRL1_LOM_WIDTH 1
-#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
-#define CAN_CTRL1_LBUF_MASK 0x10u
-#define CAN_CTRL1_LBUF_SHIFT 4
-#define CAN_CTRL1_LBUF_WIDTH 1
-#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
-#define CAN_CTRL1_TSYN_MASK 0x20u
-#define CAN_CTRL1_TSYN_SHIFT 5
-#define CAN_CTRL1_TSYN_WIDTH 1
-#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
-#define CAN_CTRL1_BOFFREC_MASK 0x40u
-#define CAN_CTRL1_BOFFREC_SHIFT 6
-#define CAN_CTRL1_BOFFREC_WIDTH 1
-#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
-#define CAN_CTRL1_SMP_MASK 0x80u
-#define CAN_CTRL1_SMP_SHIFT 7
-#define CAN_CTRL1_SMP_WIDTH 1
-#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
-#define CAN_CTRL1_RWRNMSK_MASK 0x400u
-#define CAN_CTRL1_RWRNMSK_SHIFT 10
-#define CAN_CTRL1_RWRNMSK_WIDTH 1
-#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
-#define CAN_CTRL1_TWRNMSK_MASK 0x800u
-#define CAN_CTRL1_TWRNMSK_SHIFT 11
-#define CAN_CTRL1_TWRNMSK_WIDTH 1
-#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
-#define CAN_CTRL1_LPB_MASK 0x1000u
-#define CAN_CTRL1_LPB_SHIFT 12
-#define CAN_CTRL1_LPB_WIDTH 1
-#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
-#define CAN_CTRL1_CLKSRC_MASK 0x2000u
-#define CAN_CTRL1_CLKSRC_SHIFT 13
-#define CAN_CTRL1_CLKSRC_WIDTH 1
-#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
-#define CAN_CTRL1_ERRMSK_MASK 0x4000u
-#define CAN_CTRL1_ERRMSK_SHIFT 14
-#define CAN_CTRL1_ERRMSK_WIDTH 1
-#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
-#define CAN_CTRL1_BOFFMSK_MASK 0x8000u
-#define CAN_CTRL1_BOFFMSK_SHIFT 15
-#define CAN_CTRL1_BOFFMSK_WIDTH 1
-#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
-#define CAN_CTRL1_PSEG2_MASK 0x70000u
-#define CAN_CTRL1_PSEG2_SHIFT 16
-#define CAN_CTRL1_PSEG2_WIDTH 3
-#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
-#define CAN_CTRL1_PSEG1_MASK 0x380000u
-#define CAN_CTRL1_PSEG1_SHIFT 19
-#define CAN_CTRL1_PSEG1_WIDTH 3
-#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
-#define CAN_CTRL1_RJW_MASK 0xC00000u
-#define CAN_CTRL1_RJW_SHIFT 22
-#define CAN_CTRL1_RJW_WIDTH 2
-#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
-#define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
-#define CAN_CTRL1_PRESDIV_SHIFT 24
-#define CAN_CTRL1_PRESDIV_WIDTH 8
-#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
-/* TIMER Bit Fields */
-#define CAN_TIMER_TIMER_MASK 0xFFFFu
-#define CAN_TIMER_TIMER_SHIFT 0
-#define CAN_TIMER_TIMER_WIDTH 16
-#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
-/* RXMGMASK Bit Fields */
-#define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
-#define CAN_RXMGMASK_MG_SHIFT 0
-#define CAN_RXMGMASK_MG_WIDTH 32
-#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
-/* RX14MASK Bit Fields */
-#define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
-#define CAN_RX14MASK_RX14M_SHIFT 0
-#define CAN_RX14MASK_RX14M_WIDTH 32
-#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
-/* RX15MASK Bit Fields */
-#define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
-#define CAN_RX15MASK_RX15M_SHIFT 0
-#define CAN_RX15MASK_RX15M_WIDTH 32
-#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
-/* ECR Bit Fields */
-#define CAN_ECR_TXERRCNT_MASK 0xFFu
-#define CAN_ECR_TXERRCNT_SHIFT 0
-#define CAN_ECR_TXERRCNT_WIDTH 8
-#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
-#define CAN_ECR_RXERRCNT_MASK 0xFF00u
-#define CAN_ECR_RXERRCNT_SHIFT 8
-#define CAN_ECR_RXERRCNT_WIDTH 8
-#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
-/* ESR1 Bit Fields */
-#define CAN_ESR1_WAKINT_MASK 0x1u
-#define CAN_ESR1_WAKINT_SHIFT 0
-#define CAN_ESR1_WAKINT_WIDTH 1
-#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
-#define CAN_ESR1_ERRINT_MASK 0x2u
-#define CAN_ESR1_ERRINT_SHIFT 1
-#define CAN_ESR1_ERRINT_WIDTH 1
-#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
-#define CAN_ESR1_BOFFINT_MASK 0x4u
-#define CAN_ESR1_BOFFINT_SHIFT 2
-#define CAN_ESR1_BOFFINT_WIDTH 1
-#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
-#define CAN_ESR1_RX_MASK 0x8u
-#define CAN_ESR1_RX_SHIFT 3
-#define CAN_ESR1_RX_WIDTH 1
-#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
-#define CAN_ESR1_FLTCONF_MASK 0x30u
-#define CAN_ESR1_FLTCONF_SHIFT 4
-#define CAN_ESR1_FLTCONF_WIDTH 2
-#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
-#define CAN_ESR1_TX_MASK 0x40u
-#define CAN_ESR1_TX_SHIFT 6
-#define CAN_ESR1_TX_WIDTH 1
-#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
-#define CAN_ESR1_IDLE_MASK 0x80u
-#define CAN_ESR1_IDLE_SHIFT 7
-#define CAN_ESR1_IDLE_WIDTH 1
-#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
-#define CAN_ESR1_RXWRN_MASK 0x100u
-#define CAN_ESR1_RXWRN_SHIFT 8
-#define CAN_ESR1_RXWRN_WIDTH 1
-#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
-#define CAN_ESR1_TXWRN_MASK 0x200u
-#define CAN_ESR1_TXWRN_SHIFT 9
-#define CAN_ESR1_TXWRN_WIDTH 1
-#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
-#define CAN_ESR1_STFERR_MASK 0x400u
-#define CAN_ESR1_STFERR_SHIFT 10
-#define CAN_ESR1_STFERR_WIDTH 1
-#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
-#define CAN_ESR1_FRMERR_MASK 0x800u
-#define CAN_ESR1_FRMERR_SHIFT 11
-#define CAN_ESR1_FRMERR_WIDTH 1
-#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
-#define CAN_ESR1_CRCERR_MASK 0x1000u
-#define CAN_ESR1_CRCERR_SHIFT 12
-#define CAN_ESR1_CRCERR_WIDTH 1
-#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
-#define CAN_ESR1_ACKERR_MASK 0x2000u
-#define CAN_ESR1_ACKERR_SHIFT 13
-#define CAN_ESR1_ACKERR_WIDTH 1
-#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
-#define CAN_ESR1_BIT0ERR_MASK 0x4000u
-#define CAN_ESR1_BIT0ERR_SHIFT 14
-#define CAN_ESR1_BIT0ERR_WIDTH 1
-#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
-#define CAN_ESR1_BIT1ERR_MASK 0x8000u
-#define CAN_ESR1_BIT1ERR_SHIFT 15
-#define CAN_ESR1_BIT1ERR_WIDTH 1
-#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
-#define CAN_ESR1_RWRNINT_MASK 0x10000u
-#define CAN_ESR1_RWRNINT_SHIFT 16
-#define CAN_ESR1_RWRNINT_WIDTH 1
-#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
-#define CAN_ESR1_TWRNINT_MASK 0x20000u
-#define CAN_ESR1_TWRNINT_SHIFT 17
-#define CAN_ESR1_TWRNINT_WIDTH 1
-#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
-#define CAN_ESR1_SYNCH_MASK 0x40000u
-#define CAN_ESR1_SYNCH_SHIFT 18
-#define CAN_ESR1_SYNCH_WIDTH 1
-#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
-/* IMASK1 Bit Fields */
-#define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
-#define CAN_IMASK1_BUFLM_SHIFT 0
-#define CAN_IMASK1_BUFLM_WIDTH 32
-#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
-/* IFLAG1 Bit Fields */
-#define CAN_IFLAG1_BUF0I_MASK 0x1u
-#define CAN_IFLAG1_BUF0I_SHIFT 0
-#define CAN_IFLAG1_BUF0I_WIDTH 1
-#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
-#define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
-#define CAN_IFLAG1_BUF4TO1I_SHIFT 1
-#define CAN_IFLAG1_BUF4TO1I_WIDTH 4
-#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
-#define CAN_IFLAG1_BUF5I_MASK 0x20u
-#define CAN_IFLAG1_BUF5I_SHIFT 5
-#define CAN_IFLAG1_BUF5I_WIDTH 1
-#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
-#define CAN_IFLAG1_BUF6I_MASK 0x40u
-#define CAN_IFLAG1_BUF6I_SHIFT 6
-#define CAN_IFLAG1_BUF6I_WIDTH 1
-#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
-#define CAN_IFLAG1_BUF7I_MASK 0x80u
-#define CAN_IFLAG1_BUF7I_SHIFT 7
-#define CAN_IFLAG1_BUF7I_WIDTH 1
-#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
-#define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
-#define CAN_IFLAG1_BUF31TO8I_SHIFT 8
-#define CAN_IFLAG1_BUF31TO8I_WIDTH 24
-#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
-/* CTRL2 Bit Fields */
-#define CAN_CTRL2_EACEN_MASK 0x10000u
-#define CAN_CTRL2_EACEN_SHIFT 16
-#define CAN_CTRL2_EACEN_WIDTH 1
-#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
-#define CAN_CTRL2_RRS_MASK 0x20000u
-#define CAN_CTRL2_RRS_SHIFT 17
-#define CAN_CTRL2_RRS_WIDTH 1
-#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
-#define CAN_CTRL2_MRP_MASK 0x40000u
-#define CAN_CTRL2_MRP_SHIFT 18
-#define CAN_CTRL2_MRP_WIDTH 1
-#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
-#define CAN_CTRL2_TASD_MASK 0xF80000u
-#define CAN_CTRL2_TASD_SHIFT 19
-#define CAN_CTRL2_TASD_WIDTH 5
-#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
-#define CAN_CTRL2_RFFN_MASK 0xF000000u
-#define CAN_CTRL2_RFFN_SHIFT 24
-#define CAN_CTRL2_RFFN_WIDTH 4
-#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
-#define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
-#define CAN_CTRL2_WRMFRZ_SHIFT 28
-#define CAN_CTRL2_WRMFRZ_WIDTH 1
-#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_WRMFRZ_SHIFT))&CAN_CTRL2_WRMFRZ_MASK)
-/* ESR2 Bit Fields */
-#define CAN_ESR2_IMB_MASK 0x2000u
-#define CAN_ESR2_IMB_SHIFT 13
-#define CAN_ESR2_IMB_WIDTH 1
-#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
-#define CAN_ESR2_VPS_MASK 0x4000u
-#define CAN_ESR2_VPS_SHIFT 14
-#define CAN_ESR2_VPS_WIDTH 1
-#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
-#define CAN_ESR2_LPTM_MASK 0x7F0000u
-#define CAN_ESR2_LPTM_SHIFT 16
-#define CAN_ESR2_LPTM_WIDTH 7
-#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
-/* CRCR Bit Fields */
-#define CAN_CRCR_TXCRC_MASK 0x7FFFu
-#define CAN_CRCR_TXCRC_SHIFT 0
-#define CAN_CRCR_TXCRC_WIDTH 15
-#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
-#define CAN_CRCR_MBCRC_MASK 0x7F0000u
-#define CAN_CRCR_MBCRC_SHIFT 16
-#define CAN_CRCR_MBCRC_WIDTH 7
-#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
-/* RXFGMASK Bit Fields */
-#define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
-#define CAN_RXFGMASK_FGM_SHIFT 0
-#define CAN_RXFGMASK_FGM_WIDTH 32
-#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
-/* RXFIR Bit Fields */
-#define CAN_RXFIR_IDHIT_MASK 0x1FFu
-#define CAN_RXFIR_IDHIT_SHIFT 0
-#define CAN_RXFIR_IDHIT_WIDTH 9
-#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
-/* CS Bit Fields */
-#define CAN_CS_TIME_STAMP_MASK 0xFFFFu
-#define CAN_CS_TIME_STAMP_SHIFT 0
-#define CAN_CS_TIME_STAMP_WIDTH 16
-#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
-#define CAN_CS_DLC_MASK 0xF0000u
-#define CAN_CS_DLC_SHIFT 16
-#define CAN_CS_DLC_WIDTH 4
-#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
-#define CAN_CS_RTR_MASK 0x100000u
-#define CAN_CS_RTR_SHIFT 20
-#define CAN_CS_RTR_WIDTH 1
-#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
-#define CAN_CS_IDE_MASK 0x200000u
-#define CAN_CS_IDE_SHIFT 21
-#define CAN_CS_IDE_WIDTH 1
-#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
-#define CAN_CS_SRR_MASK 0x400000u
-#define CAN_CS_SRR_SHIFT 22
-#define CAN_CS_SRR_WIDTH 1
-#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
-#define CAN_CS_CODE_MASK 0xF000000u
-#define CAN_CS_CODE_SHIFT 24
-#define CAN_CS_CODE_WIDTH 4
-#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
-/* ID Bit Fields */
-#define CAN_ID_EXT_MASK 0x3FFFFu
-#define CAN_ID_EXT_SHIFT 0
-#define CAN_ID_EXT_WIDTH 18
-#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
-#define CAN_ID_STD_MASK 0x1FFC0000u
-#define CAN_ID_STD_SHIFT 18
-#define CAN_ID_STD_WIDTH 11
-#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
-#define CAN_ID_PRIO_MASK 0xE0000000u
-#define CAN_ID_PRIO_SHIFT 29
-#define CAN_ID_PRIO_WIDTH 3
-#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
-/* WORD0 Bit Fields */
-#define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
-#define CAN_WORD0_DATA_BYTE_3_SHIFT 0
-#define CAN_WORD0_DATA_BYTE_3_WIDTH 8
-#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
-#define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
-#define CAN_WORD0_DATA_BYTE_2_SHIFT 8
-#define CAN_WORD0_DATA_BYTE_2_WIDTH 8
-#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
-#define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
-#define CAN_WORD0_DATA_BYTE_1_SHIFT 16
-#define CAN_WORD0_DATA_BYTE_1_WIDTH 8
-#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
-#define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
-#define CAN_WORD0_DATA_BYTE_0_SHIFT 24
-#define CAN_WORD0_DATA_BYTE_0_WIDTH 8
-#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
-/* WORD1 Bit Fields */
-#define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
-#define CAN_WORD1_DATA_BYTE_7_SHIFT 0
-#define CAN_WORD1_DATA_BYTE_7_WIDTH 8
-#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
-#define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
-#define CAN_WORD1_DATA_BYTE_6_SHIFT 8
-#define CAN_WORD1_DATA_BYTE_6_WIDTH 8
-#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
-#define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
-#define CAN_WORD1_DATA_BYTE_5_SHIFT 16
-#define CAN_WORD1_DATA_BYTE_5_WIDTH 8
-#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
-#define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
-#define CAN_WORD1_DATA_BYTE_4_SHIFT 24
-#define CAN_WORD1_DATA_BYTE_4_WIDTH 8
-#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
-/* RXIMR Bit Fields */
-#define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
-#define CAN_RXIMR_MI_SHIFT 0
-#define CAN_RXIMR_MI_WIDTH 32
-#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+/*! @name MCR - Module Configuration Register */
+#define CAN_MCR_MAXMB_MASK (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT (0U)
+#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK (0x300U)
+#define CAN_MCR_IDAM_SHIFT (8U)
+#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK (0x1000U)
+#define CAN_MCR_AEN_SHIFT (12U)
+#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK (0x2000U)
+#define CAN_MCR_LPRIOEN_SHIFT (13U)
+#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK (0x10000U)
+#define CAN_MCR_IRMQ_SHIFT (16U)
+#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK (0x20000U)
+#define CAN_MCR_SRXDIS_SHIFT (17U)
+#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK (0x80000U)
+#define CAN_MCR_WAKSRC_SHIFT (19U)
+#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK (0x100000U)
+#define CAN_MCR_LPMACK_SHIFT (20U)
+#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK (0x200000U)
+#define CAN_MCR_WRNEN_SHIFT (21U)
+#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK (0x400000U)
+#define CAN_MCR_SLFWAK_SHIFT (22U)
+#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK (0x800000U)
+#define CAN_MCR_SUPV_SHIFT (23U)
+#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK (0x1000000U)
+#define CAN_MCR_FRZACK_SHIFT (24U)
+#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK (0x2000000U)
+#define CAN_MCR_SOFTRST_SHIFT (25U)
+#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK (0x4000000U)
+#define CAN_MCR_WAKMSK_SHIFT (26U)
+#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK (0x8000000U)
+#define CAN_MCR_NOTRDY_SHIFT (27U)
+#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK (0x10000000U)
+#define CAN_MCR_HALT_SHIFT (28U)
+#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK (0x20000000U)
+#define CAN_MCR_RFEN_SHIFT (29U)
+#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK (0x40000000U)
+#define CAN_MCR_FRZ_SHIFT (30U)
+#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK (0x80000000U)
+#define CAN_MCR_MDIS_SHIFT (31U)
+#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+
+/*! @name CTRL1 - Control 1 register */
+#define CAN_CTRL1_PROPSEG_MASK (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT (0U)
+#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK (0x8U)
+#define CAN_CTRL1_LOM_SHIFT (3U)
+#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK (0x10U)
+#define CAN_CTRL1_LBUF_SHIFT (4U)
+#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK (0x20U)
+#define CAN_CTRL1_TSYN_SHIFT (5U)
+#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK (0x40U)
+#define CAN_CTRL1_BOFFREC_SHIFT (6U)
+#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK (0x80U)
+#define CAN_CTRL1_SMP_SHIFT (7U)
+#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
+#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
+#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
+#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
+#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK (0x1000U)
+#define CAN_CTRL1_LPB_SHIFT (12U)
+#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
+#define CAN_CTRL1_CLKSRC_SHIFT (13U)
+#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
+#define CAN_CTRL1_ERRMSK_SHIFT (14U)
+#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
+#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
+#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT (16U)
+#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT (19U)
+#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT (22U)
+#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT (24U)
+#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+
+/*! @name TIMER - Free Running Timer */
+#define CAN_TIMER_TIMER_MASK (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT (0U)
+#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+
+/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
+#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
+#define CAN_RXMGMASK_MG_SHIFT (0U)
+#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+
+/*! @name RX14MASK - Rx 14 Mask register */
+#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
+#define CAN_RX14MASK_RX14M_SHIFT (0U)
+#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+
+/*! @name RX15MASK - Rx 15 Mask register */
+#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
+#define CAN_RX15MASK_RX15M_SHIFT (0U)
+#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+
+/*! @name ECR - Error Counter */
+#define CAN_ECR_TXERRCNT_MASK (0xFFU)
+#define CAN_ECR_TXERRCNT_SHIFT (0U)
+#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
+#define CAN_ECR_RXERRCNT_SHIFT (8U)
+#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+
+/*! @name ESR1 - Error and Status 1 register */
+#define CAN_ESR1_WAKINT_MASK (0x1U)
+#define CAN_ESR1_WAKINT_SHIFT (0U)
+#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK (0x2U)
+#define CAN_ESR1_ERRINT_SHIFT (1U)
+#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK (0x4U)
+#define CAN_ESR1_BOFFINT_SHIFT (2U)
+#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK (0x8U)
+#define CAN_ESR1_RX_SHIFT (3U)
+#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT (4U)
+#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK (0x40U)
+#define CAN_ESR1_TX_SHIFT (6U)
+#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK (0x80U)
+#define CAN_ESR1_IDLE_SHIFT (7U)
+#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK (0x100U)
+#define CAN_ESR1_RXWRN_SHIFT (8U)
+#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK (0x200U)
+#define CAN_ESR1_TXWRN_SHIFT (9U)
+#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK (0x400U)
+#define CAN_ESR1_STFERR_SHIFT (10U)
+#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK (0x800U)
+#define CAN_ESR1_FRMERR_SHIFT (11U)
+#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK (0x1000U)
+#define CAN_ESR1_CRCERR_SHIFT (12U)
+#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK (0x2000U)
+#define CAN_ESR1_ACKERR_SHIFT (13U)
+#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
+#define CAN_ESR1_BIT0ERR_SHIFT (14U)
+#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
+#define CAN_ESR1_BIT1ERR_SHIFT (15U)
+#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK (0x10000U)
+#define CAN_ESR1_RWRNINT_SHIFT (16U)
+#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK (0x20000U)
+#define CAN_ESR1_TWRNINT_SHIFT (17U)
+#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK (0x40000U)
+#define CAN_ESR1_SYNCH_SHIFT (18U)
+#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+
+/*! @name IMASK1 - Interrupt Masks 1 register */
+#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
+#define CAN_IMASK1_BUFLM_SHIFT (0U)
+#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
+
+/*! @name IFLAG1 - Interrupt Flags 1 register */
+#define CAN_IFLAG1_BUF0I_MASK (0x1U)
+#define CAN_IFLAG1_BUF0I_SHIFT (0U)
+#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
+#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
+#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK (0x20U)
+#define CAN_IFLAG1_BUF5I_SHIFT (5U)
+#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK (0x40U)
+#define CAN_IFLAG1_BUF6I_SHIFT (6U)
+#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK (0x80U)
+#define CAN_IFLAG1_BUF7I_SHIFT (7U)
+#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
+#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+
+/*! @name CTRL2 - Control 2 register */
+#define CAN_CTRL2_EACEN_MASK (0x10000U)
+#define CAN_CTRL2_EACEN_SHIFT (16U)
+#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK (0x20000U)
+#define CAN_CTRL2_RRS_SHIFT (17U)
+#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK (0x40000U)
+#define CAN_CTRL2_MRP_SHIFT (18U)
+#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT (19U)
+#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT (24U)
+#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
+#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
+#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
+
+/*! @name ESR2 - Error and Status 2 register */
+#define CAN_ESR2_IMB_MASK (0x2000U)
+#define CAN_ESR2_IMB_SHIFT (13U)
+#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK (0x4000U)
+#define CAN_ESR2_VPS_SHIFT (14U)
+#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT (16U)
+#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+
+/*! @name CRCR - CRC Register */
+#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT (0U)
+#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT (16U)
+#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+
+/*! @name RXFGMASK - Rx FIFO Global Mask register */
+#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
+#define CAN_RXFGMASK_FGM_SHIFT (0U)
+#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+
+/*! @name RXFIR - Rx FIFO Information Register */
+#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT (0U)
+#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
+#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT (0U)
+#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK (0xF0000U)
+#define CAN_CS_DLC_SHIFT (16U)
+#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK (0x100000U)
+#define CAN_CS_RTR_SHIFT (20U)
+#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK (0x200000U)
+#define CAN_CS_IDE_SHIFT (21U)
+#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK (0x400000U)
+#define CAN_CS_SRR_SHIFT (22U)
+#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK (0xF000000U)
+#define CAN_CS_CODE_SHIFT (24U)
+#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT (16U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
+#define CAN_ID_EXT_MASK (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT (0U)
+#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT (18U)
+#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT (29U)
+#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT (16U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
+#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
+#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
+#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
+#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
+#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT (16U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
+#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
+#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
+#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
+#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
+#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT (16U)
+
+/*! @name RXIMR - Rx Individual Mask Registers */
+#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
+#define CAN_RXIMR_MI_SHIFT (0U)
+#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+
+/* The count of CAN_RXIMR */
+#define CAN_RXIMR_COUNT (16U)
+
/*!
* @}
@@ -3118,7 +2441,6 @@ typedef struct {
#define CAN0_BASE (0x40024000u)
/** Peripheral CAN0 base pointer */
#define CAN0 ((CAN_Type *)CAN0_BASE)
-#define CAN0_BASE_PTR (CAN0)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS { CAN0_BASE }
/** Array initializer of CAN peripheral base pointers */
@@ -3131,126 +2453,6 @@ typedef struct {
#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
-/* ----------------------------------------------------------------------------
- -- CAN - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
- * @{
- */
-
-
-/* CAN - Register instance definitions */
-/* CAN0 */
-#define CAN0_MCR CAN_MCR_REG(CAN0)
-#define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
-#define CAN0_TIMER CAN_TIMER_REG(CAN0)
-#define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
-#define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
-#define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
-#define CAN0_ECR CAN_ECR_REG(CAN0)
-#define CAN0_ESR1 CAN_ESR1_REG(CAN0)
-#define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
-#define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
-#define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
-#define CAN0_ESR2 CAN_ESR2_REG(CAN0)
-#define CAN0_CRCR CAN_CRCR_REG(CAN0)
-#define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
-#define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
-#define CAN0_CS0 CAN_CS_REG(CAN0,0)
-#define CAN0_ID0 CAN_ID_REG(CAN0,0)
-#define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
-#define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
-#define CAN0_CS1 CAN_CS_REG(CAN0,1)
-#define CAN0_ID1 CAN_ID_REG(CAN0,1)
-#define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
-#define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
-#define CAN0_CS2 CAN_CS_REG(CAN0,2)
-#define CAN0_ID2 CAN_ID_REG(CAN0,2)
-#define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
-#define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
-#define CAN0_CS3 CAN_CS_REG(CAN0,3)
-#define CAN0_ID3 CAN_ID_REG(CAN0,3)
-#define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
-#define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
-#define CAN0_CS4 CAN_CS_REG(CAN0,4)
-#define CAN0_ID4 CAN_ID_REG(CAN0,4)
-#define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
-#define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
-#define CAN0_CS5 CAN_CS_REG(CAN0,5)
-#define CAN0_ID5 CAN_ID_REG(CAN0,5)
-#define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
-#define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
-#define CAN0_CS6 CAN_CS_REG(CAN0,6)
-#define CAN0_ID6 CAN_ID_REG(CAN0,6)
-#define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
-#define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
-#define CAN0_CS7 CAN_CS_REG(CAN0,7)
-#define CAN0_ID7 CAN_ID_REG(CAN0,7)
-#define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
-#define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
-#define CAN0_CS8 CAN_CS_REG(CAN0,8)
-#define CAN0_ID8 CAN_ID_REG(CAN0,8)
-#define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
-#define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
-#define CAN0_CS9 CAN_CS_REG(CAN0,9)
-#define CAN0_ID9 CAN_ID_REG(CAN0,9)
-#define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
-#define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
-#define CAN0_CS10 CAN_CS_REG(CAN0,10)
-#define CAN0_ID10 CAN_ID_REG(CAN0,10)
-#define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
-#define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
-#define CAN0_CS11 CAN_CS_REG(CAN0,11)
-#define CAN0_ID11 CAN_ID_REG(CAN0,11)
-#define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
-#define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
-#define CAN0_CS12 CAN_CS_REG(CAN0,12)
-#define CAN0_ID12 CAN_ID_REG(CAN0,12)
-#define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
-#define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
-#define CAN0_CS13 CAN_CS_REG(CAN0,13)
-#define CAN0_ID13 CAN_ID_REG(CAN0,13)
-#define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
-#define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
-#define CAN0_CS14 CAN_CS_REG(CAN0,14)
-#define CAN0_ID14 CAN_ID_REG(CAN0,14)
-#define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
-#define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
-#define CAN0_CS15 CAN_CS_REG(CAN0,15)
-#define CAN0_ID15 CAN_ID_REG(CAN0,15)
-#define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
-#define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
-#define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
-#define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
-#define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
-#define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
-#define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
-#define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
-#define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
-#define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
-#define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
-#define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
-#define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
-#define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
-#define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
-#define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
-#define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
-#define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
-
-/* CAN - Register array accessors */
-#define CAN0_CS(index) CAN_CS_REG(CAN0,index)
-#define CAN0_ID(index) CAN_ID_REG(CAN0,index)
-#define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
-#define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
-#define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
-
-/*!
- * @}
- */ /* end of group CAN_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CAN_Peripheral_Access_Layer */
@@ -3273,30 +2475,7 @@ typedef struct {
__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
__IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
__IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type, *CMP_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register accessors */
-#define CMP_CR0_REG(base) ((base)->CR0)
-#define CMP_CR1_REG(base) ((base)->CR1)
-#define CMP_FPR_REG(base) ((base)->FPR)
-#define CMP_SCR_REG(base) ((base)->SCR)
-#define CMP_DACCR_REG(base) ((base)->DACCR)
-#define CMP_MUXCR_REG(base) ((base)->MUXCR)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
+} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
@@ -3307,100 +2486,84 @@ typedef struct {
* @{
*/
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR_WIDTH 2
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT_WIDTH 3
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_EN_WIDTH 1
-#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_OPE_WIDTH 1
-#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_COS_WIDTH 1
-#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_INV_WIDTH 1
-#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_PMODE_WIDTH 1
-#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_WE_WIDTH 1
-#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-#define CMP_CR1_SE_WIDTH 1
-#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER_WIDTH 8
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_COUT_WIDTH 1
-#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFF_WIDTH 1
-#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_CFR_WIDTH 1
-#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IEF_WIDTH 1
-#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_IER_WIDTH 1
-#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-#define CMP_SCR_DMAEN_WIDTH 1
-#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL_WIDTH 6
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_VRSEL_WIDTH 1
-#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-#define CMP_DACCR_DACEN_WIDTH 1
-#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL_WIDTH 3
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL_WIDTH 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-#define CMP_MUXCR_PSTM_MASK 0x80u
-#define CMP_MUXCR_PSTM_SHIFT 7
-#define CMP_MUXCR_PSTM_WIDTH 1
-#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSTM_SHIFT))&CMP_MUXCR_PSTM_MASK)
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK (0x80U)
+#define CMP_MUXCR_PSTM_SHIFT (7U)
+#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+
/*!
* @}
@@ -3412,17 +2575,14 @@ typedef struct {
#define CMP0_BASE (0x40073000u)
/** Peripheral CMP0 base pointer */
#define CMP0 ((CMP_Type *)CMP0_BASE)
-#define CMP0_BASE_PTR (CMP0)
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x40073008u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
-#define CMP1_BASE_PTR (CMP1)
/** Peripheral CMP2 base address */
#define CMP2_BASE (0x40073010u)
/** Peripheral CMP2 base pointer */
#define CMP2 ((CMP_Type *)CMP2_BASE)
-#define CMP2_BASE_PTR (CMP2)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/** Array initializer of CMP peripheral base pointers */
@@ -3430,44 +2590,6 @@ typedef struct {
/** Interrupt vectors for the CMP peripheral type */
#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
-/* ----------------------------------------------------------------------------
- -- CMP - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
- * @{
- */
-
-
-/* CMP - Register instance definitions */
-/* CMP0 */
-#define CMP0_CR0 CMP_CR0_REG(CMP0)
-#define CMP0_CR1 CMP_CR1_REG(CMP0)
-#define CMP0_FPR CMP_FPR_REG(CMP0)
-#define CMP0_SCR CMP_SCR_REG(CMP0)
-#define CMP0_DACCR CMP_DACCR_REG(CMP0)
-#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
-/* CMP1 */
-#define CMP1_CR0 CMP_CR0_REG(CMP1)
-#define CMP1_CR1 CMP_CR1_REG(CMP1)
-#define CMP1_FPR CMP_FPR_REG(CMP1)
-#define CMP1_SCR CMP_SCR_REG(CMP1)
-#define CMP1_DACCR CMP_DACCR_REG(CMP1)
-#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
-/* CMP2 */
-#define CMP2_CR0 CMP_CR0_REG(CMP2)
-#define CMP2_CR1 CMP_CR1_REG(CMP2)
-#define CMP2_FPR CMP_FPR_REG(CMP2)
-#define CMP2_SCR CMP_SCR_REG(CMP2)
-#define CMP2_DACCR CMP_DACCR_REG(CMP2)
-#define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
-
-/*!
- * @}
- */ /* end of group CMP_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
@@ -3496,36 +2618,7 @@ typedef struct {
__IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
__IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
-} CMT_Type, *CMT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CMT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
- * @{
- */
-
-
-/* CMT - Register accessors */
-#define CMT_CGH1_REG(base) ((base)->CGH1)
-#define CMT_CGL1_REG(base) ((base)->CGL1)
-#define CMT_CGH2_REG(base) ((base)->CGH2)
-#define CMT_CGL2_REG(base) ((base)->CGL2)
-#define CMT_OC_REG(base) ((base)->OC)
-#define CMT_MSC_REG(base) ((base)->MSC)
-#define CMT_CMD1_REG(base) ((base)->CMD1)
-#define CMT_CMD2_REG(base) ((base)->CMD2)
-#define CMT_CMD3_REG(base) ((base)->CMD3)
-#define CMT_CMD4_REG(base) ((base)->CMD4)
-#define CMT_PPS_REG(base) ((base)->PPS)
-#define CMT_DMA_REG(base) ((base)->DMA)
-
-/*!
- * @}
- */ /* end of group CMT_Register_Accessor_Macros */
-
+} CMT_Type;
/* ----------------------------------------------------------------------------
-- CMT Register Masks
@@ -3536,98 +2629,90 @@ typedef struct {
* @{
*/
-/* CGH1 Bit Fields */
-#define CMT_CGH1_PH_MASK 0xFFu
-#define CMT_CGH1_PH_SHIFT 0
-#define CMT_CGH1_PH_WIDTH 8
-#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
-/* CGL1 Bit Fields */
-#define CMT_CGL1_PL_MASK 0xFFu
-#define CMT_CGL1_PL_SHIFT 0
-#define CMT_CGL1_PL_WIDTH 8
-#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
-/* CGH2 Bit Fields */
-#define CMT_CGH2_SH_MASK 0xFFu
-#define CMT_CGH2_SH_SHIFT 0
-#define CMT_CGH2_SH_WIDTH 8
-#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
-/* CGL2 Bit Fields */
-#define CMT_CGL2_SL_MASK 0xFFu
-#define CMT_CGL2_SL_SHIFT 0
-#define CMT_CGL2_SL_WIDTH 8
-#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
-/* OC Bit Fields */
-#define CMT_OC_IROPEN_MASK 0x20u
-#define CMT_OC_IROPEN_SHIFT 5
-#define CMT_OC_IROPEN_WIDTH 1
-#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROPEN_SHIFT))&CMT_OC_IROPEN_MASK)
-#define CMT_OC_CMTPOL_MASK 0x40u
-#define CMT_OC_CMTPOL_SHIFT 6
-#define CMT_OC_CMTPOL_WIDTH 1
-#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x))<<CMT_OC_CMTPOL_SHIFT))&CMT_OC_CMTPOL_MASK)
-#define CMT_OC_IROL_MASK 0x80u
-#define CMT_OC_IROL_SHIFT 7
-#define CMT_OC_IROL_WIDTH 1
-#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x))<<CMT_OC_IROL_SHIFT))&CMT_OC_IROL_MASK)
-/* MSC Bit Fields */
-#define CMT_MSC_MCGEN_MASK 0x1u
-#define CMT_MSC_MCGEN_SHIFT 0
-#define CMT_MSC_MCGEN_WIDTH 1
-#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_MCGEN_SHIFT))&CMT_MSC_MCGEN_MASK)
-#define CMT_MSC_EOCIE_MASK 0x2u
-#define CMT_MSC_EOCIE_SHIFT 1
-#define CMT_MSC_EOCIE_WIDTH 1
-#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCIE_SHIFT))&CMT_MSC_EOCIE_MASK)
-#define CMT_MSC_FSK_MASK 0x4u
-#define CMT_MSC_FSK_SHIFT 2
-#define CMT_MSC_FSK_WIDTH 1
-#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_FSK_SHIFT))&CMT_MSC_FSK_MASK)
-#define CMT_MSC_BASE_MASK 0x8u
-#define CMT_MSC_BASE_SHIFT 3
-#define CMT_MSC_BASE_WIDTH 1
-#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_BASE_SHIFT))&CMT_MSC_BASE_MASK)
-#define CMT_MSC_EXSPC_MASK 0x10u
-#define CMT_MSC_EXSPC_SHIFT 4
-#define CMT_MSC_EXSPC_WIDTH 1
-#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EXSPC_SHIFT))&CMT_MSC_EXSPC_MASK)
-#define CMT_MSC_CMTDIV_MASK 0x60u
-#define CMT_MSC_CMTDIV_SHIFT 5
-#define CMT_MSC_CMTDIV_WIDTH 2
-#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
-#define CMT_MSC_EOCF_MASK 0x80u
-#define CMT_MSC_EOCF_SHIFT 7
-#define CMT_MSC_EOCF_WIDTH 1
-#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_EOCF_SHIFT))&CMT_MSC_EOCF_MASK)
-/* CMD1 Bit Fields */
-#define CMT_CMD1_MB_MASK 0xFFu
-#define CMT_CMD1_MB_SHIFT 0
-#define CMT_CMD1_MB_WIDTH 8
-#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
-/* CMD2 Bit Fields */
-#define CMT_CMD2_MB_MASK 0xFFu
-#define CMT_CMD2_MB_SHIFT 0
-#define CMT_CMD2_MB_WIDTH 8
-#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
-/* CMD3 Bit Fields */
-#define CMT_CMD3_SB_MASK 0xFFu
-#define CMT_CMD3_SB_SHIFT 0
-#define CMT_CMD3_SB_WIDTH 8
-#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
-/* CMD4 Bit Fields */
-#define CMT_CMD4_SB_MASK 0xFFu
-#define CMT_CMD4_SB_SHIFT 0
-#define CMT_CMD4_SB_WIDTH 8
-#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
-/* PPS Bit Fields */
-#define CMT_PPS_PPSDIV_MASK 0xFu
-#define CMT_PPS_PPSDIV_SHIFT 0
-#define CMT_PPS_PPSDIV_WIDTH 4
-#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
-/* DMA Bit Fields */
-#define CMT_DMA_DMA_MASK 0x1u
-#define CMT_DMA_DMA_SHIFT 0
-#define CMT_DMA_DMA_WIDTH 1
-#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x))<<CMT_DMA_DMA_SHIFT))&CMT_DMA_DMA_MASK)
+/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
+#define CMT_CGH1_PH_MASK (0xFFU)
+#define CMT_CGH1_PH_SHIFT (0U)
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+
+/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
+#define CMT_CGL1_PL_MASK (0xFFU)
+#define CMT_CGL1_PL_SHIFT (0U)
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+
+/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
+#define CMT_CGH2_SH_MASK (0xFFU)
+#define CMT_CGH2_SH_SHIFT (0U)
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+
+/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
+#define CMT_CGL2_SL_MASK (0xFFU)
+#define CMT_CGL2_SL_SHIFT (0U)
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+
+/*! @name OC - CMT Output Control Register */
+#define CMT_OC_IROPEN_MASK (0x20U)
+#define CMT_OC_IROPEN_SHIFT (5U)
+#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK (0x40U)
+#define CMT_OC_CMTPOL_SHIFT (6U)
+#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK (0x80U)
+#define CMT_OC_IROL_SHIFT (7U)
+#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
+
+/*! @name MSC - CMT Modulator Status and Control Register */
+#define CMT_MSC_MCGEN_MASK (0x1U)
+#define CMT_MSC_MCGEN_SHIFT (0U)
+#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK (0x2U)
+#define CMT_MSC_EOCIE_SHIFT (1U)
+#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK (0x4U)
+#define CMT_MSC_FSK_SHIFT (2U)
+#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK (0x8U)
+#define CMT_MSC_BASE_SHIFT (3U)
+#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK (0x10U)
+#define CMT_MSC_EXSPC_SHIFT (4U)
+#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK (0x60U)
+#define CMT_MSC_CMTDIV_SHIFT (5U)
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK (0x80U)
+#define CMT_MSC_EOCF_SHIFT (7U)
+#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
+
+/*! @name CMD1 - CMT Modulator Data Register Mark High */
+#define CMT_CMD1_MB_MASK (0xFFU)
+#define CMT_CMD1_MB_SHIFT (0U)
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+
+/*! @name CMD2 - CMT Modulator Data Register Mark Low */
+#define CMT_CMD2_MB_MASK (0xFFU)
+#define CMT_CMD2_MB_SHIFT (0U)
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+
+/*! @name CMD3 - CMT Modulator Data Register Space High */
+#define CMT_CMD3_SB_MASK (0xFFU)
+#define CMT_CMD3_SB_SHIFT (0U)
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+
+/*! @name CMD4 - CMT Modulator Data Register Space Low */
+#define CMT_CMD4_SB_MASK (0xFFU)
+#define CMT_CMD4_SB_SHIFT (0U)
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+
+/*! @name PPS - CMT Primary Prescaler Register */
+#define CMT_PPS_PPSDIV_MASK (0xFU)
+#define CMT_PPS_PPSDIV_SHIFT (0U)
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+
+/*! @name DMA - CMT Direct Memory Access Register */
+#define CMT_DMA_DMA_MASK (0x1U)
+#define CMT_DMA_DMA_SHIFT (0U)
+#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
+
/*!
* @}
@@ -3639,7 +2724,6 @@ typedef struct {
#define CMT_BASE (0x40062000u)
/** Peripheral CMT base pointer */
#define CMT ((CMT_Type *)CMT_BASE)
-#define CMT_BASE_PTR (CMT)
/** Array initializer of CMT peripheral base addresses */
#define CMT_BASE_ADDRS { CMT_BASE }
/** Array initializer of CMT peripheral base pointers */
@@ -3647,36 +2731,6 @@ typedef struct {
/** Interrupt vectors for the CMT peripheral type */
#define CMT_IRQS { CMT_IRQn }
-/* ----------------------------------------------------------------------------
- -- CMT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
- * @{
- */
-
-
-/* CMT - Register instance definitions */
-/* CMT */
-#define CMT_CGH1 CMT_CGH1_REG(CMT)
-#define CMT_CGL1 CMT_CGL1_REG(CMT)
-#define CMT_CGH2 CMT_CGH2_REG(CMT)
-#define CMT_CGL2 CMT_CGL2_REG(CMT)
-#define CMT_OC CMT_OC_REG(CMT)
-#define CMT_MSC CMT_MSC_REG(CMT)
-#define CMT_CMD1 CMT_CMD1_REG(CMT)
-#define CMT_CMD2 CMT_CMD2_REG(CMT)
-#define CMT_CMD3 CMT_CMD3_REG(CMT)
-#define CMT_CMD4 CMT_CMD4_REG(CMT)
-#define CMT_PPS CMT_PPS_REG(CMT)
-#define CMT_DMA CMT_DMA_REG(CMT)
-
-/*!
- * @}
- */ /* end of group CMT_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CMT_Peripheral_Access_Layer */
@@ -3726,40 +2780,7 @@ typedef struct {
__IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
} CTRL_ACCESS8BIT;
};
-} CRC_Type, *CRC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register accessors */
-#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
-#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
-#define CRC_DATA_REG(base) ((base)->DATA)
-#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
-#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
-#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
-#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
-#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
-#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
-#define CRC_GPOLY_REG(base) ((base)->GPOLY)
-#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
-#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
-#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
-#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
-#define CRC_CTRL_REG(base) ((base)->CTRL)
-#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
+} CRC_Type;
/* ----------------------------------------------------------------------------
-- CRC Register Masks
@@ -3770,134 +2791,122 @@ typedef struct {
* @{
*/
-/* DATAL Bit Fields */
-#define CRC_DATAL_DATAL_MASK 0xFFFFu
-#define CRC_DATAL_DATAL_SHIFT 0
-#define CRC_DATAL_DATAL_WIDTH 16
-#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
-/* DATAH Bit Fields */
-#define CRC_DATAH_DATAH_MASK 0xFFFFu
-#define CRC_DATAH_DATAH_SHIFT 0
-#define CRC_DATAH_DATAH_WIDTH 16
-#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
-/* DATA Bit Fields */
-#define CRC_DATA_LL_MASK 0xFFu
-#define CRC_DATA_LL_SHIFT 0
-#define CRC_DATA_LL_WIDTH 8
-#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
-#define CRC_DATA_LU_MASK 0xFF00u
-#define CRC_DATA_LU_SHIFT 8
-#define CRC_DATA_LU_WIDTH 8
-#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
-#define CRC_DATA_HL_MASK 0xFF0000u
-#define CRC_DATA_HL_SHIFT 16
-#define CRC_DATA_HL_WIDTH 8
-#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
-#define CRC_DATA_HU_MASK 0xFF000000u
-#define CRC_DATA_HU_SHIFT 24
-#define CRC_DATA_HU_WIDTH 8
-#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
-/* DATALL Bit Fields */
-#define CRC_DATALL_DATALL_MASK 0xFFu
-#define CRC_DATALL_DATALL_SHIFT 0
-#define CRC_DATALL_DATALL_WIDTH 8
-#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
-/* DATALU Bit Fields */
-#define CRC_DATALU_DATALU_MASK 0xFFu
-#define CRC_DATALU_DATALU_SHIFT 0
-#define CRC_DATALU_DATALU_WIDTH 8
-#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
-/* DATAHL Bit Fields */
-#define CRC_DATAHL_DATAHL_MASK 0xFFu
-#define CRC_DATAHL_DATAHL_SHIFT 0
-#define CRC_DATAHL_DATAHL_WIDTH 8
-#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
-/* DATAHU Bit Fields */
-#define CRC_DATAHU_DATAHU_MASK 0xFFu
-#define CRC_DATAHU_DATAHU_SHIFT 0
-#define CRC_DATAHU_DATAHU_WIDTH 8
-#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
-/* GPOLYL Bit Fields */
-#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
-#define CRC_GPOLYL_GPOLYL_SHIFT 0
-#define CRC_GPOLYL_GPOLYL_WIDTH 16
-#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
-/* GPOLYH Bit Fields */
-#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
-#define CRC_GPOLYH_GPOLYH_SHIFT 0
-#define CRC_GPOLYH_GPOLYH_WIDTH 16
-#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
-/* GPOLY Bit Fields */
-#define CRC_GPOLY_LOW_MASK 0xFFFFu
-#define CRC_GPOLY_LOW_SHIFT 0
-#define CRC_GPOLY_LOW_WIDTH 16
-#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
-#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
-#define CRC_GPOLY_HIGH_SHIFT 16
-#define CRC_GPOLY_HIGH_WIDTH 16
-#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
-/* GPOLYLL Bit Fields */
-#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
-#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
-#define CRC_GPOLYLL_GPOLYLL_WIDTH 8
-#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
-/* GPOLYLU Bit Fields */
-#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
-#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
-#define CRC_GPOLYLU_GPOLYLU_WIDTH 8
-#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
-/* GPOLYHL Bit Fields */
-#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
-#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
-#define CRC_GPOLYHL_GPOLYHL_WIDTH 8
-#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
-/* GPOLYHU Bit Fields */
-#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
-#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
-#define CRC_GPOLYHU_GPOLYHU_WIDTH 8
-#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
-/* CTRL Bit Fields */
-#define CRC_CTRL_TCRC_MASK 0x1000000u
-#define CRC_CTRL_TCRC_SHIFT 24
-#define CRC_CTRL_TCRC_WIDTH 1
-#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
-#define CRC_CTRL_WAS_MASK 0x2000000u
-#define CRC_CTRL_WAS_SHIFT 25
-#define CRC_CTRL_WAS_WIDTH 1
-#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
-#define CRC_CTRL_FXOR_MASK 0x4000000u
-#define CRC_CTRL_FXOR_SHIFT 26
-#define CRC_CTRL_FXOR_WIDTH 1
-#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
-#define CRC_CTRL_TOTR_MASK 0x30000000u
-#define CRC_CTRL_TOTR_SHIFT 28
-#define CRC_CTRL_TOTR_WIDTH 2
-#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
-#define CRC_CTRL_TOT_MASK 0xC0000000u
-#define CRC_CTRL_TOT_SHIFT 30
-#define CRC_CTRL_TOT_WIDTH 2
-#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
-/* CTRLHU Bit Fields */
-#define CRC_CTRLHU_TCRC_MASK 0x1u
-#define CRC_CTRLHU_TCRC_SHIFT 0
-#define CRC_CTRLHU_TCRC_WIDTH 1
-#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
-#define CRC_CTRLHU_WAS_MASK 0x2u
-#define CRC_CTRLHU_WAS_SHIFT 1
-#define CRC_CTRLHU_WAS_WIDTH 1
-#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
-#define CRC_CTRLHU_FXOR_MASK 0x4u
-#define CRC_CTRLHU_FXOR_SHIFT 2
-#define CRC_CTRLHU_FXOR_WIDTH 1
-#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
-#define CRC_CTRLHU_TOTR_MASK 0x30u
-#define CRC_CTRLHU_TOTR_SHIFT 4
-#define CRC_CTRLHU_TOTR_WIDTH 2
-#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
-#define CRC_CTRLHU_TOT_MASK 0xC0u
-#define CRC_CTRLHU_TOT_SHIFT 6
-#define CRC_CTRLHU_TOT_WIDTH 2
-#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+/*! @name DATAL - CRC_DATAL register. */
+#define CRC_DATAL_DATAL_MASK (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT (0U)
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+
+/*! @name DATAH - CRC_DATAH register. */
+#define CRC_DATAH_DATAH_MASK (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT (0U)
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+
+/*! @name DATA - CRC Data register */
+#define CRC_DATA_LL_MASK (0xFFU)
+#define CRC_DATA_LL_SHIFT (0U)
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK (0xFF00U)
+#define CRC_DATA_LU_SHIFT (8U)
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK (0xFF0000U)
+#define CRC_DATA_HL_SHIFT (16U)
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK (0xFF000000U)
+#define CRC_DATA_HU_SHIFT (24U)
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+
+/*! @name DATALL - CRC_DATALL register. */
+#define CRC_DATALL_DATALL_MASK (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT (0U)
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+
+/*! @name DATALU - CRC_DATALU register. */
+#define CRC_DATALU_DATALU_MASK (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT (0U)
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+
+/*! @name DATAHL - CRC_DATAHL register. */
+#define CRC_DATAHL_DATAHL_MASK (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT (0U)
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+
+/*! @name DATAHU - CRC_DATAHU register. */
+#define CRC_DATAHU_DATAHU_MASK (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT (0U)
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial register */
+#define CRC_GPOLY_LOW_MASK (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT (0U)
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT (16U)
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control register */
+#define CRC_CTRL_TCRC_MASK (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT (24U)
+#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT (25U)
+#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT (26U)
+#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT (28U)
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT (30U)
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC_MASK (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT (0U)
+#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT (1U)
+#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT (2U)
+#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT (4U)
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT (6U)
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
/*!
* @}
@@ -3909,46 +2918,11 @@ typedef struct {
#define CRC_BASE (0x40032000u)
/** Peripheral CRC base pointer */
#define CRC0 ((CRC_Type *)CRC_BASE)
-#define CRC_BASE_PTR (CRC0)
/** Array initializer of CRC peripheral base addresses */
#define CRC_BASE_ADDRS { CRC_BASE }
/** Array initializer of CRC peripheral base pointers */
#define CRC_BASE_PTRS { CRC0 }
-/* ----------------------------------------------------------------------------
- -- CRC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
- * @{
- */
-
-
-/* CRC - Register instance definitions */
-/* CRC */
-#define CRC_DATA CRC_DATA_REG(CRC0)
-#define CRC_DATAL CRC_DATAL_REG(CRC0)
-#define CRC_DATALL CRC_DATALL_REG(CRC0)
-#define CRC_DATALU CRC_DATALU_REG(CRC0)
-#define CRC_DATAH CRC_DATAH_REG(CRC0)
-#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
-#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
-#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
-#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
-#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
-#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
-#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
-#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
-#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
-#define CRC_CTRL CRC_CTRL_REG(CRC0)
-#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
-
-/*!
- * @}
- */ /* end of group CRC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group CRC_Peripheral_Access_Layer */
@@ -3973,32 +2947,7 @@ typedef struct {
__IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
__IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
__IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type, *DAC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register accessors */
-#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
-#define DAC_DATL_COUNT 16
-#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
-#define DAC_DATH_COUNT 16
-#define DAC_SR_REG(base) ((base)->SR)
-#define DAC_C0_REG(base) ((base)->C0)
-#define DAC_C1_REG(base) ((base)->C1)
-#define DAC_C2_REG(base) ((base)->C2)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
+} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
@@ -4009,88 +2958,81 @@ typedef struct {
* @{
*/
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0_WIDTH 8
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1_WIDTH 4
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPBF_WIDTH 1
-#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-#define DAC_SR_DACBFRPTF_WIDTH 1
-#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
-#define DAC_SR_DACBFWMF_MASK 0x4u
-#define DAC_SR_DACBFWMF_SHIFT 2
-#define DAC_SR_DACBFWMF_WIDTH 1
-#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBBIEN_WIDTH 1
-#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_DACBTIEN_WIDTH 1
-#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
-#define DAC_C0_DACBWIEN_MASK 0x4u
-#define DAC_C0_DACBWIEN_SHIFT 2
-#define DAC_C0_DACBWIEN_WIDTH 1
-#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_LPEN_WIDTH 1
-#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACSWTRG_WIDTH 1
-#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACTRGSEL_WIDTH 1
-#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACRFS_WIDTH 1
-#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-#define DAC_C0_DACEN_WIDTH 1
-#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFEN_WIDTH 1
-#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
-#define DAC_C1_DACBFMD_MASK 0x6u
-#define DAC_C1_DACBFMD_SHIFT 1
-#define DAC_C1_DACBFMD_WIDTH 2
-#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
-#define DAC_C1_DACBFWM_MASK 0x18u
-#define DAC_C1_DACBFWM_SHIFT 3
-#define DAC_C1_DACBFWM_WIDTH 2
-#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-#define DAC_C1_DMAEN_WIDTH 1
-#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0xFu
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFUP_WIDTH 4
-#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
-#define DAC_C2_DACBFRP_MASK 0xF0u
-#define DAC_C2_DACBFRP_SHIFT 4
-#define DAC_C2_DACBFRP_WIDTH 4
-#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK (0xFFU)
+#define DAC_DATL_DATA0_SHIFT (0U)
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT (16U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK (0xFU)
+#define DAC_DATH_DATA1_SHIFT (0U)
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT (16U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT (0U)
+#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT (1U)
+#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK (0x4U)
+#define DAC_SR_DACBFWMF_SHIFT (2U)
+#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT (0U)
+#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT (1U)
+#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK (0x4U)
+#define DAC_C0_DACBWIEN_SHIFT (2U)
+#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK (0x8U)
+#define DAC_C0_LPEN_SHIFT (3U)
+#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT (4U)
+#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT (5U)
+#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK (0x40U)
+#define DAC_C0_DACRFS_SHIFT (6U)
+#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK (0x80U)
+#define DAC_C0_DACEN_SHIFT (7U)
+#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK (0x1U)
+#define DAC_C1_DACBFEN_SHIFT (0U)
+#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK (0x6U)
+#define DAC_C1_DACBFMD_SHIFT (1U)
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK (0x18U)
+#define DAC_C1_DACBFWM_SHIFT (3U)
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK (0x80U)
+#define DAC_C1_DMAEN_SHIFT (7U)
+#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK (0xFU)
+#define DAC_C2_DACBFUP_SHIFT (0U)
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT (4U)
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
/*!
* @}
@@ -4102,12 +3044,10 @@ typedef struct {
#define DAC0_BASE (0x400CC000u)
/** Peripheral DAC0 base pointer */
#define DAC0 ((DAC_Type *)DAC0_BASE)
-#define DAC0_BASE_PTR (DAC0)
/** Peripheral DAC1 base address */
#define DAC1_BASE (0x400CD000u)
/** Peripheral DAC1 base pointer */
#define DAC1 ((DAC_Type *)DAC1_BASE)
-#define DAC1_BASE_PTR (DAC1)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
/** Array initializer of DAC peripheral base pointers */
@@ -4115,103 +3055,6 @@ typedef struct {
/** Interrupt vectors for the DAC peripheral type */
#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
-/* ----------------------------------------------------------------------------
- -- DAC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
- * @{
- */
-
-
-/* DAC - Register instance definitions */
-/* DAC0 */
-#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
-#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
-#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
-#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
-#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
-#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
-#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
-#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
-#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
-#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
-#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
-#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
-#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
-#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
-#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
-#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
-#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
-#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
-#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
-#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
-#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
-#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
-#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
-#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
-#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
-#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
-#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
-#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
-#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
-#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
-#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
-#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
-#define DAC0_SR DAC_SR_REG(DAC0)
-#define DAC0_C0 DAC_C0_REG(DAC0)
-#define DAC0_C1 DAC_C1_REG(DAC0)
-#define DAC0_C2 DAC_C2_REG(DAC0)
-/* DAC1 */
-#define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
-#define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
-#define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
-#define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
-#define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
-#define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
-#define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
-#define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
-#define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
-#define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
-#define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
-#define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
-#define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
-#define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
-#define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
-#define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
-#define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
-#define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
-#define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
-#define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
-#define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
-#define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
-#define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
-#define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
-#define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
-#define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
-#define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
-#define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
-#define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
-#define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
-#define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
-#define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
-#define DAC1_SR DAC_SR_REG(DAC1)
-#define DAC1_C0 DAC_C0_REG(DAC1)
-#define DAC1_C1 DAC_C1_REG(DAC1)
-#define DAC1_C2 DAC_C2_REG(DAC1)
-
-/* DAC - Register array accessors */
-#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
-#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
-#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
-#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
-
-/*!
- * @}
- */ /* end of group DAC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
@@ -4289,985 +3132,788 @@ typedef struct {
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[16];
-} DMA_Type, *DMA_MemMapPtr;
+} DMA_Type;
/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
+ -- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG_MASK (0x2U)
+#define DMA_CR_EDBG_SHIFT (1U)
+#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK (0x4U)
+#define DMA_CR_ERCA_SHIFT (2U)
+#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_HOE_MASK (0x10U)
+#define DMA_CR_HOE_SHIFT (4U)
+#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK (0x20U)
+#define DMA_CR_HALT_SHIFT (5U)
+#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK (0x40U)
+#define DMA_CR_CLM_SHIFT (6U)
+#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK (0x80U)
+#define DMA_CR_EMLM_SHIFT (7U)
+#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_ECX_MASK (0x10000U)
+#define DMA_CR_ECX_SHIFT (16U)
+#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK (0x20000U)
+#define DMA_CR_CX_SHIFT (17U)
+#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE_MASK (0x1U)
+#define DMA_ES_DBE_SHIFT (0U)
+#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK (0x2U)
+#define DMA_ES_SBE_SHIFT (1U)
+#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK (0x4U)
+#define DMA_ES_SGE_SHIFT (2U)
+#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK (0x8U)
+#define DMA_ES_NCE_SHIFT (3U)
+#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK (0x10U)
+#define DMA_ES_DOE_SHIFT (4U)
+#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK (0x20U)
+#define DMA_ES_DAE_SHIFT (5U)
+#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK (0x40U)
+#define DMA_ES_SOE_SHIFT (6U)
+#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK (0x80U)
+#define DMA_ES_SAE_SHIFT (7U)
+#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK (0xF00U)
+#define DMA_ES_ERRCHN_SHIFT (8U)
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK (0x4000U)
+#define DMA_ES_CPE_SHIFT (14U)
+#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_ECX_MASK (0x10000U)
+#define DMA_ES_ECX_SHIFT (16U)
+#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK (0x80000000U)
+#define DMA_ES_VLD_SHIFT (31U)
+#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+
+/*! @name ERQ - Enable Request Register */
+#define DMA_ERQ_ERQ0_MASK (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT (0U)
+#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT (1U)
+#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT (2U)
+#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT (3U)
+#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT (4U)
+#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT (5U)
+#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT (6U)
+#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT (7U)
+#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK (0x100U)
+#define DMA_ERQ_ERQ8_SHIFT (8U)
+#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK (0x200U)
+#define DMA_ERQ_ERQ9_SHIFT (9U)
+#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK (0x400U)
+#define DMA_ERQ_ERQ10_SHIFT (10U)
+#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK (0x800U)
+#define DMA_ERQ_ERQ11_SHIFT (11U)
+#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK (0x1000U)
+#define DMA_ERQ_ERQ12_SHIFT (12U)
+#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK (0x2000U)
+#define DMA_ERQ_ERQ13_SHIFT (13U)
+#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK (0x4000U)
+#define DMA_ERQ_ERQ14_SHIFT (14U)
+#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK (0x8000U)
+#define DMA_ERQ_ERQ15_SHIFT (15U)
+#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+
+/*! @name EEI - Enable Error Interrupt Register */
+#define DMA_EEI_EEI0_MASK (0x1U)
+#define DMA_EEI_EEI0_SHIFT (0U)
+#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK (0x2U)
+#define DMA_EEI_EEI1_SHIFT (1U)
+#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK (0x4U)
+#define DMA_EEI_EEI2_SHIFT (2U)
+#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK (0x8U)
+#define DMA_EEI_EEI3_SHIFT (3U)
+#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK (0x10U)
+#define DMA_EEI_EEI4_SHIFT (4U)
+#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK (0x20U)
+#define DMA_EEI_EEI5_SHIFT (5U)
+#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK (0x40U)
+#define DMA_EEI_EEI6_SHIFT (6U)
+#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK (0x80U)
+#define DMA_EEI_EEI7_SHIFT (7U)
+#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK (0x100U)
+#define DMA_EEI_EEI8_SHIFT (8U)
+#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK (0x200U)
+#define DMA_EEI_EEI9_SHIFT (9U)
+#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK (0x400U)
+#define DMA_EEI_EEI10_SHIFT (10U)
+#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK (0x800U)
+#define DMA_EEI_EEI11_SHIFT (11U)
+#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK (0x1000U)
+#define DMA_EEI_EEI12_SHIFT (12U)
+#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK (0x2000U)
+#define DMA_EEI_EEI13_SHIFT (13U)
+#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK (0x4000U)
+#define DMA_EEI_EEI14_SHIFT (14U)
+#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK (0x8000U)
+#define DMA_EEI_EEI15_SHIFT (15U)
+#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK (0xFU)
+#define DMA_CEEI_CEEI_SHIFT (0U)
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK (0x40U)
+#define DMA_CEEI_CAEE_SHIFT (6U)
+#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK (0x80U)
+#define DMA_CEEI_NOP_SHIFT (7U)
+#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK (0xFU)
+#define DMA_SEEI_SEEI_SHIFT (0U)
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK (0x40U)
+#define DMA_SEEI_SAEE_SHIFT (6U)
+#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK (0x80U)
+#define DMA_SEEI_NOP_SHIFT (7U)
+#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK (0xFU)
+#define DMA_CERQ_CERQ_SHIFT (0U)
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK (0x40U)
+#define DMA_CERQ_CAER_SHIFT (6U)
+#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK (0x80U)
+#define DMA_CERQ_NOP_SHIFT (7U)
+#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK (0xFU)
+#define DMA_SERQ_SERQ_SHIFT (0U)
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK (0x40U)
+#define DMA_SERQ_SAER_SHIFT (6U)
+#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK (0x80U)
+#define DMA_SERQ_NOP_SHIFT (7U)
+#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK (0xFU)
+#define DMA_CDNE_CDNE_SHIFT (0U)
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK (0x40U)
+#define DMA_CDNE_CADN_SHIFT (6U)
+#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK (0x80U)
+#define DMA_CDNE_NOP_SHIFT (7U)
+#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK (0xFU)
+#define DMA_SSRT_SSRT_SHIFT (0U)
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK (0x40U)
+#define DMA_SSRT_SAST_SHIFT (6U)
+#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK (0x80U)
+#define DMA_SSRT_NOP_SHIFT (7U)
+#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK (0xFU)
+#define DMA_CERR_CERR_SHIFT (0U)
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK (0x40U)
+#define DMA_CERR_CAEI_SHIFT (6U)
+#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK (0x80U)
+#define DMA_CERR_NOP_SHIFT (7U)
+#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK (0xFU)
+#define DMA_CINT_CINT_SHIFT (0U)
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK (0x40U)
+#define DMA_CINT_CAIR_SHIFT (6U)
+#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK (0x80U)
+#define DMA_CINT_NOP_SHIFT (7U)
+#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+
+/*! @name INT - Interrupt Request Register */
+#define DMA_INT_INT0_MASK (0x1U)
+#define DMA_INT_INT0_SHIFT (0U)
+#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK (0x2U)
+#define DMA_INT_INT1_SHIFT (1U)
+#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK (0x4U)
+#define DMA_INT_INT2_SHIFT (2U)
+#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK (0x8U)
+#define DMA_INT_INT3_SHIFT (3U)
+#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK (0x10U)
+#define DMA_INT_INT4_SHIFT (4U)
+#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK (0x20U)
+#define DMA_INT_INT5_SHIFT (5U)
+#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK (0x40U)
+#define DMA_INT_INT6_SHIFT (6U)
+#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK (0x80U)
+#define DMA_INT_INT7_SHIFT (7U)
+#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK (0x100U)
+#define DMA_INT_INT8_SHIFT (8U)
+#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK (0x200U)
+#define DMA_INT_INT9_SHIFT (9U)
+#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK (0x400U)
+#define DMA_INT_INT10_SHIFT (10U)
+#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK (0x800U)
+#define DMA_INT_INT11_SHIFT (11U)
+#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK (0x1000U)
+#define DMA_INT_INT12_SHIFT (12U)
+#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK (0x2000U)
+#define DMA_INT_INT13_SHIFT (13U)
+#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK (0x4000U)
+#define DMA_INT_INT14_SHIFT (14U)
+#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK (0x8000U)
+#define DMA_INT_INT15_SHIFT (15U)
+#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+
+/*! @name ERR - Error Register */
+#define DMA_ERR_ERR0_MASK (0x1U)
+#define DMA_ERR_ERR0_SHIFT (0U)
+#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK (0x2U)
+#define DMA_ERR_ERR1_SHIFT (1U)
+#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK (0x4U)
+#define DMA_ERR_ERR2_SHIFT (2U)
+#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK (0x8U)
+#define DMA_ERR_ERR3_SHIFT (3U)
+#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK (0x10U)
+#define DMA_ERR_ERR4_SHIFT (4U)
+#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK (0x20U)
+#define DMA_ERR_ERR5_SHIFT (5U)
+#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK (0x40U)
+#define DMA_ERR_ERR6_SHIFT (6U)
+#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK (0x80U)
+#define DMA_ERR_ERR7_SHIFT (7U)
+#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK (0x100U)
+#define DMA_ERR_ERR8_SHIFT (8U)
+#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK (0x200U)
+#define DMA_ERR_ERR9_SHIFT (9U)
+#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK (0x400U)
+#define DMA_ERR_ERR10_SHIFT (10U)
+#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK (0x800U)
+#define DMA_ERR_ERR11_SHIFT (11U)
+#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK (0x1000U)
+#define DMA_ERR_ERR12_SHIFT (12U)
+#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK (0x2000U)
+#define DMA_ERR_ERR13_SHIFT (13U)
+#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK (0x4000U)
+#define DMA_ERR_ERR14_SHIFT (14U)
+#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK (0x8000U)
+#define DMA_ERR_ERR15_SHIFT (15U)
+#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+
+/*! @name HRS - Hardware Request Status Register */
+#define DMA_HRS_HRS0_MASK (0x1U)
+#define DMA_HRS_HRS0_SHIFT (0U)
+#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK (0x2U)
+#define DMA_HRS_HRS1_SHIFT (1U)
+#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK (0x4U)
+#define DMA_HRS_HRS2_SHIFT (2U)
+#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK (0x8U)
+#define DMA_HRS_HRS3_SHIFT (3U)
+#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK (0x10U)
+#define DMA_HRS_HRS4_SHIFT (4U)
+#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK (0x20U)
+#define DMA_HRS_HRS5_SHIFT (5U)
+#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK (0x40U)
+#define DMA_HRS_HRS6_SHIFT (6U)
+#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK (0x80U)
+#define DMA_HRS_HRS7_SHIFT (7U)
+#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK (0x100U)
+#define DMA_HRS_HRS8_SHIFT (8U)
+#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK (0x200U)
+#define DMA_HRS_HRS9_SHIFT (9U)
+#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK (0x400U)
+#define DMA_HRS_HRS10_SHIFT (10U)
+#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK (0x800U)
+#define DMA_HRS_HRS11_SHIFT (11U)
+#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK (0x1000U)
+#define DMA_HRS_HRS12_SHIFT (12U)
+#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK (0x2000U)
+#define DMA_HRS_HRS13_SHIFT (13U)
+#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK (0x4000U)
+#define DMA_HRS_HRS14_SHIFT (14U)
+#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK (0x8000U)
+#define DMA_HRS_HRS15_SHIFT (15U)
+#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT (6U)
+#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT (7U)
+#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT (6U)
+#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT (7U)
+#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT (6U)
+#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT (7U)
+#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT (6U)
+#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT (7U)
+#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+
+/*! @name DCHPRI7 - Channel n Priority Register */
+#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT (6U)
+#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT (7U)
+#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+
+/*! @name DCHPRI6 - Channel n Priority Register */
+#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT (6U)
+#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT (7U)
+#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+
+/*! @name DCHPRI5 - Channel n Priority Register */
+#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT (6U)
+#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT (7U)
+#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+
+/*! @name DCHPRI4 - Channel n Priority Register */
+#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT (6U)
+#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT (7U)
+#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+
+/*! @name DCHPRI11 - Channel n Priority Register */
+#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK (0x40U)
+#define DMA_DCHPRI11_DPA_SHIFT (6U)
+#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK (0x80U)
+#define DMA_DCHPRI11_ECP_SHIFT (7U)
+#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+
+/*! @name DCHPRI10 - Channel n Priority Register */
+#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK (0x40U)
+#define DMA_DCHPRI10_DPA_SHIFT (6U)
+#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK (0x80U)
+#define DMA_DCHPRI10_ECP_SHIFT (7U)
+#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+
+/*! @name DCHPRI9 - Channel n Priority Register */
+#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK (0x40U)
+#define DMA_DCHPRI9_DPA_SHIFT (6U)
+#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK (0x80U)
+#define DMA_DCHPRI9_ECP_SHIFT (7U)
+#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+
+/*! @name DCHPRI8 - Channel n Priority Register */
+#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK (0x40U)
+#define DMA_DCHPRI8_DPA_SHIFT (6U)
+#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK (0x80U)
+#define DMA_DCHPRI8_ECP_SHIFT (7U)
+#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+
+/*! @name DCHPRI15 - Channel n Priority Register */
+#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK (0x40U)
+#define DMA_DCHPRI15_DPA_SHIFT (6U)
+#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK (0x80U)
+#define DMA_DCHPRI15_ECP_SHIFT (7U)
+#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+
+/*! @name DCHPRI14 - Channel n Priority Register */
+#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK (0x40U)
+#define DMA_DCHPRI14_DPA_SHIFT (6U)
+#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK (0x80U)
+#define DMA_DCHPRI14_ECP_SHIFT (7U)
+#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+
+/*! @name DCHPRI13 - Channel n Priority Register */
+#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK (0x40U)
+#define DMA_DCHPRI13_DPA_SHIFT (6U)
+#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK (0x80U)
+#define DMA_DCHPRI13_ECP_SHIFT (7U)
+#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+
+/*! @name DCHPRI12 - Channel n Priority Register */
+#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
+#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
+#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK (0x40U)
+#define DMA_DCHPRI12_DPA_SHIFT (6U)
+#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK (0x80U)
+#define DMA_DCHPRI12_ECP_SHIFT (7U)
+#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+
+/*! @name SADDR - TCD Source Address */
+#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT (0U)
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT (16U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT (0U)
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT (16U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT (0U)
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT (3U)
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT (8U)
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT (11U)
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT (16U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
+#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT (16U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT (16U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT (16U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT (0U)
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT (16U)
+
+/*! @name DADDR - TCD Destination Address */
+#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT (0U)
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT (16U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT (0U)
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT (16U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT (16U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT (16U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT (16U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START_MASK (0x1U)
+#define DMA_CSR_START_SHIFT (0U)
+#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT (1U)
+#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK (0x4U)
+#define DMA_CSR_INTHALF_SHIFT (2U)
+#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK (0x8U)
+#define DMA_CSR_DREQ_SHIFT (3U)
+#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK (0x10U)
+#define DMA_CSR_ESG_SHIFT (4U)
+#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT (5U)
+#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT (6U)
+#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK (0x80U)
+#define DMA_CSR_DONE_SHIFT (7U)
+#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK (0xC000U)
+#define DMA_CSR_BWC_SHIFT (14U)
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT (16U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT (16U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
+#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT (16U)
-/* DMA - Register accessors */
-#define DMA_CR_REG(base) ((base)->CR)
-#define DMA_ES_REG(base) ((base)->ES)
-#define DMA_ERQ_REG(base) ((base)->ERQ)
-#define DMA_EEI_REG(base) ((base)->EEI)
-#define DMA_CEEI_REG(base) ((base)->CEEI)
-#define DMA_SEEI_REG(base) ((base)->SEEI)
-#define DMA_CERQ_REG(base) ((base)->CERQ)
-#define DMA_SERQ_REG(base) ((base)->SERQ)
-#define DMA_CDNE_REG(base) ((base)->CDNE)
-#define DMA_SSRT_REG(base) ((base)->SSRT)
-#define DMA_CERR_REG(base) ((base)->CERR)
-#define DMA_CINT_REG(base) ((base)->CINT)
-#define DMA_INT_REG(base) ((base)->INT)
-#define DMA_ERR_REG(base) ((base)->ERR)
-#define DMA_HRS_REG(base) ((base)->HRS)
-#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
-#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
-#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
-#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
-#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
-#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
-#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
-#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
-#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
-#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
-#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
-#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
-#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
-#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
-#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
-#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
-#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
-#define DMA_SADDR_COUNT 16
-#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
-#define DMA_SOFF_COUNT 16
-#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
-#define DMA_ATTR_COUNT 16
-#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
-#define DMA_NBYTES_MLNO_COUNT 16
-#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
-#define DMA_NBYTES_MLOFFNO_COUNT 16
-#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
-#define DMA_NBYTES_MLOFFYES_COUNT 16
-#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
-#define DMA_SLAST_COUNT 16
-#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
-#define DMA_DADDR_COUNT 16
-#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
-#define DMA_DOFF_COUNT 16
-#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
-#define DMA_CITER_ELINKNO_COUNT 16
-#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
-#define DMA_CITER_ELINKYES_COUNT 16
-#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
-#define DMA_DLAST_SGA_COUNT 16
-#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
-#define DMA_CSR_COUNT 16
-#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
-#define DMA_BITER_ELINKNO_COUNT 16
-#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
-#define DMA_BITER_ELINKYES_COUNT 16
/*!
* @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define DMA_CR_EDBG_MASK 0x2u
-#define DMA_CR_EDBG_SHIFT 1
-#define DMA_CR_EDBG_WIDTH 1
-#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
-#define DMA_CR_ERCA_MASK 0x4u
-#define DMA_CR_ERCA_SHIFT 2
-#define DMA_CR_ERCA_WIDTH 1
-#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
-#define DMA_CR_HOE_MASK 0x10u
-#define DMA_CR_HOE_SHIFT 4
-#define DMA_CR_HOE_WIDTH 1
-#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
-#define DMA_CR_HALT_MASK 0x20u
-#define DMA_CR_HALT_SHIFT 5
-#define DMA_CR_HALT_WIDTH 1
-#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
-#define DMA_CR_CLM_MASK 0x40u
-#define DMA_CR_CLM_SHIFT 6
-#define DMA_CR_CLM_WIDTH 1
-#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
-#define DMA_CR_EMLM_MASK 0x80u
-#define DMA_CR_EMLM_SHIFT 7
-#define DMA_CR_EMLM_WIDTH 1
-#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
-#define DMA_CR_ECX_MASK 0x10000u
-#define DMA_CR_ECX_SHIFT 16
-#define DMA_CR_ECX_WIDTH 1
-#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
-#define DMA_CR_CX_MASK 0x20000u
-#define DMA_CR_CX_SHIFT 17
-#define DMA_CR_CX_WIDTH 1
-#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
-/* ES Bit Fields */
-#define DMA_ES_DBE_MASK 0x1u
-#define DMA_ES_DBE_SHIFT 0
-#define DMA_ES_DBE_WIDTH 1
-#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
-#define DMA_ES_SBE_MASK 0x2u
-#define DMA_ES_SBE_SHIFT 1
-#define DMA_ES_SBE_WIDTH 1
-#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
-#define DMA_ES_SGE_MASK 0x4u
-#define DMA_ES_SGE_SHIFT 2
-#define DMA_ES_SGE_WIDTH 1
-#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
-#define DMA_ES_NCE_MASK 0x8u
-#define DMA_ES_NCE_SHIFT 3
-#define DMA_ES_NCE_WIDTH 1
-#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
-#define DMA_ES_DOE_MASK 0x10u
-#define DMA_ES_DOE_SHIFT 4
-#define DMA_ES_DOE_WIDTH 1
-#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
-#define DMA_ES_DAE_MASK 0x20u
-#define DMA_ES_DAE_SHIFT 5
-#define DMA_ES_DAE_WIDTH 1
-#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
-#define DMA_ES_SOE_MASK 0x40u
-#define DMA_ES_SOE_SHIFT 6
-#define DMA_ES_SOE_WIDTH 1
-#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
-#define DMA_ES_SAE_MASK 0x80u
-#define DMA_ES_SAE_SHIFT 7
-#define DMA_ES_SAE_WIDTH 1
-#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
-#define DMA_ES_ERRCHN_MASK 0xF00u
-#define DMA_ES_ERRCHN_SHIFT 8
-#define DMA_ES_ERRCHN_WIDTH 4
-#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
-#define DMA_ES_CPE_MASK 0x4000u
-#define DMA_ES_CPE_SHIFT 14
-#define DMA_ES_CPE_WIDTH 1
-#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
-#define DMA_ES_ECX_MASK 0x10000u
-#define DMA_ES_ECX_SHIFT 16
-#define DMA_ES_ECX_WIDTH 1
-#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
-#define DMA_ES_VLD_MASK 0x80000000u
-#define DMA_ES_VLD_SHIFT 31
-#define DMA_ES_VLD_WIDTH 1
-#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
-/* ERQ Bit Fields */
-#define DMA_ERQ_ERQ0_MASK 0x1u
-#define DMA_ERQ_ERQ0_SHIFT 0
-#define DMA_ERQ_ERQ0_WIDTH 1
-#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
-#define DMA_ERQ_ERQ1_MASK 0x2u
-#define DMA_ERQ_ERQ1_SHIFT 1
-#define DMA_ERQ_ERQ1_WIDTH 1
-#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
-#define DMA_ERQ_ERQ2_MASK 0x4u
-#define DMA_ERQ_ERQ2_SHIFT 2
-#define DMA_ERQ_ERQ2_WIDTH 1
-#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
-#define DMA_ERQ_ERQ3_MASK 0x8u
-#define DMA_ERQ_ERQ3_SHIFT 3
-#define DMA_ERQ_ERQ3_WIDTH 1
-#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
-#define DMA_ERQ_ERQ4_MASK 0x10u
-#define DMA_ERQ_ERQ4_SHIFT 4
-#define DMA_ERQ_ERQ4_WIDTH 1
-#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
-#define DMA_ERQ_ERQ5_MASK 0x20u
-#define DMA_ERQ_ERQ5_SHIFT 5
-#define DMA_ERQ_ERQ5_WIDTH 1
-#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
-#define DMA_ERQ_ERQ6_MASK 0x40u
-#define DMA_ERQ_ERQ6_SHIFT 6
-#define DMA_ERQ_ERQ6_WIDTH 1
-#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
-#define DMA_ERQ_ERQ7_MASK 0x80u
-#define DMA_ERQ_ERQ7_SHIFT 7
-#define DMA_ERQ_ERQ7_WIDTH 1
-#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
-#define DMA_ERQ_ERQ8_MASK 0x100u
-#define DMA_ERQ_ERQ8_SHIFT 8
-#define DMA_ERQ_ERQ8_WIDTH 1
-#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
-#define DMA_ERQ_ERQ9_MASK 0x200u
-#define DMA_ERQ_ERQ9_SHIFT 9
-#define DMA_ERQ_ERQ9_WIDTH 1
-#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
-#define DMA_ERQ_ERQ10_MASK 0x400u
-#define DMA_ERQ_ERQ10_SHIFT 10
-#define DMA_ERQ_ERQ10_WIDTH 1
-#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
-#define DMA_ERQ_ERQ11_MASK 0x800u
-#define DMA_ERQ_ERQ11_SHIFT 11
-#define DMA_ERQ_ERQ11_WIDTH 1
-#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
-#define DMA_ERQ_ERQ12_MASK 0x1000u
-#define DMA_ERQ_ERQ12_SHIFT 12
-#define DMA_ERQ_ERQ12_WIDTH 1
-#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
-#define DMA_ERQ_ERQ13_MASK 0x2000u
-#define DMA_ERQ_ERQ13_SHIFT 13
-#define DMA_ERQ_ERQ13_WIDTH 1
-#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
-#define DMA_ERQ_ERQ14_MASK 0x4000u
-#define DMA_ERQ_ERQ14_SHIFT 14
-#define DMA_ERQ_ERQ14_WIDTH 1
-#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
-#define DMA_ERQ_ERQ15_MASK 0x8000u
-#define DMA_ERQ_ERQ15_SHIFT 15
-#define DMA_ERQ_ERQ15_WIDTH 1
-#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
-/* EEI Bit Fields */
-#define DMA_EEI_EEI0_MASK 0x1u
-#define DMA_EEI_EEI0_SHIFT 0
-#define DMA_EEI_EEI0_WIDTH 1
-#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
-#define DMA_EEI_EEI1_MASK 0x2u
-#define DMA_EEI_EEI1_SHIFT 1
-#define DMA_EEI_EEI1_WIDTH 1
-#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
-#define DMA_EEI_EEI2_MASK 0x4u
-#define DMA_EEI_EEI2_SHIFT 2
-#define DMA_EEI_EEI2_WIDTH 1
-#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
-#define DMA_EEI_EEI3_MASK 0x8u
-#define DMA_EEI_EEI3_SHIFT 3
-#define DMA_EEI_EEI3_WIDTH 1
-#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
-#define DMA_EEI_EEI4_MASK 0x10u
-#define DMA_EEI_EEI4_SHIFT 4
-#define DMA_EEI_EEI4_WIDTH 1
-#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
-#define DMA_EEI_EEI5_MASK 0x20u
-#define DMA_EEI_EEI5_SHIFT 5
-#define DMA_EEI_EEI5_WIDTH 1
-#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
-#define DMA_EEI_EEI6_MASK 0x40u
-#define DMA_EEI_EEI6_SHIFT 6
-#define DMA_EEI_EEI6_WIDTH 1
-#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
-#define DMA_EEI_EEI7_MASK 0x80u
-#define DMA_EEI_EEI7_SHIFT 7
-#define DMA_EEI_EEI7_WIDTH 1
-#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
-#define DMA_EEI_EEI8_MASK 0x100u
-#define DMA_EEI_EEI8_SHIFT 8
-#define DMA_EEI_EEI8_WIDTH 1
-#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
-#define DMA_EEI_EEI9_MASK 0x200u
-#define DMA_EEI_EEI9_SHIFT 9
-#define DMA_EEI_EEI9_WIDTH 1
-#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
-#define DMA_EEI_EEI10_MASK 0x400u
-#define DMA_EEI_EEI10_SHIFT 10
-#define DMA_EEI_EEI10_WIDTH 1
-#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
-#define DMA_EEI_EEI11_MASK 0x800u
-#define DMA_EEI_EEI11_SHIFT 11
-#define DMA_EEI_EEI11_WIDTH 1
-#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
-#define DMA_EEI_EEI12_MASK 0x1000u
-#define DMA_EEI_EEI12_SHIFT 12
-#define DMA_EEI_EEI12_WIDTH 1
-#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
-#define DMA_EEI_EEI13_MASK 0x2000u
-#define DMA_EEI_EEI13_SHIFT 13
-#define DMA_EEI_EEI13_WIDTH 1
-#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
-#define DMA_EEI_EEI14_MASK 0x4000u
-#define DMA_EEI_EEI14_SHIFT 14
-#define DMA_EEI_EEI14_WIDTH 1
-#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
-#define DMA_EEI_EEI15_MASK 0x8000u
-#define DMA_EEI_EEI15_SHIFT 15
-#define DMA_EEI_EEI15_WIDTH 1
-#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
-/* CEEI Bit Fields */
-#define DMA_CEEI_CEEI_MASK 0xFu
-#define DMA_CEEI_CEEI_SHIFT 0
-#define DMA_CEEI_CEEI_WIDTH 4
-#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
-#define DMA_CEEI_CAEE_MASK 0x40u
-#define DMA_CEEI_CAEE_SHIFT 6
-#define DMA_CEEI_CAEE_WIDTH 1
-#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
-#define DMA_CEEI_NOP_MASK 0x80u
-#define DMA_CEEI_NOP_SHIFT 7
-#define DMA_CEEI_NOP_WIDTH 1
-#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
-/* SEEI Bit Fields */
-#define DMA_SEEI_SEEI_MASK 0xFu
-#define DMA_SEEI_SEEI_SHIFT 0
-#define DMA_SEEI_SEEI_WIDTH 4
-#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
-#define DMA_SEEI_SAEE_MASK 0x40u
-#define DMA_SEEI_SAEE_SHIFT 6
-#define DMA_SEEI_SAEE_WIDTH 1
-#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
-#define DMA_SEEI_NOP_MASK 0x80u
-#define DMA_SEEI_NOP_SHIFT 7
-#define DMA_SEEI_NOP_WIDTH 1
-#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
-/* CERQ Bit Fields */
-#define DMA_CERQ_CERQ_MASK 0xFu
-#define DMA_CERQ_CERQ_SHIFT 0
-#define DMA_CERQ_CERQ_WIDTH 4
-#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
-#define DMA_CERQ_CAER_MASK 0x40u
-#define DMA_CERQ_CAER_SHIFT 6
-#define DMA_CERQ_CAER_WIDTH 1
-#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
-#define DMA_CERQ_NOP_MASK 0x80u
-#define DMA_CERQ_NOP_SHIFT 7
-#define DMA_CERQ_NOP_WIDTH 1
-#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
-/* SERQ Bit Fields */
-#define DMA_SERQ_SERQ_MASK 0xFu
-#define DMA_SERQ_SERQ_SHIFT 0
-#define DMA_SERQ_SERQ_WIDTH 4
-#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
-#define DMA_SERQ_SAER_MASK 0x40u
-#define DMA_SERQ_SAER_SHIFT 6
-#define DMA_SERQ_SAER_WIDTH 1
-#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
-#define DMA_SERQ_NOP_MASK 0x80u
-#define DMA_SERQ_NOP_SHIFT 7
-#define DMA_SERQ_NOP_WIDTH 1
-#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
-/* CDNE Bit Fields */
-#define DMA_CDNE_CDNE_MASK 0xFu
-#define DMA_CDNE_CDNE_SHIFT 0
-#define DMA_CDNE_CDNE_WIDTH 4
-#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
-#define DMA_CDNE_CADN_MASK 0x40u
-#define DMA_CDNE_CADN_SHIFT 6
-#define DMA_CDNE_CADN_WIDTH 1
-#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
-#define DMA_CDNE_NOP_MASK 0x80u
-#define DMA_CDNE_NOP_SHIFT 7
-#define DMA_CDNE_NOP_WIDTH 1
-#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
-/* SSRT Bit Fields */
-#define DMA_SSRT_SSRT_MASK 0xFu
-#define DMA_SSRT_SSRT_SHIFT 0
-#define DMA_SSRT_SSRT_WIDTH 4
-#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
-#define DMA_SSRT_SAST_MASK 0x40u
-#define DMA_SSRT_SAST_SHIFT 6
-#define DMA_SSRT_SAST_WIDTH 1
-#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
-#define DMA_SSRT_NOP_MASK 0x80u
-#define DMA_SSRT_NOP_SHIFT 7
-#define DMA_SSRT_NOP_WIDTH 1
-#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
-/* CERR Bit Fields */
-#define DMA_CERR_CERR_MASK 0xFu
-#define DMA_CERR_CERR_SHIFT 0
-#define DMA_CERR_CERR_WIDTH 4
-#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
-#define DMA_CERR_CAEI_MASK 0x40u
-#define DMA_CERR_CAEI_SHIFT 6
-#define DMA_CERR_CAEI_WIDTH 1
-#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
-#define DMA_CERR_NOP_MASK 0x80u
-#define DMA_CERR_NOP_SHIFT 7
-#define DMA_CERR_NOP_WIDTH 1
-#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
-/* CINT Bit Fields */
-#define DMA_CINT_CINT_MASK 0xFu
-#define DMA_CINT_CINT_SHIFT 0
-#define DMA_CINT_CINT_WIDTH 4
-#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
-#define DMA_CINT_CAIR_MASK 0x40u
-#define DMA_CINT_CAIR_SHIFT 6
-#define DMA_CINT_CAIR_WIDTH 1
-#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
-#define DMA_CINT_NOP_MASK 0x80u
-#define DMA_CINT_NOP_SHIFT 7
-#define DMA_CINT_NOP_WIDTH 1
-#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
-/* INT Bit Fields */
-#define DMA_INT_INT0_MASK 0x1u
-#define DMA_INT_INT0_SHIFT 0
-#define DMA_INT_INT0_WIDTH 1
-#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
-#define DMA_INT_INT1_MASK 0x2u
-#define DMA_INT_INT1_SHIFT 1
-#define DMA_INT_INT1_WIDTH 1
-#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
-#define DMA_INT_INT2_MASK 0x4u
-#define DMA_INT_INT2_SHIFT 2
-#define DMA_INT_INT2_WIDTH 1
-#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
-#define DMA_INT_INT3_MASK 0x8u
-#define DMA_INT_INT3_SHIFT 3
-#define DMA_INT_INT3_WIDTH 1
-#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
-#define DMA_INT_INT4_MASK 0x10u
-#define DMA_INT_INT4_SHIFT 4
-#define DMA_INT_INT4_WIDTH 1
-#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
-#define DMA_INT_INT5_MASK 0x20u
-#define DMA_INT_INT5_SHIFT 5
-#define DMA_INT_INT5_WIDTH 1
-#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
-#define DMA_INT_INT6_MASK 0x40u
-#define DMA_INT_INT6_SHIFT 6
-#define DMA_INT_INT6_WIDTH 1
-#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
-#define DMA_INT_INT7_MASK 0x80u
-#define DMA_INT_INT7_SHIFT 7
-#define DMA_INT_INT7_WIDTH 1
-#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
-#define DMA_INT_INT8_MASK 0x100u
-#define DMA_INT_INT8_SHIFT 8
-#define DMA_INT_INT8_WIDTH 1
-#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
-#define DMA_INT_INT9_MASK 0x200u
-#define DMA_INT_INT9_SHIFT 9
-#define DMA_INT_INT9_WIDTH 1
-#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
-#define DMA_INT_INT10_MASK 0x400u
-#define DMA_INT_INT10_SHIFT 10
-#define DMA_INT_INT10_WIDTH 1
-#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
-#define DMA_INT_INT11_MASK 0x800u
-#define DMA_INT_INT11_SHIFT 11
-#define DMA_INT_INT11_WIDTH 1
-#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
-#define DMA_INT_INT12_MASK 0x1000u
-#define DMA_INT_INT12_SHIFT 12
-#define DMA_INT_INT12_WIDTH 1
-#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
-#define DMA_INT_INT13_MASK 0x2000u
-#define DMA_INT_INT13_SHIFT 13
-#define DMA_INT_INT13_WIDTH 1
-#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
-#define DMA_INT_INT14_MASK 0x4000u
-#define DMA_INT_INT14_SHIFT 14
-#define DMA_INT_INT14_WIDTH 1
-#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
-#define DMA_INT_INT15_MASK 0x8000u
-#define DMA_INT_INT15_SHIFT 15
-#define DMA_INT_INT15_WIDTH 1
-#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
-/* ERR Bit Fields */
-#define DMA_ERR_ERR0_MASK 0x1u
-#define DMA_ERR_ERR0_SHIFT 0
-#define DMA_ERR_ERR0_WIDTH 1
-#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
-#define DMA_ERR_ERR1_MASK 0x2u
-#define DMA_ERR_ERR1_SHIFT 1
-#define DMA_ERR_ERR1_WIDTH 1
-#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
-#define DMA_ERR_ERR2_MASK 0x4u
-#define DMA_ERR_ERR2_SHIFT 2
-#define DMA_ERR_ERR2_WIDTH 1
-#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
-#define DMA_ERR_ERR3_MASK 0x8u
-#define DMA_ERR_ERR3_SHIFT 3
-#define DMA_ERR_ERR3_WIDTH 1
-#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
-#define DMA_ERR_ERR4_MASK 0x10u
-#define DMA_ERR_ERR4_SHIFT 4
-#define DMA_ERR_ERR4_WIDTH 1
-#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
-#define DMA_ERR_ERR5_MASK 0x20u
-#define DMA_ERR_ERR5_SHIFT 5
-#define DMA_ERR_ERR5_WIDTH 1
-#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
-#define DMA_ERR_ERR6_MASK 0x40u
-#define DMA_ERR_ERR6_SHIFT 6
-#define DMA_ERR_ERR6_WIDTH 1
-#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
-#define DMA_ERR_ERR7_MASK 0x80u
-#define DMA_ERR_ERR7_SHIFT 7
-#define DMA_ERR_ERR7_WIDTH 1
-#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
-#define DMA_ERR_ERR8_MASK 0x100u
-#define DMA_ERR_ERR8_SHIFT 8
-#define DMA_ERR_ERR8_WIDTH 1
-#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
-#define DMA_ERR_ERR9_MASK 0x200u
-#define DMA_ERR_ERR9_SHIFT 9
-#define DMA_ERR_ERR9_WIDTH 1
-#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
-#define DMA_ERR_ERR10_MASK 0x400u
-#define DMA_ERR_ERR10_SHIFT 10
-#define DMA_ERR_ERR10_WIDTH 1
-#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
-#define DMA_ERR_ERR11_MASK 0x800u
-#define DMA_ERR_ERR11_SHIFT 11
-#define DMA_ERR_ERR11_WIDTH 1
-#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
-#define DMA_ERR_ERR12_MASK 0x1000u
-#define DMA_ERR_ERR12_SHIFT 12
-#define DMA_ERR_ERR12_WIDTH 1
-#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
-#define DMA_ERR_ERR13_MASK 0x2000u
-#define DMA_ERR_ERR13_SHIFT 13
-#define DMA_ERR_ERR13_WIDTH 1
-#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
-#define DMA_ERR_ERR14_MASK 0x4000u
-#define DMA_ERR_ERR14_SHIFT 14
-#define DMA_ERR_ERR14_WIDTH 1
-#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
-#define DMA_ERR_ERR15_MASK 0x8000u
-#define DMA_ERR_ERR15_SHIFT 15
-#define DMA_ERR_ERR15_WIDTH 1
-#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
-/* HRS Bit Fields */
-#define DMA_HRS_HRS0_MASK 0x1u
-#define DMA_HRS_HRS0_SHIFT 0
-#define DMA_HRS_HRS0_WIDTH 1
-#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
-#define DMA_HRS_HRS1_MASK 0x2u
-#define DMA_HRS_HRS1_SHIFT 1
-#define DMA_HRS_HRS1_WIDTH 1
-#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
-#define DMA_HRS_HRS2_MASK 0x4u
-#define DMA_HRS_HRS2_SHIFT 2
-#define DMA_HRS_HRS2_WIDTH 1
-#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
-#define DMA_HRS_HRS3_MASK 0x8u
-#define DMA_HRS_HRS3_SHIFT 3
-#define DMA_HRS_HRS3_WIDTH 1
-#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
-#define DMA_HRS_HRS4_MASK 0x10u
-#define DMA_HRS_HRS4_SHIFT 4
-#define DMA_HRS_HRS4_WIDTH 1
-#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
-#define DMA_HRS_HRS5_MASK 0x20u
-#define DMA_HRS_HRS5_SHIFT 5
-#define DMA_HRS_HRS5_WIDTH 1
-#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
-#define DMA_HRS_HRS6_MASK 0x40u
-#define DMA_HRS_HRS6_SHIFT 6
-#define DMA_HRS_HRS6_WIDTH 1
-#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
-#define DMA_HRS_HRS7_MASK 0x80u
-#define DMA_HRS_HRS7_SHIFT 7
-#define DMA_HRS_HRS7_WIDTH 1
-#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
-#define DMA_HRS_HRS8_MASK 0x100u
-#define DMA_HRS_HRS8_SHIFT 8
-#define DMA_HRS_HRS8_WIDTH 1
-#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
-#define DMA_HRS_HRS9_MASK 0x200u
-#define DMA_HRS_HRS9_SHIFT 9
-#define DMA_HRS_HRS9_WIDTH 1
-#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
-#define DMA_HRS_HRS10_MASK 0x400u
-#define DMA_HRS_HRS10_SHIFT 10
-#define DMA_HRS_HRS10_WIDTH 1
-#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
-#define DMA_HRS_HRS11_MASK 0x800u
-#define DMA_HRS_HRS11_SHIFT 11
-#define DMA_HRS_HRS11_WIDTH 1
-#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
-#define DMA_HRS_HRS12_MASK 0x1000u
-#define DMA_HRS_HRS12_SHIFT 12
-#define DMA_HRS_HRS12_WIDTH 1
-#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
-#define DMA_HRS_HRS13_MASK 0x2000u
-#define DMA_HRS_HRS13_SHIFT 13
-#define DMA_HRS_HRS13_WIDTH 1
-#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
-#define DMA_HRS_HRS14_MASK 0x4000u
-#define DMA_HRS_HRS14_SHIFT 14
-#define DMA_HRS_HRS14_WIDTH 1
-#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
-#define DMA_HRS_HRS15_MASK 0x8000u
-#define DMA_HRS_HRS15_SHIFT 15
-#define DMA_HRS_HRS15_WIDTH 1
-#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
-/* DCHPRI3 Bit Fields */
-#define DMA_DCHPRI3_CHPRI_MASK 0xFu
-#define DMA_DCHPRI3_CHPRI_SHIFT 0
-#define DMA_DCHPRI3_CHPRI_WIDTH 4
-#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
-#define DMA_DCHPRI3_DPA_MASK 0x40u
-#define DMA_DCHPRI3_DPA_SHIFT 6
-#define DMA_DCHPRI3_DPA_WIDTH 1
-#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
-#define DMA_DCHPRI3_ECP_MASK 0x80u
-#define DMA_DCHPRI3_ECP_SHIFT 7
-#define DMA_DCHPRI3_ECP_WIDTH 1
-#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
-/* DCHPRI2 Bit Fields */
-#define DMA_DCHPRI2_CHPRI_MASK 0xFu
-#define DMA_DCHPRI2_CHPRI_SHIFT 0
-#define DMA_DCHPRI2_CHPRI_WIDTH 4
-#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
-#define DMA_DCHPRI2_DPA_MASK 0x40u
-#define DMA_DCHPRI2_DPA_SHIFT 6
-#define DMA_DCHPRI2_DPA_WIDTH 1
-#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
-#define DMA_DCHPRI2_ECP_MASK 0x80u
-#define DMA_DCHPRI2_ECP_SHIFT 7
-#define DMA_DCHPRI2_ECP_WIDTH 1
-#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
-/* DCHPRI1 Bit Fields */
-#define DMA_DCHPRI1_CHPRI_MASK 0xFu
-#define DMA_DCHPRI1_CHPRI_SHIFT 0
-#define DMA_DCHPRI1_CHPRI_WIDTH 4
-#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
-#define DMA_DCHPRI1_DPA_MASK 0x40u
-#define DMA_DCHPRI1_DPA_SHIFT 6
-#define DMA_DCHPRI1_DPA_WIDTH 1
-#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
-#define DMA_DCHPRI1_ECP_MASK 0x80u
-#define DMA_DCHPRI1_ECP_SHIFT 7
-#define DMA_DCHPRI1_ECP_WIDTH 1
-#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
-/* DCHPRI0 Bit Fields */
-#define DMA_DCHPRI0_CHPRI_MASK 0xFu
-#define DMA_DCHPRI0_CHPRI_SHIFT 0
-#define DMA_DCHPRI0_CHPRI_WIDTH 4
-#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
-#define DMA_DCHPRI0_DPA_MASK 0x40u
-#define DMA_DCHPRI0_DPA_SHIFT 6
-#define DMA_DCHPRI0_DPA_WIDTH 1
-#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
-#define DMA_DCHPRI0_ECP_MASK 0x80u
-#define DMA_DCHPRI0_ECP_SHIFT 7
-#define DMA_DCHPRI0_ECP_WIDTH 1
-#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
-/* DCHPRI7 Bit Fields */
-#define DMA_DCHPRI7_CHPRI_MASK 0xFu
-#define DMA_DCHPRI7_CHPRI_SHIFT 0
-#define DMA_DCHPRI7_CHPRI_WIDTH 4
-#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
-#define DMA_DCHPRI7_DPA_MASK 0x40u
-#define DMA_DCHPRI7_DPA_SHIFT 6
-#define DMA_DCHPRI7_DPA_WIDTH 1
-#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
-#define DMA_DCHPRI7_ECP_MASK 0x80u
-#define DMA_DCHPRI7_ECP_SHIFT 7
-#define DMA_DCHPRI7_ECP_WIDTH 1
-#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
-/* DCHPRI6 Bit Fields */
-#define DMA_DCHPRI6_CHPRI_MASK 0xFu
-#define DMA_DCHPRI6_CHPRI_SHIFT 0
-#define DMA_DCHPRI6_CHPRI_WIDTH 4
-#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
-#define DMA_DCHPRI6_DPA_MASK 0x40u
-#define DMA_DCHPRI6_DPA_SHIFT 6
-#define DMA_DCHPRI6_DPA_WIDTH 1
-#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
-#define DMA_DCHPRI6_ECP_MASK 0x80u
-#define DMA_DCHPRI6_ECP_SHIFT 7
-#define DMA_DCHPRI6_ECP_WIDTH 1
-#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
-/* DCHPRI5 Bit Fields */
-#define DMA_DCHPRI5_CHPRI_MASK 0xFu
-#define DMA_DCHPRI5_CHPRI_SHIFT 0
-#define DMA_DCHPRI5_CHPRI_WIDTH 4
-#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
-#define DMA_DCHPRI5_DPA_MASK 0x40u
-#define DMA_DCHPRI5_DPA_SHIFT 6
-#define DMA_DCHPRI5_DPA_WIDTH 1
-#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
-#define DMA_DCHPRI5_ECP_MASK 0x80u
-#define DMA_DCHPRI5_ECP_SHIFT 7
-#define DMA_DCHPRI5_ECP_WIDTH 1
-#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
-/* DCHPRI4 Bit Fields */
-#define DMA_DCHPRI4_CHPRI_MASK 0xFu
-#define DMA_DCHPRI4_CHPRI_SHIFT 0
-#define DMA_DCHPRI4_CHPRI_WIDTH 4
-#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
-#define DMA_DCHPRI4_DPA_MASK 0x40u
-#define DMA_DCHPRI4_DPA_SHIFT 6
-#define DMA_DCHPRI4_DPA_WIDTH 1
-#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
-#define DMA_DCHPRI4_ECP_MASK 0x80u
-#define DMA_DCHPRI4_ECP_SHIFT 7
-#define DMA_DCHPRI4_ECP_WIDTH 1
-#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
-/* DCHPRI11 Bit Fields */
-#define DMA_DCHPRI11_CHPRI_MASK 0xFu
-#define DMA_DCHPRI11_CHPRI_SHIFT 0
-#define DMA_DCHPRI11_CHPRI_WIDTH 4
-#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
-#define DMA_DCHPRI11_DPA_MASK 0x40u
-#define DMA_DCHPRI11_DPA_SHIFT 6
-#define DMA_DCHPRI11_DPA_WIDTH 1
-#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
-#define DMA_DCHPRI11_ECP_MASK 0x80u
-#define DMA_DCHPRI11_ECP_SHIFT 7
-#define DMA_DCHPRI11_ECP_WIDTH 1
-#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
-/* DCHPRI10 Bit Fields */
-#define DMA_DCHPRI10_CHPRI_MASK 0xFu
-#define DMA_DCHPRI10_CHPRI_SHIFT 0
-#define DMA_DCHPRI10_CHPRI_WIDTH 4
-#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
-#define DMA_DCHPRI10_DPA_MASK 0x40u
-#define DMA_DCHPRI10_DPA_SHIFT 6
-#define DMA_DCHPRI10_DPA_WIDTH 1
-#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
-#define DMA_DCHPRI10_ECP_MASK 0x80u
-#define DMA_DCHPRI10_ECP_SHIFT 7
-#define DMA_DCHPRI10_ECP_WIDTH 1
-#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
-/* DCHPRI9 Bit Fields */
-#define DMA_DCHPRI9_CHPRI_MASK 0xFu
-#define DMA_DCHPRI9_CHPRI_SHIFT 0
-#define DMA_DCHPRI9_CHPRI_WIDTH 4
-#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
-#define DMA_DCHPRI9_DPA_MASK 0x40u
-#define DMA_DCHPRI9_DPA_SHIFT 6
-#define DMA_DCHPRI9_DPA_WIDTH 1
-#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
-#define DMA_DCHPRI9_ECP_MASK 0x80u
-#define DMA_DCHPRI9_ECP_SHIFT 7
-#define DMA_DCHPRI9_ECP_WIDTH 1
-#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
-/* DCHPRI8 Bit Fields */
-#define DMA_DCHPRI8_CHPRI_MASK 0xFu
-#define DMA_DCHPRI8_CHPRI_SHIFT 0
-#define DMA_DCHPRI8_CHPRI_WIDTH 4
-#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
-#define DMA_DCHPRI8_DPA_MASK 0x40u
-#define DMA_DCHPRI8_DPA_SHIFT 6
-#define DMA_DCHPRI8_DPA_WIDTH 1
-#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
-#define DMA_DCHPRI8_ECP_MASK 0x80u
-#define DMA_DCHPRI8_ECP_SHIFT 7
-#define DMA_DCHPRI8_ECP_WIDTH 1
-#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
-/* DCHPRI15 Bit Fields */
-#define DMA_DCHPRI15_CHPRI_MASK 0xFu
-#define DMA_DCHPRI15_CHPRI_SHIFT 0
-#define DMA_DCHPRI15_CHPRI_WIDTH 4
-#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
-#define DMA_DCHPRI15_DPA_MASK 0x40u
-#define DMA_DCHPRI15_DPA_SHIFT 6
-#define DMA_DCHPRI15_DPA_WIDTH 1
-#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
-#define DMA_DCHPRI15_ECP_MASK 0x80u
-#define DMA_DCHPRI15_ECP_SHIFT 7
-#define DMA_DCHPRI15_ECP_WIDTH 1
-#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
-/* DCHPRI14 Bit Fields */
-#define DMA_DCHPRI14_CHPRI_MASK 0xFu
-#define DMA_DCHPRI14_CHPRI_SHIFT 0
-#define DMA_DCHPRI14_CHPRI_WIDTH 4
-#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
-#define DMA_DCHPRI14_DPA_MASK 0x40u
-#define DMA_DCHPRI14_DPA_SHIFT 6
-#define DMA_DCHPRI14_DPA_WIDTH 1
-#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
-#define DMA_DCHPRI14_ECP_MASK 0x80u
-#define DMA_DCHPRI14_ECP_SHIFT 7
-#define DMA_DCHPRI14_ECP_WIDTH 1
-#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
-/* DCHPRI13 Bit Fields */
-#define DMA_DCHPRI13_CHPRI_MASK 0xFu
-#define DMA_DCHPRI13_CHPRI_SHIFT 0
-#define DMA_DCHPRI13_CHPRI_WIDTH 4
-#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
-#define DMA_DCHPRI13_DPA_MASK 0x40u
-#define DMA_DCHPRI13_DPA_SHIFT 6
-#define DMA_DCHPRI13_DPA_WIDTH 1
-#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
-#define DMA_DCHPRI13_ECP_MASK 0x80u
-#define DMA_DCHPRI13_ECP_SHIFT 7
-#define DMA_DCHPRI13_ECP_WIDTH 1
-#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
-/* DCHPRI12 Bit Fields */
-#define DMA_DCHPRI12_CHPRI_MASK 0xFu
-#define DMA_DCHPRI12_CHPRI_SHIFT 0
-#define DMA_DCHPRI12_CHPRI_WIDTH 4
-#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
-#define DMA_DCHPRI12_DPA_MASK 0x40u
-#define DMA_DCHPRI12_DPA_SHIFT 6
-#define DMA_DCHPRI12_DPA_WIDTH 1
-#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
-#define DMA_DCHPRI12_ECP_MASK 0x80u
-#define DMA_DCHPRI12_ECP_SHIFT 7
-#define DMA_DCHPRI12_ECP_WIDTH 1
-#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
-/* SADDR Bit Fields */
-#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
-#define DMA_SADDR_SADDR_SHIFT 0
-#define DMA_SADDR_SADDR_WIDTH 32
-#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
-/* SOFF Bit Fields */
-#define DMA_SOFF_SOFF_MASK 0xFFFFu
-#define DMA_SOFF_SOFF_SHIFT 0
-#define DMA_SOFF_SOFF_WIDTH 16
-#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
-/* ATTR Bit Fields */
-#define DMA_ATTR_DSIZE_MASK 0x7u
-#define DMA_ATTR_DSIZE_SHIFT 0
-#define DMA_ATTR_DSIZE_WIDTH 3
-#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
-#define DMA_ATTR_DMOD_MASK 0xF8u
-#define DMA_ATTR_DMOD_SHIFT 3
-#define DMA_ATTR_DMOD_WIDTH 5
-#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
-#define DMA_ATTR_SSIZE_MASK 0x700u
-#define DMA_ATTR_SSIZE_SHIFT 8
-#define DMA_ATTR_SSIZE_WIDTH 3
-#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
-#define DMA_ATTR_SMOD_MASK 0xF800u
-#define DMA_ATTR_SMOD_SHIFT 11
-#define DMA_ATTR_SMOD_WIDTH 5
-#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
-/* NBYTES_MLNO Bit Fields */
-#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
-#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLNO_NBYTES_WIDTH 32
-#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
-/* NBYTES_MLOFFNO Bit Fields */
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
-#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH 30
-#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
-#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
-#define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
-/* NBYTES_MLOFFYES Bit Fields */
-#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
-#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
-#define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH 10
-#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
-#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
-#define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH 20
-#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
-#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
-#define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
-#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
-#define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH 1
-#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
-/* SLAST Bit Fields */
-#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
-#define DMA_SLAST_SLAST_SHIFT 0
-#define DMA_SLAST_SLAST_WIDTH 32
-#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
-/* DADDR Bit Fields */
-#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
-#define DMA_DADDR_DADDR_SHIFT 0
-#define DMA_DADDR_DADDR_WIDTH 32
-#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
-/* DOFF Bit Fields */
-#define DMA_DOFF_DOFF_MASK 0xFFFFu
-#define DMA_DOFF_DOFF_SHIFT 0
-#define DMA_DOFF_DOFF_WIDTH 16
-#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
-/* CITER_ELINKNO Bit Fields */
-#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
-#define DMA_CITER_ELINKNO_CITER_SHIFT 0
-#define DMA_CITER_ELINKNO_CITER_WIDTH 15
-#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
-#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
-#define DMA_CITER_ELINKNO_ELINK_WIDTH 1
-#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
-/* CITER_ELINKYES Bit Fields */
-#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
-#define DMA_CITER_ELINKYES_CITER_SHIFT 0
-#define DMA_CITER_ELINKYES_CITER_WIDTH 9
-#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
-#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_CITER_ELINKYES_LINKCH_WIDTH 4
-#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
-#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
-#define DMA_CITER_ELINKYES_ELINK_WIDTH 1
-#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
-/* DLAST_SGA Bit Fields */
-#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
-#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
-#define DMA_DLAST_SGA_DLASTSGA_WIDTH 32
-#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
-/* CSR Bit Fields */
-#define DMA_CSR_START_MASK 0x1u
-#define DMA_CSR_START_SHIFT 0
-#define DMA_CSR_START_WIDTH 1
-#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
-#define DMA_CSR_INTMAJOR_MASK 0x2u
-#define DMA_CSR_INTMAJOR_SHIFT 1
-#define DMA_CSR_INTMAJOR_WIDTH 1
-#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
-#define DMA_CSR_INTHALF_MASK 0x4u
-#define DMA_CSR_INTHALF_SHIFT 2
-#define DMA_CSR_INTHALF_WIDTH 1
-#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
-#define DMA_CSR_DREQ_MASK 0x8u
-#define DMA_CSR_DREQ_SHIFT 3
-#define DMA_CSR_DREQ_WIDTH 1
-#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
-#define DMA_CSR_ESG_MASK 0x10u
-#define DMA_CSR_ESG_SHIFT 4
-#define DMA_CSR_ESG_WIDTH 1
-#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
-#define DMA_CSR_MAJORELINK_MASK 0x20u
-#define DMA_CSR_MAJORELINK_SHIFT 5
-#define DMA_CSR_MAJORELINK_WIDTH 1
-#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
-#define DMA_CSR_ACTIVE_MASK 0x40u
-#define DMA_CSR_ACTIVE_SHIFT 6
-#define DMA_CSR_ACTIVE_WIDTH 1
-#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
-#define DMA_CSR_DONE_MASK 0x80u
-#define DMA_CSR_DONE_SHIFT 7
-#define DMA_CSR_DONE_WIDTH 1
-#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
-#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
-#define DMA_CSR_MAJORLINKCH_SHIFT 8
-#define DMA_CSR_MAJORLINKCH_WIDTH 4
-#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
-#define DMA_CSR_BWC_MASK 0xC000u
-#define DMA_CSR_BWC_SHIFT 14
-#define DMA_CSR_BWC_WIDTH 2
-#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
-/* BITER_ELINKNO Bit Fields */
-#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
-#define DMA_BITER_ELINKNO_BITER_SHIFT 0
-#define DMA_BITER_ELINKNO_BITER_WIDTH 15
-#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
-#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
-#define DMA_BITER_ELINKNO_ELINK_WIDTH 1
-#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
-/* BITER_ELINKYES Bit Fields */
-#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
-#define DMA_BITER_ELINKYES_BITER_SHIFT 0
-#define DMA_BITER_ELINKYES_BITER_WIDTH 9
-#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
-#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
-#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
-#define DMA_BITER_ELINKYES_LINKCH_WIDTH 4
-#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
-#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
-#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
-#define DMA_BITER_ELINKYES_ELINK_WIDTH 1
-#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Masks */
+ */ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
@@ -5275,321 +3921,14 @@ typedef struct {
#define DMA_BASE (0x40008000u)
/** Peripheral DMA base pointer */
#define DMA0 ((DMA_Type *)DMA_BASE)
-#define DMA_BASE_PTR (DMA0)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0 }
/** Interrupt vectors for the DMA peripheral type */
-#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
#define DMA_ERROR_IRQS { DMA_Error_IRQn }
-/* ----------------------------------------------------------------------------
- -- DMA - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
- * @{
- */
-
-
-/* DMA - Register instance definitions */
-/* DMA */
-#define DMA_CR DMA_CR_REG(DMA0)
-#define DMA_ES DMA_ES_REG(DMA0)
-#define DMA_ERQ DMA_ERQ_REG(DMA0)
-#define DMA_EEI DMA_EEI_REG(DMA0)
-#define DMA_CEEI DMA_CEEI_REG(DMA0)
-#define DMA_SEEI DMA_SEEI_REG(DMA0)
-#define DMA_CERQ DMA_CERQ_REG(DMA0)
-#define DMA_SERQ DMA_SERQ_REG(DMA0)
-#define DMA_CDNE DMA_CDNE_REG(DMA0)
-#define DMA_SSRT DMA_SSRT_REG(DMA0)
-#define DMA_CERR DMA_CERR_REG(DMA0)
-#define DMA_CINT DMA_CINT_REG(DMA0)
-#define DMA_INT DMA_INT_REG(DMA0)
-#define DMA_ERR DMA_ERR_REG(DMA0)
-#define DMA_HRS DMA_HRS_REG(DMA0)
-#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
-#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
-#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
-#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
-#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
-#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
-#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
-#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
-#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
-#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
-#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
-#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
-#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
-#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
-#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
-#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
-#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
-#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
-#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
-#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
-#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
-#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
-#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
-#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
-#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
-#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
-#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
-#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
-#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
-#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
-#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
-#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
-#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
-#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
-#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
-#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
-#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
-#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
-#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
-#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
-#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
-#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
-#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
-#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
-#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
-#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
-#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
-#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
-#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
-#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
-#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
-#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
-#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
-#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
-#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
-#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
-#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
-#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
-#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
-#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
-#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
-#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
-#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
-#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
-#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
-#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
-#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
-#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
-#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
-#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
-#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
-#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
-#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
-#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
-#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
-#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
-#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
-#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
-#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
-#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
-#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
-#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
-#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
-#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
-#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
-#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
-#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
-#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
-#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
-#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
-#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
-#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
-#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
-#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
-#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
-#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
-#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
-#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
-#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
-#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
-#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
-#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
-#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
-#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
-#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
-#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
-#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
-#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
-#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
-#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
-#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
-#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
-#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
-#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
-#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
-#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
-#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
-#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
-#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
-#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
-#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
-#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
-#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
-#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
-#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
-#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
-#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
-#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
-#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
-#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
-#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
-#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
-#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
-#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
-#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
-#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
-#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
-#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
-#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
-#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
-#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
-#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
-#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
-#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
-#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
-#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
-#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
-#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
-#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
-#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
-#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
-#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
-#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
-#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
-#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
-#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
-#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
-#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
-#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
-#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
-#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
-
-/* DMA - Register array accessors */
-#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
-#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
-#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
-#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
-#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
-#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
-#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
-#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
-#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
-#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
-#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
-#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
-#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
-#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
-
-/*!
- * @}
- */ /* end of group DMA_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
@@ -5607,26 +3946,7 @@ typedef struct {
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type, *DMAMUX_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register accessors */
-#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
-#define DMAMUX_CHCFG_COUNT 16
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
+} DMAMUX_Type;
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
@@ -5637,19 +3957,20 @@ typedef struct {
* @{
*/
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE_WIDTH 6
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_TRIG_WIDTH 1
-#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-#define DMAMUX_CHCFG_ENBL_WIDTH 1
-#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
+#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
+#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT (16U)
+
/*!
* @}
@@ -5661,49 +3982,11 @@ typedef struct {
#define DMAMUX_BASE (0x40021000u)
/** Peripheral DMAMUX base pointer */
#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
-#define DMAMUX_BASE_PTR (DMAMUX)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX }
-/* ----------------------------------------------------------------------------
- -- DMAMUX - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
- * @{
- */
-
-
-/* DMAMUX - Register instance definitions */
-/* DMAMUX */
-#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
-#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
-#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
-#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
-#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
-#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
-#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
-#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
-#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
-#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
-#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
-#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
-#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
-#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
-#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
-#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
-
-/* DMAMUX - Register array accessors */
-#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
-
-/*!
- * @}
- */ /* end of group DMAMUX_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
@@ -5724,70 +4007,46 @@ typedef struct {
__O uint8_t SERV; /**< Service Register, offset: 0x1 */
__IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
-} EWM_Type, *EWM_MemMapPtr;
+} EWM_Type;
/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
+ -- EWM Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN_MASK (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT (0U)
+#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT (1U)
+#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK (0x4U)
+#define EWM_CTRL_INEN_SHIFT (2U)
+#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK (0x8U)
+#define EWM_CTRL_INTEN_SHIFT (3U)
+#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
-/* EWM - Register accessors */
-#define EWM_CTRL_REG(base) ((base)->CTRL)
-#define EWM_SERV_REG(base) ((base)->SERV)
-#define EWM_CMPL_REG(base) ((base)->CMPL)
-#define EWM_CMPH_REG(base) ((base)->CMPH)
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT (0U)
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- EWM Register Masks
- ---------------------------------------------------------------------------- */
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT (0U)
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
-/*!
- * @addtogroup EWM_Register_Masks EWM Register Masks
- * @{
- */
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT (0U)
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
-/* CTRL Bit Fields */
-#define EWM_CTRL_EWMEN_MASK 0x1u
-#define EWM_CTRL_EWMEN_SHIFT 0
-#define EWM_CTRL_EWMEN_WIDTH 1
-#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
-#define EWM_CTRL_ASSIN_MASK 0x2u
-#define EWM_CTRL_ASSIN_SHIFT 1
-#define EWM_CTRL_ASSIN_WIDTH 1
-#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
-#define EWM_CTRL_INEN_MASK 0x4u
-#define EWM_CTRL_INEN_SHIFT 2
-#define EWM_CTRL_INEN_WIDTH 1
-#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
-#define EWM_CTRL_INTEN_MASK 0x8u
-#define EWM_CTRL_INTEN_SHIFT 3
-#define EWM_CTRL_INTEN_WIDTH 1
-#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
-/* SERV Bit Fields */
-#define EWM_SERV_SERVICE_MASK 0xFFu
-#define EWM_SERV_SERVICE_SHIFT 0
-#define EWM_SERV_SERVICE_WIDTH 8
-#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
-/* CMPL Bit Fields */
-#define EWM_CMPL_COMPAREL_MASK 0xFFu
-#define EWM_CMPL_COMPAREL_SHIFT 0
-#define EWM_CMPL_COMPAREL_WIDTH 8
-#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
-/* CMPH Bit Fields */
-#define EWM_CMPH_COMPAREH_MASK 0xFFu
-#define EWM_CMPH_COMPAREH_SHIFT 0
-#define EWM_CMPH_COMPAREH_WIDTH 8
-#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
/*!
* @}
@@ -5799,7 +4058,6 @@ typedef struct {
#define EWM_BASE (0x40061000u)
/** Peripheral EWM base pointer */
#define EWM ((EWM_Type *)EWM_BASE)
-#define EWM_BASE_PTR (EWM)
/** Array initializer of EWM peripheral base addresses */
#define EWM_BASE_ADDRS { EWM_BASE }
/** Array initializer of EWM peripheral base pointers */
@@ -5807,28 +4065,6 @@ typedef struct {
/** Interrupt vectors for the EWM peripheral type */
#define EWM_IRQS { WDOG_EWM_IRQn }
-/* ----------------------------------------------------------------------------
- -- EWM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
- * @{
- */
-
-
-/* EWM - Register instance definitions */
-/* EWM */
-#define EWM_CTRL EWM_CTRL_REG(EWM)
-#define EWM_SERV EWM_SERV_REG(EWM)
-#define EWM_CMPL EWM_CMPL_REG(EWM)
-#define EWM_CMPH EWM_CMPH_REG(EWM)
-
-/*!
- * @}
- */ /* end of group EWM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group EWM_Peripheral_Access_Layer */
@@ -5852,31 +4088,7 @@ typedef struct {
} CS[6];
uint8_t RESERVED_0[24];
__IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
-} FB_Type, *FB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register accessors */
-#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
-#define FB_CSAR_COUNT 6
-#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
-#define FB_CSMR_COUNT 6
-#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
-#define FB_CSCR_COUNT 6
-#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
+} FB_Type;
/* ----------------------------------------------------------------------------
-- FB Register Masks
@@ -5887,98 +4099,89 @@ typedef struct {
* @{
*/
-/* CSAR Bit Fields */
-#define FB_CSAR_BA_MASK 0xFFFF0000u
-#define FB_CSAR_BA_SHIFT 16
-#define FB_CSAR_BA_WIDTH 16
-#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
-/* CSMR Bit Fields */
-#define FB_CSMR_V_MASK 0x1u
-#define FB_CSMR_V_SHIFT 0
-#define FB_CSMR_V_WIDTH 1
-#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_V_SHIFT))&FB_CSMR_V_MASK)
-#define FB_CSMR_WP_MASK 0x100u
-#define FB_CSMR_WP_SHIFT 8
-#define FB_CSMR_WP_WIDTH 1
-#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_WP_SHIFT))&FB_CSMR_WP_MASK)
-#define FB_CSMR_BAM_MASK 0xFFFF0000u
-#define FB_CSMR_BAM_SHIFT 16
-#define FB_CSMR_BAM_WIDTH 16
-#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
-/* CSCR Bit Fields */
-#define FB_CSCR_BSTW_MASK 0x8u
-#define FB_CSCR_BSTW_SHIFT 3
-#define FB_CSCR_BSTW_WIDTH 1
-#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTW_SHIFT))&FB_CSCR_BSTW_MASK)
-#define FB_CSCR_BSTR_MASK 0x10u
-#define FB_CSCR_BSTR_SHIFT 4
-#define FB_CSCR_BSTR_WIDTH 1
-#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BSTR_SHIFT))&FB_CSCR_BSTR_MASK)
-#define FB_CSCR_BEM_MASK 0x20u
-#define FB_CSCR_BEM_SHIFT 5
-#define FB_CSCR_BEM_WIDTH 1
-#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BEM_SHIFT))&FB_CSCR_BEM_MASK)
-#define FB_CSCR_PS_MASK 0xC0u
-#define FB_CSCR_PS_SHIFT 6
-#define FB_CSCR_PS_WIDTH 2
-#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
-#define FB_CSCR_AA_MASK 0x100u
-#define FB_CSCR_AA_SHIFT 8
-#define FB_CSCR_AA_WIDTH 1
-#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_AA_SHIFT))&FB_CSCR_AA_MASK)
-#define FB_CSCR_BLS_MASK 0x200u
-#define FB_CSCR_BLS_SHIFT 9
-#define FB_CSCR_BLS_WIDTH 1
-#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_BLS_SHIFT))&FB_CSCR_BLS_MASK)
-#define FB_CSCR_WS_MASK 0xFC00u
-#define FB_CSCR_WS_SHIFT 10
-#define FB_CSCR_WS_WIDTH 6
-#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
-#define FB_CSCR_WRAH_MASK 0x30000u
-#define FB_CSCR_WRAH_SHIFT 16
-#define FB_CSCR_WRAH_WIDTH 2
-#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
-#define FB_CSCR_RDAH_MASK 0xC0000u
-#define FB_CSCR_RDAH_SHIFT 18
-#define FB_CSCR_RDAH_WIDTH 2
-#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
-#define FB_CSCR_ASET_MASK 0x300000u
-#define FB_CSCR_ASET_SHIFT 20
-#define FB_CSCR_ASET_WIDTH 2
-#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
-#define FB_CSCR_EXTS_MASK 0x400000u
-#define FB_CSCR_EXTS_SHIFT 22
-#define FB_CSCR_EXTS_WIDTH 1
-#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_EXTS_SHIFT))&FB_CSCR_EXTS_MASK)
-#define FB_CSCR_SWSEN_MASK 0x800000u
-#define FB_CSCR_SWSEN_SHIFT 23
-#define FB_CSCR_SWSEN_WIDTH 1
-#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWSEN_SHIFT))&FB_CSCR_SWSEN_MASK)
-#define FB_CSCR_SWS_MASK 0xFC000000u
-#define FB_CSCR_SWS_SHIFT 26
-#define FB_CSCR_SWS_WIDTH 6
-#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
-/* CSPMCR Bit Fields */
-#define FB_CSPMCR_GROUP5_MASK 0xF000u
-#define FB_CSPMCR_GROUP5_SHIFT 12
-#define FB_CSPMCR_GROUP5_WIDTH 4
-#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
-#define FB_CSPMCR_GROUP4_MASK 0xF0000u
-#define FB_CSPMCR_GROUP4_SHIFT 16
-#define FB_CSPMCR_GROUP4_WIDTH 4
-#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
-#define FB_CSPMCR_GROUP3_MASK 0xF00000u
-#define FB_CSPMCR_GROUP3_SHIFT 20
-#define FB_CSPMCR_GROUP3_WIDTH 4
-#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
-#define FB_CSPMCR_GROUP2_MASK 0xF000000u
-#define FB_CSPMCR_GROUP2_SHIFT 24
-#define FB_CSPMCR_GROUP2_WIDTH 4
-#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
-#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
-#define FB_CSPMCR_GROUP1_SHIFT 28
-#define FB_CSPMCR_GROUP1_WIDTH 4
-#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+/*! @name CSAR - Chip Select Address Register */
+#define FB_CSAR_BA_MASK (0xFFFF0000U)
+#define FB_CSAR_BA_SHIFT (16U)
+#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+
+/* The count of FB_CSAR */
+#define FB_CSAR_COUNT (6U)
+
+/*! @name CSMR - Chip Select Mask Register */
+#define FB_CSMR_V_MASK (0x1U)
+#define FB_CSMR_V_SHIFT (0U)
+#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK (0x100U)
+#define FB_CSMR_WP_SHIFT (8U)
+#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK (0xFFFF0000U)
+#define FB_CSMR_BAM_SHIFT (16U)
+#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+
+/* The count of FB_CSMR */
+#define FB_CSMR_COUNT (6U)
+
+/*! @name CSCR - Chip Select Control Register */
+#define FB_CSCR_BSTW_MASK (0x8U)
+#define FB_CSCR_BSTW_SHIFT (3U)
+#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK (0x10U)
+#define FB_CSCR_BSTR_SHIFT (4U)
+#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK (0x20U)
+#define FB_CSCR_BEM_SHIFT (5U)
+#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK (0xC0U)
+#define FB_CSCR_PS_SHIFT (6U)
+#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK (0x100U)
+#define FB_CSCR_AA_SHIFT (8U)
+#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK (0x200U)
+#define FB_CSCR_BLS_SHIFT (9U)
+#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK (0xFC00U)
+#define FB_CSCR_WS_SHIFT (10U)
+#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK (0x30000U)
+#define FB_CSCR_WRAH_SHIFT (16U)
+#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK (0xC0000U)
+#define FB_CSCR_RDAH_SHIFT (18U)
+#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK (0x300000U)
+#define FB_CSCR_ASET_SHIFT (20U)
+#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK (0x400000U)
+#define FB_CSCR_EXTS_SHIFT (22U)
+#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK (0x800000U)
+#define FB_CSCR_SWSEN_SHIFT (23U)
+#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK (0xFC000000U)
+#define FB_CSCR_SWS_SHIFT (26U)
+#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+
+/* The count of FB_CSCR */
+#define FB_CSCR_COUNT (6U)
+
+/*! @name CSPMCR - Chip Select port Multiplexing Control Register */
+#define FB_CSPMCR_GROUP5_MASK (0xF000U)
+#define FB_CSPMCR_GROUP5_SHIFT (12U)
+#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
+#define FB_CSPMCR_GROUP4_SHIFT (16U)
+#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
+#define FB_CSPMCR_GROUP3_SHIFT (20U)
+#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
+#define FB_CSPMCR_GROUP2_SHIFT (24U)
+#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
+#define FB_CSPMCR_GROUP1_SHIFT (28U)
+#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+
/*!
* @}
@@ -5990,54 +4193,11 @@ typedef struct {
#define FB_BASE (0x4000C000u)
/** Peripheral FB base pointer */
#define FB ((FB_Type *)FB_BASE)
-#define FB_BASE_PTR (FB)
/** Array initializer of FB peripheral base addresses */
#define FB_BASE_ADDRS { FB_BASE }
/** Array initializer of FB peripheral base pointers */
#define FB_BASE_PTRS { FB }
-/* ----------------------------------------------------------------------------
- -- FB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
- * @{
- */
-
-
-/* FB - Register instance definitions */
-/* FB */
-#define FB_CSAR0 FB_CSAR_REG(FB,0)
-#define FB_CSMR0 FB_CSMR_REG(FB,0)
-#define FB_CSCR0 FB_CSCR_REG(FB,0)
-#define FB_CSAR1 FB_CSAR_REG(FB,1)
-#define FB_CSMR1 FB_CSMR_REG(FB,1)
-#define FB_CSCR1 FB_CSCR_REG(FB,1)
-#define FB_CSAR2 FB_CSAR_REG(FB,2)
-#define FB_CSMR2 FB_CSMR_REG(FB,2)
-#define FB_CSCR2 FB_CSCR_REG(FB,2)
-#define FB_CSAR3 FB_CSAR_REG(FB,3)
-#define FB_CSMR3 FB_CSMR_REG(FB,3)
-#define FB_CSCR3 FB_CSCR_REG(FB,3)
-#define FB_CSAR4 FB_CSAR_REG(FB,4)
-#define FB_CSMR4 FB_CSMR_REG(FB,4)
-#define FB_CSCR4 FB_CSCR_REG(FB,4)
-#define FB_CSAR5 FB_CSAR_REG(FB,5)
-#define FB_CSMR5 FB_CSMR_REG(FB,5)
-#define FB_CSCR5 FB_CSCR_REG(FB,5)
-#define FB_CSPMCR FB_CSPMCR_REG(FB)
-
-/* FB - Register array accessors */
-#define FB_CSAR(index) FB_CSAR_REG(FB,index)
-#define FB_CSMR(index) FB_CSMR_REG(FB,index)
-#define FB_CSCR(index) FB_CSCR_REG(FB,index)
-
-/*!
- * @}
- */ /* end of group FB_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FB_Peripheral_Access_Layer */
@@ -6069,47 +4229,7 @@ typedef struct {
__IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
__IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
} SET[4][4];
-} FMC_Type, *FMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register accessors */
-#define FMC_PFAPR_REG(base) ((base)->PFAPR)
-#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
-#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
-#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
-#define FMC_TAGVDW0S_COUNT 4
-#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
-#define FMC_TAGVDW1S_COUNT 4
-#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
-#define FMC_TAGVDW2S_COUNT 4
-#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
-#define FMC_TAGVDW3S_COUNT 4
-#define FMC_DATA_UM_REG(base,index,index2) ((base)->SET[index][index2].DATA_UM)
-#define FMC_DATA_UM_COUNT 4
-#define FMC_DATA_UM_COUNT2 4
-#define FMC_DATA_MU_REG(base,index,index2) ((base)->SET[index][index2].DATA_MU)
-#define FMC_DATA_MU_COUNT 4
-#define FMC_DATA_MU_COUNT2 4
-#define FMC_DATA_ML_REG(base,index,index2) ((base)->SET[index][index2].DATA_ML)
-#define FMC_DATA_ML_COUNT 4
-#define FMC_DATA_ML_COUNT2 4
-#define FMC_DATA_LM_REG(base,index,index2) ((base)->SET[index][index2].DATA_LM)
-#define FMC_DATA_LM_COUNT 4
-#define FMC_DATA_LM_COUNT2 4
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
+} FMC_Type;
/* ----------------------------------------------------------------------------
-- FMC Register Masks
@@ -6120,201 +4240,202 @@ typedef struct {
* @{
*/
-/* PFAPR Bit Fields */
-#define FMC_PFAPR_M0AP_MASK 0x3u
-#define FMC_PFAPR_M0AP_SHIFT 0
-#define FMC_PFAPR_M0AP_WIDTH 2
-#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
-#define FMC_PFAPR_M1AP_MASK 0xCu
-#define FMC_PFAPR_M1AP_SHIFT 2
-#define FMC_PFAPR_M1AP_WIDTH 2
-#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
-#define FMC_PFAPR_M2AP_MASK 0x30u
-#define FMC_PFAPR_M2AP_SHIFT 4
-#define FMC_PFAPR_M2AP_WIDTH 2
-#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
-#define FMC_PFAPR_M3AP_MASK 0xC0u
-#define FMC_PFAPR_M3AP_SHIFT 6
-#define FMC_PFAPR_M3AP_WIDTH 2
-#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
-#define FMC_PFAPR_M4AP_MASK 0x300u
-#define FMC_PFAPR_M4AP_SHIFT 8
-#define FMC_PFAPR_M4AP_WIDTH 2
-#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
-#define FMC_PFAPR_M5AP_MASK 0xC00u
-#define FMC_PFAPR_M5AP_SHIFT 10
-#define FMC_PFAPR_M5AP_WIDTH 2
-#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
-#define FMC_PFAPR_M6AP_MASK 0x3000u
-#define FMC_PFAPR_M6AP_SHIFT 12
-#define FMC_PFAPR_M6AP_WIDTH 2
-#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
-#define FMC_PFAPR_M7AP_MASK 0xC000u
-#define FMC_PFAPR_M7AP_SHIFT 14
-#define FMC_PFAPR_M7AP_WIDTH 2
-#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
-#define FMC_PFAPR_M0PFD_MASK 0x10000u
-#define FMC_PFAPR_M0PFD_SHIFT 16
-#define FMC_PFAPR_M0PFD_WIDTH 1
-#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
-#define FMC_PFAPR_M1PFD_MASK 0x20000u
-#define FMC_PFAPR_M1PFD_SHIFT 17
-#define FMC_PFAPR_M1PFD_WIDTH 1
-#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
-#define FMC_PFAPR_M2PFD_MASK 0x40000u
-#define FMC_PFAPR_M2PFD_SHIFT 18
-#define FMC_PFAPR_M2PFD_WIDTH 1
-#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
-#define FMC_PFAPR_M3PFD_MASK 0x80000u
-#define FMC_PFAPR_M3PFD_SHIFT 19
-#define FMC_PFAPR_M3PFD_WIDTH 1
-#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
-#define FMC_PFAPR_M4PFD_MASK 0x100000u
-#define FMC_PFAPR_M4PFD_SHIFT 20
-#define FMC_PFAPR_M4PFD_WIDTH 1
-#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
-#define FMC_PFAPR_M5PFD_MASK 0x200000u
-#define FMC_PFAPR_M5PFD_SHIFT 21
-#define FMC_PFAPR_M5PFD_WIDTH 1
-#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
-#define FMC_PFAPR_M6PFD_MASK 0x400000u
-#define FMC_PFAPR_M6PFD_SHIFT 22
-#define FMC_PFAPR_M6PFD_WIDTH 1
-#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
-#define FMC_PFAPR_M7PFD_MASK 0x800000u
-#define FMC_PFAPR_M7PFD_SHIFT 23
-#define FMC_PFAPR_M7PFD_WIDTH 1
-#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
-/* PFB0CR Bit Fields */
-#define FMC_PFB0CR_B0SEBE_MASK 0x1u
-#define FMC_PFB0CR_B0SEBE_SHIFT 0
-#define FMC_PFB0CR_B0SEBE_WIDTH 1
-#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
-#define FMC_PFB0CR_B0IPE_MASK 0x2u
-#define FMC_PFB0CR_B0IPE_SHIFT 1
-#define FMC_PFB0CR_B0IPE_WIDTH 1
-#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
-#define FMC_PFB0CR_B0DPE_MASK 0x4u
-#define FMC_PFB0CR_B0DPE_SHIFT 2
-#define FMC_PFB0CR_B0DPE_WIDTH 1
-#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
-#define FMC_PFB0CR_B0ICE_MASK 0x8u
-#define FMC_PFB0CR_B0ICE_SHIFT 3
-#define FMC_PFB0CR_B0ICE_WIDTH 1
-#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
-#define FMC_PFB0CR_B0DCE_MASK 0x10u
-#define FMC_PFB0CR_B0DCE_SHIFT 4
-#define FMC_PFB0CR_B0DCE_WIDTH 1
-#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
-#define FMC_PFB0CR_CRC_MASK 0xE0u
-#define FMC_PFB0CR_CRC_SHIFT 5
-#define FMC_PFB0CR_CRC_WIDTH 3
-#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
-#define FMC_PFB0CR_B0MW_MASK 0x60000u
-#define FMC_PFB0CR_B0MW_SHIFT 17
-#define FMC_PFB0CR_B0MW_WIDTH 2
-#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
-#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
-#define FMC_PFB0CR_S_B_INV_SHIFT 19
-#define FMC_PFB0CR_S_B_INV_WIDTH 1
-#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
-#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
-#define FMC_PFB0CR_CINV_WAY_SHIFT 20
-#define FMC_PFB0CR_CINV_WAY_WIDTH 4
-#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
-#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
-#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
-#define FMC_PFB0CR_CLCK_WAY_WIDTH 4
-#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
-#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
-#define FMC_PFB0CR_B0RWSC_SHIFT 28
-#define FMC_PFB0CR_B0RWSC_WIDTH 4
-#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
-/* PFB1CR Bit Fields */
-#define FMC_PFB1CR_B1SEBE_MASK 0x1u
-#define FMC_PFB1CR_B1SEBE_SHIFT 0
-#define FMC_PFB1CR_B1SEBE_WIDTH 1
-#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
-#define FMC_PFB1CR_B1IPE_MASK 0x2u
-#define FMC_PFB1CR_B1IPE_SHIFT 1
-#define FMC_PFB1CR_B1IPE_WIDTH 1
-#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
-#define FMC_PFB1CR_B1DPE_MASK 0x4u
-#define FMC_PFB1CR_B1DPE_SHIFT 2
-#define FMC_PFB1CR_B1DPE_WIDTH 1
-#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
-#define FMC_PFB1CR_B1ICE_MASK 0x8u
-#define FMC_PFB1CR_B1ICE_SHIFT 3
-#define FMC_PFB1CR_B1ICE_WIDTH 1
-#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
-#define FMC_PFB1CR_B1DCE_MASK 0x10u
-#define FMC_PFB1CR_B1DCE_SHIFT 4
-#define FMC_PFB1CR_B1DCE_WIDTH 1
-#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
-#define FMC_PFB1CR_B1MW_MASK 0x60000u
-#define FMC_PFB1CR_B1MW_SHIFT 17
-#define FMC_PFB1CR_B1MW_WIDTH 2
-#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
-#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
-#define FMC_PFB1CR_B1RWSC_SHIFT 28
-#define FMC_PFB1CR_B1RWSC_WIDTH 4
-#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
-/* TAGVDW0S Bit Fields */
-#define FMC_TAGVDW0S_valid_MASK 0x1u
-#define FMC_TAGVDW0S_valid_SHIFT 0
-#define FMC_TAGVDW0S_valid_WIDTH 1
-#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
-#define FMC_TAGVDW0S_cache_tag_MASK 0xFFFC0u
-#define FMC_TAGVDW0S_cache_tag_SHIFT 6
-#define FMC_TAGVDW0S_cache_tag_WIDTH 14
-#define FMC_TAGVDW0S_cache_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_cache_tag_SHIFT))&FMC_TAGVDW0S_cache_tag_MASK)
-/* TAGVDW1S Bit Fields */
-#define FMC_TAGVDW1S_valid_MASK 0x1u
-#define FMC_TAGVDW1S_valid_SHIFT 0
-#define FMC_TAGVDW1S_valid_WIDTH 1
-#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
-#define FMC_TAGVDW1S_cache_tag_MASK 0xFFFC0u
-#define FMC_TAGVDW1S_cache_tag_SHIFT 6
-#define FMC_TAGVDW1S_cache_tag_WIDTH 14
-#define FMC_TAGVDW1S_cache_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_cache_tag_SHIFT))&FMC_TAGVDW1S_cache_tag_MASK)
-/* TAGVDW2S Bit Fields */
-#define FMC_TAGVDW2S_valid_MASK 0x1u
-#define FMC_TAGVDW2S_valid_SHIFT 0
-#define FMC_TAGVDW2S_valid_WIDTH 1
-#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
-#define FMC_TAGVDW2S_cache_tag_MASK 0xFFFC0u
-#define FMC_TAGVDW2S_cache_tag_SHIFT 6
-#define FMC_TAGVDW2S_cache_tag_WIDTH 14
-#define FMC_TAGVDW2S_cache_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_cache_tag_SHIFT))&FMC_TAGVDW2S_cache_tag_MASK)
-/* TAGVDW3S Bit Fields */
-#define FMC_TAGVDW3S_valid_MASK 0x1u
-#define FMC_TAGVDW3S_valid_SHIFT 0
-#define FMC_TAGVDW3S_valid_WIDTH 1
-#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
-#define FMC_TAGVDW3S_cache_tag_MASK 0xFFFC0u
-#define FMC_TAGVDW3S_cache_tag_SHIFT 6
-#define FMC_TAGVDW3S_cache_tag_WIDTH 14
-#define FMC_TAGVDW3S_cache_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_cache_tag_SHIFT))&FMC_TAGVDW3S_cache_tag_MASK)
-/* DATA_UM Bit Fields */
-#define FMC_DATA_UM_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_UM_data_SHIFT 0
-#define FMC_DATA_UM_data_WIDTH 32
-#define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_UM_data_SHIFT))&FMC_DATA_UM_data_MASK)
-/* DATA_MU Bit Fields */
-#define FMC_DATA_MU_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_MU_data_SHIFT 0
-#define FMC_DATA_MU_data_WIDTH 32
-#define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_MU_data_SHIFT))&FMC_DATA_MU_data_MASK)
-/* DATA_ML Bit Fields */
-#define FMC_DATA_ML_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_ML_data_SHIFT 0
-#define FMC_DATA_ML_data_WIDTH 32
-#define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_ML_data_SHIFT))&FMC_DATA_ML_data_MASK)
-/* DATA_LM Bit Fields */
-#define FMC_DATA_LM_data_MASK 0xFFFFFFFFu
-#define FMC_DATA_LM_data_SHIFT 0
-#define FMC_DATA_LM_data_WIDTH 32
-#define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_LM_data_SHIFT))&FMC_DATA_LM_data_MASK)
+/*! @name PFAPR - Flash Access Protection Register */
+#define FMC_PFAPR_M0AP_MASK (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT (0U)
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT (2U)
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT (4U)
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT (6U)
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK (0x300U)
+#define FMC_PFAPR_M4AP_SHIFT (8U)
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK (0xC00U)
+#define FMC_PFAPR_M5AP_SHIFT (10U)
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK (0x3000U)
+#define FMC_PFAPR_M6AP_SHIFT (12U)
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK (0xC000U)
+#define FMC_PFAPR_M7AP_SHIFT (14U)
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK (0x10000U)
+#define FMC_PFAPR_M0PFD_SHIFT (16U)
+#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK (0x20000U)
+#define FMC_PFAPR_M1PFD_SHIFT (17U)
+#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK (0x40000U)
+#define FMC_PFAPR_M2PFD_SHIFT (18U)
+#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK (0x80000U)
+#define FMC_PFAPR_M3PFD_SHIFT (19U)
+#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK (0x100000U)
+#define FMC_PFAPR_M4PFD_SHIFT (20U)
+#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK (0x200000U)
+#define FMC_PFAPR_M5PFD_SHIFT (21U)
+#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK (0x400000U)
+#define FMC_PFAPR_M6PFD_SHIFT (22U)
+#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK (0x800000U)
+#define FMC_PFAPR_M7PFD_SHIFT (23U)
+#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+
+/*! @name PFB0CR - Flash Bank 0 Control Register */
+#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
+#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
+#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
+#define FMC_PFB0CR_B0IPE_MASK (0x2U)
+#define FMC_PFB0CR_B0IPE_SHIFT (1U)
+#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
+#define FMC_PFB0CR_B0DPE_MASK (0x4U)
+#define FMC_PFB0CR_B0DPE_SHIFT (2U)
+#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
+#define FMC_PFB0CR_B0ICE_MASK (0x8U)
+#define FMC_PFB0CR_B0ICE_SHIFT (3U)
+#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
+#define FMC_PFB0CR_B0DCE_MASK (0x10U)
+#define FMC_PFB0CR_B0DCE_SHIFT (4U)
+#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
+#define FMC_PFB0CR_CRC_MASK (0xE0U)
+#define FMC_PFB0CR_CRC_SHIFT (5U)
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK (0x60000U)
+#define FMC_PFB0CR_B0MW_SHIFT (17U)
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
+#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
+#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
+#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
+#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
+#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
+#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
+
+/*! @name PFB1CR - Flash Bank 1 Control Register */
+#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
+#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
+#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
+#define FMC_PFB1CR_B1IPE_MASK (0x2U)
+#define FMC_PFB1CR_B1IPE_SHIFT (1U)
+#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
+#define FMC_PFB1CR_B1DPE_MASK (0x4U)
+#define FMC_PFB1CR_B1DPE_SHIFT (2U)
+#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
+#define FMC_PFB1CR_B1ICE_MASK (0x8U)
+#define FMC_PFB1CR_B1ICE_SHIFT (3U)
+#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
+#define FMC_PFB1CR_B1DCE_MASK (0x10U)
+#define FMC_PFB1CR_B1DCE_SHIFT (4U)
+#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
+#define FMC_PFB1CR_B1MW_MASK (0x60000U)
+#define FMC_PFB1CR_B1MW_SHIFT (17U)
+#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
+#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
+#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
+
+/*! @name TAGVDW0S - Cache Tag Storage */
+#define FMC_TAGVDW0S_valid_MASK (0x1U)
+#define FMC_TAGVDW0S_valid_SHIFT (0U)
+#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_cache_tag_MASK (0xFFFC0U)
+#define FMC_TAGVDW0S_cache_tag_SHIFT (6U)
+#define FMC_TAGVDW0S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_cache_tag_SHIFT)) & FMC_TAGVDW0S_cache_tag_MASK)
+
+/* The count of FMC_TAGVDW0S */
+#define FMC_TAGVDW0S_COUNT (4U)
+
+/*! @name TAGVDW1S - Cache Tag Storage */
+#define FMC_TAGVDW1S_valid_MASK (0x1U)
+#define FMC_TAGVDW1S_valid_SHIFT (0U)
+#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_cache_tag_MASK (0xFFFC0U)
+#define FMC_TAGVDW1S_cache_tag_SHIFT (6U)
+#define FMC_TAGVDW1S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_cache_tag_SHIFT)) & FMC_TAGVDW1S_cache_tag_MASK)
+
+/* The count of FMC_TAGVDW1S */
+#define FMC_TAGVDW1S_COUNT (4U)
+
+/*! @name TAGVDW2S - Cache Tag Storage */
+#define FMC_TAGVDW2S_valid_MASK (0x1U)
+#define FMC_TAGVDW2S_valid_SHIFT (0U)
+#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_cache_tag_MASK (0xFFFC0U)
+#define FMC_TAGVDW2S_cache_tag_SHIFT (6U)
+#define FMC_TAGVDW2S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_cache_tag_SHIFT)) & FMC_TAGVDW2S_cache_tag_MASK)
+
+/* The count of FMC_TAGVDW2S */
+#define FMC_TAGVDW2S_COUNT (4U)
+
+/*! @name TAGVDW3S - Cache Tag Storage */
+#define FMC_TAGVDW3S_valid_MASK (0x1U)
+#define FMC_TAGVDW3S_valid_SHIFT (0U)
+#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_cache_tag_MASK (0xFFFC0U)
+#define FMC_TAGVDW3S_cache_tag_SHIFT (6U)
+#define FMC_TAGVDW3S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_cache_tag_SHIFT)) & FMC_TAGVDW3S_cache_tag_MASK)
+
+/* The count of FMC_TAGVDW3S */
+#define FMC_TAGVDW3S_COUNT (4U)
+
+/*! @name DATA_UM - Cache Data Storage (uppermost word) */
+#define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_UM_data_SHIFT (0U)
+#define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
+
+/* The count of FMC_DATA_UM */
+#define FMC_DATA_UM_COUNT (4U)
+
+/* The count of FMC_DATA_UM */
+#define FMC_DATA_UM_COUNT2 (4U)
+
+/*! @name DATA_MU - Cache Data Storage (mid-upper word) */
+#define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_MU_data_SHIFT (0U)
+#define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
+
+/* The count of FMC_DATA_MU */
+#define FMC_DATA_MU_COUNT (4U)
+
+/* The count of FMC_DATA_MU */
+#define FMC_DATA_MU_COUNT2 (4U)
+
+/*! @name DATA_ML - Cache Data Storage (mid-lower word) */
+#define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_ML_data_SHIFT (0U)
+#define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
+
+/* The count of FMC_DATA_ML */
+#define FMC_DATA_ML_COUNT (4U)
+
+/* The count of FMC_DATA_ML */
+#define FMC_DATA_ML_COUNT2 (4U)
+
+/*! @name DATA_LM - Cache Data Storage (lowermost word) */
+#define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
+#define FMC_DATA_LM_data_SHIFT (0U)
+#define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
+
+/* The count of FMC_DATA_LM */
+#define FMC_DATA_LM_COUNT (4U)
+
+/* The count of FMC_DATA_LM */
+#define FMC_DATA_LM_COUNT2 (4U)
+
/*!
* @}
@@ -6326,123 +4447,11 @@ typedef struct {
#define FMC_BASE (0x4001F000u)
/** Peripheral FMC base pointer */
#define FMC ((FMC_Type *)FMC_BASE)
-#define FMC_BASE_PTR (FMC)
/** Array initializer of FMC peripheral base addresses */
#define FMC_BASE_ADDRS { FMC_BASE }
/** Array initializer of FMC peripheral base pointers */
#define FMC_BASE_PTRS { FMC }
-/* ----------------------------------------------------------------------------
- -- FMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
- * @{
- */
-
-
-/* FMC - Register instance definitions */
-/* FMC */
-#define FMC_PFAPR FMC_PFAPR_REG(FMC)
-#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
-#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
-#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
-#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
-#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
-#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
-#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
-#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
-#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
-#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
-#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
-#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
-#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
-#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
-#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
-#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
-#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
-#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
-#define FMC_DATAW0S0UM FMC_DATA_UM_REG(FMC,0,0)
-#define FMC_DATAW0S0MU FMC_DATA_MU_REG(FMC,0,0)
-#define FMC_DATAW0S0ML FMC_DATA_ML_REG(FMC,0,0)
-#define FMC_DATAW0S0LM FMC_DATA_LM_REG(FMC,0,0)
-#define FMC_DATAW0S1UM FMC_DATA_UM_REG(FMC,0,1)
-#define FMC_DATAW0S1MU FMC_DATA_MU_REG(FMC,0,1)
-#define FMC_DATAW0S1ML FMC_DATA_ML_REG(FMC,0,1)
-#define FMC_DATAW0S1LM FMC_DATA_LM_REG(FMC,0,1)
-#define FMC_DATAW0S2UM FMC_DATA_UM_REG(FMC,0,2)
-#define FMC_DATAW0S2MU FMC_DATA_MU_REG(FMC,0,2)
-#define FMC_DATAW0S2ML FMC_DATA_ML_REG(FMC,0,2)
-#define FMC_DATAW0S2LM FMC_DATA_LM_REG(FMC,0,2)
-#define FMC_DATAW0S3UM FMC_DATA_UM_REG(FMC,0,3)
-#define FMC_DATAW0S3MU FMC_DATA_MU_REG(FMC,0,3)
-#define FMC_DATAW0S3ML FMC_DATA_ML_REG(FMC,0,3)
-#define FMC_DATAW0S3LM FMC_DATA_LM_REG(FMC,0,3)
-#define FMC_DATAW1S0UM FMC_DATA_UM_REG(FMC,1,0)
-#define FMC_DATAW1S0MU FMC_DATA_MU_REG(FMC,1,0)
-#define FMC_DATAW1S0ML FMC_DATA_ML_REG(FMC,1,0)
-#define FMC_DATAW1S0LM FMC_DATA_LM_REG(FMC,1,0)
-#define FMC_DATAW1S1UM FMC_DATA_UM_REG(FMC,1,1)
-#define FMC_DATAW1S1MU FMC_DATA_MU_REG(FMC,1,1)
-#define FMC_DATAW1S1ML FMC_DATA_ML_REG(FMC,1,1)
-#define FMC_DATAW1S1LM FMC_DATA_LM_REG(FMC,1,1)
-#define FMC_DATAW1S2UM FMC_DATA_UM_REG(FMC,1,2)
-#define FMC_DATAW1S2MU FMC_DATA_MU_REG(FMC,1,2)
-#define FMC_DATAW1S2ML FMC_DATA_ML_REG(FMC,1,2)
-#define FMC_DATAW1S2LM FMC_DATA_LM_REG(FMC,1,2)
-#define FMC_DATAW1S3UM FMC_DATA_UM_REG(FMC,1,3)
-#define FMC_DATAW1S3MU FMC_DATA_MU_REG(FMC,1,3)
-#define FMC_DATAW1S3ML FMC_DATA_ML_REG(FMC,1,3)
-#define FMC_DATAW1S3LM FMC_DATA_LM_REG(FMC,1,3)
-#define FMC_DATAW2S0UM FMC_DATA_UM_REG(FMC,2,0)
-#define FMC_DATAW2S0MU FMC_DATA_MU_REG(FMC,2,0)
-#define FMC_DATAW2S0ML FMC_DATA_ML_REG(FMC,2,0)
-#define FMC_DATAW2S0LM FMC_DATA_LM_REG(FMC,2,0)
-#define FMC_DATAW2S1UM FMC_DATA_UM_REG(FMC,2,1)
-#define FMC_DATAW2S1MU FMC_DATA_MU_REG(FMC,2,1)
-#define FMC_DATAW2S1ML FMC_DATA_ML_REG(FMC,2,1)
-#define FMC_DATAW2S1LM FMC_DATA_LM_REG(FMC,2,1)
-#define FMC_DATAW2S2UM FMC_DATA_UM_REG(FMC,2,2)
-#define FMC_DATAW2S2MU FMC_DATA_MU_REG(FMC,2,2)
-#define FMC_DATAW2S2ML FMC_DATA_ML_REG(FMC,2,2)
-#define FMC_DATAW2S2LM FMC_DATA_LM_REG(FMC,2,2)
-#define FMC_DATAW2S3UM FMC_DATA_UM_REG(FMC,2,3)
-#define FMC_DATAW2S3MU FMC_DATA_MU_REG(FMC,2,3)
-#define FMC_DATAW2S3ML FMC_DATA_ML_REG(FMC,2,3)
-#define FMC_DATAW2S3LM FMC_DATA_LM_REG(FMC,2,3)
-#define FMC_DATAW3S0UM FMC_DATA_UM_REG(FMC,3,0)
-#define FMC_DATAW3S0MU FMC_DATA_MU_REG(FMC,3,0)
-#define FMC_DATAW3S0ML FMC_DATA_ML_REG(FMC,3,0)
-#define FMC_DATAW3S0LM FMC_DATA_LM_REG(FMC,3,0)
-#define FMC_DATAW3S1UM FMC_DATA_UM_REG(FMC,3,1)
-#define FMC_DATAW3S1MU FMC_DATA_MU_REG(FMC,3,1)
-#define FMC_DATAW3S1ML FMC_DATA_ML_REG(FMC,3,1)
-#define FMC_DATAW3S1LM FMC_DATA_LM_REG(FMC,3,1)
-#define FMC_DATAW3S2UM FMC_DATA_UM_REG(FMC,3,2)
-#define FMC_DATAW3S2MU FMC_DATA_MU_REG(FMC,3,2)
-#define FMC_DATAW3S2ML FMC_DATA_ML_REG(FMC,3,2)
-#define FMC_DATAW3S2LM FMC_DATA_LM_REG(FMC,3,2)
-#define FMC_DATAW3S3UM FMC_DATA_UM_REG(FMC,3,3)
-#define FMC_DATAW3S3MU FMC_DATA_MU_REG(FMC,3,3)
-#define FMC_DATAW3S3ML FMC_DATA_ML_REG(FMC,3,3)
-#define FMC_DATAW3S3LM FMC_DATA_LM_REG(FMC,3,3)
-
-/* FMC - Register array accessors */
-#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
-#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
-#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
-#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
-#define FMC_DATA_UM(index,index2) FMC_DATA_UM_REG(FMC,index,index2)
-#define FMC_DATA_MU(index,index2) FMC_DATA_MU_REG(FMC,index,index2)
-#define FMC_DATA_ML(index,index2) FMC_DATA_ML_REG(FMC,index,index2)
-#define FMC_DATA_LM(index,index2) FMC_DATA_LM_REG(FMC,index,index2)
-
-/*!
- * @}
- */ /* end of group FMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FMC_Peripheral_Access_Layer */
@@ -6482,46 +4491,7 @@ typedef struct {
uint8_t RESERVED_0[2];
__IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
__IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
-} FTFE_Type, *FTFE_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTFE - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
- * @{
- */
-
-
-/* FTFE - Register accessors */
-#define FTFE_FSTAT_REG(base) ((base)->FSTAT)
-#define FTFE_FCNFG_REG(base) ((base)->FCNFG)
-#define FTFE_FSEC_REG(base) ((base)->FSEC)
-#define FTFE_FOPT_REG(base) ((base)->FOPT)
-#define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
-#define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
-#define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
-#define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
-#define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
-#define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
-#define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
-#define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
-#define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
-#define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
-#define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
-#define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
-#define FTFE_FPROT3_REG(base) ((base)->FPROT3)
-#define FTFE_FPROT2_REG(base) ((base)->FPROT2)
-#define FTFE_FPROT1_REG(base) ((base)->FPROT1)
-#define FTFE_FPROT0_REG(base) ((base)->FPROT0)
-#define FTFE_FEPROT_REG(base) ((base)->FEPROT)
-#define FTFE_FDPROT_REG(base) ((base)->FDPROT)
-
-/*!
- * @}
- */ /* end of group FTFE_Register_Accessor_Macros */
-
+} FTFE_Type;
/* ----------------------------------------------------------------------------
-- FTFE Register Masks
@@ -6532,172 +4502,158 @@ typedef struct {
* @{
*/
-/* FSTAT Bit Fields */
-#define FTFE_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFE_FSTAT_MGSTAT0_SHIFT 0
-#define FTFE_FSTAT_MGSTAT0_WIDTH 1
-#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_MGSTAT0_SHIFT))&FTFE_FSTAT_MGSTAT0_MASK)
-#define FTFE_FSTAT_FPVIOL_MASK 0x10u
-#define FTFE_FSTAT_FPVIOL_SHIFT 4
-#define FTFE_FSTAT_FPVIOL_WIDTH 1
-#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_FPVIOL_SHIFT))&FTFE_FSTAT_FPVIOL_MASK)
-#define FTFE_FSTAT_ACCERR_MASK 0x20u
-#define FTFE_FSTAT_ACCERR_SHIFT 5
-#define FTFE_FSTAT_ACCERR_WIDTH 1
-#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_ACCERR_SHIFT))&FTFE_FSTAT_ACCERR_MASK)
-#define FTFE_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFE_FSTAT_RDCOLERR_SHIFT 6
-#define FTFE_FSTAT_RDCOLERR_WIDTH 1
-#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_RDCOLERR_SHIFT))&FTFE_FSTAT_RDCOLERR_MASK)
-#define FTFE_FSTAT_CCIF_MASK 0x80u
-#define FTFE_FSTAT_CCIF_SHIFT 7
-#define FTFE_FSTAT_CCIF_WIDTH 1
-#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSTAT_CCIF_SHIFT))&FTFE_FSTAT_CCIF_MASK)
-/* FCNFG Bit Fields */
-#define FTFE_FCNFG_EEERDY_MASK 0x1u
-#define FTFE_FCNFG_EEERDY_SHIFT 0
-#define FTFE_FCNFG_EEERDY_WIDTH 1
-#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_EEERDY_SHIFT))&FTFE_FCNFG_EEERDY_MASK)
-#define FTFE_FCNFG_RAMRDY_MASK 0x2u
-#define FTFE_FCNFG_RAMRDY_SHIFT 1
-#define FTFE_FCNFG_RAMRDY_WIDTH 1
-#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RAMRDY_SHIFT))&FTFE_FCNFG_RAMRDY_MASK)
-#define FTFE_FCNFG_PFLSH_MASK 0x4u
-#define FTFE_FCNFG_PFLSH_SHIFT 2
-#define FTFE_FCNFG_PFLSH_WIDTH 1
-#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_PFLSH_SHIFT))&FTFE_FCNFG_PFLSH_MASK)
-#define FTFE_FCNFG_SWAP_MASK 0x8u
-#define FTFE_FCNFG_SWAP_SHIFT 3
-#define FTFE_FCNFG_SWAP_WIDTH 1
-#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_SWAP_SHIFT))&FTFE_FCNFG_SWAP_MASK)
-#define FTFE_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFE_FCNFG_ERSSUSP_SHIFT 4
-#define FTFE_FCNFG_ERSSUSP_WIDTH 1
-#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSSUSP_SHIFT))&FTFE_FCNFG_ERSSUSP_MASK)
-#define FTFE_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFE_FCNFG_ERSAREQ_SHIFT 5
-#define FTFE_FCNFG_ERSAREQ_WIDTH 1
-#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_ERSAREQ_SHIFT))&FTFE_FCNFG_ERSAREQ_MASK)
-#define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFE_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFE_FCNFG_RDCOLLIE_WIDTH 1
-#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_RDCOLLIE_SHIFT))&FTFE_FCNFG_RDCOLLIE_MASK)
-#define FTFE_FCNFG_CCIE_MASK 0x80u
-#define FTFE_FCNFG_CCIE_SHIFT 7
-#define FTFE_FCNFG_CCIE_WIDTH 1
-#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCNFG_CCIE_SHIFT))&FTFE_FCNFG_CCIE_MASK)
-/* FSEC Bit Fields */
-#define FTFE_FSEC_SEC_MASK 0x3u
-#define FTFE_FSEC_SEC_SHIFT 0
-#define FTFE_FSEC_SEC_WIDTH 2
-#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
-#define FTFE_FSEC_FSLACC_MASK 0xCu
-#define FTFE_FSEC_FSLACC_SHIFT 2
-#define FTFE_FSEC_FSLACC_WIDTH 2
-#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
-#define FTFE_FSEC_MEEN_MASK 0x30u
-#define FTFE_FSEC_MEEN_SHIFT 4
-#define FTFE_FSEC_MEEN_WIDTH 2
-#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
-#define FTFE_FSEC_KEYEN_MASK 0xC0u
-#define FTFE_FSEC_KEYEN_SHIFT 6
-#define FTFE_FSEC_KEYEN_WIDTH 2
-#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFE_FOPT_OPT_MASK 0xFFu
-#define FTFE_FOPT_OPT_SHIFT 0
-#define FTFE_FOPT_OPT_WIDTH 8
-#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFE_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB3_CCOBn_SHIFT 0
-#define FTFE_FCCOB3_CCOBn_WIDTH 8
-#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFE_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB2_CCOBn_SHIFT 0
-#define FTFE_FCCOB2_CCOBn_WIDTH 8
-#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFE_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB1_CCOBn_SHIFT 0
-#define FTFE_FCCOB1_CCOBn_WIDTH 8
-#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFE_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB0_CCOBn_SHIFT 0
-#define FTFE_FCCOB0_CCOBn_WIDTH 8
-#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFE_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB7_CCOBn_SHIFT 0
-#define FTFE_FCCOB7_CCOBn_WIDTH 8
-#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFE_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB6_CCOBn_SHIFT 0
-#define FTFE_FCCOB6_CCOBn_WIDTH 8
-#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFE_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB5_CCOBn_SHIFT 0
-#define FTFE_FCCOB5_CCOBn_WIDTH 8
-#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFE_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB4_CCOBn_SHIFT 0
-#define FTFE_FCCOB4_CCOBn_WIDTH 8
-#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFE_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFE_FCCOBB_CCOBn_SHIFT 0
-#define FTFE_FCCOBB_CCOBn_WIDTH 8
-#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFE_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFE_FCCOBA_CCOBn_SHIFT 0
-#define FTFE_FCCOBA_CCOBn_WIDTH 8
-#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFE_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB9_CCOBn_SHIFT 0
-#define FTFE_FCCOB9_CCOBn_WIDTH 8
-#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFE_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFE_FCCOB8_CCOBn_SHIFT 0
-#define FTFE_FCCOB8_CCOBn_WIDTH 8
-#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFE_FPROT3_PROT_MASK 0xFFu
-#define FTFE_FPROT3_PROT_SHIFT 0
-#define FTFE_FPROT3_PROT_WIDTH 8
-#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFE_FPROT2_PROT_MASK 0xFFu
-#define FTFE_FPROT2_PROT_SHIFT 0
-#define FTFE_FPROT2_PROT_WIDTH 8
-#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFE_FPROT1_PROT_MASK 0xFFu
-#define FTFE_FPROT1_PROT_SHIFT 0
-#define FTFE_FPROT1_PROT_WIDTH 8
-#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFE_FPROT0_PROT_MASK 0xFFu
-#define FTFE_FPROT0_PROT_SHIFT 0
-#define FTFE_FPROT0_PROT_WIDTH 8
-#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
-/* FEPROT Bit Fields */
-#define FTFE_FEPROT_EPROT_MASK 0xFFu
-#define FTFE_FEPROT_EPROT_SHIFT 0
-#define FTFE_FEPROT_EPROT_WIDTH 8
-#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define FTFE_FDPROT_DPROT_MASK 0xFFu
-#define FTFE_FDPROT_DPROT_SHIFT 0
-#define FTFE_FDPROT_DPROT_WIDTH 8
-#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
+/*! @name FSTAT - Flash Status Register */
+#define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
+#define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
+#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK (0x10U)
+#define FTFE_FSTAT_FPVIOL_SHIFT (4U)
+#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK (0x20U)
+#define FTFE_FSTAT_ACCERR_SHIFT (5U)
+#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
+#define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
+#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK (0x80U)
+#define FTFE_FSTAT_CCIF_SHIFT (7U)
+#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFE_FCNFG_EEERDY_MASK (0x1U)
+#define FTFE_FCNFG_EEERDY_SHIFT (0U)
+#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK (0x2U)
+#define FTFE_FCNFG_RAMRDY_SHIFT (1U)
+#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK (0x4U)
+#define FTFE_FCNFG_PFLSH_SHIFT (2U)
+#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK (0x8U)
+#define FTFE_FCNFG_SWAP_SHIFT (3U)
+#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
+#define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
+#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
+#define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
+#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
+#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
+#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK (0x80U)
+#define FTFE_FCNFG_CCIE_SHIFT (7U)
+#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFE_FSEC_SEC_MASK (0x3U)
+#define FTFE_FSEC_SEC_SHIFT (0U)
+#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK (0xCU)
+#define FTFE_FSEC_FSLACC_SHIFT (2U)
+#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK (0x30U)
+#define FTFE_FSEC_MEEN_SHIFT (4U)
+#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK (0xC0U)
+#define FTFE_FSEC_KEYEN_SHIFT (6U)
+#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFE_FOPT_OPT_MASK (0xFFU)
+#define FTFE_FOPT_OPT_SHIFT (0U)
+#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
+#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
+#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
+#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
+#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFE_FPROT3_PROT_MASK (0xFFU)
+#define FTFE_FPROT3_PROT_SHIFT (0U)
+#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFE_FPROT2_PROT_MASK (0xFFU)
+#define FTFE_FPROT2_PROT_SHIFT (0U)
+#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFE_FPROT1_PROT_MASK (0xFFU)
+#define FTFE_FPROT1_PROT_SHIFT (0U)
+#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFE_FPROT0_PROT_MASK (0xFFU)
+#define FTFE_FPROT0_PROT_SHIFT (0U)
+#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
+
+/*! @name FEPROT - EEPROM Protection Register */
+#define FTFE_FEPROT_EPROT_MASK (0xFFU)
+#define FTFE_FEPROT_EPROT_SHIFT (0U)
+#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Data Flash Protection Register */
+#define FTFE_FDPROT_DPROT_MASK (0xFFU)
+#define FTFE_FDPROT_DPROT_SHIFT (0U)
+#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
+
/*!
* @}
@@ -6709,7 +4665,6 @@ typedef struct {
#define FTFE_BASE (0x40020000u)
/** Peripheral FTFE base pointer */
#define FTFE ((FTFE_Type *)FTFE_BASE)
-#define FTFE_BASE_PTR (FTFE)
/** Array initializer of FTFE peripheral base addresses */
#define FTFE_BASE_ADDRS { FTFE_BASE }
/** Array initializer of FTFE peripheral base pointers */
@@ -6718,46 +4673,6 @@ typedef struct {
#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
-/* ----------------------------------------------------------------------------
- -- FTFE - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
- * @{
- */
-
-
-/* FTFE - Register instance definitions */
-/* FTFE */
-#define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
-#define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
-#define FTFE_FSEC FTFE_FSEC_REG(FTFE)
-#define FTFE_FOPT FTFE_FOPT_REG(FTFE)
-#define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
-#define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
-#define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
-#define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
-#define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
-#define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
-#define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
-#define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
-#define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
-#define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
-#define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
-#define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
-#define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
-#define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
-#define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
-#define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
-#define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
-#define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
-
-/*!
- * @}
- */ /* end of group FTFE_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FTFE_Peripheral_Access_Layer */
@@ -6801,51 +4716,7 @@ typedef struct {
__IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
__IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
__IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type, *FTM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register accessors */
-#define FTM_SC_REG(base) ((base)->SC)
-#define FTM_CNT_REG(base) ((base)->CNT)
-#define FTM_MOD_REG(base) ((base)->MOD)
-#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
-#define FTM_CnSC_COUNT 8
-#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
-#define FTM_CnV_COUNT 8
-#define FTM_CNTIN_REG(base) ((base)->CNTIN)
-#define FTM_STATUS_REG(base) ((base)->STATUS)
-#define FTM_MODE_REG(base) ((base)->MODE)
-#define FTM_SYNC_REG(base) ((base)->SYNC)
-#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
-#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
-#define FTM_COMBINE_REG(base) ((base)->COMBINE)
-#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
-#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
-#define FTM_POL_REG(base) ((base)->POL)
-#define FTM_FMS_REG(base) ((base)->FMS)
-#define FTM_FILTER_REG(base) ((base)->FILTER)
-#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
-#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
-#define FTM_CONF_REG(base) ((base)->CONF)
-#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
-#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
-#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
-#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
-#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
+} FTM_Type;
/* ----------------------------------------------------------------------------
-- FTM Register Masks
@@ -6856,755 +4727,605 @@ typedef struct {
* @{
*/
-/* SC Bit Fields */
-#define FTM_SC_PS_MASK 0x7u
-#define FTM_SC_PS_SHIFT 0
-#define FTM_SC_PS_WIDTH 3
-#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
-#define FTM_SC_CLKS_MASK 0x18u
-#define FTM_SC_CLKS_SHIFT 3
-#define FTM_SC_CLKS_WIDTH 2
-#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
-#define FTM_SC_CPWMS_MASK 0x20u
-#define FTM_SC_CPWMS_SHIFT 5
-#define FTM_SC_CPWMS_WIDTH 1
-#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
-#define FTM_SC_TOIE_MASK 0x40u
-#define FTM_SC_TOIE_SHIFT 6
-#define FTM_SC_TOIE_WIDTH 1
-#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
-#define FTM_SC_TOF_MASK 0x80u
-#define FTM_SC_TOF_SHIFT 7
-#define FTM_SC_TOF_WIDTH 1
-#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
-/* CNT Bit Fields */
-#define FTM_CNT_COUNT_MASK 0xFFFFu
-#define FTM_CNT_COUNT_SHIFT 0
-#define FTM_CNT_COUNT_WIDTH 16
-#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define FTM_MOD_MOD_MASK 0xFFFFu
-#define FTM_MOD_MOD_SHIFT 0
-#define FTM_MOD_MOD_WIDTH 16
-#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define FTM_CnSC_DMA_MASK 0x1u
-#define FTM_CnSC_DMA_SHIFT 0
-#define FTM_CnSC_DMA_WIDTH 1
-#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
-#define FTM_CnSC_ELSA_MASK 0x4u
-#define FTM_CnSC_ELSA_SHIFT 2
-#define FTM_CnSC_ELSA_WIDTH 1
-#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
-#define FTM_CnSC_ELSB_MASK 0x8u
-#define FTM_CnSC_ELSB_SHIFT 3
-#define FTM_CnSC_ELSB_WIDTH 1
-#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
-#define FTM_CnSC_MSA_MASK 0x10u
-#define FTM_CnSC_MSA_SHIFT 4
-#define FTM_CnSC_MSA_WIDTH 1
-#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
-#define FTM_CnSC_MSB_MASK 0x20u
-#define FTM_CnSC_MSB_SHIFT 5
-#define FTM_CnSC_MSB_WIDTH 1
-#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
-#define FTM_CnSC_CHIE_MASK 0x40u
-#define FTM_CnSC_CHIE_SHIFT 6
-#define FTM_CnSC_CHIE_WIDTH 1
-#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
-#define FTM_CnSC_CHF_MASK 0x80u
-#define FTM_CnSC_CHF_SHIFT 7
-#define FTM_CnSC_CHF_WIDTH 1
-#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
-/* CnV Bit Fields */
-#define FTM_CnV_VAL_MASK 0xFFFFu
-#define FTM_CnV_VAL_SHIFT 0
-#define FTM_CnV_VAL_WIDTH 16
-#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
-/* CNTIN Bit Fields */
-#define FTM_CNTIN_INIT_MASK 0xFFFFu
-#define FTM_CNTIN_INIT_SHIFT 0
-#define FTM_CNTIN_INIT_WIDTH 16
-#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
-/* STATUS Bit Fields */
-#define FTM_STATUS_CH0F_MASK 0x1u
-#define FTM_STATUS_CH0F_SHIFT 0
-#define FTM_STATUS_CH0F_WIDTH 1
-#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
-#define FTM_STATUS_CH1F_MASK 0x2u
-#define FTM_STATUS_CH1F_SHIFT 1
-#define FTM_STATUS_CH1F_WIDTH 1
-#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
-#define FTM_STATUS_CH2F_MASK 0x4u
-#define FTM_STATUS_CH2F_SHIFT 2
-#define FTM_STATUS_CH2F_WIDTH 1
-#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
-#define FTM_STATUS_CH3F_MASK 0x8u
-#define FTM_STATUS_CH3F_SHIFT 3
-#define FTM_STATUS_CH3F_WIDTH 1
-#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
-#define FTM_STATUS_CH4F_MASK 0x10u
-#define FTM_STATUS_CH4F_SHIFT 4
-#define FTM_STATUS_CH4F_WIDTH 1
-#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
-#define FTM_STATUS_CH5F_MASK 0x20u
-#define FTM_STATUS_CH5F_SHIFT 5
-#define FTM_STATUS_CH5F_WIDTH 1
-#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
-#define FTM_STATUS_CH6F_MASK 0x40u
-#define FTM_STATUS_CH6F_SHIFT 6
-#define FTM_STATUS_CH6F_WIDTH 1
-#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
-#define FTM_STATUS_CH7F_MASK 0x80u
-#define FTM_STATUS_CH7F_SHIFT 7
-#define FTM_STATUS_CH7F_WIDTH 1
-#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
-/* MODE Bit Fields */
-#define FTM_MODE_FTMEN_MASK 0x1u
-#define FTM_MODE_FTMEN_SHIFT 0
-#define FTM_MODE_FTMEN_WIDTH 1
-#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
-#define FTM_MODE_INIT_MASK 0x2u
-#define FTM_MODE_INIT_SHIFT 1
-#define FTM_MODE_INIT_WIDTH 1
-#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
-#define FTM_MODE_WPDIS_MASK 0x4u
-#define FTM_MODE_WPDIS_SHIFT 2
-#define FTM_MODE_WPDIS_WIDTH 1
-#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
-#define FTM_MODE_PWMSYNC_MASK 0x8u
-#define FTM_MODE_PWMSYNC_SHIFT 3
-#define FTM_MODE_PWMSYNC_WIDTH 1
-#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
-#define FTM_MODE_CAPTEST_MASK 0x10u
-#define FTM_MODE_CAPTEST_SHIFT 4
-#define FTM_MODE_CAPTEST_WIDTH 1
-#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
-#define FTM_MODE_FAULTM_MASK 0x60u
-#define FTM_MODE_FAULTM_SHIFT 5
-#define FTM_MODE_FAULTM_WIDTH 2
-#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
-#define FTM_MODE_FAULTIE_MASK 0x80u
-#define FTM_MODE_FAULTIE_SHIFT 7
-#define FTM_MODE_FAULTIE_WIDTH 1
-#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
-/* SYNC Bit Fields */
-#define FTM_SYNC_CNTMIN_MASK 0x1u
-#define FTM_SYNC_CNTMIN_SHIFT 0
-#define FTM_SYNC_CNTMIN_WIDTH 1
-#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
-#define FTM_SYNC_CNTMAX_MASK 0x2u
-#define FTM_SYNC_CNTMAX_SHIFT 1
-#define FTM_SYNC_CNTMAX_WIDTH 1
-#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
-#define FTM_SYNC_REINIT_MASK 0x4u
-#define FTM_SYNC_REINIT_SHIFT 2
-#define FTM_SYNC_REINIT_WIDTH 1
-#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
-#define FTM_SYNC_SYNCHOM_MASK 0x8u
-#define FTM_SYNC_SYNCHOM_SHIFT 3
-#define FTM_SYNC_SYNCHOM_WIDTH 1
-#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
-#define FTM_SYNC_TRIG0_MASK 0x10u
-#define FTM_SYNC_TRIG0_SHIFT 4
-#define FTM_SYNC_TRIG0_WIDTH 1
-#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
-#define FTM_SYNC_TRIG1_MASK 0x20u
-#define FTM_SYNC_TRIG1_SHIFT 5
-#define FTM_SYNC_TRIG1_WIDTH 1
-#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
-#define FTM_SYNC_TRIG2_MASK 0x40u
-#define FTM_SYNC_TRIG2_SHIFT 6
-#define FTM_SYNC_TRIG2_WIDTH 1
-#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
-#define FTM_SYNC_SWSYNC_MASK 0x80u
-#define FTM_SYNC_SWSYNC_SHIFT 7
-#define FTM_SYNC_SWSYNC_WIDTH 1
-#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
-/* OUTINIT Bit Fields */
-#define FTM_OUTINIT_CH0OI_MASK 0x1u
-#define FTM_OUTINIT_CH0OI_SHIFT 0
-#define FTM_OUTINIT_CH0OI_WIDTH 1
-#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
-#define FTM_OUTINIT_CH1OI_MASK 0x2u
-#define FTM_OUTINIT_CH1OI_SHIFT 1
-#define FTM_OUTINIT_CH1OI_WIDTH 1
-#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
-#define FTM_OUTINIT_CH2OI_MASK 0x4u
-#define FTM_OUTINIT_CH2OI_SHIFT 2
-#define FTM_OUTINIT_CH2OI_WIDTH 1
-#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
-#define FTM_OUTINIT_CH3OI_MASK 0x8u
-#define FTM_OUTINIT_CH3OI_SHIFT 3
-#define FTM_OUTINIT_CH3OI_WIDTH 1
-#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
-#define FTM_OUTINIT_CH4OI_MASK 0x10u
-#define FTM_OUTINIT_CH4OI_SHIFT 4
-#define FTM_OUTINIT_CH4OI_WIDTH 1
-#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
-#define FTM_OUTINIT_CH5OI_MASK 0x20u
-#define FTM_OUTINIT_CH5OI_SHIFT 5
-#define FTM_OUTINIT_CH5OI_WIDTH 1
-#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
-#define FTM_OUTINIT_CH6OI_MASK 0x40u
-#define FTM_OUTINIT_CH6OI_SHIFT 6
-#define FTM_OUTINIT_CH6OI_WIDTH 1
-#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
-#define FTM_OUTINIT_CH7OI_MASK 0x80u
-#define FTM_OUTINIT_CH7OI_SHIFT 7
-#define FTM_OUTINIT_CH7OI_WIDTH 1
-#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
-/* OUTMASK Bit Fields */
-#define FTM_OUTMASK_CH0OM_MASK 0x1u
-#define FTM_OUTMASK_CH0OM_SHIFT 0
-#define FTM_OUTMASK_CH0OM_WIDTH 1
-#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
-#define FTM_OUTMASK_CH1OM_MASK 0x2u
-#define FTM_OUTMASK_CH1OM_SHIFT 1
-#define FTM_OUTMASK_CH1OM_WIDTH 1
-#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
-#define FTM_OUTMASK_CH2OM_MASK 0x4u
-#define FTM_OUTMASK_CH2OM_SHIFT 2
-#define FTM_OUTMASK_CH2OM_WIDTH 1
-#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
-#define FTM_OUTMASK_CH3OM_MASK 0x8u
-#define FTM_OUTMASK_CH3OM_SHIFT 3
-#define FTM_OUTMASK_CH3OM_WIDTH 1
-#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
-#define FTM_OUTMASK_CH4OM_MASK 0x10u
-#define FTM_OUTMASK_CH4OM_SHIFT 4
-#define FTM_OUTMASK_CH4OM_WIDTH 1
-#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
-#define FTM_OUTMASK_CH5OM_MASK 0x20u
-#define FTM_OUTMASK_CH5OM_SHIFT 5
-#define FTM_OUTMASK_CH5OM_WIDTH 1
-#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
-#define FTM_OUTMASK_CH6OM_MASK 0x40u
-#define FTM_OUTMASK_CH6OM_SHIFT 6
-#define FTM_OUTMASK_CH6OM_WIDTH 1
-#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
-#define FTM_OUTMASK_CH7OM_MASK 0x80u
-#define FTM_OUTMASK_CH7OM_SHIFT 7
-#define FTM_OUTMASK_CH7OM_WIDTH 1
-#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
-/* COMBINE Bit Fields */
-#define FTM_COMBINE_COMBINE0_MASK 0x1u
-#define FTM_COMBINE_COMBINE0_SHIFT 0
-#define FTM_COMBINE_COMBINE0_WIDTH 1
-#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
-#define FTM_COMBINE_COMP0_MASK 0x2u
-#define FTM_COMBINE_COMP0_SHIFT 1
-#define FTM_COMBINE_COMP0_WIDTH 1
-#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
-#define FTM_COMBINE_DECAPEN0_MASK 0x4u
-#define FTM_COMBINE_DECAPEN0_SHIFT 2
-#define FTM_COMBINE_DECAPEN0_WIDTH 1
-#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
-#define FTM_COMBINE_DECAP0_MASK 0x8u
-#define FTM_COMBINE_DECAP0_SHIFT 3
-#define FTM_COMBINE_DECAP0_WIDTH 1
-#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
-#define FTM_COMBINE_DTEN0_MASK 0x10u
-#define FTM_COMBINE_DTEN0_SHIFT 4
-#define FTM_COMBINE_DTEN0_WIDTH 1
-#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
-#define FTM_COMBINE_SYNCEN0_MASK 0x20u
-#define FTM_COMBINE_SYNCEN0_SHIFT 5
-#define FTM_COMBINE_SYNCEN0_WIDTH 1
-#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
-#define FTM_COMBINE_FAULTEN0_MASK 0x40u
-#define FTM_COMBINE_FAULTEN0_SHIFT 6
-#define FTM_COMBINE_FAULTEN0_WIDTH 1
-#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
-#define FTM_COMBINE_COMBINE1_MASK 0x100u
-#define FTM_COMBINE_COMBINE1_SHIFT 8
-#define FTM_COMBINE_COMBINE1_WIDTH 1
-#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
-#define FTM_COMBINE_COMP1_MASK 0x200u
-#define FTM_COMBINE_COMP1_SHIFT 9
-#define FTM_COMBINE_COMP1_WIDTH 1
-#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
-#define FTM_COMBINE_DECAPEN1_MASK 0x400u
-#define FTM_COMBINE_DECAPEN1_SHIFT 10
-#define FTM_COMBINE_DECAPEN1_WIDTH 1
-#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
-#define FTM_COMBINE_DECAP1_MASK 0x800u
-#define FTM_COMBINE_DECAP1_SHIFT 11
-#define FTM_COMBINE_DECAP1_WIDTH 1
-#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
-#define FTM_COMBINE_DTEN1_MASK 0x1000u
-#define FTM_COMBINE_DTEN1_SHIFT 12
-#define FTM_COMBINE_DTEN1_WIDTH 1
-#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
-#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
-#define FTM_COMBINE_SYNCEN1_SHIFT 13
-#define FTM_COMBINE_SYNCEN1_WIDTH 1
-#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
-#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
-#define FTM_COMBINE_FAULTEN1_SHIFT 14
-#define FTM_COMBINE_FAULTEN1_WIDTH 1
-#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
-#define FTM_COMBINE_COMBINE2_MASK 0x10000u
-#define FTM_COMBINE_COMBINE2_SHIFT 16
-#define FTM_COMBINE_COMBINE2_WIDTH 1
-#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
-#define FTM_COMBINE_COMP2_MASK 0x20000u
-#define FTM_COMBINE_COMP2_SHIFT 17
-#define FTM_COMBINE_COMP2_WIDTH 1
-#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
-#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
-#define FTM_COMBINE_DECAPEN2_SHIFT 18
-#define FTM_COMBINE_DECAPEN2_WIDTH 1
-#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
-#define FTM_COMBINE_DECAP2_MASK 0x80000u
-#define FTM_COMBINE_DECAP2_SHIFT 19
-#define FTM_COMBINE_DECAP2_WIDTH 1
-#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
-#define FTM_COMBINE_DTEN2_MASK 0x100000u
-#define FTM_COMBINE_DTEN2_SHIFT 20
-#define FTM_COMBINE_DTEN2_WIDTH 1
-#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
-#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
-#define FTM_COMBINE_SYNCEN2_SHIFT 21
-#define FTM_COMBINE_SYNCEN2_WIDTH 1
-#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
-#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
-#define FTM_COMBINE_FAULTEN2_SHIFT 22
-#define FTM_COMBINE_FAULTEN2_WIDTH 1
-#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
-#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
-#define FTM_COMBINE_COMBINE3_SHIFT 24
-#define FTM_COMBINE_COMBINE3_WIDTH 1
-#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
-#define FTM_COMBINE_COMP3_MASK 0x2000000u
-#define FTM_COMBINE_COMP3_SHIFT 25
-#define FTM_COMBINE_COMP3_WIDTH 1
-#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
-#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
-#define FTM_COMBINE_DECAPEN3_SHIFT 26
-#define FTM_COMBINE_DECAPEN3_WIDTH 1
-#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
-#define FTM_COMBINE_DECAP3_MASK 0x8000000u
-#define FTM_COMBINE_DECAP3_SHIFT 27
-#define FTM_COMBINE_DECAP3_WIDTH 1
-#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
-#define FTM_COMBINE_DTEN3_MASK 0x10000000u
-#define FTM_COMBINE_DTEN3_SHIFT 28
-#define FTM_COMBINE_DTEN3_WIDTH 1
-#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
-#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
-#define FTM_COMBINE_SYNCEN3_SHIFT 29
-#define FTM_COMBINE_SYNCEN3_WIDTH 1
-#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
-#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
-#define FTM_COMBINE_FAULTEN3_SHIFT 30
-#define FTM_COMBINE_FAULTEN3_WIDTH 1
-#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
-/* DEADTIME Bit Fields */
-#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
-#define FTM_DEADTIME_DTVAL_SHIFT 0
-#define FTM_DEADTIME_DTVAL_WIDTH 6
-#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
-#define FTM_DEADTIME_DTPS_MASK 0xC0u
-#define FTM_DEADTIME_DTPS_SHIFT 6
-#define FTM_DEADTIME_DTPS_WIDTH 2
-#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
-/* EXTTRIG Bit Fields */
-#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
-#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
-#define FTM_EXTTRIG_CH2TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
-#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
-#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
-#define FTM_EXTTRIG_CH3TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
-#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
-#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
-#define FTM_EXTTRIG_CH4TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
-#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
-#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
-#define FTM_EXTTRIG_CH5TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
-#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
-#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
-#define FTM_EXTTRIG_CH0TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
-#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
-#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
-#define FTM_EXTTRIG_CH1TRIG_WIDTH 1
-#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
-#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
-#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
-#define FTM_EXTTRIG_INITTRIGEN_WIDTH 1
-#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
-#define FTM_EXTTRIG_TRIGF_MASK 0x80u
-#define FTM_EXTTRIG_TRIGF_SHIFT 7
-#define FTM_EXTTRIG_TRIGF_WIDTH 1
-#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
-/* POL Bit Fields */
-#define FTM_POL_POL0_MASK 0x1u
-#define FTM_POL_POL0_SHIFT 0
-#define FTM_POL_POL0_WIDTH 1
-#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
-#define FTM_POL_POL1_MASK 0x2u
-#define FTM_POL_POL1_SHIFT 1
-#define FTM_POL_POL1_WIDTH 1
-#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
-#define FTM_POL_POL2_MASK 0x4u
-#define FTM_POL_POL2_SHIFT 2
-#define FTM_POL_POL2_WIDTH 1
-#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
-#define FTM_POL_POL3_MASK 0x8u
-#define FTM_POL_POL3_SHIFT 3
-#define FTM_POL_POL3_WIDTH 1
-#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
-#define FTM_POL_POL4_MASK 0x10u
-#define FTM_POL_POL4_SHIFT 4
-#define FTM_POL_POL4_WIDTH 1
-#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
-#define FTM_POL_POL5_MASK 0x20u
-#define FTM_POL_POL5_SHIFT 5
-#define FTM_POL_POL5_WIDTH 1
-#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
-#define FTM_POL_POL6_MASK 0x40u
-#define FTM_POL_POL6_SHIFT 6
-#define FTM_POL_POL6_WIDTH 1
-#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
-#define FTM_POL_POL7_MASK 0x80u
-#define FTM_POL_POL7_SHIFT 7
-#define FTM_POL_POL7_WIDTH 1
-#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
-/* FMS Bit Fields */
-#define FTM_FMS_FAULTF0_MASK 0x1u
-#define FTM_FMS_FAULTF0_SHIFT 0
-#define FTM_FMS_FAULTF0_WIDTH 1
-#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
-#define FTM_FMS_FAULTF1_MASK 0x2u
-#define FTM_FMS_FAULTF1_SHIFT 1
-#define FTM_FMS_FAULTF1_WIDTH 1
-#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
-#define FTM_FMS_FAULTF2_MASK 0x4u
-#define FTM_FMS_FAULTF2_SHIFT 2
-#define FTM_FMS_FAULTF2_WIDTH 1
-#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
-#define FTM_FMS_FAULTF3_MASK 0x8u
-#define FTM_FMS_FAULTF3_SHIFT 3
-#define FTM_FMS_FAULTF3_WIDTH 1
-#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
-#define FTM_FMS_FAULTIN_MASK 0x20u
-#define FTM_FMS_FAULTIN_SHIFT 5
-#define FTM_FMS_FAULTIN_WIDTH 1
-#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
-#define FTM_FMS_WPEN_MASK 0x40u
-#define FTM_FMS_WPEN_SHIFT 6
-#define FTM_FMS_WPEN_WIDTH 1
-#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
-#define FTM_FMS_FAULTF_MASK 0x80u
-#define FTM_FMS_FAULTF_SHIFT 7
-#define FTM_FMS_FAULTF_WIDTH 1
-#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
-/* FILTER Bit Fields */
-#define FTM_FILTER_CH0FVAL_MASK 0xFu
-#define FTM_FILTER_CH0FVAL_SHIFT 0
-#define FTM_FILTER_CH0FVAL_WIDTH 4
-#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
-#define FTM_FILTER_CH1FVAL_MASK 0xF0u
-#define FTM_FILTER_CH1FVAL_SHIFT 4
-#define FTM_FILTER_CH1FVAL_WIDTH 4
-#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
-#define FTM_FILTER_CH2FVAL_MASK 0xF00u
-#define FTM_FILTER_CH2FVAL_SHIFT 8
-#define FTM_FILTER_CH2FVAL_WIDTH 4
-#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
-#define FTM_FILTER_CH3FVAL_MASK 0xF000u
-#define FTM_FILTER_CH3FVAL_SHIFT 12
-#define FTM_FILTER_CH3FVAL_WIDTH 4
-#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
-/* FLTCTRL Bit Fields */
-#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
-#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
-#define FTM_FLTCTRL_FAULT0EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
-#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
-#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
-#define FTM_FLTCTRL_FAULT1EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
-#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
-#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
-#define FTM_FLTCTRL_FAULT2EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
-#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
-#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
-#define FTM_FLTCTRL_FAULT3EN_WIDTH 1
-#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
-#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
-#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
-#define FTM_FLTCTRL_FFLTR0EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
-#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
-#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
-#define FTM_FLTCTRL_FFLTR1EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
-#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
-#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
-#define FTM_FLTCTRL_FFLTR2EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
-#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
-#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
-#define FTM_FLTCTRL_FFLTR3EN_WIDTH 1
-#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
-#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
-#define FTM_FLTCTRL_FFVAL_SHIFT 8
-#define FTM_FLTCTRL_FFVAL_WIDTH 4
-#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
-/* QDCTRL Bit Fields */
-#define FTM_QDCTRL_QUADEN_MASK 0x1u
-#define FTM_QDCTRL_QUADEN_SHIFT 0
-#define FTM_QDCTRL_QUADEN_WIDTH 1
-#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
-#define FTM_QDCTRL_TOFDIR_MASK 0x2u
-#define FTM_QDCTRL_TOFDIR_SHIFT 1
-#define FTM_QDCTRL_TOFDIR_WIDTH 1
-#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
-#define FTM_QDCTRL_QUADIR_MASK 0x4u
-#define FTM_QDCTRL_QUADIR_SHIFT 2
-#define FTM_QDCTRL_QUADIR_WIDTH 1
-#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
-#define FTM_QDCTRL_QUADMODE_MASK 0x8u
-#define FTM_QDCTRL_QUADMODE_SHIFT 3
-#define FTM_QDCTRL_QUADMODE_WIDTH 1
-#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
-#define FTM_QDCTRL_PHBPOL_MASK 0x10u
-#define FTM_QDCTRL_PHBPOL_SHIFT 4
-#define FTM_QDCTRL_PHBPOL_WIDTH 1
-#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
-#define FTM_QDCTRL_PHAPOL_MASK 0x20u
-#define FTM_QDCTRL_PHAPOL_SHIFT 5
-#define FTM_QDCTRL_PHAPOL_WIDTH 1
-#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
-#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
-#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
-#define FTM_QDCTRL_PHBFLTREN_WIDTH 1
-#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
-#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
-#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
-#define FTM_QDCTRL_PHAFLTREN_WIDTH 1
-#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
-/* CONF Bit Fields */
-#define FTM_CONF_NUMTOF_MASK 0x1Fu
-#define FTM_CONF_NUMTOF_SHIFT 0
-#define FTM_CONF_NUMTOF_WIDTH 5
-#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
-#define FTM_CONF_BDMMODE_MASK 0xC0u
-#define FTM_CONF_BDMMODE_SHIFT 6
-#define FTM_CONF_BDMMODE_WIDTH 2
-#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
-#define FTM_CONF_GTBEEN_MASK 0x200u
-#define FTM_CONF_GTBEEN_SHIFT 9
-#define FTM_CONF_GTBEEN_WIDTH 1
-#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
-#define FTM_CONF_GTBEOUT_MASK 0x400u
-#define FTM_CONF_GTBEOUT_SHIFT 10
-#define FTM_CONF_GTBEOUT_WIDTH 1
-#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
-/* FLTPOL Bit Fields */
-#define FTM_FLTPOL_FLT0POL_MASK 0x1u
-#define FTM_FLTPOL_FLT0POL_SHIFT 0
-#define FTM_FLTPOL_FLT0POL_WIDTH 1
-#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
-#define FTM_FLTPOL_FLT1POL_MASK 0x2u
-#define FTM_FLTPOL_FLT1POL_SHIFT 1
-#define FTM_FLTPOL_FLT1POL_WIDTH 1
-#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
-#define FTM_FLTPOL_FLT2POL_MASK 0x4u
-#define FTM_FLTPOL_FLT2POL_SHIFT 2
-#define FTM_FLTPOL_FLT2POL_WIDTH 1
-#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
-#define FTM_FLTPOL_FLT3POL_MASK 0x8u
-#define FTM_FLTPOL_FLT3POL_SHIFT 3
-#define FTM_FLTPOL_FLT3POL_WIDTH 1
-#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
-/* SYNCONF Bit Fields */
-#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
-#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
-#define FTM_SYNCONF_HWTRIGMODE_WIDTH 1
-#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
-#define FTM_SYNCONF_CNTINC_MASK 0x4u
-#define FTM_SYNCONF_CNTINC_SHIFT 2
-#define FTM_SYNCONF_CNTINC_WIDTH 1
-#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
-#define FTM_SYNCONF_INVC_MASK 0x10u
-#define FTM_SYNCONF_INVC_SHIFT 4
-#define FTM_SYNCONF_INVC_WIDTH 1
-#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
-#define FTM_SYNCONF_SWOC_MASK 0x20u
-#define FTM_SYNCONF_SWOC_SHIFT 5
-#define FTM_SYNCONF_SWOC_WIDTH 1
-#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
-#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
-#define FTM_SYNCONF_SYNCMODE_SHIFT 7
-#define FTM_SYNCONF_SYNCMODE_WIDTH 1
-#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
-#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
-#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
-#define FTM_SYNCONF_SWRSTCNT_WIDTH 1
-#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
-#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
-#define FTM_SYNCONF_SWWRBUF_SHIFT 9
-#define FTM_SYNCONF_SWWRBUF_WIDTH 1
-#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
-#define FTM_SYNCONF_SWOM_MASK 0x400u
-#define FTM_SYNCONF_SWOM_SHIFT 10
-#define FTM_SYNCONF_SWOM_WIDTH 1
-#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
-#define FTM_SYNCONF_SWINVC_MASK 0x800u
-#define FTM_SYNCONF_SWINVC_SHIFT 11
-#define FTM_SYNCONF_SWINVC_WIDTH 1
-#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
-#define FTM_SYNCONF_SWSOC_MASK 0x1000u
-#define FTM_SYNCONF_SWSOC_SHIFT 12
-#define FTM_SYNCONF_SWSOC_WIDTH 1
-#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
-#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
-#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
-#define FTM_SYNCONF_HWRSTCNT_WIDTH 1
-#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
-#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
-#define FTM_SYNCONF_HWWRBUF_SHIFT 17
-#define FTM_SYNCONF_HWWRBUF_WIDTH 1
-#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
-#define FTM_SYNCONF_HWOM_MASK 0x40000u
-#define FTM_SYNCONF_HWOM_SHIFT 18
-#define FTM_SYNCONF_HWOM_WIDTH 1
-#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
-#define FTM_SYNCONF_HWINVC_MASK 0x80000u
-#define FTM_SYNCONF_HWINVC_SHIFT 19
-#define FTM_SYNCONF_HWINVC_WIDTH 1
-#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
-#define FTM_SYNCONF_HWSOC_MASK 0x100000u
-#define FTM_SYNCONF_HWSOC_SHIFT 20
-#define FTM_SYNCONF_HWSOC_WIDTH 1
-#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
-/* INVCTRL Bit Fields */
-#define FTM_INVCTRL_INV0EN_MASK 0x1u
-#define FTM_INVCTRL_INV0EN_SHIFT 0
-#define FTM_INVCTRL_INV0EN_WIDTH 1
-#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
-#define FTM_INVCTRL_INV1EN_MASK 0x2u
-#define FTM_INVCTRL_INV1EN_SHIFT 1
-#define FTM_INVCTRL_INV1EN_WIDTH 1
-#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
-#define FTM_INVCTRL_INV2EN_MASK 0x4u
-#define FTM_INVCTRL_INV2EN_SHIFT 2
-#define FTM_INVCTRL_INV2EN_WIDTH 1
-#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
-#define FTM_INVCTRL_INV3EN_MASK 0x8u
-#define FTM_INVCTRL_INV3EN_SHIFT 3
-#define FTM_INVCTRL_INV3EN_WIDTH 1
-#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
-/* SWOCTRL Bit Fields */
-#define FTM_SWOCTRL_CH0OC_MASK 0x1u
-#define FTM_SWOCTRL_CH0OC_SHIFT 0
-#define FTM_SWOCTRL_CH0OC_WIDTH 1
-#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
-#define FTM_SWOCTRL_CH1OC_MASK 0x2u
-#define FTM_SWOCTRL_CH1OC_SHIFT 1
-#define FTM_SWOCTRL_CH1OC_WIDTH 1
-#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
-#define FTM_SWOCTRL_CH2OC_MASK 0x4u
-#define FTM_SWOCTRL_CH2OC_SHIFT 2
-#define FTM_SWOCTRL_CH2OC_WIDTH 1
-#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
-#define FTM_SWOCTRL_CH3OC_MASK 0x8u
-#define FTM_SWOCTRL_CH3OC_SHIFT 3
-#define FTM_SWOCTRL_CH3OC_WIDTH 1
-#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
-#define FTM_SWOCTRL_CH4OC_MASK 0x10u
-#define FTM_SWOCTRL_CH4OC_SHIFT 4
-#define FTM_SWOCTRL_CH4OC_WIDTH 1
-#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
-#define FTM_SWOCTRL_CH5OC_MASK 0x20u
-#define FTM_SWOCTRL_CH5OC_SHIFT 5
-#define FTM_SWOCTRL_CH5OC_WIDTH 1
-#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
-#define FTM_SWOCTRL_CH6OC_MASK 0x40u
-#define FTM_SWOCTRL_CH6OC_SHIFT 6
-#define FTM_SWOCTRL_CH6OC_WIDTH 1
-#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
-#define FTM_SWOCTRL_CH7OC_MASK 0x80u
-#define FTM_SWOCTRL_CH7OC_SHIFT 7
-#define FTM_SWOCTRL_CH7OC_WIDTH 1
-#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
-#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
-#define FTM_SWOCTRL_CH0OCV_SHIFT 8
-#define FTM_SWOCTRL_CH0OCV_WIDTH 1
-#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
-#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
-#define FTM_SWOCTRL_CH1OCV_SHIFT 9
-#define FTM_SWOCTRL_CH1OCV_WIDTH 1
-#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
-#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
-#define FTM_SWOCTRL_CH2OCV_SHIFT 10
-#define FTM_SWOCTRL_CH2OCV_WIDTH 1
-#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
-#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
-#define FTM_SWOCTRL_CH3OCV_SHIFT 11
-#define FTM_SWOCTRL_CH3OCV_WIDTH 1
-#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
-#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
-#define FTM_SWOCTRL_CH4OCV_SHIFT 12
-#define FTM_SWOCTRL_CH4OCV_WIDTH 1
-#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
-#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
-#define FTM_SWOCTRL_CH5OCV_SHIFT 13
-#define FTM_SWOCTRL_CH5OCV_WIDTH 1
-#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
-#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
-#define FTM_SWOCTRL_CH6OCV_SHIFT 14
-#define FTM_SWOCTRL_CH6OCV_WIDTH 1
-#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
-#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
-#define FTM_SWOCTRL_CH7OCV_SHIFT 15
-#define FTM_SWOCTRL_CH7OCV_WIDTH 1
-#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
-/* PWMLOAD Bit Fields */
-#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
-#define FTM_PWMLOAD_CH0SEL_SHIFT 0
-#define FTM_PWMLOAD_CH0SEL_WIDTH 1
-#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
-#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
-#define FTM_PWMLOAD_CH1SEL_SHIFT 1
-#define FTM_PWMLOAD_CH1SEL_WIDTH 1
-#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
-#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
-#define FTM_PWMLOAD_CH2SEL_SHIFT 2
-#define FTM_PWMLOAD_CH2SEL_WIDTH 1
-#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
-#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
-#define FTM_PWMLOAD_CH3SEL_SHIFT 3
-#define FTM_PWMLOAD_CH3SEL_WIDTH 1
-#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
-#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
-#define FTM_PWMLOAD_CH4SEL_SHIFT 4
-#define FTM_PWMLOAD_CH4SEL_WIDTH 1
-#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
-#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
-#define FTM_PWMLOAD_CH5SEL_SHIFT 5
-#define FTM_PWMLOAD_CH5SEL_WIDTH 1
-#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
-#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
-#define FTM_PWMLOAD_CH6SEL_SHIFT 6
-#define FTM_PWMLOAD_CH6SEL_WIDTH 1
-#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
-#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
-#define FTM_PWMLOAD_CH7SEL_SHIFT 7
-#define FTM_PWMLOAD_CH7SEL_WIDTH 1
-#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
-#define FTM_PWMLOAD_LDOK_MASK 0x200u
-#define FTM_PWMLOAD_LDOK_SHIFT 9
-#define FTM_PWMLOAD_LDOK_WIDTH 1
-#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
+/*! @name SC - Status And Control */
+#define FTM_SC_PS_MASK (0x7U)
+#define FTM_SC_PS_SHIFT (0U)
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK (0x18U)
+#define FTM_SC_CLKS_SHIFT (3U)
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK (0x20U)
+#define FTM_SC_CPWMS_SHIFT (5U)
+#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK (0x40U)
+#define FTM_SC_TOIE_SHIFT (6U)
+#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK (0x80U)
+#define FTM_SC_TOF_SHIFT (7U)
+#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+
+/*! @name CNT - Counter */
+#define FTM_CNT_COUNT_MASK (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT (0U)
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define FTM_MOD_MOD_MASK (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT (0U)
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status And Control */
+#define FTM_CnSC_DMA_MASK (0x1U)
+#define FTM_CnSC_DMA_SHIFT (0U)
+#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK (0x4U)
+#define FTM_CnSC_ELSA_SHIFT (2U)
+#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK (0x8U)
+#define FTM_CnSC_ELSB_SHIFT (3U)
+#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK (0x10U)
+#define FTM_CnSC_MSA_SHIFT (4U)
+#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK (0x20U)
+#define FTM_CnSC_MSB_SHIFT (5U)
+#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK (0x40U)
+#define FTM_CnSC_CHIE_SHIFT (6U)
+#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK (0x80U)
+#define FTM_CnSC_CHF_SHIFT (7U)
+#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT (8U)
+
+/*! @name CnV - Channel (n) Value */
+#define FTM_CnV_VAL_MASK (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT (0U)
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+#define FTM_CNTIN_INIT_MASK (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT (0U)
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+
+/*! @name STATUS - Capture And Compare Status */
+#define FTM_STATUS_CH0F_MASK (0x1U)
+#define FTM_STATUS_CH0F_SHIFT (0U)
+#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK (0x2U)
+#define FTM_STATUS_CH1F_SHIFT (1U)
+#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK (0x4U)
+#define FTM_STATUS_CH2F_SHIFT (2U)
+#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK (0x8U)
+#define FTM_STATUS_CH3F_SHIFT (3U)
+#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK (0x10U)
+#define FTM_STATUS_CH4F_SHIFT (4U)
+#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK (0x20U)
+#define FTM_STATUS_CH5F_SHIFT (5U)
+#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK (0x40U)
+#define FTM_STATUS_CH6F_SHIFT (6U)
+#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK (0x80U)
+#define FTM_STATUS_CH7F_SHIFT (7U)
+#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+
+/*! @name MODE - Features Mode Selection */
+#define FTM_MODE_FTMEN_MASK (0x1U)
+#define FTM_MODE_FTMEN_SHIFT (0U)
+#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK (0x2U)
+#define FTM_MODE_INIT_SHIFT (1U)
+#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK (0x4U)
+#define FTM_MODE_WPDIS_SHIFT (2U)
+#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK (0x8U)
+#define FTM_MODE_PWMSYNC_SHIFT (3U)
+#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK (0x10U)
+#define FTM_MODE_CAPTEST_SHIFT (4U)
+#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK (0x60U)
+#define FTM_MODE_FAULTM_SHIFT (5U)
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK (0x80U)
+#define FTM_MODE_FAULTIE_SHIFT (7U)
+#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+
+/*! @name SYNC - Synchronization */
+#define FTM_SYNC_CNTMIN_MASK (0x1U)
+#define FTM_SYNC_CNTMIN_SHIFT (0U)
+#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK (0x2U)
+#define FTM_SYNC_CNTMAX_SHIFT (1U)
+#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK (0x4U)
+#define FTM_SYNC_REINIT_SHIFT (2U)
+#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK (0x8U)
+#define FTM_SYNC_SYNCHOM_SHIFT (3U)
+#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK (0x10U)
+#define FTM_SYNC_TRIG0_SHIFT (4U)
+#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK (0x20U)
+#define FTM_SYNC_TRIG1_SHIFT (5U)
+#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK (0x40U)
+#define FTM_SYNC_TRIG2_SHIFT (6U)
+#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK (0x80U)
+#define FTM_SYNC_SWSYNC_SHIFT (7U)
+#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+
+/*! @name OUTINIT - Initial State For Channels Output */
+#define FTM_OUTINIT_CH0OI_MASK (0x1U)
+#define FTM_OUTINIT_CH0OI_SHIFT (0U)
+#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK (0x2U)
+#define FTM_OUTINIT_CH1OI_SHIFT (1U)
+#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK (0x4U)
+#define FTM_OUTINIT_CH2OI_SHIFT (2U)
+#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK (0x8U)
+#define FTM_OUTINIT_CH3OI_SHIFT (3U)
+#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK (0x10U)
+#define FTM_OUTINIT_CH4OI_SHIFT (4U)
+#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK (0x20U)
+#define FTM_OUTINIT_CH5OI_SHIFT (5U)
+#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK (0x40U)
+#define FTM_OUTINIT_CH6OI_SHIFT (6U)
+#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK (0x80U)
+#define FTM_OUTINIT_CH7OI_SHIFT (7U)
+#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+
+/*! @name OUTMASK - Output Mask */
+#define FTM_OUTMASK_CH0OM_MASK (0x1U)
+#define FTM_OUTMASK_CH0OM_SHIFT (0U)
+#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK (0x2U)
+#define FTM_OUTMASK_CH1OM_SHIFT (1U)
+#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK (0x4U)
+#define FTM_OUTMASK_CH2OM_SHIFT (2U)
+#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK (0x8U)
+#define FTM_OUTMASK_CH3OM_SHIFT (3U)
+#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK (0x10U)
+#define FTM_OUTMASK_CH4OM_SHIFT (4U)
+#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK (0x20U)
+#define FTM_OUTMASK_CH5OM_SHIFT (5U)
+#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK (0x40U)
+#define FTM_OUTMASK_CH6OM_SHIFT (6U)
+#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK (0x80U)
+#define FTM_OUTMASK_CH7OM_SHIFT (7U)
+#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+
+/*! @name COMBINE - Function For Linked Channels */
+#define FTM_COMBINE_COMBINE0_MASK (0x1U)
+#define FTM_COMBINE_COMBINE0_SHIFT (0U)
+#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK (0x2U)
+#define FTM_COMBINE_COMP0_SHIFT (1U)
+#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
+#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
+#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK (0x8U)
+#define FTM_COMBINE_DECAP0_SHIFT (3U)
+#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK (0x10U)
+#define FTM_COMBINE_DTEN0_SHIFT (4U)
+#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
+#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
+#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
+#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
+#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK (0x100U)
+#define FTM_COMBINE_COMBINE1_SHIFT (8U)
+#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK (0x200U)
+#define FTM_COMBINE_COMP1_SHIFT (9U)
+#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
+#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
+#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK (0x800U)
+#define FTM_COMBINE_DECAP1_SHIFT (11U)
+#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK (0x1000U)
+#define FTM_COMBINE_DTEN1_SHIFT (12U)
+#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
+#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
+#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
+#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
+#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
+#define FTM_COMBINE_COMBINE2_SHIFT (16U)
+#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK (0x20000U)
+#define FTM_COMBINE_COMP2_SHIFT (17U)
+#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
+#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
+#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK (0x80000U)
+#define FTM_COMBINE_DECAP2_SHIFT (19U)
+#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK (0x100000U)
+#define FTM_COMBINE_DTEN2_SHIFT (20U)
+#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
+#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
+#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
+#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
+#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
+#define FTM_COMBINE_COMBINE3_SHIFT (24U)
+#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK (0x2000000U)
+#define FTM_COMBINE_COMP3_SHIFT (25U)
+#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
+#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
+#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
+#define FTM_COMBINE_DECAP3_SHIFT (27U)
+#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
+#define FTM_COMBINE_DTEN3_SHIFT (28U)
+#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
+#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
+#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
+#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
+#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT (0U)
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT (6U)
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+
+/*! @name EXTTRIG - FTM External Trigger */
+#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
+#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
+#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
+#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
+#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
+#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
+#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
+#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
+#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
+#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
+#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
+#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
+#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
+#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
+#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
+#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+
+/*! @name POL - Channels Polarity */
+#define FTM_POL_POL0_MASK (0x1U)
+#define FTM_POL_POL0_SHIFT (0U)
+#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK (0x2U)
+#define FTM_POL_POL1_SHIFT (1U)
+#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK (0x4U)
+#define FTM_POL_POL2_SHIFT (2U)
+#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK (0x8U)
+#define FTM_POL_POL3_SHIFT (3U)
+#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK (0x10U)
+#define FTM_POL_POL4_SHIFT (4U)
+#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK (0x20U)
+#define FTM_POL_POL5_SHIFT (5U)
+#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK (0x40U)
+#define FTM_POL_POL6_SHIFT (6U)
+#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK (0x80U)
+#define FTM_POL_POL7_SHIFT (7U)
+#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+
+/*! @name FMS - Fault Mode Status */
+#define FTM_FMS_FAULTF0_MASK (0x1U)
+#define FTM_FMS_FAULTF0_SHIFT (0U)
+#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK (0x2U)
+#define FTM_FMS_FAULTF1_SHIFT (1U)
+#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK (0x4U)
+#define FTM_FMS_FAULTF2_SHIFT (2U)
+#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK (0x8U)
+#define FTM_FMS_FAULTF3_SHIFT (3U)
+#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK (0x20U)
+#define FTM_FMS_FAULTIN_SHIFT (5U)
+#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK (0x40U)
+#define FTM_FMS_WPEN_SHIFT (6U)
+#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK (0x80U)
+#define FTM_FMS_FAULTF_SHIFT (7U)
+#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+
+/*! @name FILTER - Input Capture Filter Control */
+#define FTM_FILTER_CH0FVAL_MASK (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT (0U)
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT (4U)
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT (8U)
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT (12U)
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+
+/*! @name FLTCTRL - Fault Control */
+#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
+#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
+#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
+#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
+#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
+#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
+#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
+#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
+#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
+#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
+#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
+#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
+#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control And Status */
+#define FTM_QDCTRL_QUADEN_MASK (0x1U)
+#define FTM_QDCTRL_QUADEN_SHIFT (0U)
+#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
+#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
+#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK (0x4U)
+#define FTM_QDCTRL_QUADIR_SHIFT (2U)
+#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
+#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
+#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
+#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
+#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
+#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
+#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
+#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
+#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
+#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
+#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+
+/*! @name CONF - Configuration */
+#define FTM_CONF_NUMTOF_MASK (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT (0U)
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT (6U)
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK (0x200U)
+#define FTM_CONF_GTBEEN_SHIFT (9U)
+#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK (0x400U)
+#define FTM_CONF_GTBEOUT_SHIFT (10U)
+#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
+#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
+#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
+#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
+#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
+#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
+#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
+#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
+#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+
+/*! @name SYNCONF - Synchronization Configuration */
+#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
+#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK (0x4U)
+#define FTM_SYNCONF_CNTINC_SHIFT (2U)
+#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK (0x10U)
+#define FTM_SYNCONF_INVC_SHIFT (4U)
+#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK (0x20U)
+#define FTM_SYNCONF_SWOC_SHIFT (5U)
+#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
+#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
+#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
+#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
+#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
+#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
+#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK (0x400U)
+#define FTM_SYNCONF_SWOM_SHIFT (10U)
+#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK (0x800U)
+#define FTM_SYNCONF_SWINVC_SHIFT (11U)
+#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
+#define FTM_SYNCONF_SWSOC_SHIFT (12U)
+#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
+#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
+#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
+#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
+#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK (0x40000U)
+#define FTM_SYNCONF_HWOM_SHIFT (18U)
+#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
+#define FTM_SYNCONF_HWINVC_SHIFT (19U)
+#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
+#define FTM_SYNCONF_HWSOC_SHIFT (20U)
+#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+
+/*! @name INVCTRL - FTM Inverting Control */
+#define FTM_INVCTRL_INV0EN_MASK (0x1U)
+#define FTM_INVCTRL_INV0EN_SHIFT (0U)
+#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK (0x2U)
+#define FTM_INVCTRL_INV1EN_SHIFT (1U)
+#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK (0x4U)
+#define FTM_INVCTRL_INV2EN_SHIFT (2U)
+#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK (0x8U)
+#define FTM_INVCTRL_INV3EN_SHIFT (3U)
+#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+
+/*! @name SWOCTRL - FTM Software Output Control */
+#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
+#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
+#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
+#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
+#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
+#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
+#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
+#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
+#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
+#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
+#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
+#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
+#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
+#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
+#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
+#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
+#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
+#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
+#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
+#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
+#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
+#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
+#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
+#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
+#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
+#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
+#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
+#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
+#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
+#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
+#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
+#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
+#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+
+/*! @name PWMLOAD - FTM PWM Load */
+#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
+#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
+#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
+#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
+#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
+#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
+#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
+#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
+#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
+#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
+#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
+#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
+#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
+#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
+#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
+#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
+#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK (0x200U)
+#define FTM_PWMLOAD_LDOK_SHIFT (9U)
+#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+
/*!
* @}
@@ -7616,22 +5337,18 @@ typedef struct {
#define FTM0_BASE (0x40038000u)
/** Peripheral FTM0 base pointer */
#define FTM0 ((FTM_Type *)FTM0_BASE)
-#define FTM0_BASE_PTR (FTM0)
/** Peripheral FTM1 base address */
#define FTM1_BASE (0x40039000u)
/** Peripheral FTM1 base pointer */
#define FTM1 ((FTM_Type *)FTM1_BASE)
-#define FTM1_BASE_PTR (FTM1)
/** Peripheral FTM2 base address */
#define FTM2_BASE (0x400B8000u)
/** Peripheral FTM2 base pointer */
#define FTM2 ((FTM_Type *)FTM2_BASE)
-#define FTM2_BASE_PTR (FTM2)
/** Peripheral FTM3 base address */
#define FTM3_BASE (0x400B9000u)
/** Peripheral FTM3 base pointer */
#define FTM3 ((FTM_Type *)FTM3_BASE)
-#define FTM3_BASE_PTR (FTM3)
/** Array initializer of FTM peripheral base addresses */
#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
/** Array initializer of FTM peripheral base pointers */
@@ -7639,169 +5356,6 @@ typedef struct {
/** Interrupt vectors for the FTM peripheral type */
#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
-/* ----------------------------------------------------------------------------
- -- FTM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
- * @{
- */
-
-
-/* FTM - Register instance definitions */
-/* FTM0 */
-#define FTM0_SC FTM_SC_REG(FTM0)
-#define FTM0_CNT FTM_CNT_REG(FTM0)
-#define FTM0_MOD FTM_MOD_REG(FTM0)
-#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
-#define FTM0_C0V FTM_CnV_REG(FTM0,0)
-#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
-#define FTM0_C1V FTM_CnV_REG(FTM0,1)
-#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
-#define FTM0_C2V FTM_CnV_REG(FTM0,2)
-#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
-#define FTM0_C3V FTM_CnV_REG(FTM0,3)
-#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
-#define FTM0_C4V FTM_CnV_REG(FTM0,4)
-#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
-#define FTM0_C5V FTM_CnV_REG(FTM0,5)
-#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
-#define FTM0_C6V FTM_CnV_REG(FTM0,6)
-#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
-#define FTM0_C7V FTM_CnV_REG(FTM0,7)
-#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
-#define FTM0_STATUS FTM_STATUS_REG(FTM0)
-#define FTM0_MODE FTM_MODE_REG(FTM0)
-#define FTM0_SYNC FTM_SYNC_REG(FTM0)
-#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
-#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
-#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
-#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
-#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
-#define FTM0_POL FTM_POL_REG(FTM0)
-#define FTM0_FMS FTM_FMS_REG(FTM0)
-#define FTM0_FILTER FTM_FILTER_REG(FTM0)
-#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
-#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
-#define FTM0_CONF FTM_CONF_REG(FTM0)
-#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
-#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
-#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
-#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
-#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
-/* FTM1 */
-#define FTM1_SC FTM_SC_REG(FTM1)
-#define FTM1_CNT FTM_CNT_REG(FTM1)
-#define FTM1_MOD FTM_MOD_REG(FTM1)
-#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
-#define FTM1_C0V FTM_CnV_REG(FTM1,0)
-#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
-#define FTM1_C1V FTM_CnV_REG(FTM1,1)
-#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
-#define FTM1_STATUS FTM_STATUS_REG(FTM1)
-#define FTM1_MODE FTM_MODE_REG(FTM1)
-#define FTM1_SYNC FTM_SYNC_REG(FTM1)
-#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
-#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
-#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
-#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
-#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
-#define FTM1_POL FTM_POL_REG(FTM1)
-#define FTM1_FMS FTM_FMS_REG(FTM1)
-#define FTM1_FILTER FTM_FILTER_REG(FTM1)
-#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
-#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
-#define FTM1_CONF FTM_CONF_REG(FTM1)
-#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
-#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
-#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
-#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
-#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
-/* FTM2 */
-#define FTM2_SC FTM_SC_REG(FTM2)
-#define FTM2_CNT FTM_CNT_REG(FTM2)
-#define FTM2_MOD FTM_MOD_REG(FTM2)
-#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
-#define FTM2_C0V FTM_CnV_REG(FTM2,0)
-#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
-#define FTM2_C1V FTM_CnV_REG(FTM2,1)
-#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
-#define FTM2_STATUS FTM_STATUS_REG(FTM2)
-#define FTM2_MODE FTM_MODE_REG(FTM2)
-#define FTM2_SYNC FTM_SYNC_REG(FTM2)
-#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
-#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
-#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
-#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
-#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
-#define FTM2_POL FTM_POL_REG(FTM2)
-#define FTM2_FMS FTM_FMS_REG(FTM2)
-#define FTM2_FILTER FTM_FILTER_REG(FTM2)
-#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
-#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
-#define FTM2_CONF FTM_CONF_REG(FTM2)
-#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
-#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
-#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
-#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
-#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
-/* FTM3 */
-#define FTM3_SC FTM_SC_REG(FTM3)
-#define FTM3_CNT FTM_CNT_REG(FTM3)
-#define FTM3_MOD FTM_MOD_REG(FTM3)
-#define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
-#define FTM3_C0V FTM_CnV_REG(FTM3,0)
-#define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
-#define FTM3_C1V FTM_CnV_REG(FTM3,1)
-#define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
-#define FTM3_C2V FTM_CnV_REG(FTM3,2)
-#define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
-#define FTM3_C3V FTM_CnV_REG(FTM3,3)
-#define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
-#define FTM3_C4V FTM_CnV_REG(FTM3,4)
-#define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
-#define FTM3_C5V FTM_CnV_REG(FTM3,5)
-#define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
-#define FTM3_C6V FTM_CnV_REG(FTM3,6)
-#define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
-#define FTM3_C7V FTM_CnV_REG(FTM3,7)
-#define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
-#define FTM3_STATUS FTM_STATUS_REG(FTM3)
-#define FTM3_MODE FTM_MODE_REG(FTM3)
-#define FTM3_SYNC FTM_SYNC_REG(FTM3)
-#define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
-#define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
-#define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
-#define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
-#define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
-#define FTM3_POL FTM_POL_REG(FTM3)
-#define FTM3_FMS FTM_FMS_REG(FTM3)
-#define FTM3_FILTER FTM_FILTER_REG(FTM3)
-#define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
-#define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
-#define FTM3_CONF FTM_CONF_REG(FTM3)
-#define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
-#define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
-#define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
-#define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
-#define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
-
-/* FTM - Register array accessors */
-#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
-#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
-#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
-#define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
-#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
-#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
-#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
-#define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
-
-/*!
- * @}
- */ /* end of group FTM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group FTM_Peripheral_Access_Layer */
@@ -7824,70 +5378,47 @@ typedef struct {
__O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
__I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type, *GPIO_MemMapPtr;
+} GPIO_Type;
/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
+ -- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT (0U)
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
-/* GPIO - Register accessors */
-#define GPIO_PDOR_REG(base) ((base)->PDOR)
-#define GPIO_PSOR_REG(base) ((base)->PSOR)
-#define GPIO_PCOR_REG(base) ((base)->PCOR)
-#define GPIO_PTOR_REG(base) ((base)->PTOR)
-#define GPIO_PDIR_REG(base) ((base)->PDIR)
-#define GPIO_PDDR_REG(base) ((base)->PDDR)
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT (0U)
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT (0U)
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT (0U)
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT (0U)
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT (0U)
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO_WIDTH 32
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO_WIDTH 32
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO_WIDTH 32
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO_WIDTH 32
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI_WIDTH 32
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD_WIDTH 32
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
/*!
* @}
@@ -7899,84 +5430,27 @@ typedef struct {
#define GPIOA_BASE (0x400FF000u)
/** Peripheral GPIOA base pointer */
#define GPIOA ((GPIO_Type *)GPIOA_BASE)
-#define GPIOA_BASE_PTR (GPIOA)
/** Peripheral GPIOB base address */
#define GPIOB_BASE (0x400FF040u)
/** Peripheral GPIOB base pointer */
#define GPIOB ((GPIO_Type *)GPIOB_BASE)
-#define GPIOB_BASE_PTR (GPIOB)
/** Peripheral GPIOC base address */
#define GPIOC_BASE (0x400FF080u)
/** Peripheral GPIOC base pointer */
#define GPIOC ((GPIO_Type *)GPIOC_BASE)
-#define GPIOC_BASE_PTR (GPIOC)
/** Peripheral GPIOD base address */
#define GPIOD_BASE (0x400FF0C0u)
/** Peripheral GPIOD base pointer */
#define GPIOD ((GPIO_Type *)GPIOD_BASE)
-#define GPIOD_BASE_PTR (GPIOD)
/** Peripheral GPIOE base address */
#define GPIOE_BASE (0x400FF100u)
/** Peripheral GPIOE base pointer */
#define GPIOE ((GPIO_Type *)GPIOE_BASE)
-#define GPIOE_BASE_PTR (GPIOE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
-/* ----------------------------------------------------------------------------
- -- GPIO - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
- * @{
- */
-
-
-/* GPIO - Register instance definitions */
-/* GPIOA */
-#define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
-#define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
-#define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
-#define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
-#define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
-#define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
-/* GPIOB */
-#define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
-#define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
-#define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
-#define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
-#define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
-#define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
-/* GPIOC */
-#define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
-#define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
-#define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
-#define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
-#define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
-#define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
-/* GPIOD */
-#define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
-#define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
-#define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
-#define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
-#define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
-#define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
-/* GPIOE */
-#define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
-#define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
-#define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
-#define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
-#define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
-#define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
@@ -8005,36 +5479,7 @@ typedef struct {
__IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
__IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
__IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type, *I2C_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register accessors */
-#define I2C_A1_REG(base) ((base)->A1)
-#define I2C_F_REG(base) ((base)->F)
-#define I2C_C1_REG(base) ((base)->C1)
-#define I2C_S_REG(base) ((base)->S)
-#define I2C_D_REG(base) ((base)->D)
-#define I2C_C2_REG(base) ((base)->C2)
-#define I2C_FLT_REG(base) ((base)->FLT)
-#define I2C_RA_REG(base) ((base)->RA)
-#define I2C_SMB_REG(base) ((base)->SMB)
-#define I2C_A2_REG(base) ((base)->A2)
-#define I2C_SLTH_REG(base) ((base)->SLTH)
-#define I2C_SLTL_REG(base) ((base)->SLTL)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
+} I2C_Type;
/* ----------------------------------------------------------------------------
-- I2C Register Masks
@@ -8045,190 +5490,159 @@ typedef struct {
* @{
*/
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD_WIDTH 7
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR_WIDTH 6
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT_WIDTH 2
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_DMAEN_WIDTH 1
-#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_DMAEN_SHIFT))&I2C_C1_DMAEN_MASK)
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_WUEN_WIDTH 1
-#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_WUEN_SHIFT))&I2C_C1_WUEN_MASK)
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_RSTA_WIDTH 1
-#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_RSTA_SHIFT))&I2C_C1_RSTA_MASK)
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TXAK_WIDTH 1
-#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TXAK_SHIFT))&I2C_C1_TXAK_MASK)
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_TX_WIDTH 1
-#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_TX_SHIFT))&I2C_C1_TX_MASK)
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_MST_WIDTH 1
-#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_MST_SHIFT))&I2C_C1_MST_MASK)
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICIE_WIDTH 1
-#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICIE_SHIFT))&I2C_C1_IICIE_MASK)
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-#define I2C_C1_IICEN_WIDTH 1
-#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C1_IICEN_SHIFT))&I2C_C1_IICEN_MASK)
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_RXAK_WIDTH 1
-#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RXAK_SHIFT))&I2C_S_RXAK_MASK)
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_IICIF_WIDTH 1
-#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IICIF_SHIFT))&I2C_S_IICIF_MASK)
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_SRW_WIDTH 1
-#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_SRW_SHIFT))&I2C_S_SRW_MASK)
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_RAM_WIDTH 1
-#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_RAM_SHIFT))&I2C_S_RAM_MASK)
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_ARBL_WIDTH 1
-#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_ARBL_SHIFT))&I2C_S_ARBL_MASK)
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_BUSY_WIDTH 1
-#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_BUSY_SHIFT))&I2C_S_BUSY_MASK)
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_IAAS_WIDTH 1
-#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_IAAS_SHIFT))&I2C_S_IAAS_MASK)
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-#define I2C_S_TCF_WIDTH 1
-#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x))<<I2C_S_TCF_SHIFT))&I2C_S_TCF_MASK)
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA_WIDTH 8
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD_WIDTH 3
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_RMEN_WIDTH 1
-#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_RMEN_SHIFT))&I2C_C2_RMEN_MASK)
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_SBRC_WIDTH 1
-#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_SBRC_SHIFT))&I2C_C2_SBRC_MASK)
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_HDRS_WIDTH 1
-#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_HDRS_SHIFT))&I2C_C2_HDRS_MASK)
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_ADEXT_WIDTH 1
-#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_ADEXT_SHIFT))&I2C_C2_ADEXT_MASK)
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-#define I2C_C2_GCAEN_WIDTH 1
-#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_GCAEN_SHIFT))&I2C_C2_GCAEN_MASK)
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0xFu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT_WIDTH 4
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STARTF_MASK 0x10u
-#define I2C_FLT_STARTF_SHIFT 4
-#define I2C_FLT_STARTF_WIDTH 1
-#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STARTF_SHIFT))&I2C_FLT_STARTF_MASK)
-#define I2C_FLT_SSIE_MASK 0x20u
-#define I2C_FLT_SSIE_SHIFT 5
-#define I2C_FLT_SSIE_WIDTH 1
-#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SSIE_SHIFT))&I2C_FLT_SSIE_MASK)
-#define I2C_FLT_STOPF_MASK 0x40u
-#define I2C_FLT_STOPF_SHIFT 6
-#define I2C_FLT_STOPF_WIDTH 1
-#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_STOPF_SHIFT))&I2C_FLT_STOPF_MASK)
-#define I2C_FLT_SHEN_MASK 0x80u
-#define I2C_FLT_SHEN_SHIFT 7
-#define I2C_FLT_SHEN_WIDTH 1
-#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_SHEN_SHIFT))&I2C_FLT_SHEN_MASK)
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD_WIDTH 7
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2IE_WIDTH 1
-#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2IE_SHIFT))&I2C_SMB_SHTF2IE_MASK)
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF2_WIDTH 1
-#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF2_SHIFT))&I2C_SMB_SHTF2_MASK)
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SHTF1_WIDTH 1
-#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SHTF1_SHIFT))&I2C_SMB_SHTF1_MASK)
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_SLTF_WIDTH 1
-#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SLTF_SHIFT))&I2C_SMB_SLTF_MASK)
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_TCKSEL_WIDTH 1
-#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_TCKSEL_SHIFT))&I2C_SMB_TCKSEL_MASK)
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_SIICAEN_WIDTH 1
-#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_SIICAEN_SHIFT))&I2C_SMB_SIICAEN_MASK)
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_ALERTEN_WIDTH 1
-#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_ALERTEN_SHIFT))&I2C_SMB_ALERTEN_MASK)
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-#define I2C_SMB_FACK_WIDTH 1
-#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x))<<I2C_SMB_FACK_SHIFT))&I2C_SMB_FACK_MASK)
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD_WIDTH 7
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT_WIDTH 8
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT_WIDTH 8
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK (0xFEU)
+#define I2C_A1_AD_SHIFT (1U)
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK (0x3FU)
+#define I2C_F_ICR_SHIFT (0U)
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK (0xC0U)
+#define I2C_F_MULT_SHIFT (6U)
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK (0x1U)
+#define I2C_C1_DMAEN_SHIFT (0U)
+#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK (0x2U)
+#define I2C_C1_WUEN_SHIFT (1U)
+#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK (0x4U)
+#define I2C_C1_RSTA_SHIFT (2U)
+#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK (0x8U)
+#define I2C_C1_TXAK_SHIFT (3U)
+#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK (0x10U)
+#define I2C_C1_TX_SHIFT (4U)
+#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK (0x20U)
+#define I2C_C1_MST_SHIFT (5U)
+#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK (0x40U)
+#define I2C_C1_IICIE_SHIFT (6U)
+#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK (0x80U)
+#define I2C_C1_IICEN_SHIFT (7U)
+#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK (0x1U)
+#define I2C_S_RXAK_SHIFT (0U)
+#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK (0x2U)
+#define I2C_S_IICIF_SHIFT (1U)
+#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK (0x4U)
+#define I2C_S_SRW_SHIFT (2U)
+#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK (0x8U)
+#define I2C_S_RAM_SHIFT (3U)
+#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK (0x10U)
+#define I2C_S_ARBL_SHIFT (4U)
+#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK (0x20U)
+#define I2C_S_BUSY_SHIFT (5U)
+#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK (0x40U)
+#define I2C_S_IAAS_SHIFT (6U)
+#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK (0x80U)
+#define I2C_S_TCF_SHIFT (7U)
+#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK (0xFFU)
+#define I2C_D_DATA_SHIFT (0U)
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK (0x7U)
+#define I2C_C2_AD_SHIFT (0U)
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK (0x8U)
+#define I2C_C2_RMEN_SHIFT (3U)
+#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK (0x10U)
+#define I2C_C2_SBRC_SHIFT (4U)
+#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK (0x20U)
+#define I2C_C2_HDRS_SHIFT (5U)
+#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK (0x40U)
+#define I2C_C2_ADEXT_SHIFT (6U)
+#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK (0x80U)
+#define I2C_C2_GCAEN_SHIFT (7U)
+#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter Register */
+#define I2C_FLT_FLT_MASK (0xFU)
+#define I2C_FLT_FLT_SHIFT (0U)
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK (0x10U)
+#define I2C_FLT_STARTF_SHIFT (4U)
+#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK (0x20U)
+#define I2C_FLT_SSIE_SHIFT (5U)
+#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK (0x40U)
+#define I2C_FLT_STOPF_SHIFT (6U)
+#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK (0x80U)
+#define I2C_FLT_SHEN_SHIFT (7U)
+#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK (0xFEU)
+#define I2C_RA_RAD_SHIFT (1U)
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT (0U)
+#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK (0x2U)
+#define I2C_SMB_SHTF2_SHIFT (1U)
+#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK (0x4U)
+#define I2C_SMB_SHTF1_SHIFT (2U)
+#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK (0x8U)
+#define I2C_SMB_SLTF_SHIFT (3U)
+#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT (4U)
+#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT (5U)
+#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT (6U)
+#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK (0x80U)
+#define I2C_SMB_FACK_SHIFT (7U)
+#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK (0xFEU)
+#define I2C_A2_SAD_SHIFT (1U)
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT (0U)
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT (0U)
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
/*!
* @}
@@ -8240,17 +5654,14 @@ typedef struct {
#define I2C0_BASE (0x40066000u)
/** Peripheral I2C0 base pointer */
#define I2C0 ((I2C_Type *)I2C0_BASE)
-#define I2C0_BASE_PTR (I2C0)
/** Peripheral I2C1 base address */
#define I2C1_BASE (0x40067000u)
/** Peripheral I2C1 base pointer */
#define I2C1 ((I2C_Type *)I2C1_BASE)
-#define I2C1_BASE_PTR (I2C1)
/** Peripheral I2C2 base address */
#define I2C2_BASE (0x400E6000u)
/** Peripheral I2C2 base pointer */
#define I2C2 ((I2C_Type *)I2C2_BASE)
-#define I2C2_BASE_PTR (I2C2)
/** Array initializer of I2C peripheral base addresses */
#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
/** Array initializer of I2C peripheral base pointers */
@@ -8258,62 +5669,6 @@ typedef struct {
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
-/* ----------------------------------------------------------------------------
- -- I2C - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
- * @{
- */
-
-
-/* I2C - Register instance definitions */
-/* I2C0 */
-#define I2C0_A1 I2C_A1_REG(I2C0)
-#define I2C0_F I2C_F_REG(I2C0)
-#define I2C0_C1 I2C_C1_REG(I2C0)
-#define I2C0_S I2C_S_REG(I2C0)
-#define I2C0_D I2C_D_REG(I2C0)
-#define I2C0_C2 I2C_C2_REG(I2C0)
-#define I2C0_FLT I2C_FLT_REG(I2C0)
-#define I2C0_RA I2C_RA_REG(I2C0)
-#define I2C0_SMB I2C_SMB_REG(I2C0)
-#define I2C0_A2 I2C_A2_REG(I2C0)
-#define I2C0_SLTH I2C_SLTH_REG(I2C0)
-#define I2C0_SLTL I2C_SLTL_REG(I2C0)
-/* I2C1 */
-#define I2C1_A1 I2C_A1_REG(I2C1)
-#define I2C1_F I2C_F_REG(I2C1)
-#define I2C1_C1 I2C_C1_REG(I2C1)
-#define I2C1_S I2C_S_REG(I2C1)
-#define I2C1_D I2C_D_REG(I2C1)
-#define I2C1_C2 I2C_C2_REG(I2C1)
-#define I2C1_FLT I2C_FLT_REG(I2C1)
-#define I2C1_RA I2C_RA_REG(I2C1)
-#define I2C1_SMB I2C_SMB_REG(I2C1)
-#define I2C1_A2 I2C_A2_REG(I2C1)
-#define I2C1_SLTH I2C_SLTH_REG(I2C1)
-#define I2C1_SLTL I2C_SLTL_REG(I2C1)
-/* I2C2 */
-#define I2C2_A1 I2C_A1_REG(I2C2)
-#define I2C2_F I2C_F_REG(I2C2)
-#define I2C2_C1 I2C_C1_REG(I2C2)
-#define I2C2_S I2C_S_REG(I2C2)
-#define I2C2_D I2C_D_REG(I2C2)
-#define I2C2_C2 I2C_C2_REG(I2C2)
-#define I2C2_FLT I2C_FLT_REG(I2C2)
-#define I2C2_RA I2C_RA_REG(I2C2)
-#define I2C2_SMB I2C_SMB_REG(I2C2)
-#define I2C2_A2 I2C_A2_REG(I2C2)
-#define I2C2_SLTH I2C_SLTH_REG(I2C2)
-#define I2C2_SLTL I2C_SLTL_REG(I2C2)
-
-/*!
- * @}
- */ /* end of group I2C_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
@@ -8358,48 +5713,7 @@ typedef struct {
uint8_t RESERVED_7[28];
__IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
__IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
-} I2S_Type, *I2S_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register accessors */
-#define I2S_TCSR_REG(base) ((base)->TCSR)
-#define I2S_TCR1_REG(base) ((base)->TCR1)
-#define I2S_TCR2_REG(base) ((base)->TCR2)
-#define I2S_TCR3_REG(base) ((base)->TCR3)
-#define I2S_TCR4_REG(base) ((base)->TCR4)
-#define I2S_TCR5_REG(base) ((base)->TCR5)
-#define I2S_TDR_REG(base,index) ((base)->TDR[index])
-#define I2S_TDR_COUNT 2
-#define I2S_TFR_REG(base,index) ((base)->TFR[index])
-#define I2S_TFR_COUNT 2
-#define I2S_TMR_REG(base) ((base)->TMR)
-#define I2S_RCSR_REG(base) ((base)->RCSR)
-#define I2S_RCR1_REG(base) ((base)->RCR1)
-#define I2S_RCR2_REG(base) ((base)->RCR2)
-#define I2S_RCR3_REG(base) ((base)->RCR3)
-#define I2S_RCR4_REG(base) ((base)->RCR4)
-#define I2S_RCR5_REG(base) ((base)->RCR5)
-#define I2S_RDR_REG(base,index) ((base)->RDR[index])
-#define I2S_RDR_COUNT 2
-#define I2S_RFR_REG(base,index) ((base)->RFR[index])
-#define I2S_RFR_COUNT 2
-#define I2S_RMR_REG(base) ((base)->RMR)
-#define I2S_MCR_REG(base) ((base)->MCR)
-#define I2S_MDR_REG(base) ((base)->MDR)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
+} I2S_Type;
/* ----------------------------------------------------------------------------
-- I2S Register Masks
@@ -8410,374 +5724,319 @@ typedef struct {
* @{
*/
-/* TCSR Bit Fields */
-#define I2S_TCSR_FRDE_MASK 0x1u
-#define I2S_TCSR_FRDE_SHIFT 0
-#define I2S_TCSR_FRDE_WIDTH 1
-#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
-#define I2S_TCSR_FWDE_MASK 0x2u
-#define I2S_TCSR_FWDE_SHIFT 1
-#define I2S_TCSR_FWDE_WIDTH 1
-#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
-#define I2S_TCSR_FRIE_MASK 0x100u
-#define I2S_TCSR_FRIE_SHIFT 8
-#define I2S_TCSR_FRIE_WIDTH 1
-#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
-#define I2S_TCSR_FWIE_MASK 0x200u
-#define I2S_TCSR_FWIE_SHIFT 9
-#define I2S_TCSR_FWIE_WIDTH 1
-#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
-#define I2S_TCSR_FEIE_MASK 0x400u
-#define I2S_TCSR_FEIE_SHIFT 10
-#define I2S_TCSR_FEIE_WIDTH 1
-#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
-#define I2S_TCSR_SEIE_MASK 0x800u
-#define I2S_TCSR_SEIE_SHIFT 11
-#define I2S_TCSR_SEIE_WIDTH 1
-#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
-#define I2S_TCSR_WSIE_MASK 0x1000u
-#define I2S_TCSR_WSIE_SHIFT 12
-#define I2S_TCSR_WSIE_WIDTH 1
-#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
-#define I2S_TCSR_FRF_MASK 0x10000u
-#define I2S_TCSR_FRF_SHIFT 16
-#define I2S_TCSR_FRF_WIDTH 1
-#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
-#define I2S_TCSR_FWF_MASK 0x20000u
-#define I2S_TCSR_FWF_SHIFT 17
-#define I2S_TCSR_FWF_WIDTH 1
-#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
-#define I2S_TCSR_FEF_MASK 0x40000u
-#define I2S_TCSR_FEF_SHIFT 18
-#define I2S_TCSR_FEF_WIDTH 1
-#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
-#define I2S_TCSR_SEF_MASK 0x80000u
-#define I2S_TCSR_SEF_SHIFT 19
-#define I2S_TCSR_SEF_WIDTH 1
-#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
-#define I2S_TCSR_WSF_MASK 0x100000u
-#define I2S_TCSR_WSF_SHIFT 20
-#define I2S_TCSR_WSF_WIDTH 1
-#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
-#define I2S_TCSR_SR_MASK 0x1000000u
-#define I2S_TCSR_SR_SHIFT 24
-#define I2S_TCSR_SR_WIDTH 1
-#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
-#define I2S_TCSR_FR_MASK 0x2000000u
-#define I2S_TCSR_FR_SHIFT 25
-#define I2S_TCSR_FR_WIDTH 1
-#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
-#define I2S_TCSR_BCE_MASK 0x10000000u
-#define I2S_TCSR_BCE_SHIFT 28
-#define I2S_TCSR_BCE_WIDTH 1
-#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
-#define I2S_TCSR_DBGE_MASK 0x20000000u
-#define I2S_TCSR_DBGE_SHIFT 29
-#define I2S_TCSR_DBGE_WIDTH 1
-#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
-#define I2S_TCSR_STOPE_MASK 0x40000000u
-#define I2S_TCSR_STOPE_SHIFT 30
-#define I2S_TCSR_STOPE_WIDTH 1
-#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
-#define I2S_TCSR_TE_MASK 0x80000000u
-#define I2S_TCSR_TE_SHIFT 31
-#define I2S_TCSR_TE_WIDTH 1
-#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
-/* TCR1 Bit Fields */
-#define I2S_TCR1_TFW_MASK 0x7u
-#define I2S_TCR1_TFW_SHIFT 0
-#define I2S_TCR1_TFW_WIDTH 3
-#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
-/* TCR2 Bit Fields */
-#define I2S_TCR2_DIV_MASK 0xFFu
-#define I2S_TCR2_DIV_SHIFT 0
-#define I2S_TCR2_DIV_WIDTH 8
-#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
-#define I2S_TCR2_BCD_MASK 0x1000000u
-#define I2S_TCR2_BCD_SHIFT 24
-#define I2S_TCR2_BCD_WIDTH 1
-#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
-#define I2S_TCR2_BCP_MASK 0x2000000u
-#define I2S_TCR2_BCP_SHIFT 25
-#define I2S_TCR2_BCP_WIDTH 1
-#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
-#define I2S_TCR2_MSEL_MASK 0xC000000u
-#define I2S_TCR2_MSEL_SHIFT 26
-#define I2S_TCR2_MSEL_WIDTH 2
-#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
-#define I2S_TCR2_BCI_MASK 0x10000000u
-#define I2S_TCR2_BCI_SHIFT 28
-#define I2S_TCR2_BCI_WIDTH 1
-#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
-#define I2S_TCR2_BCS_MASK 0x20000000u
-#define I2S_TCR2_BCS_SHIFT 29
-#define I2S_TCR2_BCS_WIDTH 1
-#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
-#define I2S_TCR2_SYNC_MASK 0xC0000000u
-#define I2S_TCR2_SYNC_SHIFT 30
-#define I2S_TCR2_SYNC_WIDTH 2
-#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
-/* TCR3 Bit Fields */
-#define I2S_TCR3_WDFL_MASK 0x1Fu
-#define I2S_TCR3_WDFL_SHIFT 0
-#define I2S_TCR3_WDFL_WIDTH 5
-#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
-#define I2S_TCR3_TCE_MASK 0x30000u
-#define I2S_TCR3_TCE_SHIFT 16
-#define I2S_TCR3_TCE_WIDTH 2
-#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
-/* TCR4 Bit Fields */
-#define I2S_TCR4_FSD_MASK 0x1u
-#define I2S_TCR4_FSD_SHIFT 0
-#define I2S_TCR4_FSD_WIDTH 1
-#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
-#define I2S_TCR4_FSP_MASK 0x2u
-#define I2S_TCR4_FSP_SHIFT 1
-#define I2S_TCR4_FSP_WIDTH 1
-#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
-#define I2S_TCR4_FSE_MASK 0x8u
-#define I2S_TCR4_FSE_SHIFT 3
-#define I2S_TCR4_FSE_WIDTH 1
-#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
-#define I2S_TCR4_MF_MASK 0x10u
-#define I2S_TCR4_MF_SHIFT 4
-#define I2S_TCR4_MF_WIDTH 1
-#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
-#define I2S_TCR4_SYWD_MASK 0x1F00u
-#define I2S_TCR4_SYWD_SHIFT 8
-#define I2S_TCR4_SYWD_WIDTH 5
-#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
-#define I2S_TCR4_FRSZ_MASK 0x1F0000u
-#define I2S_TCR4_FRSZ_SHIFT 16
-#define I2S_TCR4_FRSZ_WIDTH 5
-#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
-/* TCR5 Bit Fields */
-#define I2S_TCR5_FBT_MASK 0x1F00u
-#define I2S_TCR5_FBT_SHIFT 8
-#define I2S_TCR5_FBT_WIDTH 5
-#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
-#define I2S_TCR5_W0W_MASK 0x1F0000u
-#define I2S_TCR5_W0W_SHIFT 16
-#define I2S_TCR5_W0W_WIDTH 5
-#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
-#define I2S_TCR5_WNW_MASK 0x1F000000u
-#define I2S_TCR5_WNW_SHIFT 24
-#define I2S_TCR5_WNW_WIDTH 5
-#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
-/* TDR Bit Fields */
-#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
-#define I2S_TDR_TDR_SHIFT 0
-#define I2S_TDR_TDR_WIDTH 32
-#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
-/* TFR Bit Fields */
-#define I2S_TFR_RFP_MASK 0xFu
-#define I2S_TFR_RFP_SHIFT 0
-#define I2S_TFR_RFP_WIDTH 4
-#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
-#define I2S_TFR_WFP_MASK 0xF0000u
-#define I2S_TFR_WFP_SHIFT 16
-#define I2S_TFR_WFP_WIDTH 4
-#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
-/* TMR Bit Fields */
-#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
-#define I2S_TMR_TWM_SHIFT 0
-#define I2S_TMR_TWM_WIDTH 32
-#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
-/* RCSR Bit Fields */
-#define I2S_RCSR_FRDE_MASK 0x1u
-#define I2S_RCSR_FRDE_SHIFT 0
-#define I2S_RCSR_FRDE_WIDTH 1
-#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
-#define I2S_RCSR_FWDE_MASK 0x2u
-#define I2S_RCSR_FWDE_SHIFT 1
-#define I2S_RCSR_FWDE_WIDTH 1
-#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
-#define I2S_RCSR_FRIE_MASK 0x100u
-#define I2S_RCSR_FRIE_SHIFT 8
-#define I2S_RCSR_FRIE_WIDTH 1
-#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
-#define I2S_RCSR_FWIE_MASK 0x200u
-#define I2S_RCSR_FWIE_SHIFT 9
-#define I2S_RCSR_FWIE_WIDTH 1
-#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
-#define I2S_RCSR_FEIE_MASK 0x400u
-#define I2S_RCSR_FEIE_SHIFT 10
-#define I2S_RCSR_FEIE_WIDTH 1
-#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
-#define I2S_RCSR_SEIE_MASK 0x800u
-#define I2S_RCSR_SEIE_SHIFT 11
-#define I2S_RCSR_SEIE_WIDTH 1
-#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
-#define I2S_RCSR_WSIE_MASK 0x1000u
-#define I2S_RCSR_WSIE_SHIFT 12
-#define I2S_RCSR_WSIE_WIDTH 1
-#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
-#define I2S_RCSR_FRF_MASK 0x10000u
-#define I2S_RCSR_FRF_SHIFT 16
-#define I2S_RCSR_FRF_WIDTH 1
-#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
-#define I2S_RCSR_FWF_MASK 0x20000u
-#define I2S_RCSR_FWF_SHIFT 17
-#define I2S_RCSR_FWF_WIDTH 1
-#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
-#define I2S_RCSR_FEF_MASK 0x40000u
-#define I2S_RCSR_FEF_SHIFT 18
-#define I2S_RCSR_FEF_WIDTH 1
-#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
-#define I2S_RCSR_SEF_MASK 0x80000u
-#define I2S_RCSR_SEF_SHIFT 19
-#define I2S_RCSR_SEF_WIDTH 1
-#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
-#define I2S_RCSR_WSF_MASK 0x100000u
-#define I2S_RCSR_WSF_SHIFT 20
-#define I2S_RCSR_WSF_WIDTH 1
-#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
-#define I2S_RCSR_SR_MASK 0x1000000u
-#define I2S_RCSR_SR_SHIFT 24
-#define I2S_RCSR_SR_WIDTH 1
-#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
-#define I2S_RCSR_FR_MASK 0x2000000u
-#define I2S_RCSR_FR_SHIFT 25
-#define I2S_RCSR_FR_WIDTH 1
-#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
-#define I2S_RCSR_BCE_MASK 0x10000000u
-#define I2S_RCSR_BCE_SHIFT 28
-#define I2S_RCSR_BCE_WIDTH 1
-#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
-#define I2S_RCSR_DBGE_MASK 0x20000000u
-#define I2S_RCSR_DBGE_SHIFT 29
-#define I2S_RCSR_DBGE_WIDTH 1
-#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
-#define I2S_RCSR_STOPE_MASK 0x40000000u
-#define I2S_RCSR_STOPE_SHIFT 30
-#define I2S_RCSR_STOPE_WIDTH 1
-#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
-#define I2S_RCSR_RE_MASK 0x80000000u
-#define I2S_RCSR_RE_SHIFT 31
-#define I2S_RCSR_RE_WIDTH 1
-#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
-/* RCR1 Bit Fields */
-#define I2S_RCR1_RFW_MASK 0x7u
-#define I2S_RCR1_RFW_SHIFT 0
-#define I2S_RCR1_RFW_WIDTH 3
-#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
-/* RCR2 Bit Fields */
-#define I2S_RCR2_DIV_MASK 0xFFu
-#define I2S_RCR2_DIV_SHIFT 0
-#define I2S_RCR2_DIV_WIDTH 8
-#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
-#define I2S_RCR2_BCD_MASK 0x1000000u
-#define I2S_RCR2_BCD_SHIFT 24
-#define I2S_RCR2_BCD_WIDTH 1
-#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
-#define I2S_RCR2_BCP_MASK 0x2000000u
-#define I2S_RCR2_BCP_SHIFT 25
-#define I2S_RCR2_BCP_WIDTH 1
-#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
-#define I2S_RCR2_MSEL_MASK 0xC000000u
-#define I2S_RCR2_MSEL_SHIFT 26
-#define I2S_RCR2_MSEL_WIDTH 2
-#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
-#define I2S_RCR2_BCI_MASK 0x10000000u
-#define I2S_RCR2_BCI_SHIFT 28
-#define I2S_RCR2_BCI_WIDTH 1
-#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
-#define I2S_RCR2_BCS_MASK 0x20000000u
-#define I2S_RCR2_BCS_SHIFT 29
-#define I2S_RCR2_BCS_WIDTH 1
-#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
-#define I2S_RCR2_SYNC_MASK 0xC0000000u
-#define I2S_RCR2_SYNC_SHIFT 30
-#define I2S_RCR2_SYNC_WIDTH 2
-#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
-/* RCR3 Bit Fields */
-#define I2S_RCR3_WDFL_MASK 0x1Fu
-#define I2S_RCR3_WDFL_SHIFT 0
-#define I2S_RCR3_WDFL_WIDTH 5
-#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
-#define I2S_RCR3_RCE_MASK 0x30000u
-#define I2S_RCR3_RCE_SHIFT 16
-#define I2S_RCR3_RCE_WIDTH 2
-#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
-/* RCR4 Bit Fields */
-#define I2S_RCR4_FSD_MASK 0x1u
-#define I2S_RCR4_FSD_SHIFT 0
-#define I2S_RCR4_FSD_WIDTH 1
-#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
-#define I2S_RCR4_FSP_MASK 0x2u
-#define I2S_RCR4_FSP_SHIFT 1
-#define I2S_RCR4_FSP_WIDTH 1
-#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
-#define I2S_RCR4_FSE_MASK 0x8u
-#define I2S_RCR4_FSE_SHIFT 3
-#define I2S_RCR4_FSE_WIDTH 1
-#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
-#define I2S_RCR4_MF_MASK 0x10u
-#define I2S_RCR4_MF_SHIFT 4
-#define I2S_RCR4_MF_WIDTH 1
-#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
-#define I2S_RCR4_SYWD_MASK 0x1F00u
-#define I2S_RCR4_SYWD_SHIFT 8
-#define I2S_RCR4_SYWD_WIDTH 5
-#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
-#define I2S_RCR4_FRSZ_MASK 0x1F0000u
-#define I2S_RCR4_FRSZ_SHIFT 16
-#define I2S_RCR4_FRSZ_WIDTH 5
-#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
-/* RCR5 Bit Fields */
-#define I2S_RCR5_FBT_MASK 0x1F00u
-#define I2S_RCR5_FBT_SHIFT 8
-#define I2S_RCR5_FBT_WIDTH 5
-#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
-#define I2S_RCR5_W0W_MASK 0x1F0000u
-#define I2S_RCR5_W0W_SHIFT 16
-#define I2S_RCR5_W0W_WIDTH 5
-#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
-#define I2S_RCR5_WNW_MASK 0x1F000000u
-#define I2S_RCR5_WNW_SHIFT 24
-#define I2S_RCR5_WNW_WIDTH 5
-#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
-/* RDR Bit Fields */
-#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
-#define I2S_RDR_RDR_SHIFT 0
-#define I2S_RDR_RDR_WIDTH 32
-#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
-/* RFR Bit Fields */
-#define I2S_RFR_RFP_MASK 0xFu
-#define I2S_RFR_RFP_SHIFT 0
-#define I2S_RFR_RFP_WIDTH 4
-#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
-#define I2S_RFR_WFP_MASK 0xF0000u
-#define I2S_RFR_WFP_SHIFT 16
-#define I2S_RFR_WFP_WIDTH 4
-#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
-/* RMR Bit Fields */
-#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
-#define I2S_RMR_RWM_SHIFT 0
-#define I2S_RMR_RWM_WIDTH 32
-#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
-/* MCR Bit Fields */
-#define I2S_MCR_MICS_MASK 0x3000000u
-#define I2S_MCR_MICS_SHIFT 24
-#define I2S_MCR_MICS_WIDTH 2
-#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
-#define I2S_MCR_MOE_MASK 0x40000000u
-#define I2S_MCR_MOE_SHIFT 30
-#define I2S_MCR_MOE_WIDTH 1
-#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
-#define I2S_MCR_DUF_MASK 0x80000000u
-#define I2S_MCR_DUF_SHIFT 31
-#define I2S_MCR_DUF_WIDTH 1
-#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
-/* MDR Bit Fields */
-#define I2S_MDR_DIVIDE_MASK 0xFFFu
-#define I2S_MDR_DIVIDE_SHIFT 0
-#define I2S_MDR_DIVIDE_WIDTH 12
-#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
-#define I2S_MDR_FRACT_MASK 0xFF000u
-#define I2S_MDR_FRACT_SHIFT 12
-#define I2S_MDR_FRACT_WIDTH 8
-#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FRDE_MASK (0x1U)
+#define I2S_TCSR_FRDE_SHIFT (0U)
+#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK (0x2U)
+#define I2S_TCSR_FWDE_SHIFT (1U)
+#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK (0x100U)
+#define I2S_TCSR_FRIE_SHIFT (8U)
+#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK (0x200U)
+#define I2S_TCSR_FWIE_SHIFT (9U)
+#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK (0x400U)
+#define I2S_TCSR_FEIE_SHIFT (10U)
+#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK (0x800U)
+#define I2S_TCSR_SEIE_SHIFT (11U)
+#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT (12U)
+#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK (0x10000U)
+#define I2S_TCSR_FRF_SHIFT (16U)
+#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK (0x20000U)
+#define I2S_TCSR_FWF_SHIFT (17U)
+#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK (0x40000U)
+#define I2S_TCSR_FEF_SHIFT (18U)
+#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK (0x80000U)
+#define I2S_TCSR_SEF_SHIFT (19U)
+#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK (0x100000U)
+#define I2S_TCSR_WSF_SHIFT (20U)
+#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK (0x1000000U)
+#define I2S_TCSR_SR_SHIFT (24U)
+#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK (0x2000000U)
+#define I2S_TCSR_FR_SHIFT (25U)
+#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT (28U)
+#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT (29U)
+#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT (30U)
+#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK (0x80000000U)
+#define I2S_TCSR_TE_SHIFT (31U)
+#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+#define I2S_TCR1_TFW_MASK (0x7U)
+#define I2S_TCR1_TFW_SHIFT (0U)
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK (0xFFU)
+#define I2S_TCR2_DIV_SHIFT (0U)
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT (24U)
+#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT (25U)
+#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT (26U)
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT (28U)
+#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT (29U)
+#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT (30U)
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT (0U)
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK (0x30000U)
+#define I2S_TCR3_TCE_SHIFT (16U)
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK (0x1U)
+#define I2S_TCR4_FSD_SHIFT (0U)
+#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK (0x2U)
+#define I2S_TCR4_FSP_SHIFT (1U)
+#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSE_MASK (0x8U)
+#define I2S_TCR4_FSE_SHIFT (3U)
+#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK (0x10U)
+#define I2S_TCR4_MF_SHIFT (4U)
+#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT (8U)
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT (16U)
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT (8U)
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT (16U)
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT (24U)
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT (0U)
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+#define I2S_TFR_RFP_MASK (0xFU)
+#define I2S_TFR_RFP_SHIFT (0U)
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK (0xF0000U)
+#define I2S_TFR_WFP_SHIFT (16U)
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT (2U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
+#define I2S_TMR_TWM_SHIFT (0U)
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FRDE_MASK (0x1U)
+#define I2S_RCSR_FRDE_SHIFT (0U)
+#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK (0x2U)
+#define I2S_RCSR_FWDE_SHIFT (1U)
+#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK (0x100U)
+#define I2S_RCSR_FRIE_SHIFT (8U)
+#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK (0x200U)
+#define I2S_RCSR_FWIE_SHIFT (9U)
+#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK (0x400U)
+#define I2S_RCSR_FEIE_SHIFT (10U)
+#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK (0x800U)
+#define I2S_RCSR_SEIE_SHIFT (11U)
+#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT (12U)
+#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK (0x10000U)
+#define I2S_RCSR_FRF_SHIFT (16U)
+#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK (0x20000U)
+#define I2S_RCSR_FWF_SHIFT (17U)
+#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK (0x40000U)
+#define I2S_RCSR_FEF_SHIFT (18U)
+#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK (0x80000U)
+#define I2S_RCSR_SEF_SHIFT (19U)
+#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK (0x100000U)
+#define I2S_RCSR_WSF_SHIFT (20U)
+#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK (0x1000000U)
+#define I2S_RCSR_SR_SHIFT (24U)
+#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK (0x2000000U)
+#define I2S_RCSR_FR_SHIFT (25U)
+#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT (28U)
+#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT (29U)
+#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT (30U)
+#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK (0x80000000U)
+#define I2S_RCSR_RE_SHIFT (31U)
+#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+#define I2S_RCR1_RFW_MASK (0x7U)
+#define I2S_RCR1_RFW_SHIFT (0U)
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK (0xFFU)
+#define I2S_RCR2_DIV_SHIFT (0U)
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT (24U)
+#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT (25U)
+#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT (26U)
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT (28U)
+#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT (29U)
+#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT (30U)
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT (0U)
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK (0x30000U)
+#define I2S_RCR3_RCE_SHIFT (16U)
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK (0x1U)
+#define I2S_RCR4_FSD_SHIFT (0U)
+#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK (0x2U)
+#define I2S_RCR4_FSP_SHIFT (1U)
+#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSE_MASK (0x8U)
+#define I2S_RCR4_FSE_SHIFT (3U)
+#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK (0x10U)
+#define I2S_RCR4_MF_SHIFT (4U)
+#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT (8U)
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT (16U)
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT (8U)
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT (16U)
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT (24U)
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT (0U)
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+#define I2S_RFR_RFP_MASK (0xFU)
+#define I2S_RFR_RFP_SHIFT (0U)
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK (0xF0000U)
+#define I2S_RFR_WFP_SHIFT (16U)
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT (2U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
+#define I2S_RMR_RWM_SHIFT (0U)
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK (0x3000000U)
+#define I2S_MCR_MICS_SHIFT (24U)
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK (0x40000000U)
+#define I2S_MCR_MOE_SHIFT (30U)
+#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK (0x80000000U)
+#define I2S_MCR_DUF_SHIFT (31U)
+#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT (0U)
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT (12U)
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
/*!
* @}
@@ -8789,7 +6048,6 @@ typedef struct {
#define I2S0_BASE (0x4002F000u)
/** Peripheral I2S0 base pointer */
#define I2S0 ((I2S_Type *)I2S0_BASE)
-#define I2S0_BASE_PTR (I2S0)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { I2S0_BASE }
/** Array initializer of I2S peripheral base pointers */
@@ -8798,54 +6056,6 @@ typedef struct {
#define I2S_RX_IRQS { I2S0_Rx_IRQn }
#define I2S_TX_IRQS { I2S0_Tx_IRQn }
-/* ----------------------------------------------------------------------------
- -- I2S - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
- * @{
- */
-
-
-/* I2S - Register instance definitions */
-/* I2S0 */
-#define I2S0_TCSR I2S_TCSR_REG(I2S0)
-#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
-#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
-#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
-#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
-#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
-#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
-#define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
-#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
-#define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
-#define I2S0_TMR I2S_TMR_REG(I2S0)
-#define I2S0_RCSR I2S_RCSR_REG(I2S0)
-#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
-#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
-#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
-#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
-#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
-#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
-#define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
-#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
-#define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
-#define I2S0_RMR I2S_RMR_REG(I2S0)
-#define I2S0_MCR I2S_MCR_REG(I2S0)
-#define I2S0_MDR I2S_MDR_REG(I2S0)
-
-/* I2S - Register array accessors */
-#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
-#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
-#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
-#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
-
-/*!
- * @}
- */ /* end of group I2S_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
@@ -8873,35 +6083,7 @@ typedef struct {
__IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
__IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
__IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
-} LLWU_Type, *LLWU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register accessors */
-#define LLWU_PE1_REG(base) ((base)->PE1)
-#define LLWU_PE2_REG(base) ((base)->PE2)
-#define LLWU_PE3_REG(base) ((base)->PE3)
-#define LLWU_PE4_REG(base) ((base)->PE4)
-#define LLWU_ME_REG(base) ((base)->ME)
-#define LLWU_F1_REG(base) ((base)->F1)
-#define LLWU_F2_REG(base) ((base)->F2)
-#define LLWU_F3_REG(base) ((base)->F3)
-#define LLWU_FILT1_REG(base) ((base)->FILT1)
-#define LLWU_FILT2_REG(base) ((base)->FILT2)
-#define LLWU_RST_REG(base) ((base)->RST)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
+} LLWU_Type;
/* ----------------------------------------------------------------------------
-- LLWU Register Masks
@@ -8912,241 +6094,196 @@ typedef struct {
* @{
*/
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0_WIDTH 2
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1_WIDTH 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2_WIDTH 2
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3_WIDTH 2
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4_WIDTH 2
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5_WIDTH 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6_WIDTH 2
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7_WIDTH 2
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8_WIDTH 2
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9_WIDTH 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10_WIDTH 2
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11_WIDTH 2
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12_WIDTH 2
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13_WIDTH 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14_WIDTH 2
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15_WIDTH 2
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME0_WIDTH 1
-#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME1_WIDTH 1
-#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME2_WIDTH 1
-#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME3_WIDTH 1
-#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME4_WIDTH 1
-#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME5_WIDTH 1
-#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME6_WIDTH 1
-#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-#define LLWU_ME_WUME7_WIDTH 1
-#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF0_WIDTH 1
-#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF0_SHIFT))&LLWU_F1_WUF0_MASK)
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF1_WIDTH 1
-#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF1_SHIFT))&LLWU_F1_WUF1_MASK)
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF2_WIDTH 1
-#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF2_SHIFT))&LLWU_F1_WUF2_MASK)
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF3_WIDTH 1
-#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF3_SHIFT))&LLWU_F1_WUF3_MASK)
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF4_WIDTH 1
-#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF4_SHIFT))&LLWU_F1_WUF4_MASK)
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF5_WIDTH 1
-#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF5_SHIFT))&LLWU_F1_WUF5_MASK)
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF6_WIDTH 1
-#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF6_SHIFT))&LLWU_F1_WUF6_MASK)
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-#define LLWU_F1_WUF7_WIDTH 1
-#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F1_WUF7_SHIFT))&LLWU_F1_WUF7_MASK)
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF8_WIDTH 1
-#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF8_SHIFT))&LLWU_F2_WUF8_MASK)
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF9_WIDTH 1
-#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF9_SHIFT))&LLWU_F2_WUF9_MASK)
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF10_WIDTH 1
-#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF10_SHIFT))&LLWU_F2_WUF10_MASK)
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF11_WIDTH 1
-#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF11_SHIFT))&LLWU_F2_WUF11_MASK)
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF12_WIDTH 1
-#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF12_SHIFT))&LLWU_F2_WUF12_MASK)
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF13_WIDTH 1
-#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF13_SHIFT))&LLWU_F2_WUF13_MASK)
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF14_WIDTH 1
-#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF14_SHIFT))&LLWU_F2_WUF14_MASK)
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-#define LLWU_F2_WUF15_WIDTH 1
-#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F2_WUF15_SHIFT))&LLWU_F2_WUF15_MASK)
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF0_WIDTH 1
-#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF0_SHIFT))&LLWU_F3_MWUF0_MASK)
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF1_WIDTH 1
-#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF1_SHIFT))&LLWU_F3_MWUF1_MASK)
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF2_WIDTH 1
-#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF2_SHIFT))&LLWU_F3_MWUF2_MASK)
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF3_WIDTH 1
-#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF3_SHIFT))&LLWU_F3_MWUF3_MASK)
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF4_WIDTH 1
-#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF4_SHIFT))&LLWU_F3_MWUF4_MASK)
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF5_WIDTH 1
-#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF5_SHIFT))&LLWU_F3_MWUF5_MASK)
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF6_WIDTH 1
-#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF6_SHIFT))&LLWU_F3_MWUF6_MASK)
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-#define LLWU_F3_MWUF7_WIDTH 1
-#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_F3_MWUF7_SHIFT))&LLWU_F3_MWUF7_MASK)
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL_WIDTH 4
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE_WIDTH 2
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-#define LLWU_FILT1_FILTF_WIDTH 1
-#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL_WIDTH 4
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE_WIDTH 2
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-#define LLWU_FILT2_FILTF_WIDTH 1
-#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
-/* RST Bit Fields */
-#define LLWU_RST_RSTFILT_MASK 0x1u
-#define LLWU_RST_RSTFILT_SHIFT 0
-#define LLWU_RST_RSTFILT_WIDTH 1
-#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x))<<LLWU_RST_RSTFILT_SHIFT))&LLWU_RST_RSTFILT_MASK)
-#define LLWU_RST_LLRSTE_MASK 0x2u
-#define LLWU_RST_LLRSTE_SHIFT 1
-#define LLWU_RST_LLRSTE_WIDTH 1
-#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_RST_LLRSTE_SHIFT))&LLWU_RST_LLRSTE_MASK)
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT (0U)
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT (2U)
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT (4U)
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT (6U)
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT (0U)
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT (2U)
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT (4U)
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT (6U)
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT (0U)
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT (2U)
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT (4U)
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT (6U)
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT (0U)
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT (2U)
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT (4U)
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT (6U)
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK (0x1U)
+#define LLWU_ME_WUME0_SHIFT (0U)
+#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK (0x2U)
+#define LLWU_ME_WUME1_SHIFT (1U)
+#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK (0x4U)
+#define LLWU_ME_WUME2_SHIFT (2U)
+#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK (0x8U)
+#define LLWU_ME_WUME3_SHIFT (3U)
+#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK (0x10U)
+#define LLWU_ME_WUME4_SHIFT (4U)
+#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK (0x20U)
+#define LLWU_ME_WUME5_SHIFT (5U)
+#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK (0x40U)
+#define LLWU_ME_WUME6_SHIFT (6U)
+#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK (0x80U)
+#define LLWU_ME_WUME7_SHIFT (7U)
+#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name F1 - LLWU Flag 1 register */
+#define LLWU_F1_WUF0_MASK (0x1U)
+#define LLWU_F1_WUF0_SHIFT (0U)
+#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
+#define LLWU_F1_WUF1_MASK (0x2U)
+#define LLWU_F1_WUF1_SHIFT (1U)
+#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
+#define LLWU_F1_WUF2_MASK (0x4U)
+#define LLWU_F1_WUF2_SHIFT (2U)
+#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
+#define LLWU_F1_WUF3_MASK (0x8U)
+#define LLWU_F1_WUF3_SHIFT (3U)
+#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
+#define LLWU_F1_WUF4_MASK (0x10U)
+#define LLWU_F1_WUF4_SHIFT (4U)
+#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
+#define LLWU_F1_WUF5_MASK (0x20U)
+#define LLWU_F1_WUF5_SHIFT (5U)
+#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
+#define LLWU_F1_WUF6_MASK (0x40U)
+#define LLWU_F1_WUF6_SHIFT (6U)
+#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
+#define LLWU_F1_WUF7_MASK (0x80U)
+#define LLWU_F1_WUF7_SHIFT (7U)
+#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
+
+/*! @name F2 - LLWU Flag 2 register */
+#define LLWU_F2_WUF8_MASK (0x1U)
+#define LLWU_F2_WUF8_SHIFT (0U)
+#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
+#define LLWU_F2_WUF9_MASK (0x2U)
+#define LLWU_F2_WUF9_SHIFT (1U)
+#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
+#define LLWU_F2_WUF10_MASK (0x4U)
+#define LLWU_F2_WUF10_SHIFT (2U)
+#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
+#define LLWU_F2_WUF11_MASK (0x8U)
+#define LLWU_F2_WUF11_SHIFT (3U)
+#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
+#define LLWU_F2_WUF12_MASK (0x10U)
+#define LLWU_F2_WUF12_SHIFT (4U)
+#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
+#define LLWU_F2_WUF13_MASK (0x20U)
+#define LLWU_F2_WUF13_SHIFT (5U)
+#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
+#define LLWU_F2_WUF14_MASK (0x40U)
+#define LLWU_F2_WUF14_SHIFT (6U)
+#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
+#define LLWU_F2_WUF15_MASK (0x80U)
+#define LLWU_F2_WUF15_SHIFT (7U)
+#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
+
+/*! @name F3 - LLWU Flag 3 register */
+#define LLWU_F3_MWUF0_MASK (0x1U)
+#define LLWU_F3_MWUF0_SHIFT (0U)
+#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
+#define LLWU_F3_MWUF1_MASK (0x2U)
+#define LLWU_F3_MWUF1_SHIFT (1U)
+#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
+#define LLWU_F3_MWUF2_MASK (0x4U)
+#define LLWU_F3_MWUF2_SHIFT (2U)
+#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
+#define LLWU_F3_MWUF3_MASK (0x8U)
+#define LLWU_F3_MWUF3_SHIFT (3U)
+#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
+#define LLWU_F3_MWUF4_MASK (0x10U)
+#define LLWU_F3_MWUF4_SHIFT (4U)
+#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
+#define LLWU_F3_MWUF5_MASK (0x20U)
+#define LLWU_F3_MWUF5_SHIFT (5U)
+#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
+#define LLWU_F3_MWUF6_MASK (0x40U)
+#define LLWU_F3_MWUF6_SHIFT (6U)
+#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
+#define LLWU_F3_MWUF7_MASK (0x80U)
+#define LLWU_F3_MWUF7_SHIFT (7U)
+#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT (0U)
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT (5U)
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT (7U)
+#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT (0U)
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT (5U)
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT (7U)
+#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
+/*! @name RST - LLWU Reset Enable register */
+#define LLWU_RST_RSTFILT_MASK (0x1U)
+#define LLWU_RST_RSTFILT_SHIFT (0U)
+#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
+#define LLWU_RST_LLRSTE_MASK (0x2U)
+#define LLWU_RST_LLRSTE_SHIFT (1U)
+#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
+
/*!
* @}
@@ -9158,7 +6295,6 @@ typedef struct {
#define LLWU_BASE (0x4007C000u)
/** Peripheral LLWU base pointer */
#define LLWU ((LLWU_Type *)LLWU_BASE)
-#define LLWU_BASE_PTR (LLWU)
/** Array initializer of LLWU peripheral base addresses */
#define LLWU_BASE_ADDRS { LLWU_BASE }
/** Array initializer of LLWU peripheral base pointers */
@@ -9166,35 +6302,6 @@ typedef struct {
/** Interrupt vectors for the LLWU peripheral type */
#define LLWU_IRQS { LLWU_IRQn }
-/* ----------------------------------------------------------------------------
- -- LLWU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
- * @{
- */
-
-
-/* LLWU - Register instance definitions */
-/* LLWU */
-#define LLWU_PE1 LLWU_PE1_REG(LLWU)
-#define LLWU_PE2 LLWU_PE2_REG(LLWU)
-#define LLWU_PE3 LLWU_PE3_REG(LLWU)
-#define LLWU_PE4 LLWU_PE4_REG(LLWU)
-#define LLWU_ME LLWU_ME_REG(LLWU)
-#define LLWU_F1 LLWU_F1_REG(LLWU)
-#define LLWU_F2 LLWU_F2_REG(LLWU)
-#define LLWU_F3 LLWU_F3_REG(LLWU)
-#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
-#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
-#define LLWU_RST LLWU_RST_REG(LLWU)
-
-/*!
- * @}
- */ /* end of group LLWU_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LLWU_Peripheral_Access_Layer */
@@ -9215,28 +6322,7 @@ typedef struct {
__IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
__IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
__IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type, *LPTMR_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register accessors */
-#define LPTMR_CSR_REG(base) ((base)->CSR)
-#define LPTMR_PSR_REG(base) ((base)->PSR)
-#define LPTMR_CMR_REG(base) ((base)->CMR)
-#define LPTMR_CNR_REG(base) ((base)->CNR)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
+} LPTMR_Type;
/* ----------------------------------------------------------------------------
-- LPTMR Register Masks
@@ -9247,58 +6333,50 @@ typedef struct {
* @{
*/
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TEN_WIDTH 1
-#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TMS_WIDTH 1
-#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TFC_WIDTH 1
-#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPP_WIDTH 1
-#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS_WIDTH 2
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TIE_WIDTH 1
-#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-#define LPTMR_CSR_TCF_WIDTH 1
-#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS_WIDTH 2
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PBYP_WIDTH 1
-#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE_WIDTH 4
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE_WIDTH 16
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER_WIDTH 16
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK (0x1U)
+#define LPTMR_CSR_TEN_SHIFT (0U)
+#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK (0x2U)
+#define LPTMR_CSR_TMS_SHIFT (1U)
+#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK (0x4U)
+#define LPTMR_CSR_TFC_SHIFT (2U)
+#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK (0x8U)
+#define LPTMR_CSR_TPP_SHIFT (3U)
+#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK (0x30U)
+#define LPTMR_CSR_TPS_SHIFT (4U)
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK (0x40U)
+#define LPTMR_CSR_TIE_SHIFT (6U)
+#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK (0x80U)
+#define LPTMR_CSR_TCF_SHIFT (7U)
+#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK (0x3U)
+#define LPTMR_PSR_PCS_SHIFT (0U)
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT (2U)
+#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT (3U)
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT (0U)
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT (0U)
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
/*!
* @}
@@ -9310,7 +6388,6 @@ typedef struct {
#define LPTMR0_BASE (0x40040000u)
/** Peripheral LPTMR0 base pointer */
#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-#define LPTMR0_BASE_PTR (LPTMR0)
/** Array initializer of LPTMR peripheral base addresses */
#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
/** Array initializer of LPTMR peripheral base pointers */
@@ -9318,28 +6395,6 @@ typedef struct {
/** Interrupt vectors for the LPTMR peripheral type */
#define LPTMR_IRQS { LPTMR0_IRQn }
-/* ----------------------------------------------------------------------------
- -- LPTMR - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
- * @{
- */
-
-
-/* LPTMR - Register instance definitions */
-/* LPTMR0 */
-#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
-#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
-#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
-#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
-
-/*!
- * @}
- */ /* end of group LPTMR_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group LPTMR_Peripheral_Access_Layer */
@@ -9370,36 +6425,7 @@ typedef struct {
__IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
__IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
__IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
-} MCG_Type, *MCG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register accessors */
-#define MCG_C1_REG(base) ((base)->C1)
-#define MCG_C2_REG(base) ((base)->C2)
-#define MCG_C3_REG(base) ((base)->C3)
-#define MCG_C4_REG(base) ((base)->C4)
-#define MCG_C5_REG(base) ((base)->C5)
-#define MCG_C6_REG(base) ((base)->C6)
-#define MCG_S_REG(base) ((base)->S)
-#define MCG_SC_REG(base) ((base)->SC)
-#define MCG_ATCVH_REG(base) ((base)->ATCVH)
-#define MCG_ATCVL_REG(base) ((base)->ATCVL)
-#define MCG_C7_REG(base) ((base)->C7)
-#define MCG_C8_REG(base) ((base)->C8)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
+} MCG_Type;
/* ----------------------------------------------------------------------------
-- MCG Register Masks
@@ -9410,190 +6436,159 @@ typedef struct {
* @{
*/
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IREFSTEN_WIDTH 1
-#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IRCLKEN_WIDTH 1
-#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_IREFS_WIDTH 1
-#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV_WIDTH 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS_WIDTH 2
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_IRCS_WIDTH 1
-#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_LP_WIDTH 1
-#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
-#define MCG_C2_EREFS_MASK 0x4u
-#define MCG_C2_EREFS_SHIFT 2
-#define MCG_C2_EREFS_WIDTH 1
-#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
-#define MCG_C2_HGO_MASK 0x8u
-#define MCG_C2_HGO_SHIFT 3
-#define MCG_C2_HGO_WIDTH 1
-#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
-#define MCG_C2_RANGE_MASK 0x30u
-#define MCG_C2_RANGE_SHIFT 4
-#define MCG_C2_RANGE_WIDTH 2
-#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-#define MCG_C2_LOCRE0_WIDTH 1
-#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM_WIDTH 8
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_SCFTRIM_WIDTH 1
-#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM_WIDTH 4
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS_WIDTH 2
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-#define MCG_C4_DMX32_WIDTH 1
-#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK 0x1Fu
-#define MCG_C5_PRDIV0_SHIFT 0
-#define MCG_C5_PRDIV0_WIDTH 5
-#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK 0x20u
-#define MCG_C5_PLLSTEN0_SHIFT 5
-#define MCG_C5_PLLSTEN0_WIDTH 1
-#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
-#define MCG_C5_PLLCLKEN0_MASK 0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT 6
-#define MCG_C5_PLLCLKEN0_WIDTH 1
-#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK 0x1Fu
-#define MCG_C6_VDIV0_SHIFT 0
-#define MCG_C6_VDIV0_WIDTH 5
-#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK 0x20u
-#define MCG_C6_CME0_SHIFT 5
-#define MCG_C6_CME0_WIDTH 1
-#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
-#define MCG_C6_PLLS_MASK 0x40u
-#define MCG_C6_PLLS_SHIFT 6
-#define MCG_C6_PLLS_WIDTH 1
-#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
-#define MCG_C6_LOLIE0_MASK 0x80u
-#define MCG_C6_LOLIE0_SHIFT 7
-#define MCG_C6_LOLIE0_WIDTH 1
-#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_IRCST_WIDTH 1
-#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_OSCINIT0_WIDTH 1
-#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST_WIDTH 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_IREFST_WIDTH 1
-#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
-#define MCG_S_PLLST_MASK 0x20u
-#define MCG_S_PLLST_SHIFT 5
-#define MCG_S_PLLST_WIDTH 1
-#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
-#define MCG_S_LOCK0_MASK 0x40u
-#define MCG_S_LOCK0_SHIFT 6
-#define MCG_S_LOCK0_WIDTH 1
-#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
-#define MCG_S_LOLS0_MASK 0x80u
-#define MCG_S_LOLS0_SHIFT 7
-#define MCG_S_LOLS0_WIDTH 1
-#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_LOCS0_WIDTH 1
-#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV_WIDTH 3
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_FLTPRSRV_WIDTH 1
-#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMF_WIDTH 1
-#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATMS_WIDTH 1
-#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-#define MCG_SC_ATME_WIDTH 1
-#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH_WIDTH 8
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL_WIDTH 8
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C7 Bit Fields */
-#define MCG_C7_OSCSEL_MASK 0x1u
-#define MCG_C7_OSCSEL_SHIFT 0
-#define MCG_C7_OSCSEL_WIDTH 1
-#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
-/* C8 Bit Fields */
-#define MCG_C8_LOCS1_MASK 0x1u
-#define MCG_C8_LOCS1_SHIFT 0
-#define MCG_C8_LOCS1_WIDTH 1
-#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
-#define MCG_C8_CME1_MASK 0x20u
-#define MCG_C8_CME1_SHIFT 5
-#define MCG_C8_CME1_WIDTH 1
-#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
-#define MCG_C8_LOLRE_MASK 0x40u
-#define MCG_C8_LOLRE_SHIFT 6
-#define MCG_C8_LOLRE_WIDTH 1
-#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
-#define MCG_C8_LOCRE1_MASK 0x80u
-#define MCG_C8_LOCRE1_SHIFT 7
-#define MCG_C8_LOCRE1_WIDTH 1
-#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT (0U)
+#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT (1U)
+#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK (0x4U)
+#define MCG_C1_IREFS_SHIFT (2U)
+#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK (0x38U)
+#define MCG_C1_FRDIV_SHIFT (3U)
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK (0xC0U)
+#define MCG_C1_CLKS_SHIFT (6U)
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK (0x1U)
+#define MCG_C2_IRCS_SHIFT (0U)
+#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK (0x2U)
+#define MCG_C2_LP_SHIFT (1U)
+#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK (0x4U)
+#define MCG_C2_EREFS_SHIFT (2U)
+#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
+#define MCG_C2_HGO_MASK (0x8U)
+#define MCG_C2_HGO_SHIFT (3U)
+#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK (0x30U)
+#define MCG_C2_RANGE_SHIFT (4U)
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_LOCRE0_MASK (0x80U)
+#define MCG_C2_LOCRE0_SHIFT (7U)
+#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT (0U)
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT (0U)
+#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT (1U)
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT (5U)
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK (0x80U)
+#define MCG_C4_DMX32_SHIFT (7U)
+#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV0_MASK (0x1FU)
+#define MCG_C5_PRDIV0_SHIFT (0U)
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK (0x20U)
+#define MCG_C5_PLLSTEN0_SHIFT (5U)
+#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
+#define MCG_C5_PLLCLKEN0_MASK (0x40U)
+#define MCG_C5_PLLCLKEN0_SHIFT (6U)
+#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV0_MASK (0x1FU)
+#define MCG_C6_VDIV0_SHIFT (0U)
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK (0x20U)
+#define MCG_C6_CME0_SHIFT (5U)
+#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK (0x40U)
+#define MCG_C6_PLLS_SHIFT (6U)
+#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_LOLIE0_MASK (0x80U)
+#define MCG_C6_LOLIE0_SHIFT (7U)
+#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK (0x1U)
+#define MCG_S_IRCST_SHIFT (0U)
+#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK (0x2U)
+#define MCG_S_OSCINIT0_SHIFT (1U)
+#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_CLKST_MASK (0xCU)
+#define MCG_S_CLKST_SHIFT (2U)
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK (0x10U)
+#define MCG_S_IREFST_SHIFT (4U)
+#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_PLLST_MASK (0x20U)
+#define MCG_S_PLLST_SHIFT (5U)
+#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_LOCK0_MASK (0x40U)
+#define MCG_S_LOCK0_SHIFT (6U)
+#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOLS0_MASK (0x80U)
+#define MCG_S_LOLS0_SHIFT (7U)
+#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK (0x1U)
+#define MCG_SC_LOCS0_SHIFT (0U)
+#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK (0xEU)
+#define MCG_SC_FCRDIV_SHIFT (1U)
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT (4U)
+#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK (0x20U)
+#define MCG_SC_ATMF_SHIFT (5U)
+#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK (0x40U)
+#define MCG_SC_ATMS_SHIFT (6U)
+#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK (0x80U)
+#define MCG_SC_ATME_SHIFT (7U)
+#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT (0U)
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT (0U)
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK (0x1U)
+#define MCG_C7_OSCSEL_SHIFT (0U)
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1_MASK (0x1U)
+#define MCG_C8_LOCS1_SHIFT (0U)
+#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK (0x20U)
+#define MCG_C8_CME1_SHIFT (5U)
+#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK (0x40U)
+#define MCG_C8_LOLRE_SHIFT (6U)
+#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK (0x80U)
+#define MCG_C8_LOCRE1_SHIFT (7U)
+#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+
/*!
* @}
@@ -9605,42 +6600,11 @@ typedef struct {
#define MCG_BASE (0x40064000u)
/** Peripheral MCG base pointer */
#define MCG ((MCG_Type *)MCG_BASE)
-#define MCG_BASE_PTR (MCG)
/** Array initializer of MCG peripheral base addresses */
#define MCG_BASE_ADDRS { MCG_BASE }
/** Array initializer of MCG peripheral base pointers */
#define MCG_BASE_PTRS { MCG }
-/* ----------------------------------------------------------------------------
- -- MCG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
- * @{
- */
-
-
-/* MCG - Register instance definitions */
-/* MCG */
-#define MCG_C1 MCG_C1_REG(MCG)
-#define MCG_C2 MCG_C2_REG(MCG)
-#define MCG_C3 MCG_C3_REG(MCG)
-#define MCG_C4 MCG_C4_REG(MCG)
-#define MCG_C5 MCG_C5_REG(MCG)
-#define MCG_C6 MCG_C6_REG(MCG)
-#define MCG_S MCG_S_REG(MCG)
-#define MCG_SC MCG_SC_REG(MCG)
-#define MCG_ATCVH MCG_ATCVH_REG(MCG)
-#define MCG_ATCVL MCG_ATCVL_REG(MCG)
-#define MCG_C7 MCG_C7_REG(MCG)
-#define MCG_C8 MCG_C8_REG(MCG)
-
-/*!
- * @}
- */ /* end of group MCG_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group MCG_Peripheral_Access_Layer */
@@ -9667,32 +6631,7 @@ typedef struct {
__I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
uint8_t RESERVED_1[16];
__IO uint32_t PID; /**< Process ID register, offset: 0x30 */
-} MCM_Type, *MCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register accessors */
-#define MCM_PLASC_REG(base) ((base)->PLASC)
-#define MCM_PLAMC_REG(base) ((base)->PLAMC)
-#define MCM_CR_REG(base) ((base)->CR)
-#define MCM_ISCR_REG(base) ((base)->ISCR)
-#define MCM_ETBCC_REG(base) ((base)->ETBCC)
-#define MCM_ETBRL_REG(base) ((base)->ETBRL)
-#define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
-#define MCM_PID_REG(base) ((base)->PID)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
+} MCM_Type;
/* ----------------------------------------------------------------------------
-- MCM Register Masks
@@ -9703,130 +6642,109 @@ typedef struct {
* @{
*/
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK 0xFFu
-#define MCM_PLASC_ASC_SHIFT 0
-#define MCM_PLASC_ASC_WIDTH 8
-#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK 0xFFu
-#define MCM_PLAMC_AMC_SHIFT 0
-#define MCM_PLAMC_AMC_WIDTH 8
-#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* CR Bit Fields */
-#define MCM_CR_SRAMUAP_MASK 0x3000000u
-#define MCM_CR_SRAMUAP_SHIFT 24
-#define MCM_CR_SRAMUAP_WIDTH 2
-#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
-#define MCM_CR_SRAMUWP_MASK 0x4000000u
-#define MCM_CR_SRAMUWP_SHIFT 26
-#define MCM_CR_SRAMUWP_WIDTH 1
-#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUWP_SHIFT))&MCM_CR_SRAMUWP_MASK)
-#define MCM_CR_SRAMLAP_MASK 0x30000000u
-#define MCM_CR_SRAMLAP_SHIFT 28
-#define MCM_CR_SRAMLAP_WIDTH 2
-#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
-#define MCM_CR_SRAMLWP_MASK 0x40000000u
-#define MCM_CR_SRAMLWP_SHIFT 30
-#define MCM_CR_SRAMLWP_WIDTH 1
-#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLWP_SHIFT))&MCM_CR_SRAMLWP_MASK)
-/* ISCR Bit Fields */
-#define MCM_ISCR_IRQ_MASK 0x2u
-#define MCM_ISCR_IRQ_SHIFT 1
-#define MCM_ISCR_IRQ_WIDTH 1
-#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_IRQ_SHIFT))&MCM_ISCR_IRQ_MASK)
-#define MCM_ISCR_NMI_MASK 0x4u
-#define MCM_ISCR_NMI_SHIFT 2
-#define MCM_ISCR_NMI_WIDTH 1
-#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_NMI_SHIFT))&MCM_ISCR_NMI_MASK)
-#define MCM_ISCR_DHREQ_MASK 0x8u
-#define MCM_ISCR_DHREQ_SHIFT 3
-#define MCM_ISCR_DHREQ_WIDTH 1
-#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_DHREQ_SHIFT))&MCM_ISCR_DHREQ_MASK)
-#define MCM_ISCR_FIOC_MASK 0x100u
-#define MCM_ISCR_FIOC_SHIFT 8
-#define MCM_ISCR_FIOC_WIDTH 1
-#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
-#define MCM_ISCR_FDZC_MASK 0x200u
-#define MCM_ISCR_FDZC_SHIFT 9
-#define MCM_ISCR_FDZC_WIDTH 1
-#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
-#define MCM_ISCR_FOFC_MASK 0x400u
-#define MCM_ISCR_FOFC_SHIFT 10
-#define MCM_ISCR_FOFC_WIDTH 1
-#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
-#define MCM_ISCR_FUFC_MASK 0x800u
-#define MCM_ISCR_FUFC_SHIFT 11
-#define MCM_ISCR_FUFC_WIDTH 1
-#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
-#define MCM_ISCR_FIXC_MASK 0x1000u
-#define MCM_ISCR_FIXC_SHIFT 12
-#define MCM_ISCR_FIXC_WIDTH 1
-#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
-#define MCM_ISCR_FIDC_MASK 0x8000u
-#define MCM_ISCR_FIDC_SHIFT 15
-#define MCM_ISCR_FIDC_WIDTH 1
-#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
-#define MCM_ISCR_FIOCE_MASK 0x1000000u
-#define MCM_ISCR_FIOCE_SHIFT 24
-#define MCM_ISCR_FIOCE_WIDTH 1
-#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
-#define MCM_ISCR_FDZCE_MASK 0x2000000u
-#define MCM_ISCR_FDZCE_SHIFT 25
-#define MCM_ISCR_FDZCE_WIDTH 1
-#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
-#define MCM_ISCR_FOFCE_MASK 0x4000000u
-#define MCM_ISCR_FOFCE_SHIFT 26
-#define MCM_ISCR_FOFCE_WIDTH 1
-#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
-#define MCM_ISCR_FUFCE_MASK 0x8000000u
-#define MCM_ISCR_FUFCE_SHIFT 27
-#define MCM_ISCR_FUFCE_WIDTH 1
-#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
-#define MCM_ISCR_FIXCE_MASK 0x10000000u
-#define MCM_ISCR_FIXCE_SHIFT 28
-#define MCM_ISCR_FIXCE_WIDTH 1
-#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
-#define MCM_ISCR_FIDCE_MASK 0x80000000u
-#define MCM_ISCR_FIDCE_SHIFT 31
-#define MCM_ISCR_FIDCE_WIDTH 1
-#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
-/* ETBCC Bit Fields */
-#define MCM_ETBCC_CNTEN_MASK 0x1u
-#define MCM_ETBCC_CNTEN_SHIFT 0
-#define MCM_ETBCC_CNTEN_WIDTH 1
-#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_CNTEN_SHIFT))&MCM_ETBCC_CNTEN_MASK)
-#define MCM_ETBCC_RSPT_MASK 0x6u
-#define MCM_ETBCC_RSPT_SHIFT 1
-#define MCM_ETBCC_RSPT_WIDTH 2
-#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
-#define MCM_ETBCC_RLRQ_MASK 0x8u
-#define MCM_ETBCC_RLRQ_SHIFT 3
-#define MCM_ETBCC_RLRQ_WIDTH 1
-#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RLRQ_SHIFT))&MCM_ETBCC_RLRQ_MASK)
-#define MCM_ETBCC_ETDIS_MASK 0x10u
-#define MCM_ETBCC_ETDIS_SHIFT 4
-#define MCM_ETBCC_ETDIS_WIDTH 1
-#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ETDIS_SHIFT))&MCM_ETBCC_ETDIS_MASK)
-#define MCM_ETBCC_ITDIS_MASK 0x20u
-#define MCM_ETBCC_ITDIS_SHIFT 5
-#define MCM_ETBCC_ITDIS_WIDTH 1
-#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_ITDIS_SHIFT))&MCM_ETBCC_ITDIS_MASK)
-/* ETBRL Bit Fields */
-#define MCM_ETBRL_RELOAD_MASK 0x7FFu
-#define MCM_ETBRL_RELOAD_SHIFT 0
-#define MCM_ETBRL_RELOAD_WIDTH 11
-#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
-/* ETBCNT Bit Fields */
-#define MCM_ETBCNT_COUNTER_MASK 0x7FFu
-#define MCM_ETBCNT_COUNTER_SHIFT 0
-#define MCM_ETBCNT_COUNTER_WIDTH 11
-#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
-/* PID Bit Fields */
-#define MCM_PID_PID_MASK 0xFFu
-#define MCM_PID_PID_SHIFT 0
-#define MCM_PID_PID_WIDTH 8
-#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK (0xFFU)
+#define MCM_PLASC_ASC_SHIFT (0U)
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT (0U)
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name CR - Control Register */
+#define MCM_CR_SRAMUAP_MASK (0x3000000U)
+#define MCM_CR_SRAMUAP_SHIFT (24U)
+#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK (0x4000000U)
+#define MCM_CR_SRAMUWP_SHIFT (26U)
+#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK (0x30000000U)
+#define MCM_CR_SRAMLAP_SHIFT (28U)
+#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK (0x40000000U)
+#define MCM_CR_SRAMLWP_SHIFT (30U)
+#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
+
+/*! @name ISCR - Interrupt Status Register */
+#define MCM_ISCR_IRQ_MASK (0x2U)
+#define MCM_ISCR_IRQ_SHIFT (1U)
+#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK (0x4U)
+#define MCM_ISCR_NMI_SHIFT (2U)
+#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK (0x8U)
+#define MCM_ISCR_DHREQ_SHIFT (3U)
+#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK (0x100U)
+#define MCM_ISCR_FIOC_SHIFT (8U)
+#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK (0x200U)
+#define MCM_ISCR_FDZC_SHIFT (9U)
+#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK (0x400U)
+#define MCM_ISCR_FOFC_SHIFT (10U)
+#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK (0x800U)
+#define MCM_ISCR_FUFC_SHIFT (11U)
+#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK (0x1000U)
+#define MCM_ISCR_FIXC_SHIFT (12U)
+#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK (0x8000U)
+#define MCM_ISCR_FIDC_SHIFT (15U)
+#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK (0x1000000U)
+#define MCM_ISCR_FIOCE_SHIFT (24U)
+#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK (0x2000000U)
+#define MCM_ISCR_FDZCE_SHIFT (25U)
+#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK (0x4000000U)
+#define MCM_ISCR_FOFCE_SHIFT (26U)
+#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK (0x8000000U)
+#define MCM_ISCR_FUFCE_SHIFT (27U)
+#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK (0x10000000U)
+#define MCM_ISCR_FIXCE_SHIFT (28U)
+#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK (0x80000000U)
+#define MCM_ISCR_FIDCE_SHIFT (31U)
+#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+
+/*! @name ETBCC - ETB Counter Control register */
+#define MCM_ETBCC_CNTEN_MASK (0x1U)
+#define MCM_ETBCC_CNTEN_SHIFT (0U)
+#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK (0x6U)
+#define MCM_ETBCC_RSPT_SHIFT (1U)
+#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK (0x8U)
+#define MCM_ETBCC_RLRQ_SHIFT (3U)
+#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK (0x10U)
+#define MCM_ETBCC_ETDIS_SHIFT (4U)
+#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK (0x20U)
+#define MCM_ETBCC_ITDIS_SHIFT (5U)
+#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
+
+/*! @name ETBRL - ETB Reload register */
+#define MCM_ETBRL_RELOAD_MASK (0x7FFU)
+#define MCM_ETBRL_RELOAD_SHIFT (0U)
+#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
+
+/*! @name ETBCNT - ETB Counter Value register */
+#define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
+#define MCM_ETBCNT_COUNTER_SHIFT (0U)
+#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
+
+/*! @name PID - Process ID register */
+#define MCM_PID_PID_MASK (0xFFU)
+#define MCM_PID_PID_SHIFT (0U)
+#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
+
/*!
* @}
@@ -9838,7 +6756,6 @@ typedef struct {
#define MCM_BASE (0xE0080000u)
/** Peripheral MCM base pointer */
#define MCM ((MCM_Type *)MCM_BASE)
-#define MCM_BASE_PTR (MCM)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
@@ -9846,442 +6763,11 @@ typedef struct {
/** Interrupt vectors for the MCM peripheral type */
#define MCM_IRQS { MCM_IRQn }
-/* ----------------------------------------------------------------------------
- -- MCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
- * @{
- */
-
-
-/* MCM - Register instance definitions */
-/* MCM */
-#define MCM_PLASC MCM_PLASC_REG(MCM)
-#define MCM_PLAMC MCM_PLAMC_REG(MCM)
-#define MCM_CR MCM_CR_REG(MCM)
-#define MCM_ISCR MCM_ISCR_REG(MCM)
-#define MCM_ETBCC MCM_ETBCC_REG(MCM)
-#define MCM_ETBRL MCM_ETBRL_REG(MCM)
-#define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
-#define MCM_PID MCM_PID_REG(MCM)
-
-/*!
- * @}
- */ /* end of group MCM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
-/* ----------------------------------------------------------------------------
- -- MPU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
- * @{
- */
-
-/** MPU - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
- uint8_t RESERVED_0[12];
- struct { /* offset: 0x10, array step: 0x8 */
- __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
- __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
- } SP[5];
- uint8_t RESERVED_1[968];
- __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
- uint8_t RESERVED_2[832];
- __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
-} MPU_Type, *MPU_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- MPU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
- * @{
- */
-
-
-/* MPU - Register accessors */
-#define MPU_CESR_REG(base) ((base)->CESR)
-#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
-#define MPU_EAR_COUNT 5
-#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
-#define MPU_EDR_COUNT 5
-#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
-#define MPU_WORD_COUNT 12
-#define MPU_WORD_COUNT2 4
-#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
-#define MPU_RGDAAC_COUNT 12
-
-/*!
- * @}
- */ /* end of group MPU_Register_Accessor_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- MPU Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Masks MPU Register Masks
- * @{
- */
-
-/* CESR Bit Fields */
-#define MPU_CESR_VLD_MASK 0x1u
-#define MPU_CESR_VLD_SHIFT 0
-#define MPU_CESR_VLD_WIDTH 1
-#define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
-#define MPU_CESR_NRGD_MASK 0xF00u
-#define MPU_CESR_NRGD_SHIFT 8
-#define MPU_CESR_NRGD_WIDTH 4
-#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
-#define MPU_CESR_NSP_MASK 0xF000u
-#define MPU_CESR_NSP_SHIFT 12
-#define MPU_CESR_NSP_WIDTH 4
-#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
-#define MPU_CESR_HRL_MASK 0xF0000u
-#define MPU_CESR_HRL_SHIFT 16
-#define MPU_CESR_HRL_WIDTH 4
-#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
-#define MPU_CESR_SPERR_MASK 0xF8000000u
-#define MPU_CESR_SPERR_SHIFT 27
-#define MPU_CESR_SPERR_WIDTH 5
-#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
-/* EAR Bit Fields */
-#define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
-#define MPU_EAR_EADDR_SHIFT 0
-#define MPU_EAR_EADDR_WIDTH 32
-#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
-/* EDR Bit Fields */
-#define MPU_EDR_ERW_MASK 0x1u
-#define MPU_EDR_ERW_SHIFT 0
-#define MPU_EDR_ERW_WIDTH 1
-#define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
-#define MPU_EDR_EATTR_MASK 0xEu
-#define MPU_EDR_EATTR_SHIFT 1
-#define MPU_EDR_EATTR_WIDTH 3
-#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
-#define MPU_EDR_EMN_MASK 0xF0u
-#define MPU_EDR_EMN_SHIFT 4
-#define MPU_EDR_EMN_WIDTH 4
-#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
-#define MPU_EDR_EPID_MASK 0xFF00u
-#define MPU_EDR_EPID_SHIFT 8
-#define MPU_EDR_EPID_WIDTH 8
-#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
-#define MPU_EDR_EACD_MASK 0xFFFF0000u
-#define MPU_EDR_EACD_SHIFT 16
-#define MPU_EDR_EACD_WIDTH 16
-#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
-/* WORD Bit Fields */
-#define MPU_WORD_VLD_MASK 0x1u
-#define MPU_WORD_VLD_SHIFT 0
-#define MPU_WORD_VLD_WIDTH 1
-#define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_VLD_SHIFT))&MPU_WORD_VLD_MASK)
-#define MPU_WORD_M0UM_MASK 0x7u
-#define MPU_WORD_M0UM_SHIFT 0
-#define MPU_WORD_M0UM_WIDTH 3
-#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
-#define MPU_WORD_M0SM_MASK 0x18u
-#define MPU_WORD_M0SM_SHIFT 3
-#define MPU_WORD_M0SM_WIDTH 2
-#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
-#define MPU_WORD_M0PE_MASK 0x20u
-#define MPU_WORD_M0PE_SHIFT 5
-#define MPU_WORD_M0PE_WIDTH 1
-#define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0PE_SHIFT))&MPU_WORD_M0PE_MASK)
-#define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
-#define MPU_WORD_ENDADDR_SHIFT 5
-#define MPU_WORD_ENDADDR_WIDTH 27
-#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
-#define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
-#define MPU_WORD_SRTADDR_SHIFT 5
-#define MPU_WORD_SRTADDR_WIDTH 27
-#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
-#define MPU_WORD_M1UM_MASK 0x1C0u
-#define MPU_WORD_M1UM_SHIFT 6
-#define MPU_WORD_M1UM_WIDTH 3
-#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
-#define MPU_WORD_M1SM_MASK 0x600u
-#define MPU_WORD_M1SM_SHIFT 9
-#define MPU_WORD_M1SM_WIDTH 2
-#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
-#define MPU_WORD_M1PE_MASK 0x800u
-#define MPU_WORD_M1PE_SHIFT 11
-#define MPU_WORD_M1PE_WIDTH 1
-#define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1PE_SHIFT))&MPU_WORD_M1PE_MASK)
-#define MPU_WORD_M2UM_MASK 0x7000u
-#define MPU_WORD_M2UM_SHIFT 12
-#define MPU_WORD_M2UM_WIDTH 3
-#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
-#define MPU_WORD_M2SM_MASK 0x18000u
-#define MPU_WORD_M2SM_SHIFT 15
-#define MPU_WORD_M2SM_WIDTH 2
-#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
-#define MPU_WORD_PIDMASK_MASK 0xFF0000u
-#define MPU_WORD_PIDMASK_SHIFT 16
-#define MPU_WORD_PIDMASK_WIDTH 8
-#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
-#define MPU_WORD_M2PE_MASK 0x20000u
-#define MPU_WORD_M2PE_SHIFT 17
-#define MPU_WORD_M2PE_WIDTH 1
-#define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2PE_SHIFT))&MPU_WORD_M2PE_MASK)
-#define MPU_WORD_M3UM_MASK 0x1C0000u
-#define MPU_WORD_M3UM_SHIFT 18
-#define MPU_WORD_M3UM_WIDTH 3
-#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
-#define MPU_WORD_M3SM_MASK 0x600000u
-#define MPU_WORD_M3SM_SHIFT 21
-#define MPU_WORD_M3SM_WIDTH 2
-#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
-#define MPU_WORD_M3PE_MASK 0x800000u
-#define MPU_WORD_M3PE_SHIFT 23
-#define MPU_WORD_M3PE_WIDTH 1
-#define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3PE_SHIFT))&MPU_WORD_M3PE_MASK)
-#define MPU_WORD_PID_MASK 0xFF000000u
-#define MPU_WORD_PID_SHIFT 24
-#define MPU_WORD_PID_WIDTH 8
-#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
-#define MPU_WORD_M4WE_MASK 0x1000000u
-#define MPU_WORD_M4WE_SHIFT 24
-#define MPU_WORD_M4WE_WIDTH 1
-#define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4WE_SHIFT))&MPU_WORD_M4WE_MASK)
-#define MPU_WORD_M4RE_MASK 0x2000000u
-#define MPU_WORD_M4RE_SHIFT 25
-#define MPU_WORD_M4RE_WIDTH 1
-#define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M4RE_SHIFT))&MPU_WORD_M4RE_MASK)
-#define MPU_WORD_M5WE_MASK 0x4000000u
-#define MPU_WORD_M5WE_SHIFT 26
-#define MPU_WORD_M5WE_WIDTH 1
-#define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5WE_SHIFT))&MPU_WORD_M5WE_MASK)
-#define MPU_WORD_M5RE_MASK 0x8000000u
-#define MPU_WORD_M5RE_SHIFT 27
-#define MPU_WORD_M5RE_WIDTH 1
-#define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M5RE_SHIFT))&MPU_WORD_M5RE_MASK)
-#define MPU_WORD_M6WE_MASK 0x10000000u
-#define MPU_WORD_M6WE_SHIFT 28
-#define MPU_WORD_M6WE_WIDTH 1
-#define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6WE_SHIFT))&MPU_WORD_M6WE_MASK)
-#define MPU_WORD_M6RE_MASK 0x20000000u
-#define MPU_WORD_M6RE_SHIFT 29
-#define MPU_WORD_M6RE_WIDTH 1
-#define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M6RE_SHIFT))&MPU_WORD_M6RE_MASK)
-#define MPU_WORD_M7WE_MASK 0x40000000u
-#define MPU_WORD_M7WE_SHIFT 30
-#define MPU_WORD_M7WE_WIDTH 1
-#define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7WE_SHIFT))&MPU_WORD_M7WE_MASK)
-#define MPU_WORD_M7RE_MASK 0x80000000u
-#define MPU_WORD_M7RE_SHIFT 31
-#define MPU_WORD_M7RE_WIDTH 1
-#define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M7RE_SHIFT))&MPU_WORD_M7RE_MASK)
-/* RGDAAC Bit Fields */
-#define MPU_RGDAAC_M0UM_MASK 0x7u
-#define MPU_RGDAAC_M0UM_SHIFT 0
-#define MPU_RGDAAC_M0UM_WIDTH 3
-#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
-#define MPU_RGDAAC_M0SM_MASK 0x18u
-#define MPU_RGDAAC_M0SM_SHIFT 3
-#define MPU_RGDAAC_M0SM_WIDTH 2
-#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
-#define MPU_RGDAAC_M0PE_MASK 0x20u
-#define MPU_RGDAAC_M0PE_SHIFT 5
-#define MPU_RGDAAC_M0PE_WIDTH 1
-#define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
-#define MPU_RGDAAC_M1UM_MASK 0x1C0u
-#define MPU_RGDAAC_M1UM_SHIFT 6
-#define MPU_RGDAAC_M1UM_WIDTH 3
-#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
-#define MPU_RGDAAC_M1SM_MASK 0x600u
-#define MPU_RGDAAC_M1SM_SHIFT 9
-#define MPU_RGDAAC_M1SM_WIDTH 2
-#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
-#define MPU_RGDAAC_M1PE_MASK 0x800u
-#define MPU_RGDAAC_M1PE_SHIFT 11
-#define MPU_RGDAAC_M1PE_WIDTH 1
-#define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
-#define MPU_RGDAAC_M2UM_MASK 0x7000u
-#define MPU_RGDAAC_M2UM_SHIFT 12
-#define MPU_RGDAAC_M2UM_WIDTH 3
-#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
-#define MPU_RGDAAC_M2SM_MASK 0x18000u
-#define MPU_RGDAAC_M2SM_SHIFT 15
-#define MPU_RGDAAC_M2SM_WIDTH 2
-#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
-#define MPU_RGDAAC_M2PE_MASK 0x20000u
-#define MPU_RGDAAC_M2PE_SHIFT 17
-#define MPU_RGDAAC_M2PE_WIDTH 1
-#define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2PE_SHIFT))&MPU_RGDAAC_M2PE_MASK)
-#define MPU_RGDAAC_M3UM_MASK 0x1C0000u
-#define MPU_RGDAAC_M3UM_SHIFT 18
-#define MPU_RGDAAC_M3UM_WIDTH 3
-#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
-#define MPU_RGDAAC_M3SM_MASK 0x600000u
-#define MPU_RGDAAC_M3SM_SHIFT 21
-#define MPU_RGDAAC_M3SM_WIDTH 2
-#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
-#define MPU_RGDAAC_M3PE_MASK 0x800000u
-#define MPU_RGDAAC_M3PE_SHIFT 23
-#define MPU_RGDAAC_M3PE_WIDTH 1
-#define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3PE_SHIFT))&MPU_RGDAAC_M3PE_MASK)
-#define MPU_RGDAAC_M4WE_MASK 0x1000000u
-#define MPU_RGDAAC_M4WE_SHIFT 24
-#define MPU_RGDAAC_M4WE_WIDTH 1
-#define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
-#define MPU_RGDAAC_M4RE_MASK 0x2000000u
-#define MPU_RGDAAC_M4RE_SHIFT 25
-#define MPU_RGDAAC_M4RE_WIDTH 1
-#define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
-#define MPU_RGDAAC_M5WE_MASK 0x4000000u
-#define MPU_RGDAAC_M5WE_SHIFT 26
-#define MPU_RGDAAC_M5WE_WIDTH 1
-#define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
-#define MPU_RGDAAC_M5RE_MASK 0x8000000u
-#define MPU_RGDAAC_M5RE_SHIFT 27
-#define MPU_RGDAAC_M5RE_WIDTH 1
-#define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
-#define MPU_RGDAAC_M6WE_MASK 0x10000000u
-#define MPU_RGDAAC_M6WE_SHIFT 28
-#define MPU_RGDAAC_M6WE_WIDTH 1
-#define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
-#define MPU_RGDAAC_M6RE_MASK 0x20000000u
-#define MPU_RGDAAC_M6RE_SHIFT 29
-#define MPU_RGDAAC_M6RE_WIDTH 1
-#define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
-#define MPU_RGDAAC_M7WE_MASK 0x40000000u
-#define MPU_RGDAAC_M7WE_SHIFT 30
-#define MPU_RGDAAC_M7WE_WIDTH 1
-#define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
-#define MPU_RGDAAC_M7RE_MASK 0x80000000u
-#define MPU_RGDAAC_M7RE_SHIFT 31
-#define MPU_RGDAAC_M7RE_WIDTH 1
-#define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
-
-/*!
- * @}
- */ /* end of group MPU_Register_Masks */
-
-
-/* MPU - Peripheral instance base addresses */
-/** Peripheral MPU base address */
-#define MPU_BASE (0x4000D000u)
-/** Peripheral MPU base pointer */
-#define MPU ((MPU_Type *)MPU_BASE)
-#define MPU_BASE_PTR (MPU)
-/** Array initializer of MPU peripheral base addresses */
-#define MPU_BASE_ADDRS { MPU_BASE }
-/** Array initializer of MPU peripheral base pointers */
-#define MPU_BASE_PTRS { MPU }
-
-/* ----------------------------------------------------------------------------
- -- MPU - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
- * @{
- */
-
-
-/* MPU - Register instance definitions */
-/* MPU */
-#define MPU_CESR MPU_CESR_REG(MPU)
-#define MPU_EAR0 MPU_EAR_REG(MPU,0)
-#define MPU_EDR0 MPU_EDR_REG(MPU,0)
-#define MPU_EAR1 MPU_EAR_REG(MPU,1)
-#define MPU_EDR1 MPU_EDR_REG(MPU,1)
-#define MPU_EAR2 MPU_EAR_REG(MPU,2)
-#define MPU_EDR2 MPU_EDR_REG(MPU,2)
-#define MPU_EAR3 MPU_EAR_REG(MPU,3)
-#define MPU_EDR3 MPU_EDR_REG(MPU,3)
-#define MPU_EAR4 MPU_EAR_REG(MPU,4)
-#define MPU_EDR4 MPU_EDR_REG(MPU,4)
-#define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
-#define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
-#define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
-#define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
-#define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
-#define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
-#define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
-#define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
-#define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
-#define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
-#define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
-#define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
-#define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
-#define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
-#define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
-#define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
-#define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
-#define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
-#define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
-#define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
-#define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
-#define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
-#define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
-#define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
-#define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
-#define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
-#define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
-#define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
-#define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
-#define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
-#define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
-#define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
-#define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
-#define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
-#define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
-#define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
-#define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
-#define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
-#define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
-#define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
-#define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
-#define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
-#define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
-#define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
-#define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
-#define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
-#define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
-#define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
-#define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
-#define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
-#define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
-#define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
-#define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
-#define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
-#define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
-#define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
-#define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
-#define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
-#define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
-#define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
-
-/* MPU - Register array accessors */
-#define MPU_EAR(index) MPU_EAR_REG(MPU,index)
-#define MPU_EDR(index) MPU_EDR_REG(MPU,index)
-#define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
-#define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
-
-/*!
- * @}
- */ /* end of group MPU_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group MPU_Peripheral_Access_Layer */
-
-
/* ----------------------------------------------------------------------------
-- NV Peripheral Access Layer
---------------------------------------------------------------------------- */
@@ -10309,40 +6795,7 @@ typedef struct {
__I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
__I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
__I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
-} NV_Type, *NV_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register accessors */
-#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
-#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
-#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
-#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
-#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
-#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
-#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
-#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
-#define NV_FPROT3_REG(base) ((base)->FPROT3)
-#define NV_FPROT2_REG(base) ((base)->FPROT2)
-#define NV_FPROT1_REG(base) ((base)->FPROT1)
-#define NV_FPROT0_REG(base) ((base)->FPROT0)
-#define NV_FSEC_REG(base) ((base)->FSEC)
-#define NV_FOPT_REG(base) ((base)->FOPT)
-#define NV_FEPROT_REG(base) ((base)->FEPROT)
-#define NV_FDPROT_REG(base) ((base)->FDPROT)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
+} NV_Type;
/* ----------------------------------------------------------------------------
-- NV Register Masks
@@ -10353,106 +6806,101 @@ typedef struct {
* @{
*/
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY_WIDTH 8
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY_WIDTH 8
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY_WIDTH 8
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY_WIDTH 8
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY_WIDTH 8
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY_WIDTH 8
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY_WIDTH 8
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY_WIDTH 8
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT_WIDTH 8
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT_WIDTH 8
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT_WIDTH 8
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT_WIDTH 8
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC_WIDTH 2
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC_WIDTH 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN_WIDTH 2
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN_WIDTH 2
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT_MASK 0x1u
-#define NV_FOPT_LPBOOT_SHIFT 0
-#define NV_FOPT_LPBOOT_WIDTH 1
-#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
-#define NV_FOPT_EZPORT_DIS_MASK 0x2u
-#define NV_FOPT_EZPORT_DIS_SHIFT 1
-#define NV_FOPT_EZPORT_DIS_WIDTH 1
-#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
-#define NV_FOPT_NMI_DIS_MASK 0x4u
-#define NV_FOPT_NMI_DIS_SHIFT 2
-#define NV_FOPT_NMI_DIS_WIDTH 1
-#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
-/* FEPROT Bit Fields */
-#define NV_FEPROT_EPROT_MASK 0xFFu
-#define NV_FEPROT_EPROT_SHIFT 0
-#define NV_FEPROT_EPROT_WIDTH 8
-#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
-/* FDPROT Bit Fields */
-#define NV_FDPROT_DPROT_MASK 0xFFu
-#define NV_FDPROT_DPROT_SHIFT 0
-#define NV_FDPROT_DPROT_WIDTH 8
-#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT (0U)
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT (0U)
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT (0U)
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT (0U)
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT (0U)
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT (0U)
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT (0U)
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT (0U)
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK (0xFFU)
+#define NV_FPROT3_PROT_SHIFT (0U)
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK (0xFFU)
+#define NV_FPROT2_PROT_SHIFT (0U)
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK (0xFFU)
+#define NV_FPROT1_PROT_SHIFT (0U)
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK (0xFFU)
+#define NV_FPROT0_PROT_SHIFT (0U)
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK (0x3U)
+#define NV_FSEC_SEC_SHIFT (0U)
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK (0xCU)
+#define NV_FSEC_FSLACC_SHIFT (2U)
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK (0x30U)
+#define NV_FSEC_MEEN_SHIFT (4U)
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT (6U)
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT_MASK (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT (0U)
+#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
+#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
+#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_NMI_DIS_MASK (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT (2U)
+#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+
+/*! @name FEPROT - Non-volatile EERAM Protection Register */
+#define NV_FEPROT_EPROT_MASK (0xFFU)
+#define NV_FEPROT_EPROT_SHIFT (0U)
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Non-volatile D-Flash Protection Register */
+#define NV_FDPROT_DPROT_MASK (0xFFU)
+#define NV_FDPROT_DPROT_SHIFT (0U)
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
+
/*!
* @}
@@ -10464,46 +6912,11 @@ typedef struct {
#define FTFE_FlashConfig_BASE (0x400u)
/** Peripheral FTFE_FlashConfig base pointer */
#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
-#define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
/** Array initializer of NV peripheral base addresses */
#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
/** Array initializer of NV peripheral base pointers */
#define NV_BASE_PTRS { FTFE_FlashConfig }
-/* ----------------------------------------------------------------------------
- -- NV - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
- * @{
- */
-
-
-/* NV - Register instance definitions */
-/* FTFE_FlashConfig */
-#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
-#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
-#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
-#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
-#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
-#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
-#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
-#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
-#define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
-#define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
-#define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
-#define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
-#define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
-#define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
-#define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
-#define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
-
-/*!
- * @}
- */ /* end of group NV_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group NV_Peripheral_Access_Layer */
@@ -10521,25 +6934,7 @@ typedef struct {
/** OSC - Register Layout Typedef */
typedef struct {
__IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
-} OSC_Type, *OSC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register accessors */
-#define OSC_CR_REG(base) ((base)->CR)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
+} OSC_Type;
/* ----------------------------------------------------------------------------
-- OSC Register Masks
@@ -10550,31 +6945,26 @@ typedef struct {
* @{
*/
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC16P_WIDTH 1
-#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC8P_WIDTH 1
-#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC4P_WIDTH 1
-#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_SC2P_WIDTH 1
-#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_EREFSTEN_WIDTH 1
-#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-#define OSC_CR_ERCLKEN_WIDTH 1
-#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P_MASK (0x1U)
+#define OSC_CR_SC16P_SHIFT (0U)
+#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
+#define OSC_CR_SC8P_MASK (0x2U)
+#define OSC_CR_SC8P_SHIFT (1U)
+#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
+#define OSC_CR_SC4P_MASK (0x4U)
+#define OSC_CR_SC4P_SHIFT (2U)
+#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
+#define OSC_CR_SC2P_MASK (0x8U)
+#define OSC_CR_SC2P_SHIFT (3U)
+#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
+#define OSC_CR_EREFSTEN_MASK (0x20U)
+#define OSC_CR_EREFSTEN_SHIFT (5U)
+#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
+#define OSC_CR_ERCLKEN_MASK (0x80U)
+#define OSC_CR_ERCLKEN_SHIFT (7U)
+#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
+
/*!
* @}
@@ -10586,31 +6976,11 @@ typedef struct {
#define OSC_BASE (0x40065000u)
/** Peripheral OSC base pointer */
#define OSC ((OSC_Type *)OSC_BASE)
-#define OSC_BASE_PTR (OSC)
/** Array initializer of OSC peripheral base addresses */
#define OSC_BASE_ADDRS { OSC_BASE }
/** Array initializer of OSC peripheral base pointers */
#define OSC_BASE_PTRS { OSC }
-/* ----------------------------------------------------------------------------
- -- OSC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
- * @{
- */
-
-
-/* OSC - Register instance definitions */
-/* OSC */
-#define OSC_CR OSC_CR_REG(OSC)
-
-/*!
- * @}
- */ /* end of group OSC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group OSC_Peripheral_Access_Layer */
@@ -10645,42 +7015,7 @@ typedef struct {
uint8_t RESERVED_1[48];
__IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
__IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
-} PDB_Type, *PDB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register accessors */
-#define PDB_SC_REG(base) ((base)->SC)
-#define PDB_MOD_REG(base) ((base)->MOD)
-#define PDB_CNT_REG(base) ((base)->CNT)
-#define PDB_IDLY_REG(base) ((base)->IDLY)
-#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
-#define PDB_C1_COUNT 2
-#define PDB_S_REG(base,index) ((base)->CH[index].S)
-#define PDB_S_COUNT 2
-#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
-#define PDB_DLY_COUNT 2
-#define PDB_DLY_COUNT2 2
-#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
-#define PDB_INTC_COUNT 2
-#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
-#define PDB_INT_COUNT 2
-#define PDB_POEN_REG(base) ((base)->POEN)
-#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
-#define PDB_PODLY_COUNT 3
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
+} PDB_Type;
/* ----------------------------------------------------------------------------
-- PDB Register Masks
@@ -10691,125 +7026,130 @@ typedef struct {
* @{
*/
-/* SC Bit Fields */
-#define PDB_SC_LDOK_MASK 0x1u
-#define PDB_SC_LDOK_SHIFT 0
-#define PDB_SC_LDOK_WIDTH 1
-#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
-#define PDB_SC_CONT_MASK 0x2u
-#define PDB_SC_CONT_SHIFT 1
-#define PDB_SC_CONT_WIDTH 1
-#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
-#define PDB_SC_MULT_MASK 0xCu
-#define PDB_SC_MULT_SHIFT 2
-#define PDB_SC_MULT_WIDTH 2
-#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
-#define PDB_SC_PDBIE_MASK 0x20u
-#define PDB_SC_PDBIE_SHIFT 5
-#define PDB_SC_PDBIE_WIDTH 1
-#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
-#define PDB_SC_PDBIF_MASK 0x40u
-#define PDB_SC_PDBIF_SHIFT 6
-#define PDB_SC_PDBIF_WIDTH 1
-#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
-#define PDB_SC_PDBEN_MASK 0x80u
-#define PDB_SC_PDBEN_SHIFT 7
-#define PDB_SC_PDBEN_WIDTH 1
-#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
-#define PDB_SC_TRGSEL_MASK 0xF00u
-#define PDB_SC_TRGSEL_SHIFT 8
-#define PDB_SC_TRGSEL_WIDTH 4
-#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
-#define PDB_SC_PRESCALER_MASK 0x7000u
-#define PDB_SC_PRESCALER_SHIFT 12
-#define PDB_SC_PRESCALER_WIDTH 3
-#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
-#define PDB_SC_DMAEN_MASK 0x8000u
-#define PDB_SC_DMAEN_SHIFT 15
-#define PDB_SC_DMAEN_WIDTH 1
-#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
-#define PDB_SC_SWTRIG_MASK 0x10000u
-#define PDB_SC_SWTRIG_SHIFT 16
-#define PDB_SC_SWTRIG_WIDTH 1
-#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
-#define PDB_SC_PDBEIE_MASK 0x20000u
-#define PDB_SC_PDBEIE_SHIFT 17
-#define PDB_SC_PDBEIE_WIDTH 1
-#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
-#define PDB_SC_LDMOD_MASK 0xC0000u
-#define PDB_SC_LDMOD_SHIFT 18
-#define PDB_SC_LDMOD_WIDTH 2
-#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
-/* MOD Bit Fields */
-#define PDB_MOD_MOD_MASK 0xFFFFu
-#define PDB_MOD_MOD_SHIFT 0
-#define PDB_MOD_MOD_WIDTH 16
-#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
-/* CNT Bit Fields */
-#define PDB_CNT_CNT_MASK 0xFFFFu
-#define PDB_CNT_CNT_SHIFT 0
-#define PDB_CNT_CNT_WIDTH 16
-#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
-/* IDLY Bit Fields */
-#define PDB_IDLY_IDLY_MASK 0xFFFFu
-#define PDB_IDLY_IDLY_SHIFT 0
-#define PDB_IDLY_IDLY_WIDTH 16
-#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
-/* C1 Bit Fields */
-#define PDB_C1_EN_MASK 0xFFu
-#define PDB_C1_EN_SHIFT 0
-#define PDB_C1_EN_WIDTH 8
-#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
-#define PDB_C1_TOS_MASK 0xFF00u
-#define PDB_C1_TOS_SHIFT 8
-#define PDB_C1_TOS_WIDTH 8
-#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
-#define PDB_C1_BB_MASK 0xFF0000u
-#define PDB_C1_BB_SHIFT 16
-#define PDB_C1_BB_WIDTH 8
-#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
-/* S Bit Fields */
-#define PDB_S_ERR_MASK 0xFFu
-#define PDB_S_ERR_SHIFT 0
-#define PDB_S_ERR_WIDTH 8
-#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
-#define PDB_S_CF_MASK 0xFF0000u
-#define PDB_S_CF_SHIFT 16
-#define PDB_S_CF_WIDTH 8
-#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
-/* DLY Bit Fields */
-#define PDB_DLY_DLY_MASK 0xFFFFu
-#define PDB_DLY_DLY_SHIFT 0
-#define PDB_DLY_DLY_WIDTH 16
-#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
-/* INTC Bit Fields */
-#define PDB_INTC_TOE_MASK 0x1u
-#define PDB_INTC_TOE_SHIFT 0
-#define PDB_INTC_TOE_WIDTH 1
-#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
-#define PDB_INTC_EXT_MASK 0x2u
-#define PDB_INTC_EXT_SHIFT 1
-#define PDB_INTC_EXT_WIDTH 1
-#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
-/* INT Bit Fields */
-#define PDB_INT_INT_MASK 0xFFFFu
-#define PDB_INT_INT_SHIFT 0
-#define PDB_INT_INT_WIDTH 16
-#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
-/* POEN Bit Fields */
-#define PDB_POEN_POEN_MASK 0xFFu
-#define PDB_POEN_POEN_SHIFT 0
-#define PDB_POEN_POEN_WIDTH 8
-#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
-/* PODLY Bit Fields */
-#define PDB_PODLY_DLY2_MASK 0xFFFFu
-#define PDB_PODLY_DLY2_SHIFT 0
-#define PDB_PODLY_DLY2_WIDTH 16
-#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
-#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
-#define PDB_PODLY_DLY1_SHIFT 16
-#define PDB_PODLY_DLY1_WIDTH 16
-#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+/*! @name SC - Status and Control register */
+#define PDB_SC_LDOK_MASK (0x1U)
+#define PDB_SC_LDOK_SHIFT (0U)
+#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK (0x2U)
+#define PDB_SC_CONT_SHIFT (1U)
+#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK (0xCU)
+#define PDB_SC_MULT_SHIFT (2U)
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK (0x20U)
+#define PDB_SC_PDBIE_SHIFT (5U)
+#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK (0x40U)
+#define PDB_SC_PDBIF_SHIFT (6U)
+#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK (0x80U)
+#define PDB_SC_PDBEN_SHIFT (7U)
+#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT (8U)
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT (12U)
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK (0x8000U)
+#define PDB_SC_DMAEN_SHIFT (15U)
+#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK (0x10000U)
+#define PDB_SC_SWTRIG_SHIFT (16U)
+#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK (0x20000U)
+#define PDB_SC_PDBEIE_SHIFT (17U)
+#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT (18U)
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+
+/*! @name MOD - Modulus register */
+#define PDB_MOD_MOD_MASK (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT (0U)
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+
+/*! @name CNT - Counter register */
+#define PDB_CNT_CNT_MASK (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT (0U)
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+
+/*! @name IDLY - Interrupt Delay register */
+#define PDB_IDLY_IDLY_MASK (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT (0U)
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+
+/*! @name C1 - Channel n Control register 1 */
+#define PDB_C1_EN_MASK (0xFFU)
+#define PDB_C1_EN_SHIFT (0U)
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK (0xFF00U)
+#define PDB_C1_TOS_SHIFT (8U)
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK (0xFF0000U)
+#define PDB_C1_BB_SHIFT (16U)
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT (2U)
+
+/*! @name S - Channel n Status register */
+#define PDB_S_ERR_MASK (0xFFU)
+#define PDB_S_ERR_SHIFT (0U)
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK (0xFF0000U)
+#define PDB_S_CF_SHIFT (16U)
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+
+/* The count of PDB_S */
+#define PDB_S_COUNT (2U)
+
+/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
+#define PDB_DLY_DLY_MASK (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT (0U)
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT (2U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2 (2U)
+
+/*! @name INTC - DAC Interval Trigger n Control register */
+#define PDB_INTC_TOE_MASK (0x1U)
+#define PDB_INTC_TOE_SHIFT (0U)
+#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK (0x2U)
+#define PDB_INTC_EXT_SHIFT (1U)
+#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+
+/* The count of PDB_INTC */
+#define PDB_INTC_COUNT (2U)
+
+/*! @name INT - DAC Interval n register */
+#define PDB_INT_INT_MASK (0xFFFFU)
+#define PDB_INT_INT_SHIFT (0U)
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+
+/* The count of PDB_INT */
+#define PDB_INT_COUNT (2U)
+
+/*! @name POEN - Pulse-Out n Enable register */
+#define PDB_POEN_POEN_MASK (0xFFU)
+#define PDB_POEN_POEN_SHIFT (0U)
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+
+/*! @name PODLY - Pulse-Out n Delay register */
+#define PDB_PODLY_DLY2_MASK (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT (0U)
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT (16U)
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT (3U)
+
/*!
* @}
@@ -10821,7 +7161,6 @@ typedef struct {
#define PDB0_BASE (0x40036000u)
/** Peripheral PDB0 base pointer */
#define PDB0 ((PDB_Type *)PDB0_BASE)
-#define PDB0_BASE_PTR (PDB0)
/** Array initializer of PDB peripheral base addresses */
#define PDB_BASE_ADDRS { PDB0_BASE }
/** Array initializer of PDB peripheral base pointers */
@@ -10829,52 +7168,6 @@ typedef struct {
/** Interrupt vectors for the PDB peripheral type */
#define PDB_IRQS { PDB0_IRQn }
-/* ----------------------------------------------------------------------------
- -- PDB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
- * @{
- */
-
-
-/* PDB - Register instance definitions */
-/* PDB0 */
-#define PDB0_SC PDB_SC_REG(PDB0)
-#define PDB0_MOD PDB_MOD_REG(PDB0)
-#define PDB0_CNT PDB_CNT_REG(PDB0)
-#define PDB0_IDLY PDB_IDLY_REG(PDB0)
-#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
-#define PDB0_CH0S PDB_S_REG(PDB0,0)
-#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
-#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
-#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
-#define PDB0_CH1S PDB_S_REG(PDB0,1)
-#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
-#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
-#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
-#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
-#define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
-#define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
-#define PDB0_POEN PDB_POEN_REG(PDB0)
-#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
-#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
-#define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
-
-/* PDB - Register array accessors */
-#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
-#define PDB0_S(index) PDB_S_REG(PDB0,index)
-#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
-#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
-#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
-#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
-
-/*!
- * @}
- */ /* end of group PDB_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PDB_Peripheral_Access_Layer */
@@ -10899,80 +7192,63 @@ typedef struct {
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[4];
-} PIT_Type, *PIT_MemMapPtr;
+} PIT_Type;
/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
+ -- PIT Register Masks
---------------------------------------------------------------------------- */
/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK (0x1U)
+#define PIT_MCR_FRZ_SHIFT (0U)
+#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK (0x2U)
+#define PIT_MCR_MDIS_SHIFT (1U)
+#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
-/* PIT - Register accessors */
-#define PIT_MCR_REG(base) ((base)->MCR)
-#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
-#define PIT_LDVAL_COUNT 4
-#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
-#define PIT_CVAL_COUNT 4
-#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
-#define PIT_TCTRL_COUNT 4
-#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
-#define PIT_TFLG_COUNT 4
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT (0U)
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT (4U)
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT (0U)
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT (4U)
-/*!
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK (0x1U)
+#define PIT_TCTRL_TEN_SHIFT (0U)
+#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK (0x2U)
+#define PIT_TCTRL_TIE_SHIFT (1U)
+#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK (0x4U)
+#define PIT_TCTRL_CHN_SHIFT (2U)
+#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK (0x1U)
+#define PIT_TFLG_TIF_SHIFT (0U)
+#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT (4U)
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_FRZ_WIDTH 1
-#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-#define PIT_MCR_MDIS_WIDTH 1
-#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV_WIDTH 32
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL_WIDTH 32
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TEN_WIDTH 1
-#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-#define PIT_TCTRL_TIE_WIDTH 1
-#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
-#define PIT_TCTRL_CHN_MASK 0x4u
-#define PIT_TCTRL_CHN_SHIFT 2
-#define PIT_TCTRL_CHN_WIDTH 1
-#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-#define PIT_TFLG_TIF_WIDTH 1
-#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
/*!
* @}
@@ -10984,54 +7260,12 @@ typedef struct {
#define PIT_BASE (0x40037000u)
/** Peripheral PIT base pointer */
#define PIT ((PIT_Type *)PIT_BASE)
-#define PIT_BASE_PTR (PIT)
/** Array initializer of PIT peripheral base addresses */
#define PIT_BASE_ADDRS { PIT_BASE }
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASE_PTRS { PIT }
/** Interrupt vectors for the PIT peripheral type */
-#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- PIT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
- * @{
- */
-
-
-/* PIT - Register instance definitions */
-/* PIT */
-#define PIT_MCR PIT_MCR_REG(PIT)
-#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
-#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
-#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
-#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
-#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
-#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
-#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
-#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
-#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
-#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
-#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
-#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
-#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
-#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
-#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
-#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
-
-/* PIT - Register array accessors */
-#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
-#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
-#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
-#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
-
-/*!
- * @}
- */ /* end of group PIT_Register_Accessor_Macros */
-
+#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
/*!
* @}
@@ -11052,27 +7286,7 @@ typedef struct {
__IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
__IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
__IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type, *PMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register accessors */
-#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
-#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
-#define PMC_REGSC_REG(base) ((base)->REGSC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
+} PMC_Type;
/* ----------------------------------------------------------------------------
-- PMC Register Masks
@@ -11083,61 +7297,51 @@ typedef struct {
* @{
*/
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV_WIDTH 2
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDRE_WIDTH 1
-#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDIE_WIDTH 1
-#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDACK_WIDTH 1
-#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-#define PMC_LVDSC1_LVDF_WIDTH 1
-#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV_WIDTH 2
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWIE_WIDTH 1
-#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWACK_WIDTH 1
-#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-#define PMC_LVDSC2_LVWF_WIDTH 1
-#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_BGBE_WIDTH 1
-#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_REGONS_WIDTH 1
-#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-#define PMC_REGSC_ACKISO_WIDTH 1
-#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
-#define PMC_REGSC_BGEN_MASK 0x10u
-#define PMC_REGSC_BGEN_SHIFT 4
-#define PMC_REGSC_BGEN_WIDTH 1
-#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT (0U)
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT (4U)
+#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT (5U)
+#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT (6U)
+#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT (7U)
+#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT (0U)
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT (5U)
+#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT (6U)
+#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT (7U)
+#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK (0x1U)
+#define PMC_REGSC_BGBE_SHIFT (0U)
+#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK (0x4U)
+#define PMC_REGSC_REGONS_SHIFT (2U)
+#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT (3U)
+#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK (0x10U)
+#define PMC_REGSC_BGEN_SHIFT (4U)
+#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+
/*!
* @}
@@ -11149,7 +7353,6 @@ typedef struct {
#define PMC_BASE (0x4007D000u)
/** Peripheral PMC base pointer */
#define PMC ((PMC_Type *)PMC_BASE)
-#define PMC_BASE_PTR (PMC)
/** Array initializer of PMC peripheral base addresses */
#define PMC_BASE_ADDRS { PMC_BASE }
/** Array initializer of PMC peripheral base pointers */
@@ -11157,27 +7360,6 @@ typedef struct {
/** Interrupt vectors for the PMC peripheral type */
#define PMC_IRQS { LVD_LVW_IRQn }
-/* ----------------------------------------------------------------------------
- -- PMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
- * @{
- */
-
-
-/* PMC - Register instance definitions */
-/* PMC */
-#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
-#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
-#define PMC_REGSC PMC_REGSC_REG(PMC)
-
-/*!
- * @}
- */ /* end of group PMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PMC_Peripheral_Access_Layer */
@@ -11203,32 +7385,7 @@ typedef struct {
__IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
__IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
__IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
-} PORT_Type, *PORT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register accessors */
-#define PORT_PCR_REG(base,index) ((base)->PCR[index])
-#define PORT_PCR_COUNT 32
-#define PORT_GPCLR_REG(base) ((base)->GPCLR)
-#define PORT_GPCHR_REG(base) ((base)->GPCHR)
-#define PORT_ISFR_REG(base) ((base)->ISFR)
-#define PORT_DFER_REG(base) ((base)->DFER)
-#define PORT_DFCR_REG(base) ((base)->DFCR)
-#define PORT_DFWR_REG(base) ((base)->DFWR)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
+} PORT_Type;
/* ----------------------------------------------------------------------------
-- PORT Register Masks
@@ -11239,85 +7396,77 @@ typedef struct {
* @{
*/
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PS_WIDTH 1
-#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_PE_WIDTH 1
-#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_SRE_WIDTH 1
-#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_PFE_WIDTH 1
-#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
-#define PORT_PCR_ODE_MASK 0x20u
-#define PORT_PCR_ODE_SHIFT 5
-#define PORT_PCR_ODE_WIDTH 1
-#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_DSE_WIDTH 1
-#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX_WIDTH 3
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_LK_MASK 0x8000u
-#define PORT_PCR_LK_SHIFT 15
-#define PORT_PCR_LK_WIDTH 1
-#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC_WIDTH 4
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-#define PORT_PCR_ISF_WIDTH 1
-#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD_WIDTH 16
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE_WIDTH 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD_WIDTH 16
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE_WIDTH 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF_WIDTH 32
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-/* DFER Bit Fields */
-#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
-#define PORT_DFER_DFE_SHIFT 0
-#define PORT_DFER_DFE_WIDTH 32
-#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
-/* DFCR Bit Fields */
-#define PORT_DFCR_CS_MASK 0x1u
-#define PORT_DFCR_CS_SHIFT 0
-#define PORT_DFCR_CS_WIDTH 1
-#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
-/* DFWR Bit Fields */
-#define PORT_DFWR_FILT_MASK 0x1Fu
-#define PORT_DFWR_FILT_SHIFT 0
-#define PORT_DFWR_FILT_WIDTH 5
-#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+/*! @name PCR - Pin Control Register n */
+#define PORT_PCR_PS_MASK (0x1U)
+#define PORT_PCR_PS_SHIFT (0U)
+#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
+#define PORT_PCR_PE_MASK (0x2U)
+#define PORT_PCR_PE_SHIFT (1U)
+#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
+#define PORT_PCR_SRE_MASK (0x4U)
+#define PORT_PCR_SRE_SHIFT (2U)
+#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
+#define PORT_PCR_PFE_MASK (0x10U)
+#define PORT_PCR_PFE_SHIFT (4U)
+#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
+#define PORT_PCR_ODE_MASK (0x20U)
+#define PORT_PCR_ODE_SHIFT (5U)
+#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
+#define PORT_PCR_DSE_MASK (0x40U)
+#define PORT_PCR_DSE_SHIFT (6U)
+#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
+#define PORT_PCR_MUX_MASK (0x700U)
+#define PORT_PCR_MUX_SHIFT (8U)
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK (0x8000U)
+#define PORT_PCR_LK_SHIFT (15U)
+#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
+#define PORT_PCR_IRQC_MASK (0xF0000U)
+#define PORT_PCR_IRQC_SHIFT (16U)
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK (0x1000000U)
+#define PORT_PCR_ISF_SHIFT (24U)
+#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT (0U)
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT (16U)
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT (0U)
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT (16U)
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT (0U)
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+/*! @name DFER - Digital Filter Enable Register */
+#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT (0U)
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+
+/*! @name DFCR - Digital Filter Clock Register */
+#define PORT_DFCR_CS_MASK (0x1U)
+#define PORT_DFCR_CS_SHIFT (0U)
+#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+
+/*! @name DFWR - Digital Filter Width Register */
+#define PORT_DFWR_FILT_MASK (0x1FU)
+#define PORT_DFWR_FILT_SHIFT (0U)
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+
/*!
* @}
@@ -11329,27 +7478,22 @@ typedef struct {
#define PORTA_BASE (0x40049000u)
/** Peripheral PORTA base pointer */
#define PORTA ((PORT_Type *)PORTA_BASE)
-#define PORTA_BASE_PTR (PORTA)
/** Peripheral PORTB base address */
#define PORTB_BASE (0x4004A000u)
/** Peripheral PORTB base pointer */
#define PORTB ((PORT_Type *)PORTB_BASE)
-#define PORTB_BASE_PTR (PORTB)
/** Peripheral PORTC base address */
#define PORTC_BASE (0x4004B000u)
/** Peripheral PORTC base pointer */
#define PORTC ((PORT_Type *)PORTC_BASE)
-#define PORTC_BASE_PTR (PORTC)
/** Peripheral PORTD base address */
#define PORTD_BASE (0x4004C000u)
/** Peripheral PORTD base pointer */
#define PORTD ((PORT_Type *)PORTD_BASE)
-#define PORTD_BASE_PTR (PORTD)
/** Peripheral PORTE base address */
#define PORTE_BASE (0x4004D000u)
/** Peripheral PORTE base pointer */
#define PORTE ((PORT_Type *)PORTE_BASE)
-#define PORTE_BASE_PTR (PORTE)
/** Array initializer of PORT peripheral base addresses */
#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
/** Array initializer of PORT peripheral base pointers */
@@ -11357,213 +7501,6 @@ typedef struct {
/** Interrupt vectors for the PORT peripheral type */
#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
-/* ----------------------------------------------------------------------------
- -- PORT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
- * @{
- */
-
-
-/* PORT - Register instance definitions */
-/* PORTA */
-#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
-#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
-#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
-#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
-#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
-#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
-#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
-#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
-#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
-#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
-#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
-#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
-#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
-#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
-#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
-#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
-#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
-#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
-#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
-#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
-#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
-#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
-#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
-#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
-#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
-#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
-#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
-#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
-#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
-#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
-#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
-#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
-#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
-#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
-#define PORTA_ISFR PORT_ISFR_REG(PORTA)
-/* PORTB */
-#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
-#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
-#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
-#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
-#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
-#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
-#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
-#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
-#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
-#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
-#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
-#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
-#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
-#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
-#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
-#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
-#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
-#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
-#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
-#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
-#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
-#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
-#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
-#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
-#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
-#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
-#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
-#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
-#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
-#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
-#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
-#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
-#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
-#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
-#define PORTB_ISFR PORT_ISFR_REG(PORTB)
-/* PORTC */
-#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
-#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
-#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
-#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
-#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
-#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
-#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
-#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
-#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
-#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
-#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
-#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
-#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
-#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
-#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
-#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
-#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
-#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
-#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
-#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
-#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
-#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
-#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
-#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
-#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
-#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
-#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
-#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
-#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
-#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
-#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
-#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
-#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
-#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
-#define PORTC_ISFR PORT_ISFR_REG(PORTC)
-/* PORTD */
-#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
-#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
-#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
-#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
-#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
-#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
-#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
-#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
-#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
-#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
-#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
-#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
-#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
-#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
-#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
-#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
-#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
-#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
-#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
-#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
-#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
-#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
-#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
-#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
-#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
-#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
-#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
-#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
-#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
-#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
-#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
-#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
-#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
-#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
-#define PORTD_ISFR PORT_ISFR_REG(PORTD)
-#define PORTD_DFER PORT_DFER_REG(PORTD)
-#define PORTD_DFCR PORT_DFCR_REG(PORTD)
-#define PORTD_DFWR PORT_DFWR_REG(PORTD)
-/* PORTE */
-#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
-#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
-#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
-#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
-#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
-#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
-#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
-#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
-#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
-#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
-#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
-#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
-#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
-#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
-#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
-#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
-#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
-#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
-#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
-#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
-#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
-#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
-#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
-#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
-#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
-#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
-#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
-#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
-#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
-#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
-#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
-#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
-#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
-#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
-#define PORTE_ISFR PORT_ISFR_REG(PORTE)
-
-/* PORT - Register array accessors */
-#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
-#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
-#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
-#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
-#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
-
-/*!
- * @}
- */ /* end of group PORT_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group PORT_Peripheral_Access_Layer */
@@ -11587,29 +7524,7 @@ typedef struct {
__IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
uint8_t RESERVED_1[1];
__I uint8_t MR; /**< Mode Register, offset: 0x7 */
-} RCM_Type, *RCM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register accessors */
-#define RCM_SRS0_REG(base) ((base)->SRS0)
-#define RCM_SRS1_REG(base) ((base)->SRS1)
-#define RCM_RPFC_REG(base) ((base)->RPFC)
-#define RCM_RPFW_REG(base) ((base)->RPFW)
-#define RCM_MR_REG(base) ((base)->MR)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
+} RCM_Type;
/* ----------------------------------------------------------------------------
-- RCM Register Masks
@@ -11620,79 +7535,67 @@ typedef struct {
* @{
*/
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_WAKEUP_WIDTH 1
-#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LVD_WIDTH 1
-#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOC_WIDTH 1
-#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
-#define RCM_SRS0_LOL_MASK 0x8u
-#define RCM_SRS0_LOL_SHIFT 3
-#define RCM_SRS0_LOL_WIDTH 1
-#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_WDOG_WIDTH 1
-#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_PIN_WIDTH 1
-#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-#define RCM_SRS0_POR_WIDTH 1
-#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
-/* SRS1 Bit Fields */
-#define RCM_SRS1_JTAG_MASK 0x1u
-#define RCM_SRS1_JTAG_SHIFT 0
-#define RCM_SRS1_JTAG_WIDTH 1
-#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_LOCKUP_WIDTH 1
-#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_SW_WIDTH 1
-#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_MDM_AP_WIDTH 1
-#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
-#define RCM_SRS1_EZPT_MASK 0x10u
-#define RCM_SRS1_EZPT_SHIFT 4
-#define RCM_SRS1_EZPT_WIDTH 1
-#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_EZPT_SHIFT))&RCM_SRS1_EZPT_MASK)
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-#define RCM_SRS1_SACKERR_WIDTH 1
-#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW_WIDTH 2
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-#define RCM_RPFC_RSTFLTSS_WIDTH 1
-#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL_WIDTH 5
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-/* MR Bit Fields */
-#define RCM_MR_EZP_MS_MASK 0x2u
-#define RCM_MR_EZP_MS_SHIFT 1
-#define RCM_MR_EZP_MS_WIDTH 1
-#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_EZP_MS_SHIFT))&RCM_MR_EZP_MS_MASK)
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT (0U)
+#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK (0x2U)
+#define RCM_SRS0_LVD_SHIFT (1U)
+#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK (0x4U)
+#define RCM_SRS0_LOC_SHIFT (2U)
+#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK (0x8U)
+#define RCM_SRS0_LOL_SHIFT (3U)
+#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK (0x20U)
+#define RCM_SRS0_WDOG_SHIFT (5U)
+#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK (0x40U)
+#define RCM_SRS0_PIN_SHIFT (6U)
+#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK (0x80U)
+#define RCM_SRS0_POR_SHIFT (7U)
+#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_JTAG_MASK (0x1U)
+#define RCM_SRS1_JTAG_SHIFT (0U)
+#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT (1U)
+#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK (0x4U)
+#define RCM_SRS1_SW_SHIFT (2U)
+#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT (3U)
+#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK (0x10U)
+#define RCM_SRS1_EZPT_SHIFT (4U)
+#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT (5U)
+#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
+#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_EZP_MS_MASK (0x2U)
+#define RCM_MR_EZP_MS_SHIFT (1U)
+#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+
/*!
* @}
@@ -11704,35 +7607,11 @@ typedef struct {
#define RCM_BASE (0x4007F000u)
/** Peripheral RCM base pointer */
#define RCM ((RCM_Type *)RCM_BASE)
-#define RCM_BASE_PTR (RCM)
/** Array initializer of RCM peripheral base addresses */
#define RCM_BASE_ADDRS { RCM_BASE }
/** Array initializer of RCM peripheral base pointers */
#define RCM_BASE_PTRS { RCM }
-/* ----------------------------------------------------------------------------
- -- RCM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
- * @{
- */
-
-
-/* RCM - Register instance definitions */
-/* RCM */
-#define RCM_SRS0 RCM_SRS0_REG(RCM)
-#define RCM_SRS1 RCM_SRS1_REG(RCM)
-#define RCM_RPFC RCM_RPFC_REG(RCM)
-#define RCM_RPFW RCM_RPFW_REG(RCM)
-#define RCM_MR RCM_MR_REG(RCM)
-
-/*!
- * @}
- */ /* end of group RCM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RCM_Peripheral_Access_Layer */
@@ -11750,26 +7629,7 @@ typedef struct {
/** RFSYS - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type, *RFSYS_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register accessors */
-#define RFSYS_REG_REG(base,index) ((base)->REG[index])
-#define RFSYS_REG_COUNT 8
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
+} RFSYS_Type;
/* ----------------------------------------------------------------------------
-- RFSYS Register Masks
@@ -11780,23 +7640,23 @@ typedef struct {
* @{
*/
-/* REG Bit Fields */
-#define RFSYS_REG_LL_MASK 0xFFu
-#define RFSYS_REG_LL_SHIFT 0
-#define RFSYS_REG_LL_WIDTH 8
-#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
-#define RFSYS_REG_LH_MASK 0xFF00u
-#define RFSYS_REG_LH_SHIFT 8
-#define RFSYS_REG_LH_WIDTH 8
-#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
-#define RFSYS_REG_HL_MASK 0xFF0000u
-#define RFSYS_REG_HL_SHIFT 16
-#define RFSYS_REG_HL_WIDTH 8
-#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
-#define RFSYS_REG_HH_MASK 0xFF000000u
-#define RFSYS_REG_HH_SHIFT 24
-#define RFSYS_REG_HH_WIDTH 8
-#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK (0xFFU)
+#define RFSYS_REG_LL_SHIFT (0U)
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK (0xFF00U)
+#define RFSYS_REG_LH_SHIFT (8U)
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT (16U)
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT (24U)
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT (8U)
+
/*!
* @}
@@ -11808,41 +7668,11 @@ typedef struct {
#define RFSYS_BASE (0x40041000u)
/** Peripheral RFSYS base pointer */
#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
-#define RFSYS_BASE_PTR (RFSYS)
/** Array initializer of RFSYS peripheral base addresses */
#define RFSYS_BASE_ADDRS { RFSYS_BASE }
/** Array initializer of RFSYS peripheral base pointers */
#define RFSYS_BASE_PTRS { RFSYS }
-/* ----------------------------------------------------------------------------
- -- RFSYS - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
- * @{
- */
-
-
-/* RFSYS - Register instance definitions */
-/* RFSYS */
-#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
-#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
-#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
-#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
-#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
-#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
-#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
-#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
-
-/* RFSYS - Register array accessors */
-#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
-
-/*!
- * @}
- */ /* end of group RFSYS_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RFSYS_Peripheral_Access_Layer */
@@ -11860,26 +7690,7 @@ typedef struct {
/** RFVBAT - Register Layout Typedef */
typedef struct {
__IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type, *RFVBAT_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register accessors */
-#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
-#define RFVBAT_REG_COUNT 8
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
+} RFVBAT_Type;
/* ----------------------------------------------------------------------------
-- RFVBAT Register Masks
@@ -11890,23 +7701,23 @@ typedef struct {
* @{
*/
-/* REG Bit Fields */
-#define RFVBAT_REG_LL_MASK 0xFFu
-#define RFVBAT_REG_LL_SHIFT 0
-#define RFVBAT_REG_LL_WIDTH 8
-#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
-#define RFVBAT_REG_LH_MASK 0xFF00u
-#define RFVBAT_REG_LH_SHIFT 8
-#define RFVBAT_REG_LH_WIDTH 8
-#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
-#define RFVBAT_REG_HL_MASK 0xFF0000u
-#define RFVBAT_REG_HL_SHIFT 16
-#define RFVBAT_REG_HL_WIDTH 8
-#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
-#define RFVBAT_REG_HH_MASK 0xFF000000u
-#define RFVBAT_REG_HH_SHIFT 24
-#define RFVBAT_REG_HH_WIDTH 8
-#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK (0xFFU)
+#define RFVBAT_REG_LL_SHIFT (0U)
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT (8U)
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT (16U)
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT (24U)
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT (8U)
+
/*!
* @}
@@ -11918,41 +7729,11 @@ typedef struct {
#define RFVBAT_BASE (0x4003E000u)
/** Peripheral RFVBAT base pointer */
#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
-#define RFVBAT_BASE_PTR (RFVBAT)
/** Array initializer of RFVBAT peripheral base addresses */
#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
/** Array initializer of RFVBAT peripheral base pointers */
#define RFVBAT_BASE_PTRS { RFVBAT }
-/* ----------------------------------------------------------------------------
- -- RFVBAT - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
- * @{
- */
-
-
-/* RFVBAT - Register instance definitions */
-/* RFVBAT */
-#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
-#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
-#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
-#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
-#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
-#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
-#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
-#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
-
-/* RFVBAT - Register array accessors */
-#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
-
-/*!
- * @}
- */ /* end of group RFVBAT_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RFVBAT_Peripheral_Access_Layer */
@@ -11984,38 +7765,7 @@ typedef struct {
uint8_t RESERVED_0[2000];
__IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
__IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type, *RTC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register accessors */
-#define RTC_TSR_REG(base) ((base)->TSR)
-#define RTC_TPR_REG(base) ((base)->TPR)
-#define RTC_TAR_REG(base) ((base)->TAR)
-#define RTC_TCR_REG(base) ((base)->TCR)
-#define RTC_CR_REG(base) ((base)->CR)
-#define RTC_SR_REG(base) ((base)->SR)
-#define RTC_LR_REG(base) ((base)->LR)
-#define RTC_IER_REG(base) ((base)->IER)
-#define RTC_TTSR_REG(base) ((base)->TTSR)
-#define RTC_MER_REG(base) ((base)->MER)
-#define RTC_MCLR_REG(base) ((base)->MCLR)
-#define RTC_MCHR_REG(base) ((base)->MCHR)
-#define RTC_WAR_REG(base) ((base)->WAR)
-#define RTC_RAR_REG(base) ((base)->RAR)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
+} RTC_Type;
/* ----------------------------------------------------------------------------
-- RTC Register Masks
@@ -12026,280 +7776,229 @@ typedef struct {
* @{
*/
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR_WIDTH 32
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR_WIDTH 16
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR_WIDTH 32
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR_WIDTH 8
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR_WIDTH 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV_WIDTH 8
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC_WIDTH 8
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_SWR_WIDTH 1
-#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_WPE_WIDTH 1
-#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_SUP_WIDTH 1
-#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_UM_WIDTH 1
-#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
-#define RTC_CR_WPS_MASK 0x10u
-#define RTC_CR_WPS_SHIFT 4
-#define RTC_CR_WPS_WIDTH 1
-#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_OSCE_WIDTH 1
-#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_CLKO_WIDTH 1
-#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC16P_WIDTH 1
-#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC8P_WIDTH 1
-#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC4P_WIDTH 1
-#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-#define RTC_CR_SC2P_WIDTH 1
-#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TIF_WIDTH 1
-#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TOF_WIDTH 1
-#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TAF_WIDTH 1
-#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
-#define RTC_SR_MOF_MASK 0x8u
-#define RTC_SR_MOF_SHIFT 3
-#define RTC_SR_MOF_WIDTH 1
-#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_MOF_SHIFT))&RTC_SR_MOF_MASK)
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-#define RTC_SR_TCE_WIDTH 1
-#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_TCL_WIDTH 1
-#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_CRL_WIDTH 1
-#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_SRL_WIDTH 1
-#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-#define RTC_LR_LRL_WIDTH 1
-#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
-#define RTC_LR_TTSL_MASK 0x100u
-#define RTC_LR_TTSL_SHIFT 8
-#define RTC_LR_TTSL_WIDTH 1
-#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TTSL_SHIFT))&RTC_LR_TTSL_MASK)
-#define RTC_LR_MEL_MASK 0x200u
-#define RTC_LR_MEL_SHIFT 9
-#define RTC_LR_MEL_WIDTH 1
-#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_MEL_SHIFT))&RTC_LR_MEL_MASK)
-#define RTC_LR_MCLL_MASK 0x400u
-#define RTC_LR_MCLL_SHIFT 10
-#define RTC_LR_MCLL_WIDTH 1
-#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_MCLL_SHIFT))&RTC_LR_MCLL_MASK)
-#define RTC_LR_MCHL_MASK 0x800u
-#define RTC_LR_MCHL_SHIFT 11
-#define RTC_LR_MCHL_WIDTH 1
-#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_MCHL_SHIFT))&RTC_LR_MCHL_MASK)
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TIIE_WIDTH 1
-#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TOIE_WIDTH 1
-#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TAIE_WIDTH 1
-#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
-#define RTC_IER_MOIE_MASK 0x8u
-#define RTC_IER_MOIE_SHIFT 3
-#define RTC_IER_MOIE_WIDTH 1
-#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_MOIE_SHIFT))&RTC_IER_MOIE_MASK)
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-#define RTC_IER_TSIE_WIDTH 1
-#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
-#define RTC_IER_WPON_MASK 0x80u
-#define RTC_IER_WPON_SHIFT 7
-#define RTC_IER_WPON_WIDTH 1
-#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
-/* TTSR Bit Fields */
-#define RTC_TTSR_TTS_MASK 0xFFFFFFFFu
-#define RTC_TTSR_TTS_SHIFT 0
-#define RTC_TTSR_TTS_WIDTH 32
-#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x))<<RTC_TTSR_TTS_SHIFT))&RTC_TTSR_TTS_MASK)
-/* MER Bit Fields */
-#define RTC_MER_MCE_MASK 0x10u
-#define RTC_MER_MCE_SHIFT 4
-#define RTC_MER_MCE_WIDTH 1
-#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_MER_MCE_SHIFT))&RTC_MER_MCE_MASK)
-/* MCLR Bit Fields */
-#define RTC_MCLR_MCL_MASK 0xFFFFFFFFu
-#define RTC_MCLR_MCL_SHIFT 0
-#define RTC_MCLR_MCL_WIDTH 32
-#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_MCLR_MCL_SHIFT))&RTC_MCLR_MCL_MASK)
-/* MCHR Bit Fields */
-#define RTC_MCHR_MCH_MASK 0xFFFFFFFFu
-#define RTC_MCHR_MCH_SHIFT 0
-#define RTC_MCHR_MCH_WIDTH 32
-#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x))<<RTC_MCHR_MCH_SHIFT))&RTC_MCHR_MCH_MASK)
-/* WAR Bit Fields */
-#define RTC_WAR_TSRW_MASK 0x1u
-#define RTC_WAR_TSRW_SHIFT 0
-#define RTC_WAR_TSRW_WIDTH 1
-#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
-#define RTC_WAR_TPRW_MASK 0x2u
-#define RTC_WAR_TPRW_SHIFT 1
-#define RTC_WAR_TPRW_WIDTH 1
-#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
-#define RTC_WAR_TARW_MASK 0x4u
-#define RTC_WAR_TARW_SHIFT 2
-#define RTC_WAR_TARW_WIDTH 1
-#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
-#define RTC_WAR_TCRW_MASK 0x8u
-#define RTC_WAR_TCRW_SHIFT 3
-#define RTC_WAR_TCRW_WIDTH 1
-#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
-#define RTC_WAR_CRW_MASK 0x10u
-#define RTC_WAR_CRW_SHIFT 4
-#define RTC_WAR_CRW_WIDTH 1
-#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
-#define RTC_WAR_SRW_MASK 0x20u
-#define RTC_WAR_SRW_SHIFT 5
-#define RTC_WAR_SRW_WIDTH 1
-#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
-#define RTC_WAR_LRW_MASK 0x40u
-#define RTC_WAR_LRW_SHIFT 6
-#define RTC_WAR_LRW_WIDTH 1
-#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
-#define RTC_WAR_IERW_MASK 0x80u
-#define RTC_WAR_IERW_SHIFT 7
-#define RTC_WAR_IERW_WIDTH 1
-#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
-#define RTC_WAR_TTSW_MASK 0x100u
-#define RTC_WAR_TTSW_SHIFT 8
-#define RTC_WAR_TTSW_WIDTH 1
-#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TTSW_SHIFT))&RTC_WAR_TTSW_MASK)
-#define RTC_WAR_MERW_MASK 0x200u
-#define RTC_WAR_MERW_SHIFT 9
-#define RTC_WAR_MERW_WIDTH 1
-#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_MERW_SHIFT))&RTC_WAR_MERW_MASK)
-#define RTC_WAR_MCLW_MASK 0x400u
-#define RTC_WAR_MCLW_SHIFT 10
-#define RTC_WAR_MCLW_WIDTH 1
-#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_MCLW_SHIFT))&RTC_WAR_MCLW_MASK)
-#define RTC_WAR_MCHW_MASK 0x800u
-#define RTC_WAR_MCHW_SHIFT 11
-#define RTC_WAR_MCHW_WIDTH 1
-#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x))<<RTC_WAR_MCHW_SHIFT))&RTC_WAR_MCHW_MASK)
-/* RAR Bit Fields */
-#define RTC_RAR_TSRR_MASK 0x1u
-#define RTC_RAR_TSRR_SHIFT 0
-#define RTC_RAR_TSRR_WIDTH 1
-#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
-#define RTC_RAR_TPRR_MASK 0x2u
-#define RTC_RAR_TPRR_SHIFT 1
-#define RTC_RAR_TPRR_WIDTH 1
-#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
-#define RTC_RAR_TARR_MASK 0x4u
-#define RTC_RAR_TARR_SHIFT 2
-#define RTC_RAR_TARR_WIDTH 1
-#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
-#define RTC_RAR_TCRR_MASK 0x8u
-#define RTC_RAR_TCRR_SHIFT 3
-#define RTC_RAR_TCRR_WIDTH 1
-#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
-#define RTC_RAR_CRR_MASK 0x10u
-#define RTC_RAR_CRR_SHIFT 4
-#define RTC_RAR_CRR_WIDTH 1
-#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
-#define RTC_RAR_SRR_MASK 0x20u
-#define RTC_RAR_SRR_SHIFT 5
-#define RTC_RAR_SRR_WIDTH 1
-#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
-#define RTC_RAR_LRR_MASK 0x40u
-#define RTC_RAR_LRR_SHIFT 6
-#define RTC_RAR_LRR_WIDTH 1
-#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
-#define RTC_RAR_IERR_MASK 0x80u
-#define RTC_RAR_IERR_SHIFT 7
-#define RTC_RAR_IERR_WIDTH 1
-#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
-#define RTC_RAR_TTSR_MASK 0x100u
-#define RTC_RAR_TTSR_SHIFT 8
-#define RTC_RAR_TTSR_WIDTH 1
-#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TTSR_SHIFT))&RTC_RAR_TTSR_MASK)
-#define RTC_RAR_MERR_MASK 0x200u
-#define RTC_RAR_MERR_SHIFT 9
-#define RTC_RAR_MERR_WIDTH 1
-#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_MERR_SHIFT))&RTC_RAR_MERR_MASK)
-#define RTC_RAR_MCLR_MASK 0x400u
-#define RTC_RAR_MCLR_SHIFT 10
-#define RTC_RAR_MCLR_WIDTH 1
-#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_MCLR_SHIFT))&RTC_RAR_MCLR_MASK)
-#define RTC_RAR_MCHR_MASK 0x800u
-#define RTC_RAR_MCHR_SHIFT 11
-#define RTC_RAR_MCHR_WIDTH 1
-#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x))<<RTC_RAR_MCHR_SHIFT))&RTC_RAR_MCHR_MASK)
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT (0U)
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT (0U)
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT (0U)
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK (0xFFU)
+#define RTC_TCR_TCR_SHIFT (0U)
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK (0xFF00U)
+#define RTC_TCR_CIR_SHIFT (8U)
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT (16U)
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT (24U)
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK (0x1U)
+#define RTC_CR_SWR_SHIFT (0U)
+#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK (0x2U)
+#define RTC_CR_WPE_SHIFT (1U)
+#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK (0x4U)
+#define RTC_CR_SUP_SHIFT (2U)
+#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK (0x8U)
+#define RTC_CR_UM_SHIFT (3U)
+#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK (0x10U)
+#define RTC_CR_WPS_SHIFT (4U)
+#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK (0x100U)
+#define RTC_CR_OSCE_SHIFT (8U)
+#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK (0x200U)
+#define RTC_CR_CLKO_SHIFT (9U)
+#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK (0x400U)
+#define RTC_CR_SC16P_SHIFT (10U)
+#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK (0x800U)
+#define RTC_CR_SC8P_SHIFT (11U)
+#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK (0x1000U)
+#define RTC_CR_SC4P_SHIFT (12U)
+#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK (0x2000U)
+#define RTC_CR_SC2P_SHIFT (13U)
+#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK (0x1U)
+#define RTC_SR_TIF_SHIFT (0U)
+#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK (0x2U)
+#define RTC_SR_TOF_SHIFT (1U)
+#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK (0x4U)
+#define RTC_SR_TAF_SHIFT (2U)
+#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_MOF_MASK (0x8U)
+#define RTC_SR_MOF_SHIFT (3U)
+#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
+#define RTC_SR_TCE_MASK (0x10U)
+#define RTC_SR_TCE_SHIFT (4U)
+#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK (0x8U)
+#define RTC_LR_TCL_SHIFT (3U)
+#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK (0x10U)
+#define RTC_LR_CRL_SHIFT (4U)
+#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK (0x20U)
+#define RTC_LR_SRL_SHIFT (5U)
+#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK (0x40U)
+#define RTC_LR_LRL_SHIFT (6U)
+#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+#define RTC_LR_TTSL_MASK (0x100U)
+#define RTC_LR_TTSL_SHIFT (8U)
+#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
+#define RTC_LR_MEL_MASK (0x200U)
+#define RTC_LR_MEL_SHIFT (9U)
+#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
+#define RTC_LR_MCLL_MASK (0x400U)
+#define RTC_LR_MCLL_SHIFT (10U)
+#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
+#define RTC_LR_MCHL_MASK (0x800U)
+#define RTC_LR_MCHL_SHIFT (11U)
+#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK (0x1U)
+#define RTC_IER_TIIE_SHIFT (0U)
+#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK (0x2U)
+#define RTC_IER_TOIE_SHIFT (1U)
+#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK (0x4U)
+#define RTC_IER_TAIE_SHIFT (2U)
+#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_MOIE_MASK (0x8U)
+#define RTC_IER_MOIE_SHIFT (3U)
+#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
+#define RTC_IER_TSIE_MASK (0x10U)
+#define RTC_IER_TSIE_SHIFT (4U)
+#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK (0x80U)
+#define RTC_IER_WPON_SHIFT (7U)
+#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+/*! @name TTSR - RTC Tamper Time Seconds Register */
+#define RTC_TTSR_TTS_MASK (0xFFFFFFFFU)
+#define RTC_TTSR_TTS_SHIFT (0U)
+#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
+
+/*! @name MER - RTC Monotonic Enable Register */
+#define RTC_MER_MCE_MASK (0x10U)
+#define RTC_MER_MCE_SHIFT (4U)
+#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
+
+/*! @name MCLR - RTC Monotonic Counter Low Register */
+#define RTC_MCLR_MCL_MASK (0xFFFFFFFFU)
+#define RTC_MCLR_MCL_SHIFT (0U)
+#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
+
+/*! @name MCHR - RTC Monotonic Counter High Register */
+#define RTC_MCHR_MCH_MASK (0xFFFFFFFFU)
+#define RTC_MCHR_MCH_SHIFT (0U)
+#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW_MASK (0x1U)
+#define RTC_WAR_TSRW_SHIFT (0U)
+#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK (0x2U)
+#define RTC_WAR_TPRW_SHIFT (1U)
+#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK (0x4U)
+#define RTC_WAR_TARW_SHIFT (2U)
+#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK (0x8U)
+#define RTC_WAR_TCRW_SHIFT (3U)
+#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK (0x10U)
+#define RTC_WAR_CRW_SHIFT (4U)
+#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK (0x20U)
+#define RTC_WAR_SRW_SHIFT (5U)
+#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK (0x40U)
+#define RTC_WAR_LRW_SHIFT (6U)
+#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK (0x80U)
+#define RTC_WAR_IERW_SHIFT (7U)
+#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+#define RTC_WAR_TTSW_MASK (0x100U)
+#define RTC_WAR_TTSW_SHIFT (8U)
+#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
+#define RTC_WAR_MERW_MASK (0x200U)
+#define RTC_WAR_MERW_SHIFT (9U)
+#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
+#define RTC_WAR_MCLW_MASK (0x400U)
+#define RTC_WAR_MCLW_SHIFT (10U)
+#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
+#define RTC_WAR_MCHW_MASK (0x800U)
+#define RTC_WAR_MCHW_SHIFT (11U)
+#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR_MASK (0x1U)
+#define RTC_RAR_TSRR_SHIFT (0U)
+#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK (0x2U)
+#define RTC_RAR_TPRR_SHIFT (1U)
+#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK (0x4U)
+#define RTC_RAR_TARR_SHIFT (2U)
+#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK (0x8U)
+#define RTC_RAR_TCRR_SHIFT (3U)
+#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK (0x10U)
+#define RTC_RAR_CRR_SHIFT (4U)
+#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK (0x20U)
+#define RTC_RAR_SRR_SHIFT (5U)
+#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK (0x40U)
+#define RTC_RAR_LRR_SHIFT (6U)
+#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK (0x80U)
+#define RTC_RAR_IERR_SHIFT (7U)
+#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+#define RTC_RAR_TTSR_MASK (0x100U)
+#define RTC_RAR_TTSR_SHIFT (8U)
+#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
+#define RTC_RAR_MERR_MASK (0x200U)
+#define RTC_RAR_MERR_SHIFT (9U)
+#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
+#define RTC_RAR_MCLR_MASK (0x400U)
+#define RTC_RAR_MCLR_SHIFT (10U)
+#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
+#define RTC_RAR_MCHR_MASK (0x800U)
+#define RTC_RAR_MCHR_SHIFT (11U)
+#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
+
/*!
* @}
@@ -12311,7 +8010,6 @@ typedef struct {
#define RTC_BASE (0x4003D000u)
/** Peripheral RTC base pointer */
#define RTC ((RTC_Type *)RTC_BASE)
-#define RTC_BASE_PTR (RTC)
/** Array initializer of RTC peripheral base addresses */
#define RTC_BASE_ADDRS { RTC_BASE }
/** Array initializer of RTC peripheral base pointers */
@@ -12320,38 +8018,6 @@ typedef struct {
#define RTC_IRQS { RTC_IRQn }
#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
-/* ----------------------------------------------------------------------------
- -- RTC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
- * @{
- */
-
-
-/* RTC - Register instance definitions */
-/* RTC */
-#define RTC_TSR RTC_TSR_REG(RTC)
-#define RTC_TPR RTC_TPR_REG(RTC)
-#define RTC_TAR RTC_TAR_REG(RTC)
-#define RTC_TCR RTC_TCR_REG(RTC)
-#define RTC_CR RTC_CR_REG(RTC)
-#define RTC_SR RTC_SR_REG(RTC)
-#define RTC_LR RTC_LR_REG(RTC)
-#define RTC_IER RTC_IER_REG(RTC)
-#define RTC_TTSR RTC_TTSR_REG(RTC)
-#define RTC_MER RTC_MER_REG(RTC)
-#define RTC_MCLR RTC_MCLR_REG(RTC)
-#define RTC_MCHR RTC_MCHR_REG(RTC)
-#define RTC_WAR RTC_WAR_REG(RTC)
-#define RTC_RAR RTC_RAR_REG(RTC)
-
-/*!
- * @}
- */ /* end of group RTC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group RTC_Peripheral_Access_Layer */
@@ -12392,46 +8058,7 @@ typedef struct {
__IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
uint8_t RESERVED_2[52];
__I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
-} SDHC_Type, *SDHC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SDHC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
- * @{
- */
-
-
-/* SDHC - Register accessors */
-#define SDHC_DSADDR_REG(base) ((base)->DSADDR)
-#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
-#define SDHC_CMDARG_REG(base) ((base)->CMDARG)
-#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
-#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
-#define SDHC_CMDRSP_COUNT 4
-#define SDHC_DATPORT_REG(base) ((base)->DATPORT)
-#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
-#define SDHC_PROCTL_REG(base) ((base)->PROCTL)
-#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
-#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
-#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
-#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
-#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
-#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
-#define SDHC_WML_REG(base) ((base)->WML)
-#define SDHC_FEVT_REG(base) ((base)->FEVT)
-#define SDHC_ADMAES_REG(base) ((base)->ADMAES)
-#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
-#define SDHC_VENDOR_REG(base) ((base)->VENDOR)
-#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
-#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
-
-/*!
- * @}
- */ /* end of group SDHC_Register_Accessor_Macros */
-
+} SDHC_Type;
/* ----------------------------------------------------------------------------
-- SDHC Register Masks
@@ -12442,663 +8069,528 @@ typedef struct {
* @{
*/
-/* DSADDR Bit Fields */
-#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
-#define SDHC_DSADDR_DSADDR_SHIFT 2
-#define SDHC_DSADDR_DSADDR_WIDTH 30
-#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
-/* BLKATTR Bit Fields */
-#define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
-#define SDHC_BLKATTR_BLKSIZE_SHIFT 0
-#define SDHC_BLKATTR_BLKSIZE_WIDTH 13
-#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
-#define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
-#define SDHC_BLKATTR_BLKCNT_SHIFT 16
-#define SDHC_BLKATTR_BLKCNT_WIDTH 16
-#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
-/* CMDARG Bit Fields */
-#define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
-#define SDHC_CMDARG_CMDARG_SHIFT 0
-#define SDHC_CMDARG_CMDARG_WIDTH 32
-#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
-/* XFERTYP Bit Fields */
-#define SDHC_XFERTYP_DMAEN_MASK 0x1u
-#define SDHC_XFERTYP_DMAEN_SHIFT 0
-#define SDHC_XFERTYP_DMAEN_WIDTH 1
-#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DMAEN_SHIFT))&SDHC_XFERTYP_DMAEN_MASK)
-#define SDHC_XFERTYP_BCEN_MASK 0x2u
-#define SDHC_XFERTYP_BCEN_SHIFT 1
-#define SDHC_XFERTYP_BCEN_WIDTH 1
-#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_BCEN_SHIFT))&SDHC_XFERTYP_BCEN_MASK)
-#define SDHC_XFERTYP_AC12EN_MASK 0x4u
-#define SDHC_XFERTYP_AC12EN_SHIFT 2
-#define SDHC_XFERTYP_AC12EN_WIDTH 1
-#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_AC12EN_SHIFT))&SDHC_XFERTYP_AC12EN_MASK)
-#define SDHC_XFERTYP_DTDSEL_MASK 0x10u
-#define SDHC_XFERTYP_DTDSEL_SHIFT 4
-#define SDHC_XFERTYP_DTDSEL_WIDTH 1
-#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DTDSEL_SHIFT))&SDHC_XFERTYP_DTDSEL_MASK)
-#define SDHC_XFERTYP_MSBSEL_MASK 0x20u
-#define SDHC_XFERTYP_MSBSEL_SHIFT 5
-#define SDHC_XFERTYP_MSBSEL_WIDTH 1
-#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_MSBSEL_SHIFT))&SDHC_XFERTYP_MSBSEL_MASK)
-#define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
-#define SDHC_XFERTYP_RSPTYP_SHIFT 16
-#define SDHC_XFERTYP_RSPTYP_WIDTH 2
-#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
-#define SDHC_XFERTYP_CCCEN_MASK 0x80000u
-#define SDHC_XFERTYP_CCCEN_SHIFT 19
-#define SDHC_XFERTYP_CCCEN_WIDTH 1
-#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CCCEN_SHIFT))&SDHC_XFERTYP_CCCEN_MASK)
-#define SDHC_XFERTYP_CICEN_MASK 0x100000u
-#define SDHC_XFERTYP_CICEN_SHIFT 20
-#define SDHC_XFERTYP_CICEN_WIDTH 1
-#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CICEN_SHIFT))&SDHC_XFERTYP_CICEN_MASK)
-#define SDHC_XFERTYP_DPSEL_MASK 0x200000u
-#define SDHC_XFERTYP_DPSEL_SHIFT 21
-#define SDHC_XFERTYP_DPSEL_WIDTH 1
-#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_DPSEL_SHIFT))&SDHC_XFERTYP_DPSEL_MASK)
-#define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
-#define SDHC_XFERTYP_CMDTYP_SHIFT 22
-#define SDHC_XFERTYP_CMDTYP_WIDTH 2
-#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
-#define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
-#define SDHC_XFERTYP_CMDINX_SHIFT 24
-#define SDHC_XFERTYP_CMDINX_WIDTH 6
-#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
-/* CMDRSP Bit Fields */
-#define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP0_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP0_WIDTH 32
-#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
-#define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP1_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP1_WIDTH 32
-#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
-#define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP2_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP2_WIDTH 32
-#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
-#define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
-#define SDHC_CMDRSP_CMDRSP3_SHIFT 0
-#define SDHC_CMDRSP_CMDRSP3_WIDTH 32
-#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
-/* DATPORT Bit Fields */
-#define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
-#define SDHC_DATPORT_DATCONT_SHIFT 0
-#define SDHC_DATPORT_DATCONT_WIDTH 32
-#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
-/* PRSSTAT Bit Fields */
-#define SDHC_PRSSTAT_CIHB_MASK 0x1u
-#define SDHC_PRSSTAT_CIHB_SHIFT 0
-#define SDHC_PRSSTAT_CIHB_WIDTH 1
-#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CIHB_SHIFT))&SDHC_PRSSTAT_CIHB_MASK)
-#define SDHC_PRSSTAT_CDIHB_MASK 0x2u
-#define SDHC_PRSSTAT_CDIHB_SHIFT 1
-#define SDHC_PRSSTAT_CDIHB_WIDTH 1
-#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CDIHB_SHIFT))&SDHC_PRSSTAT_CDIHB_MASK)
-#define SDHC_PRSSTAT_DLA_MASK 0x4u
-#define SDHC_PRSSTAT_DLA_SHIFT 2
-#define SDHC_PRSSTAT_DLA_WIDTH 1
-#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLA_SHIFT))&SDHC_PRSSTAT_DLA_MASK)
-#define SDHC_PRSSTAT_SDSTB_MASK 0x8u
-#define SDHC_PRSSTAT_SDSTB_SHIFT 3
-#define SDHC_PRSSTAT_SDSTB_WIDTH 1
-#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDSTB_SHIFT))&SDHC_PRSSTAT_SDSTB_MASK)
-#define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
-#define SDHC_PRSSTAT_IPGOFF_SHIFT 4
-#define SDHC_PRSSTAT_IPGOFF_WIDTH 1
-#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_IPGOFF_SHIFT))&SDHC_PRSSTAT_IPGOFF_MASK)
-#define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
-#define SDHC_PRSSTAT_HCKOFF_SHIFT 5
-#define SDHC_PRSSTAT_HCKOFF_WIDTH 1
-#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_HCKOFF_SHIFT))&SDHC_PRSSTAT_HCKOFF_MASK)
-#define SDHC_PRSSTAT_PEROFF_MASK 0x40u
-#define SDHC_PRSSTAT_PEROFF_SHIFT 6
-#define SDHC_PRSSTAT_PEROFF_WIDTH 1
-#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_PEROFF_SHIFT))&SDHC_PRSSTAT_PEROFF_MASK)
-#define SDHC_PRSSTAT_SDOFF_MASK 0x80u
-#define SDHC_PRSSTAT_SDOFF_SHIFT 7
-#define SDHC_PRSSTAT_SDOFF_WIDTH 1
-#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_SDOFF_SHIFT))&SDHC_PRSSTAT_SDOFF_MASK)
-#define SDHC_PRSSTAT_WTA_MASK 0x100u
-#define SDHC_PRSSTAT_WTA_SHIFT 8
-#define SDHC_PRSSTAT_WTA_WIDTH 1
-#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_WTA_SHIFT))&SDHC_PRSSTAT_WTA_MASK)
-#define SDHC_PRSSTAT_RTA_MASK 0x200u
-#define SDHC_PRSSTAT_RTA_SHIFT 9
-#define SDHC_PRSSTAT_RTA_WIDTH 1
-#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_RTA_SHIFT))&SDHC_PRSSTAT_RTA_MASK)
-#define SDHC_PRSSTAT_BWEN_MASK 0x400u
-#define SDHC_PRSSTAT_BWEN_SHIFT 10
-#define SDHC_PRSSTAT_BWEN_WIDTH 1
-#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BWEN_SHIFT))&SDHC_PRSSTAT_BWEN_MASK)
-#define SDHC_PRSSTAT_BREN_MASK 0x800u
-#define SDHC_PRSSTAT_BREN_SHIFT 11
-#define SDHC_PRSSTAT_BREN_WIDTH 1
-#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_BREN_SHIFT))&SDHC_PRSSTAT_BREN_MASK)
-#define SDHC_PRSSTAT_CINS_MASK 0x10000u
-#define SDHC_PRSSTAT_CINS_SHIFT 16
-#define SDHC_PRSSTAT_CINS_WIDTH 1
-#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CINS_SHIFT))&SDHC_PRSSTAT_CINS_MASK)
-#define SDHC_PRSSTAT_CLSL_MASK 0x800000u
-#define SDHC_PRSSTAT_CLSL_SHIFT 23
-#define SDHC_PRSSTAT_CLSL_WIDTH 1
-#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_CLSL_SHIFT))&SDHC_PRSSTAT_CLSL_MASK)
-#define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
-#define SDHC_PRSSTAT_DLSL_SHIFT 24
-#define SDHC_PRSSTAT_DLSL_WIDTH 8
-#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
-/* PROCTL Bit Fields */
-#define SDHC_PROCTL_LCTL_MASK 0x1u
-#define SDHC_PROCTL_LCTL_SHIFT 0
-#define SDHC_PROCTL_LCTL_WIDTH 1
-#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_LCTL_SHIFT))&SDHC_PROCTL_LCTL_MASK)
-#define SDHC_PROCTL_DTW_MASK 0x6u
-#define SDHC_PROCTL_DTW_SHIFT 1
-#define SDHC_PROCTL_DTW_WIDTH 2
-#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
-#define SDHC_PROCTL_D3CD_MASK 0x8u
-#define SDHC_PROCTL_D3CD_SHIFT 3
-#define SDHC_PROCTL_D3CD_WIDTH 1
-#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_D3CD_SHIFT))&SDHC_PROCTL_D3CD_MASK)
-#define SDHC_PROCTL_EMODE_MASK 0x30u
-#define SDHC_PROCTL_EMODE_SHIFT 4
-#define SDHC_PROCTL_EMODE_WIDTH 2
-#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
-#define SDHC_PROCTL_CDTL_MASK 0x40u
-#define SDHC_PROCTL_CDTL_SHIFT 6
-#define SDHC_PROCTL_CDTL_WIDTH 1
-#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDTL_SHIFT))&SDHC_PROCTL_CDTL_MASK)
-#define SDHC_PROCTL_CDSS_MASK 0x80u
-#define SDHC_PROCTL_CDSS_SHIFT 7
-#define SDHC_PROCTL_CDSS_WIDTH 1
-#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CDSS_SHIFT))&SDHC_PROCTL_CDSS_MASK)
-#define SDHC_PROCTL_DMAS_MASK 0x300u
-#define SDHC_PROCTL_DMAS_SHIFT 8
-#define SDHC_PROCTL_DMAS_WIDTH 2
-#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
-#define SDHC_PROCTL_SABGREQ_MASK 0x10000u
-#define SDHC_PROCTL_SABGREQ_SHIFT 16
-#define SDHC_PROCTL_SABGREQ_WIDTH 1
-#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_SABGREQ_SHIFT))&SDHC_PROCTL_SABGREQ_MASK)
-#define SDHC_PROCTL_CREQ_MASK 0x20000u
-#define SDHC_PROCTL_CREQ_SHIFT 17
-#define SDHC_PROCTL_CREQ_WIDTH 1
-#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_CREQ_SHIFT))&SDHC_PROCTL_CREQ_MASK)
-#define SDHC_PROCTL_RWCTL_MASK 0x40000u
-#define SDHC_PROCTL_RWCTL_SHIFT 18
-#define SDHC_PROCTL_RWCTL_WIDTH 1
-#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_RWCTL_SHIFT))&SDHC_PROCTL_RWCTL_MASK)
-#define SDHC_PROCTL_IABG_MASK 0x80000u
-#define SDHC_PROCTL_IABG_SHIFT 19
-#define SDHC_PROCTL_IABG_WIDTH 1
-#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_IABG_SHIFT))&SDHC_PROCTL_IABG_MASK)
-#define SDHC_PROCTL_WECINT_MASK 0x1000000u
-#define SDHC_PROCTL_WECINT_SHIFT 24
-#define SDHC_PROCTL_WECINT_WIDTH 1
-#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINT_SHIFT))&SDHC_PROCTL_WECINT_MASK)
-#define SDHC_PROCTL_WECINS_MASK 0x2000000u
-#define SDHC_PROCTL_WECINS_SHIFT 25
-#define SDHC_PROCTL_WECINS_WIDTH 1
-#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECINS_SHIFT))&SDHC_PROCTL_WECINS_MASK)
-#define SDHC_PROCTL_WECRM_MASK 0x4000000u
-#define SDHC_PROCTL_WECRM_SHIFT 26
-#define SDHC_PROCTL_WECRM_WIDTH 1
-#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_WECRM_SHIFT))&SDHC_PROCTL_WECRM_MASK)
-/* SYSCTL Bit Fields */
-#define SDHC_SYSCTL_IPGEN_MASK 0x1u
-#define SDHC_SYSCTL_IPGEN_SHIFT 0
-#define SDHC_SYSCTL_IPGEN_WIDTH 1
-#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_IPGEN_SHIFT))&SDHC_SYSCTL_IPGEN_MASK)
-#define SDHC_SYSCTL_HCKEN_MASK 0x2u
-#define SDHC_SYSCTL_HCKEN_SHIFT 1
-#define SDHC_SYSCTL_HCKEN_WIDTH 1
-#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_HCKEN_SHIFT))&SDHC_SYSCTL_HCKEN_MASK)
-#define SDHC_SYSCTL_PEREN_MASK 0x4u
-#define SDHC_SYSCTL_PEREN_SHIFT 2
-#define SDHC_SYSCTL_PEREN_WIDTH 1
-#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_PEREN_SHIFT))&SDHC_SYSCTL_PEREN_MASK)
-#define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
-#define SDHC_SYSCTL_SDCLKEN_SHIFT 3
-#define SDHC_SYSCTL_SDCLKEN_WIDTH 1
-#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKEN_SHIFT))&SDHC_SYSCTL_SDCLKEN_MASK)
-#define SDHC_SYSCTL_DVS_MASK 0xF0u
-#define SDHC_SYSCTL_DVS_SHIFT 4
-#define SDHC_SYSCTL_DVS_WIDTH 4
-#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
-#define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
-#define SDHC_SYSCTL_SDCLKFS_SHIFT 8
-#define SDHC_SYSCTL_SDCLKFS_WIDTH 8
-#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
-#define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
-#define SDHC_SYSCTL_DTOCV_SHIFT 16
-#define SDHC_SYSCTL_DTOCV_WIDTH 4
-#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
-#define SDHC_SYSCTL_RSTA_MASK 0x1000000u
-#define SDHC_SYSCTL_RSTA_SHIFT 24
-#define SDHC_SYSCTL_RSTA_WIDTH 1
-#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTA_SHIFT))&SDHC_SYSCTL_RSTA_MASK)
-#define SDHC_SYSCTL_RSTC_MASK 0x2000000u
-#define SDHC_SYSCTL_RSTC_SHIFT 25
-#define SDHC_SYSCTL_RSTC_WIDTH 1
-#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTC_SHIFT))&SDHC_SYSCTL_RSTC_MASK)
-#define SDHC_SYSCTL_RSTD_MASK 0x4000000u
-#define SDHC_SYSCTL_RSTD_SHIFT 26
-#define SDHC_SYSCTL_RSTD_WIDTH 1
-#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_RSTD_SHIFT))&SDHC_SYSCTL_RSTD_MASK)
-#define SDHC_SYSCTL_INITA_MASK 0x8000000u
-#define SDHC_SYSCTL_INITA_SHIFT 27
-#define SDHC_SYSCTL_INITA_WIDTH 1
-#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_INITA_SHIFT))&SDHC_SYSCTL_INITA_MASK)
-/* IRQSTAT Bit Fields */
-#define SDHC_IRQSTAT_CC_MASK 0x1u
-#define SDHC_IRQSTAT_CC_SHIFT 0
-#define SDHC_IRQSTAT_CC_WIDTH 1
-#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CC_SHIFT))&SDHC_IRQSTAT_CC_MASK)
-#define SDHC_IRQSTAT_TC_MASK 0x2u
-#define SDHC_IRQSTAT_TC_SHIFT 1
-#define SDHC_IRQSTAT_TC_WIDTH 1
-#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_TC_SHIFT))&SDHC_IRQSTAT_TC_MASK)
-#define SDHC_IRQSTAT_BGE_MASK 0x4u
-#define SDHC_IRQSTAT_BGE_SHIFT 2
-#define SDHC_IRQSTAT_BGE_WIDTH 1
-#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BGE_SHIFT))&SDHC_IRQSTAT_BGE_MASK)
-#define SDHC_IRQSTAT_DINT_MASK 0x8u
-#define SDHC_IRQSTAT_DINT_SHIFT 3
-#define SDHC_IRQSTAT_DINT_WIDTH 1
-#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DINT_SHIFT))&SDHC_IRQSTAT_DINT_MASK)
-#define SDHC_IRQSTAT_BWR_MASK 0x10u
-#define SDHC_IRQSTAT_BWR_SHIFT 4
-#define SDHC_IRQSTAT_BWR_WIDTH 1
-#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BWR_SHIFT))&SDHC_IRQSTAT_BWR_MASK)
-#define SDHC_IRQSTAT_BRR_MASK 0x20u
-#define SDHC_IRQSTAT_BRR_SHIFT 5
-#define SDHC_IRQSTAT_BRR_WIDTH 1
-#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_BRR_SHIFT))&SDHC_IRQSTAT_BRR_MASK)
-#define SDHC_IRQSTAT_CINS_MASK 0x40u
-#define SDHC_IRQSTAT_CINS_SHIFT 6
-#define SDHC_IRQSTAT_CINS_WIDTH 1
-#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINS_SHIFT))&SDHC_IRQSTAT_CINS_MASK)
-#define SDHC_IRQSTAT_CRM_MASK 0x80u
-#define SDHC_IRQSTAT_CRM_SHIFT 7
-#define SDHC_IRQSTAT_CRM_WIDTH 1
-#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CRM_SHIFT))&SDHC_IRQSTAT_CRM_MASK)
-#define SDHC_IRQSTAT_CINT_MASK 0x100u
-#define SDHC_IRQSTAT_CINT_SHIFT 8
-#define SDHC_IRQSTAT_CINT_WIDTH 1
-#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CINT_SHIFT))&SDHC_IRQSTAT_CINT_MASK)
-#define SDHC_IRQSTAT_CTOE_MASK 0x10000u
-#define SDHC_IRQSTAT_CTOE_SHIFT 16
-#define SDHC_IRQSTAT_CTOE_WIDTH 1
-#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CTOE_SHIFT))&SDHC_IRQSTAT_CTOE_MASK)
-#define SDHC_IRQSTAT_CCE_MASK 0x20000u
-#define SDHC_IRQSTAT_CCE_SHIFT 17
-#define SDHC_IRQSTAT_CCE_WIDTH 1
-#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CCE_SHIFT))&SDHC_IRQSTAT_CCE_MASK)
-#define SDHC_IRQSTAT_CEBE_MASK 0x40000u
-#define SDHC_IRQSTAT_CEBE_SHIFT 18
-#define SDHC_IRQSTAT_CEBE_WIDTH 1
-#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CEBE_SHIFT))&SDHC_IRQSTAT_CEBE_MASK)
-#define SDHC_IRQSTAT_CIE_MASK 0x80000u
-#define SDHC_IRQSTAT_CIE_SHIFT 19
-#define SDHC_IRQSTAT_CIE_WIDTH 1
-#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_CIE_SHIFT))&SDHC_IRQSTAT_CIE_MASK)
-#define SDHC_IRQSTAT_DTOE_MASK 0x100000u
-#define SDHC_IRQSTAT_DTOE_SHIFT 20
-#define SDHC_IRQSTAT_DTOE_WIDTH 1
-#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DTOE_SHIFT))&SDHC_IRQSTAT_DTOE_MASK)
-#define SDHC_IRQSTAT_DCE_MASK 0x200000u
-#define SDHC_IRQSTAT_DCE_SHIFT 21
-#define SDHC_IRQSTAT_DCE_WIDTH 1
-#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DCE_SHIFT))&SDHC_IRQSTAT_DCE_MASK)
-#define SDHC_IRQSTAT_DEBE_MASK 0x400000u
-#define SDHC_IRQSTAT_DEBE_SHIFT 22
-#define SDHC_IRQSTAT_DEBE_WIDTH 1
-#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DEBE_SHIFT))&SDHC_IRQSTAT_DEBE_MASK)
-#define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
-#define SDHC_IRQSTAT_AC12E_SHIFT 24
-#define SDHC_IRQSTAT_AC12E_WIDTH 1
-#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_AC12E_SHIFT))&SDHC_IRQSTAT_AC12E_MASK)
-#define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
-#define SDHC_IRQSTAT_DMAE_SHIFT 28
-#define SDHC_IRQSTAT_DMAE_WIDTH 1
-#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTAT_DMAE_SHIFT))&SDHC_IRQSTAT_DMAE_MASK)
-/* IRQSTATEN Bit Fields */
-#define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
-#define SDHC_IRQSTATEN_CCSEN_SHIFT 0
-#define SDHC_IRQSTATEN_CCSEN_WIDTH 1
-#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCSEN_SHIFT))&SDHC_IRQSTATEN_CCSEN_MASK)
-#define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
-#define SDHC_IRQSTATEN_TCSEN_SHIFT 1
-#define SDHC_IRQSTATEN_TCSEN_WIDTH 1
-#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_TCSEN_SHIFT))&SDHC_IRQSTATEN_TCSEN_MASK)
-#define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
-#define SDHC_IRQSTATEN_BGESEN_SHIFT 2
-#define SDHC_IRQSTATEN_BGESEN_WIDTH 1
-#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BGESEN_SHIFT))&SDHC_IRQSTATEN_BGESEN_MASK)
-#define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
-#define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
-#define SDHC_IRQSTATEN_DINTSEN_WIDTH 1
-#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DINTSEN_SHIFT))&SDHC_IRQSTATEN_DINTSEN_MASK)
-#define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
-#define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
-#define SDHC_IRQSTATEN_BWRSEN_WIDTH 1
-#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BWRSEN_SHIFT))&SDHC_IRQSTATEN_BWRSEN_MASK)
-#define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
-#define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
-#define SDHC_IRQSTATEN_BRRSEN_WIDTH 1
-#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_BRRSEN_SHIFT))&SDHC_IRQSTATEN_BRRSEN_MASK)
-#define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
-#define SDHC_IRQSTATEN_CINSEN_SHIFT 6
-#define SDHC_IRQSTATEN_CINSEN_WIDTH 1
-#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINSEN_SHIFT))&SDHC_IRQSTATEN_CINSEN_MASK)
-#define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
-#define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
-#define SDHC_IRQSTATEN_CRMSEN_WIDTH 1
-#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CRMSEN_SHIFT))&SDHC_IRQSTATEN_CRMSEN_MASK)
-#define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
-#define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
-#define SDHC_IRQSTATEN_CINTSEN_WIDTH 1
-#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CINTSEN_SHIFT))&SDHC_IRQSTATEN_CINTSEN_MASK)
-#define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
-#define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
-#define SDHC_IRQSTATEN_CTOESEN_WIDTH 1
-#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CTOESEN_SHIFT))&SDHC_IRQSTATEN_CTOESEN_MASK)
-#define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
-#define SDHC_IRQSTATEN_CCESEN_SHIFT 17
-#define SDHC_IRQSTATEN_CCESEN_WIDTH 1
-#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CCESEN_SHIFT))&SDHC_IRQSTATEN_CCESEN_MASK)
-#define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
-#define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
-#define SDHC_IRQSTATEN_CEBESEN_WIDTH 1
-#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CEBESEN_SHIFT))&SDHC_IRQSTATEN_CEBESEN_MASK)
-#define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
-#define SDHC_IRQSTATEN_CIESEN_SHIFT 19
-#define SDHC_IRQSTATEN_CIESEN_WIDTH 1
-#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_CIESEN_SHIFT))&SDHC_IRQSTATEN_CIESEN_MASK)
-#define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
-#define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
-#define SDHC_IRQSTATEN_DTOESEN_WIDTH 1
-#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DTOESEN_SHIFT))&SDHC_IRQSTATEN_DTOESEN_MASK)
-#define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
-#define SDHC_IRQSTATEN_DCESEN_SHIFT 21
-#define SDHC_IRQSTATEN_DCESEN_WIDTH 1
-#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DCESEN_SHIFT))&SDHC_IRQSTATEN_DCESEN_MASK)
-#define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
-#define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
-#define SDHC_IRQSTATEN_DEBESEN_WIDTH 1
-#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DEBESEN_SHIFT))&SDHC_IRQSTATEN_DEBESEN_MASK)
-#define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
-#define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
-#define SDHC_IRQSTATEN_AC12ESEN_WIDTH 1
-#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_AC12ESEN_SHIFT))&SDHC_IRQSTATEN_AC12ESEN_MASK)
-#define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
-#define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
-#define SDHC_IRQSTATEN_DMAESEN_WIDTH 1
-#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSTATEN_DMAESEN_SHIFT))&SDHC_IRQSTATEN_DMAESEN_MASK)
-/* IRQSIGEN Bit Fields */
-#define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
-#define SDHC_IRQSIGEN_CCIEN_SHIFT 0
-#define SDHC_IRQSIGEN_CCIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCIEN_SHIFT))&SDHC_IRQSIGEN_CCIEN_MASK)
-#define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
-#define SDHC_IRQSIGEN_TCIEN_SHIFT 1
-#define SDHC_IRQSIGEN_TCIEN_WIDTH 1
-#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_TCIEN_SHIFT))&SDHC_IRQSIGEN_TCIEN_MASK)
-#define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
-#define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
-#define SDHC_IRQSIGEN_BGEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BGEIEN_SHIFT))&SDHC_IRQSIGEN_BGEIEN_MASK)
-#define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
-#define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
-#define SDHC_IRQSIGEN_DINTIEN_WIDTH 1
-#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DINTIEN_SHIFT))&SDHC_IRQSIGEN_DINTIEN_MASK)
-#define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
-#define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
-#define SDHC_IRQSIGEN_BWRIEN_WIDTH 1
-#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BWRIEN_SHIFT))&SDHC_IRQSIGEN_BWRIEN_MASK)
-#define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
-#define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
-#define SDHC_IRQSIGEN_BRRIEN_WIDTH 1
-#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_BRRIEN_SHIFT))&SDHC_IRQSIGEN_BRRIEN_MASK)
-#define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
-#define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
-#define SDHC_IRQSIGEN_CINSIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINSIEN_SHIFT))&SDHC_IRQSIGEN_CINSIEN_MASK)
-#define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
-#define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
-#define SDHC_IRQSIGEN_CRMIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CRMIEN_SHIFT))&SDHC_IRQSIGEN_CRMIEN_MASK)
-#define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
-#define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
-#define SDHC_IRQSIGEN_CINTIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CINTIEN_SHIFT))&SDHC_IRQSIGEN_CINTIEN_MASK)
-#define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
-#define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
-#define SDHC_IRQSIGEN_CTOEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CTOEIEN_SHIFT))&SDHC_IRQSIGEN_CTOEIEN_MASK)
-#define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
-#define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
-#define SDHC_IRQSIGEN_CCEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CCEIEN_SHIFT))&SDHC_IRQSIGEN_CCEIEN_MASK)
-#define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
-#define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
-#define SDHC_IRQSIGEN_CEBEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CEBEIEN_SHIFT))&SDHC_IRQSIGEN_CEBEIEN_MASK)
-#define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
-#define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
-#define SDHC_IRQSIGEN_CIEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_CIEIEN_SHIFT))&SDHC_IRQSIGEN_CIEIEN_MASK)
-#define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
-#define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
-#define SDHC_IRQSIGEN_DTOEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DTOEIEN_SHIFT))&SDHC_IRQSIGEN_DTOEIEN_MASK)
-#define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
-#define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
-#define SDHC_IRQSIGEN_DCEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DCEIEN_SHIFT))&SDHC_IRQSIGEN_DCEIEN_MASK)
-#define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
-#define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
-#define SDHC_IRQSIGEN_DEBEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DEBEIEN_SHIFT))&SDHC_IRQSIGEN_DEBEIEN_MASK)
-#define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
-#define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
-#define SDHC_IRQSIGEN_AC12EIEN_WIDTH 1
-#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_AC12EIEN_SHIFT))&SDHC_IRQSIGEN_AC12EIEN_MASK)
-#define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
-#define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
-#define SDHC_IRQSIGEN_DMAEIEN_WIDTH 1
-#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_IRQSIGEN_DMAEIEN_SHIFT))&SDHC_IRQSIGEN_DMAEIEN_MASK)
-/* AC12ERR Bit Fields */
-#define SDHC_AC12ERR_AC12NE_MASK 0x1u
-#define SDHC_AC12ERR_AC12NE_SHIFT 0
-#define SDHC_AC12ERR_AC12NE_WIDTH 1
-#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12NE_SHIFT))&SDHC_AC12ERR_AC12NE_MASK)
-#define SDHC_AC12ERR_AC12TOE_MASK 0x2u
-#define SDHC_AC12ERR_AC12TOE_SHIFT 1
-#define SDHC_AC12ERR_AC12TOE_WIDTH 1
-#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12TOE_SHIFT))&SDHC_AC12ERR_AC12TOE_MASK)
-#define SDHC_AC12ERR_AC12EBE_MASK 0x4u
-#define SDHC_AC12ERR_AC12EBE_SHIFT 2
-#define SDHC_AC12ERR_AC12EBE_WIDTH 1
-#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12EBE_SHIFT))&SDHC_AC12ERR_AC12EBE_MASK)
-#define SDHC_AC12ERR_AC12CE_MASK 0x8u
-#define SDHC_AC12ERR_AC12CE_SHIFT 3
-#define SDHC_AC12ERR_AC12CE_WIDTH 1
-#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12CE_SHIFT))&SDHC_AC12ERR_AC12CE_MASK)
-#define SDHC_AC12ERR_AC12IE_MASK 0x10u
-#define SDHC_AC12ERR_AC12IE_SHIFT 4
-#define SDHC_AC12ERR_AC12IE_WIDTH 1
-#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_AC12IE_SHIFT))&SDHC_AC12ERR_AC12IE_MASK)
-#define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
-#define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
-#define SDHC_AC12ERR_CNIBAC12E_WIDTH 1
-#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x))<<SDHC_AC12ERR_CNIBAC12E_SHIFT))&SDHC_AC12ERR_CNIBAC12E_MASK)
-/* HTCAPBLT Bit Fields */
-#define SDHC_HTCAPBLT_MBL_MASK 0x70000u
-#define SDHC_HTCAPBLT_MBL_SHIFT 16
-#define SDHC_HTCAPBLT_MBL_WIDTH 3
-#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
-#define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
-#define SDHC_HTCAPBLT_ADMAS_SHIFT 20
-#define SDHC_HTCAPBLT_ADMAS_WIDTH 1
-#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_ADMAS_SHIFT))&SDHC_HTCAPBLT_ADMAS_MASK)
-#define SDHC_HTCAPBLT_HSS_MASK 0x200000u
-#define SDHC_HTCAPBLT_HSS_SHIFT 21
-#define SDHC_HTCAPBLT_HSS_WIDTH 1
-#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_HSS_SHIFT))&SDHC_HTCAPBLT_HSS_MASK)
-#define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
-#define SDHC_HTCAPBLT_DMAS_SHIFT 22
-#define SDHC_HTCAPBLT_DMAS_WIDTH 1
-#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_DMAS_SHIFT))&SDHC_HTCAPBLT_DMAS_MASK)
-#define SDHC_HTCAPBLT_SRS_MASK 0x800000u
-#define SDHC_HTCAPBLT_SRS_SHIFT 23
-#define SDHC_HTCAPBLT_SRS_WIDTH 1
-#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_SRS_SHIFT))&SDHC_HTCAPBLT_SRS_MASK)
-#define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
-#define SDHC_HTCAPBLT_VS33_SHIFT 24
-#define SDHC_HTCAPBLT_VS33_WIDTH 1
-#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_VS33_SHIFT))&SDHC_HTCAPBLT_VS33_MASK)
-/* WML Bit Fields */
-#define SDHC_WML_RDWML_MASK 0xFFu
-#define SDHC_WML_RDWML_SHIFT 0
-#define SDHC_WML_RDWML_WIDTH 8
-#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
-#define SDHC_WML_WRWML_MASK 0xFF0000u
-#define SDHC_WML_WRWML_SHIFT 16
-#define SDHC_WML_WRWML_WIDTH 8
-#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
-/* FEVT Bit Fields */
-#define SDHC_FEVT_AC12NE_MASK 0x1u
-#define SDHC_FEVT_AC12NE_SHIFT 0
-#define SDHC_FEVT_AC12NE_WIDTH 1
-#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12NE_SHIFT))&SDHC_FEVT_AC12NE_MASK)
-#define SDHC_FEVT_AC12TOE_MASK 0x2u
-#define SDHC_FEVT_AC12TOE_SHIFT 1
-#define SDHC_FEVT_AC12TOE_WIDTH 1
-#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12TOE_SHIFT))&SDHC_FEVT_AC12TOE_MASK)
-#define SDHC_FEVT_AC12CE_MASK 0x4u
-#define SDHC_FEVT_AC12CE_SHIFT 2
-#define SDHC_FEVT_AC12CE_WIDTH 1
-#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12CE_SHIFT))&SDHC_FEVT_AC12CE_MASK)
-#define SDHC_FEVT_AC12EBE_MASK 0x8u
-#define SDHC_FEVT_AC12EBE_SHIFT 3
-#define SDHC_FEVT_AC12EBE_WIDTH 1
-#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12EBE_SHIFT))&SDHC_FEVT_AC12EBE_MASK)
-#define SDHC_FEVT_AC12IE_MASK 0x10u
-#define SDHC_FEVT_AC12IE_SHIFT 4
-#define SDHC_FEVT_AC12IE_WIDTH 1
-#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12IE_SHIFT))&SDHC_FEVT_AC12IE_MASK)
-#define SDHC_FEVT_CNIBAC12E_MASK 0x80u
-#define SDHC_FEVT_CNIBAC12E_SHIFT 7
-#define SDHC_FEVT_CNIBAC12E_WIDTH 1
-#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CNIBAC12E_SHIFT))&SDHC_FEVT_CNIBAC12E_MASK)
-#define SDHC_FEVT_CTOE_MASK 0x10000u
-#define SDHC_FEVT_CTOE_SHIFT 16
-#define SDHC_FEVT_CTOE_WIDTH 1
-#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CTOE_SHIFT))&SDHC_FEVT_CTOE_MASK)
-#define SDHC_FEVT_CCE_MASK 0x20000u
-#define SDHC_FEVT_CCE_SHIFT 17
-#define SDHC_FEVT_CCE_WIDTH 1
-#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CCE_SHIFT))&SDHC_FEVT_CCE_MASK)
-#define SDHC_FEVT_CEBE_MASK 0x40000u
-#define SDHC_FEVT_CEBE_SHIFT 18
-#define SDHC_FEVT_CEBE_WIDTH 1
-#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CEBE_SHIFT))&SDHC_FEVT_CEBE_MASK)
-#define SDHC_FEVT_CIE_MASK 0x80000u
-#define SDHC_FEVT_CIE_SHIFT 19
-#define SDHC_FEVT_CIE_WIDTH 1
-#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CIE_SHIFT))&SDHC_FEVT_CIE_MASK)
-#define SDHC_FEVT_DTOE_MASK 0x100000u
-#define SDHC_FEVT_DTOE_SHIFT 20
-#define SDHC_FEVT_DTOE_WIDTH 1
-#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DTOE_SHIFT))&SDHC_FEVT_DTOE_MASK)
-#define SDHC_FEVT_DCE_MASK 0x200000u
-#define SDHC_FEVT_DCE_SHIFT 21
-#define SDHC_FEVT_DCE_WIDTH 1
-#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DCE_SHIFT))&SDHC_FEVT_DCE_MASK)
-#define SDHC_FEVT_DEBE_MASK 0x400000u
-#define SDHC_FEVT_DEBE_SHIFT 22
-#define SDHC_FEVT_DEBE_WIDTH 1
-#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DEBE_SHIFT))&SDHC_FEVT_DEBE_MASK)
-#define SDHC_FEVT_AC12E_MASK 0x1000000u
-#define SDHC_FEVT_AC12E_SHIFT 24
-#define SDHC_FEVT_AC12E_WIDTH 1
-#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_AC12E_SHIFT))&SDHC_FEVT_AC12E_MASK)
-#define SDHC_FEVT_DMAE_MASK 0x10000000u
-#define SDHC_FEVT_DMAE_SHIFT 28
-#define SDHC_FEVT_DMAE_WIDTH 1
-#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_DMAE_SHIFT))&SDHC_FEVT_DMAE_MASK)
-#define SDHC_FEVT_CINT_MASK 0x80000000u
-#define SDHC_FEVT_CINT_SHIFT 31
-#define SDHC_FEVT_CINT_WIDTH 1
-#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_FEVT_CINT_SHIFT))&SDHC_FEVT_CINT_MASK)
-/* ADMAES Bit Fields */
-#define SDHC_ADMAES_ADMAES_MASK 0x3u
-#define SDHC_ADMAES_ADMAES_SHIFT 0
-#define SDHC_ADMAES_ADMAES_WIDTH 2
-#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
-#define SDHC_ADMAES_ADMALME_MASK 0x4u
-#define SDHC_ADMAES_ADMALME_SHIFT 2
-#define SDHC_ADMAES_ADMALME_WIDTH 1
-#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMALME_SHIFT))&SDHC_ADMAES_ADMALME_MASK)
-#define SDHC_ADMAES_ADMADCE_MASK 0x8u
-#define SDHC_ADMAES_ADMADCE_SHIFT 3
-#define SDHC_ADMAES_ADMADCE_WIDTH 1
-#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMADCE_SHIFT))&SDHC_ADMAES_ADMADCE_MASK)
-/* ADSADDR Bit Fields */
-#define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
-#define SDHC_ADSADDR_ADSADDR_SHIFT 2
-#define SDHC_ADSADDR_ADSADDR_WIDTH 30
-#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
-/* VENDOR Bit Fields */
-#define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
-#define SDHC_VENDOR_EXTDMAEN_SHIFT 0
-#define SDHC_VENDOR_EXTDMAEN_WIDTH 1
-#define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXTDMAEN_SHIFT))&SDHC_VENDOR_EXTDMAEN_MASK)
-#define SDHC_VENDOR_EXBLKNU_MASK 0x2u
-#define SDHC_VENDOR_EXBLKNU_SHIFT 1
-#define SDHC_VENDOR_EXBLKNU_WIDTH 1
-#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_EXBLKNU_SHIFT))&SDHC_VENDOR_EXBLKNU_MASK)
-#define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
-#define SDHC_VENDOR_INTSTVAL_SHIFT 16
-#define SDHC_VENDOR_INTSTVAL_WIDTH 8
-#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
-/* MMCBOOT Bit Fields */
-#define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
-#define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
-#define SDHC_MMCBOOT_DTOCVACK_WIDTH 4
-#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
-#define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
-#define SDHC_MMCBOOT_BOOTACK_SHIFT 4
-#define SDHC_MMCBOOT_BOOTACK_WIDTH 1
-#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTACK_SHIFT))&SDHC_MMCBOOT_BOOTACK_MASK)
-#define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
-#define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
-#define SDHC_MMCBOOT_BOOTMODE_WIDTH 1
-#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTMODE_SHIFT))&SDHC_MMCBOOT_BOOTMODE_MASK)
-#define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
-#define SDHC_MMCBOOT_BOOTEN_SHIFT 6
-#define SDHC_MMCBOOT_BOOTEN_WIDTH 1
-#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTEN_SHIFT))&SDHC_MMCBOOT_BOOTEN_MASK)
-#define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
-#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
-#define SDHC_MMCBOOT_AUTOSABGEN_WIDTH 1
-#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_AUTOSABGEN_SHIFT))&SDHC_MMCBOOT_AUTOSABGEN_MASK)
-#define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
-#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
-#define SDHC_MMCBOOT_BOOTBLKCNT_WIDTH 16
-#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
-/* HOSTVER Bit Fields */
-#define SDHC_HOSTVER_SVN_MASK 0xFFu
-#define SDHC_HOSTVER_SVN_SHIFT 0
-#define SDHC_HOSTVER_SVN_WIDTH 8
-#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
-#define SDHC_HOSTVER_VVN_MASK 0xFF00u
-#define SDHC_HOSTVER_VVN_SHIFT 8
-#define SDHC_HOSTVER_VVN_WIDTH 8
-#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+/*! @name DSADDR - DMA System Address register */
+#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
+#define SDHC_DSADDR_DSADDR_SHIFT (2U)
+#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
+
+/*! @name BLKATTR - Block Attributes register */
+#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
+#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
+#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
+#define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
+#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
+
+/*! @name CMDARG - Command Argument register */
+#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
+#define SDHC_CMDARG_CMDARG_SHIFT (0U)
+#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
+
+/*! @name XFERTYP - Transfer Type register */
+#define SDHC_XFERTYP_DMAEN_MASK (0x1U)
+#define SDHC_XFERTYP_DMAEN_SHIFT (0U)
+#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK (0x2U)
+#define SDHC_XFERTYP_BCEN_SHIFT (1U)
+#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK (0x4U)
+#define SDHC_XFERTYP_AC12EN_SHIFT (2U)
+#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
+#define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
+#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
+#define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
+#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
+#define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
+#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
+#define SDHC_XFERTYP_CCCEN_SHIFT (19U)
+#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK (0x100000U)
+#define SDHC_XFERTYP_CICEN_SHIFT (20U)
+#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
+#define SDHC_XFERTYP_DPSEL_SHIFT (21U)
+#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
+#define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
+#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
+#define SDHC_XFERTYP_CMDINX_SHIFT (24U)
+#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
+
+/*! @name CMDRSP - Command Response 0..Command Response 3 */
+#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
+#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
+
+/* The count of SDHC_CMDRSP */
+#define SDHC_CMDRSP_COUNT (4U)
+
+/*! @name DATPORT - Buffer Data Port register */
+#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
+#define SDHC_DATPORT_DATCONT_SHIFT (0U)
+#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
+
+/*! @name PRSSTAT - Present State register */
+#define SDHC_PRSSTAT_CIHB_MASK (0x1U)
+#define SDHC_PRSSTAT_CIHB_SHIFT (0U)
+#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
+#define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
+#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK (0x4U)
+#define SDHC_PRSSTAT_DLA_SHIFT (2U)
+#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
+#define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
+#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
+#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
+#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
+#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
+#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
+#define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
+#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
+#define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
+#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK (0x100U)
+#define SDHC_PRSSTAT_WTA_SHIFT (8U)
+#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK (0x200U)
+#define SDHC_PRSSTAT_RTA_SHIFT (9U)
+#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK (0x400U)
+#define SDHC_PRSSTAT_BWEN_SHIFT (10U)
+#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK (0x800U)
+#define SDHC_PRSSTAT_BREN_SHIFT (11U)
+#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK (0x10000U)
+#define SDHC_PRSSTAT_CINS_SHIFT (16U)
+#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
+#define SDHC_PRSSTAT_CLSL_SHIFT (23U)
+#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
+#define SDHC_PRSSTAT_DLSL_SHIFT (24U)
+#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
+
+/*! @name PROCTL - Protocol Control register */
+#define SDHC_PROCTL_LCTL_MASK (0x1U)
+#define SDHC_PROCTL_LCTL_SHIFT (0U)
+#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK (0x6U)
+#define SDHC_PROCTL_DTW_SHIFT (1U)
+#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK (0x8U)
+#define SDHC_PROCTL_D3CD_SHIFT (3U)
+#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK (0x30U)
+#define SDHC_PROCTL_EMODE_SHIFT (4U)
+#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK (0x40U)
+#define SDHC_PROCTL_CDTL_SHIFT (6U)
+#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK (0x80U)
+#define SDHC_PROCTL_CDSS_SHIFT (7U)
+#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK (0x300U)
+#define SDHC_PROCTL_DMAS_SHIFT (8U)
+#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
+#define SDHC_PROCTL_SABGREQ_SHIFT (16U)
+#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK (0x20000U)
+#define SDHC_PROCTL_CREQ_SHIFT (17U)
+#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK (0x40000U)
+#define SDHC_PROCTL_RWCTL_SHIFT (18U)
+#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK (0x80000U)
+#define SDHC_PROCTL_IABG_SHIFT (19U)
+#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK (0x1000000U)
+#define SDHC_PROCTL_WECINT_SHIFT (24U)
+#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK (0x2000000U)
+#define SDHC_PROCTL_WECINS_SHIFT (25U)
+#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK (0x4000000U)
+#define SDHC_PROCTL_WECRM_SHIFT (26U)
+#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
+
+/*! @name SYSCTL - System Control register */
+#define SDHC_SYSCTL_IPGEN_MASK (0x1U)
+#define SDHC_SYSCTL_IPGEN_SHIFT (0U)
+#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK (0x2U)
+#define SDHC_SYSCTL_HCKEN_SHIFT (1U)
+#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK (0x4U)
+#define SDHC_SYSCTL_PEREN_SHIFT (2U)
+#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
+#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
+#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK (0xF0U)
+#define SDHC_SYSCTL_DVS_SHIFT (4U)
+#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
+#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
+#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
+#define SDHC_SYSCTL_DTOCV_SHIFT (16U)
+#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
+#define SDHC_SYSCTL_RSTA_SHIFT (24U)
+#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
+#define SDHC_SYSCTL_RSTC_SHIFT (25U)
+#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
+#define SDHC_SYSCTL_RSTD_SHIFT (26U)
+#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK (0x8000000U)
+#define SDHC_SYSCTL_INITA_SHIFT (27U)
+#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
+
+/*! @name IRQSTAT - Interrupt Status register */
+#define SDHC_IRQSTAT_CC_MASK (0x1U)
+#define SDHC_IRQSTAT_CC_SHIFT (0U)
+#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK (0x2U)
+#define SDHC_IRQSTAT_TC_SHIFT (1U)
+#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK (0x4U)
+#define SDHC_IRQSTAT_BGE_SHIFT (2U)
+#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK (0x8U)
+#define SDHC_IRQSTAT_DINT_SHIFT (3U)
+#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK (0x10U)
+#define SDHC_IRQSTAT_BWR_SHIFT (4U)
+#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK (0x20U)
+#define SDHC_IRQSTAT_BRR_SHIFT (5U)
+#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK (0x40U)
+#define SDHC_IRQSTAT_CINS_SHIFT (6U)
+#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK (0x80U)
+#define SDHC_IRQSTAT_CRM_SHIFT (7U)
+#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK (0x100U)
+#define SDHC_IRQSTAT_CINT_SHIFT (8U)
+#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
+#define SDHC_IRQSTAT_CTOE_SHIFT (16U)
+#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK (0x20000U)
+#define SDHC_IRQSTAT_CCE_SHIFT (17U)
+#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
+#define SDHC_IRQSTAT_CEBE_SHIFT (18U)
+#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK (0x80000U)
+#define SDHC_IRQSTAT_CIE_SHIFT (19U)
+#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
+#define SDHC_IRQSTAT_DTOE_SHIFT (20U)
+#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK (0x200000U)
+#define SDHC_IRQSTAT_DCE_SHIFT (21U)
+#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
+#define SDHC_IRQSTAT_DEBE_SHIFT (22U)
+#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
+#define SDHC_IRQSTAT_AC12E_SHIFT (24U)
+#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
+#define SDHC_IRQSTAT_DMAE_SHIFT (28U)
+#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
+
+/*! @name IRQSTATEN - Interrupt Status Enable register */
+#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
+#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
+#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
+#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
+#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
+#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
+#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
+#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
+#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
+#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
+#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
+#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
+#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
+#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
+#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
+#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
+#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
+#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
+#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
+#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
+#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
+#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
+#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
+#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
+#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
+#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
+
+/*! @name IRQSIGEN - Interrupt Signal Enable register */
+#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
+#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
+#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
+#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
+#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
+#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
+#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
+#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
+#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
+#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
+#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
+#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
+#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
+#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
+#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
+#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
+#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
+#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
+#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
+#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
+#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
+
+/*! @name AC12ERR - Auto CMD12 Error Status Register */
+#define SDHC_AC12ERR_AC12NE_MASK (0x1U)
+#define SDHC_AC12ERR_AC12NE_SHIFT (0U)
+#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
+#define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
+#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
+#define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
+#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK (0x8U)
+#define SDHC_AC12ERR_AC12CE_SHIFT (3U)
+#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK (0x10U)
+#define SDHC_AC12ERR_AC12IE_SHIFT (4U)
+#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
+#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
+
+/*! @name HTCAPBLT - Host Controller Capabilities */
+#define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
+#define SDHC_HTCAPBLT_MBL_SHIFT (16U)
+#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
+#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
+#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
+#define SDHC_HTCAPBLT_HSS_SHIFT (21U)
+#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
+#define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
+#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
+#define SDHC_HTCAPBLT_SRS_SHIFT (23U)
+#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
+#define SDHC_HTCAPBLT_VS33_SHIFT (24U)
+#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
+
+/*! @name WML - Watermark Level Register */
+#define SDHC_WML_RDWML_MASK (0xFFU)
+#define SDHC_WML_RDWML_SHIFT (0U)
+#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK (0xFF0000U)
+#define SDHC_WML_WRWML_SHIFT (16U)
+#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
+
+/*! @name FEVT - Force Event register */
+#define SDHC_FEVT_AC12NE_MASK (0x1U)
+#define SDHC_FEVT_AC12NE_SHIFT (0U)
+#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK (0x2U)
+#define SDHC_FEVT_AC12TOE_SHIFT (1U)
+#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK (0x4U)
+#define SDHC_FEVT_AC12CE_SHIFT (2U)
+#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK (0x8U)
+#define SDHC_FEVT_AC12EBE_SHIFT (3U)
+#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK (0x10U)
+#define SDHC_FEVT_AC12IE_SHIFT (4U)
+#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
+#define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
+#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK (0x10000U)
+#define SDHC_FEVT_CTOE_SHIFT (16U)
+#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK (0x20000U)
+#define SDHC_FEVT_CCE_SHIFT (17U)
+#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK (0x40000U)
+#define SDHC_FEVT_CEBE_SHIFT (18U)
+#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK (0x80000U)
+#define SDHC_FEVT_CIE_SHIFT (19U)
+#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK (0x100000U)
+#define SDHC_FEVT_DTOE_SHIFT (20U)
+#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK (0x200000U)
+#define SDHC_FEVT_DCE_SHIFT (21U)
+#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK (0x400000U)
+#define SDHC_FEVT_DEBE_SHIFT (22U)
+#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK (0x1000000U)
+#define SDHC_FEVT_AC12E_SHIFT (24U)
+#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK (0x10000000U)
+#define SDHC_FEVT_DMAE_SHIFT (28U)
+#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK (0x80000000U)
+#define SDHC_FEVT_CINT_SHIFT (31U)
+#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
+
+/*! @name ADMAES - ADMA Error Status register */
+#define SDHC_ADMAES_ADMAES_MASK (0x3U)
+#define SDHC_ADMAES_ADMAES_SHIFT (0U)
+#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK (0x4U)
+#define SDHC_ADMAES_ADMALME_SHIFT (2U)
+#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK (0x8U)
+#define SDHC_ADMAES_ADMADCE_SHIFT (3U)
+#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
+
+/*! @name ADSADDR - ADMA System Addressregister */
+#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
+#define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
+#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
+
+/*! @name VENDOR - Vendor Specific register */
+#define SDHC_VENDOR_EXTDMAEN_MASK (0x1U)
+#define SDHC_VENDOR_EXTDMAEN_SHIFT (0U)
+#define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
+#define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
+#define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
+#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
+#define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
+#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
+
+/*! @name MMCBOOT - MMC Boot register */
+#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
+#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
+#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
+#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
+#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
+#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
+#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
+#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
+#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+
+/*! @name HOSTVER - Host Controller Version */
+#define SDHC_HOSTVER_SVN_MASK (0xFFU)
+#define SDHC_HOSTVER_SVN_SHIFT (0U)
+#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK (0xFF00U)
+#define SDHC_HOSTVER_VVN_SHIFT (8U)
+#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
+
/*!
* @}
@@ -13110,58 +8602,12 @@ typedef struct {
#define SDHC_BASE (0x400B1000u)
/** Peripheral SDHC base pointer */
#define SDHC ((SDHC_Type *)SDHC_BASE)
-#define SDHC_BASE_PTR (SDHC)
/** Array initializer of SDHC peripheral base addresses */
-#define SDHC_BASE_ADDRS { SDHC_BASE }
-/** Array initializer of SDHC peripheral base pointers */
-#define SDHC_BASE_PTRS { SDHC }
-/** Interrupt vectors for the SDHC peripheral type */
-#define SDHC_IRQS { SDHC_IRQn }
-
-/* ----------------------------------------------------------------------------
- -- SDHC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
- * @{
- */
-
-
-/* SDHC - Register instance definitions */
-/* SDHC */
-#define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
-#define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
-#define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
-#define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
-#define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
-#define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
-#define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
-#define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
-#define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
-#define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
-#define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
-#define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
-#define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
-#define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
-#define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
-#define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
-#define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
-#define SDHC_WML SDHC_WML_REG(SDHC)
-#define SDHC_FEVT SDHC_FEVT_REG(SDHC)
-#define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
-#define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
-#define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
-#define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
-#define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
-
-/* SDHC - Register array accessors */
-#define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
-
-/*!
- * @}
- */ /* end of group SDHC_Register_Accessor_Macros */
-
+#define SDHC_BASE_ADDRS { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS { SDHC_IRQn }
/*!
* @}
@@ -13205,46 +8651,7 @@ typedef struct {
__I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
__I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
__I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
-} SIM_Type, *SIM_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register accessors */
-#define SIM_SOPT1_REG(base) ((base)->SOPT1)
-#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
-#define SIM_SOPT2_REG(base) ((base)->SOPT2)
-#define SIM_SOPT4_REG(base) ((base)->SOPT4)
-#define SIM_SOPT5_REG(base) ((base)->SOPT5)
-#define SIM_SOPT7_REG(base) ((base)->SOPT7)
-#define SIM_SDID_REG(base) ((base)->SDID)
-#define SIM_SCGC1_REG(base) ((base)->SCGC1)
-#define SIM_SCGC2_REG(base) ((base)->SCGC2)
-#define SIM_SCGC3_REG(base) ((base)->SCGC3)
-#define SIM_SCGC4_REG(base) ((base)->SCGC4)
-#define SIM_SCGC5_REG(base) ((base)->SCGC5)
-#define SIM_SCGC6_REG(base) ((base)->SCGC6)
-#define SIM_SCGC7_REG(base) ((base)->SCGC7)
-#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
-#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
-#define SIM_FCFG1_REG(base) ((base)->FCFG1)
-#define SIM_FCFG2_REG(base) ((base)->FCFG2)
-#define SIM_UIDH_REG(base) ((base)->UIDH)
-#define SIM_UIDMH_REG(base) ((base)->UIDMH)
-#define SIM_UIDML_REG(base) ((base)->UIDML)
-#define SIM_UIDL_REG(base) ((base)->UIDL)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
+} SIM_Type;
/* ----------------------------------------------------------------------------
-- SIM Register Masks
@@ -13255,476 +8662,386 @@ typedef struct {
* @{
*/
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
-#define SIM_SOPT1_RAMSIZE_SHIFT 12
-#define SIM_SOPT1_RAMSIZE_WIDTH 4
-#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL_WIDTH 2
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT 29
-#define SIM_SOPT1_USBVSTBY_WIDTH 1
-#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBVSTBY_SHIFT))&SIM_SOPT1_USBVSTBY_MASK)
-#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT 30
-#define SIM_SOPT1_USBSSTBY_WIDTH 1
-#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBSSTBY_SHIFT))&SIM_SOPT1_USBSSTBY_MASK)
-#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT 31
-#define SIM_SOPT1_USBREGEN_WIDTH 1
-#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_USBREGEN_SHIFT))&SIM_SOPT1_USBREGEN_MASK)
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT 24
-#define SIM_SOPT1CFG_URWE_WIDTH 1
-#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_URWE_SHIFT))&SIM_SOPT1CFG_URWE_MASK)
-#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT 25
-#define SIM_SOPT1CFG_UVSWE_WIDTH 1
-#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_UVSWE_SHIFT))&SIM_SOPT1CFG_UVSWE_MASK)
-#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT 26
-#define SIM_SOPT1CFG_USSWE_WIDTH 1
-#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1CFG_USSWE_SHIFT))&SIM_SOPT1CFG_USSWE_MASK)
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_RTCCLKOUTSEL_WIDTH 1
-#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL_WIDTH 3
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_FBSL_MASK 0x300u
-#define SIM_SOPT2_FBSL_SHIFT 8
-#define SIM_SOPT2_FBSL_WIDTH 2
-#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
-#define SIM_SOPT2_PTD7PAD_MASK 0x800u
-#define SIM_SOPT2_PTD7PAD_SHIFT 11
-#define SIM_SOPT2_PTD7PAD_WIDTH 1
-#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PTD7PAD_SHIFT))&SIM_SOPT2_PTD7PAD_MASK)
-#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
-#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
-#define SIM_SOPT2_TRACECLKSEL_WIDTH 1
-#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_PLLFLLSEL_WIDTH 1
-#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-#define SIM_SOPT2_USBSRC_WIDTH 1
-#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
-#define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
-#define SIM_SOPT2_SDHCSRC_SHIFT 28
-#define SIM_SOPT2_SDHCSRC_WIDTH 2
-#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
-#define SIM_SOPT4_FTM0FLT0_SHIFT 0
-#define SIM_SOPT4_FTM0FLT0_WIDTH 1
-#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT0_SHIFT))&SIM_SOPT4_FTM0FLT0_MASK)
-#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
-#define SIM_SOPT4_FTM0FLT1_SHIFT 1
-#define SIM_SOPT4_FTM0FLT1_WIDTH 1
-#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT1_SHIFT))&SIM_SOPT4_FTM0FLT1_MASK)
-#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
-#define SIM_SOPT4_FTM0FLT2_SHIFT 2
-#define SIM_SOPT4_FTM0FLT2_WIDTH 1
-#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0FLT2_SHIFT))&SIM_SOPT4_FTM0FLT2_MASK)
-#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
-#define SIM_SOPT4_FTM1FLT0_SHIFT 4
-#define SIM_SOPT4_FTM1FLT0_WIDTH 1
-#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1FLT0_SHIFT))&SIM_SOPT4_FTM1FLT0_MASK)
-#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
-#define SIM_SOPT4_FTM2FLT0_SHIFT 8
-#define SIM_SOPT4_FTM2FLT0_WIDTH 1
-#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2FLT0_SHIFT))&SIM_SOPT4_FTM2FLT0_MASK)
-#define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
-#define SIM_SOPT4_FTM3FLT0_SHIFT 12
-#define SIM_SOPT4_FTM3FLT0_WIDTH 1
-#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3FLT0_SHIFT))&SIM_SOPT4_FTM3FLT0_MASK)
-#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
-#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_FTM1CH0SRC_WIDTH 2
-#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
-#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
-#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
-#define SIM_SOPT4_FTM2CH0SRC_WIDTH 2
-#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
-#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_FTM0CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0CLKSEL_SHIFT))&SIM_SOPT4_FTM0CLKSEL_MASK)
-#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_FTM1CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CLKSEL_SHIFT))&SIM_SOPT4_FTM1CLKSEL_MASK)
-#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
-#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
-#define SIM_SOPT4_FTM2CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CLKSEL_SHIFT))&SIM_SOPT4_FTM2CLKSEL_MASK)
-#define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
-#define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
-#define SIM_SOPT4_FTM3CLKSEL_WIDTH 1
-#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3CLKSEL_SHIFT))&SIM_SOPT4_FTM3CLKSEL_MASK)
-#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
-#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
-#define SIM_SOPT4_FTM0TRG0SRC_WIDTH 1
-#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG0SRC_SHIFT))&SIM_SOPT4_FTM0TRG0SRC_MASK)
-#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
-#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
-#define SIM_SOPT4_FTM0TRG1SRC_WIDTH 1
-#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM0TRG1SRC_SHIFT))&SIM_SOPT4_FTM0TRG1SRC_MASK)
-#define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
-#define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
-#define SIM_SOPT4_FTM3TRG0SRC_WIDTH 1
-#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG0SRC_SHIFT))&SIM_SOPT4_FTM3TRG0SRC_MASK)
-#define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
-#define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
-#define SIM_SOPT4_FTM3TRG1SRC_WIDTH 1
-#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM3TRG1SRC_SHIFT))&SIM_SOPT4_FTM3TRG1SRC_MASK)
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0TXSRC_WIDTH 2
-#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART0RXSRC_WIDTH 2
-#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
-#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1TXSRC_WIDTH 2
-#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART1RXSRC_WIDTH 2
-#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL_WIDTH 4
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0PRETRGSEL_WIDTH 1
-#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-#define SIM_SOPT7_ADC0ALTTRGEN_WIDTH 1
-#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
-#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
-#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
-#define SIM_SOPT7_ADC1TRGSEL_WIDTH 4
-#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
-#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
-#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
-#define SIM_SOPT7_ADC1PRETRGSEL_WIDTH 1
-#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1PRETRGSEL_SHIFT))&SIM_SOPT7_ADC1PRETRGSEL_MASK)
-#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
-#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
-#define SIM_SOPT7_ADC1ALTTRGEN_WIDTH 1
-#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1ALTTRGEN_SHIFT))&SIM_SOPT7_ADC1ALTTRGEN_MASK)
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID_WIDTH 4
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_FAMID_MASK 0x70u
-#define SIM_SDID_FAMID_SHIFT 4
-#define SIM_SDID_FAMID_WIDTH 3
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-#define SIM_SDID_DIEID_MASK 0xF80u
-#define SIM_SDID_DIEID_SHIFT 7
-#define SIM_SDID_DIEID_WIDTH 5
-#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID_WIDTH 4
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-/* SCGC1 Bit Fields */
-#define SIM_SCGC1_I2C2_MASK 0x40u
-#define SIM_SCGC1_I2C2_SHIFT 6
-#define SIM_SCGC1_I2C2_WIDTH 1
-#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_I2C2_SHIFT))&SIM_SCGC1_I2C2_MASK)
-#define SIM_SCGC1_UART4_MASK 0x400u
-#define SIM_SCGC1_UART4_SHIFT 10
-#define SIM_SCGC1_UART4_WIDTH 1
-#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART4_SHIFT))&SIM_SCGC1_UART4_MASK)
-#define SIM_SCGC1_UART5_MASK 0x800u
-#define SIM_SCGC1_UART5_SHIFT 11
-#define SIM_SCGC1_UART5_WIDTH 1
-#define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC1_UART5_SHIFT))&SIM_SCGC1_UART5_MASK)
-/* SCGC2 Bit Fields */
-#define SIM_SCGC2_DAC0_MASK 0x1000u
-#define SIM_SCGC2_DAC0_SHIFT 12
-#define SIM_SCGC2_DAC0_WIDTH 1
-#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC0_SHIFT))&SIM_SCGC2_DAC0_MASK)
-#define SIM_SCGC2_DAC1_MASK 0x2000u
-#define SIM_SCGC2_DAC1_SHIFT 13
-#define SIM_SCGC2_DAC1_WIDTH 1
-#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC2_DAC1_SHIFT))&SIM_SCGC2_DAC1_MASK)
-/* SCGC3 Bit Fields */
-#define SIM_SCGC3_SPI2_MASK 0x1000u
-#define SIM_SCGC3_SPI2_SHIFT 12
-#define SIM_SCGC3_SPI2_WIDTH 1
-#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SPI2_SHIFT))&SIM_SCGC3_SPI2_MASK)
-#define SIM_SCGC3_SDHC_MASK 0x20000u
-#define SIM_SCGC3_SDHC_SHIFT 17
-#define SIM_SCGC3_SDHC_WIDTH 1
-#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_SDHC_SHIFT))&SIM_SCGC3_SDHC_MASK)
-#define SIM_SCGC3_FTM2_MASK 0x1000000u
-#define SIM_SCGC3_FTM2_SHIFT 24
-#define SIM_SCGC3_FTM2_WIDTH 1
-#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM2_SHIFT))&SIM_SCGC3_FTM2_MASK)
-#define SIM_SCGC3_FTM3_MASK 0x2000000u
-#define SIM_SCGC3_FTM3_SHIFT 25
-#define SIM_SCGC3_FTM3_WIDTH 1
-#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_FTM3_SHIFT))&SIM_SCGC3_FTM3_MASK)
-#define SIM_SCGC3_ADC1_MASK 0x8000000u
-#define SIM_SCGC3_ADC1_SHIFT 27
-#define SIM_SCGC3_ADC1_WIDTH 1
-#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC3_ADC1_SHIFT))&SIM_SCGC3_ADC1_MASK)
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_EWM_MASK 0x2u
-#define SIM_SCGC4_EWM_SHIFT 1
-#define SIM_SCGC4_EWM_WIDTH 1
-#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
-#define SIM_SCGC4_CMT_MASK 0x4u
-#define SIM_SCGC4_CMT_SHIFT 2
-#define SIM_SCGC4_CMT_WIDTH 1
-#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMT_SHIFT))&SIM_SCGC4_CMT_MASK)
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_I2C0_WIDTH 1
-#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
-#define SIM_SCGC4_I2C1_MASK 0x80u
-#define SIM_SCGC4_I2C1_SHIFT 7
-#define SIM_SCGC4_I2C1_WIDTH 1
-#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C1_SHIFT))&SIM_SCGC4_I2C1_MASK)
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART0_WIDTH 1
-#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART1_WIDTH 1
-#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_UART2_WIDTH 1
-#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
-#define SIM_SCGC4_UART3_MASK 0x2000u
-#define SIM_SCGC4_UART3_SHIFT 13
-#define SIM_SCGC4_UART3_WIDTH 1
-#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART3_SHIFT))&SIM_SCGC4_UART3_MASK)
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_USBOTG_WIDTH 1
-#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_CMP_WIDTH 1
-#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
-#define SIM_SCGC4_VREF_MASK 0x100000u
-#define SIM_SCGC4_VREF_SHIFT 20
-#define SIM_SCGC4_VREF_WIDTH 1
-#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_VREF_SHIFT))&SIM_SCGC4_VREF_MASK)
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTMR_MASK 0x1u
-#define SIM_SCGC5_LPTMR_SHIFT 0
-#define SIM_SCGC5_LPTMR_WIDTH 1
-#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTA_WIDTH 1
-#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTB_WIDTH 1
-#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTC_WIDTH 1
-#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTD_WIDTH 1
-#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-#define SIM_SCGC5_PORTE_WIDTH 1
-#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTF_MASK 0x1u
-#define SIM_SCGC6_FTF_SHIFT 0
-#define SIM_SCGC6_FTF_WIDTH 1
-#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_DMAMUX_WIDTH 1
-#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
-#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
-#define SIM_SCGC6_FLEXCAN0_SHIFT 4
-#define SIM_SCGC6_FLEXCAN0_WIDTH 1
-#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
-#define SIM_SCGC6_SPI0_MASK 0x1000u
-#define SIM_SCGC6_SPI0_SHIFT 12
-#define SIM_SCGC6_SPI0_WIDTH 1
-#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
-#define SIM_SCGC6_SPI1_MASK 0x2000u
-#define SIM_SCGC6_SPI1_SHIFT 13
-#define SIM_SCGC6_SPI1_WIDTH 1
-#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
-#define SIM_SCGC6_I2S_MASK 0x8000u
-#define SIM_SCGC6_I2S_SHIFT 15
-#define SIM_SCGC6_I2S_WIDTH 1
-#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S_SHIFT))&SIM_SCGC6_I2S_MASK)
-#define SIM_SCGC6_CRC_MASK 0x40000u
-#define SIM_SCGC6_CRC_SHIFT 18
-#define SIM_SCGC6_CRC_WIDTH 1
-#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
-#define SIM_SCGC6_USBDCD_MASK 0x200000u
-#define SIM_SCGC6_USBDCD_SHIFT 21
-#define SIM_SCGC6_USBDCD_WIDTH 1
-#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_USBDCD_SHIFT))&SIM_SCGC6_USBDCD_MASK)
-#define SIM_SCGC6_PDB_MASK 0x400000u
-#define SIM_SCGC6_PDB_SHIFT 22
-#define SIM_SCGC6_PDB_WIDTH 1
-#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_PIT_WIDTH 1
-#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
-#define SIM_SCGC6_FTM0_MASK 0x1000000u
-#define SIM_SCGC6_FTM0_SHIFT 24
-#define SIM_SCGC6_FTM0_WIDTH 1
-#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM0_SHIFT))&SIM_SCGC6_FTM0_MASK)
-#define SIM_SCGC6_FTM1_MASK 0x2000000u
-#define SIM_SCGC6_FTM1_SHIFT 25
-#define SIM_SCGC6_FTM1_WIDTH 1
-#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM1_SHIFT))&SIM_SCGC6_FTM1_MASK)
-#define SIM_SCGC6_FTM2_MASK 0x4000000u
-#define SIM_SCGC6_FTM2_SHIFT 26
-#define SIM_SCGC6_FTM2_WIDTH 1
-#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTM2_SHIFT))&SIM_SCGC6_FTM2_MASK)
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_ADC0_WIDTH 1
-#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-#define SIM_SCGC6_RTC_WIDTH 1
-#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
-#define SIM_SCGC6_DAC0_MASK 0x80000000u
-#define SIM_SCGC6_DAC0_SHIFT 31
-#define SIM_SCGC6_DAC0_WIDTH 1
-#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_FLEXBUS_MASK 0x1u
-#define SIM_SCGC7_FLEXBUS_SHIFT 0
-#define SIM_SCGC7_FLEXBUS_WIDTH 1
-#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_FLEXBUS_SHIFT))&SIM_SCGC7_FLEXBUS_MASK)
-#define SIM_SCGC7_DMA_MASK 0x2u
-#define SIM_SCGC7_DMA_SHIFT 1
-#define SIM_SCGC7_DMA_WIDTH 1
-#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
-#define SIM_SCGC7_MPU_MASK 0x4u
-#define SIM_SCGC7_MPU_SHIFT 2
-#define SIM_SCGC7_MPU_WIDTH 1
-#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_MPU_SHIFT))&SIM_SCGC7_MPU_MASK)
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
-#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
-#define SIM_CLKDIV1_OUTDIV3_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
-#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
-#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
-#define SIM_CLKDIV1_OUTDIV2_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1_WIDTH 4
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* CLKDIV2 Bit Fields */
-#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
-#define SIM_CLKDIV2_USBFRAC_SHIFT 0
-#define SIM_CLKDIV2_USBFRAC_WIDTH 1
-#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
-#define SIM_CLKDIV2_USBDIV_MASK 0xEu
-#define SIM_CLKDIV2_USBDIV_SHIFT 1
-#define SIM_CLKDIV2_USBDIV_WIDTH 3
-#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDIS_WIDTH 1
-#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_FLASHDOZE_WIDTH 1
-#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
-#define SIM_FCFG1_DEPART_MASK 0xF00u
-#define SIM_FCFG1_DEPART_SHIFT 8
-#define SIM_FCFG1_DEPART_WIDTH 4
-#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
-#define SIM_FCFG1_EESIZE_MASK 0xF0000u
-#define SIM_FCFG1_EESIZE_SHIFT 16
-#define SIM_FCFG1_EESIZE_WIDTH 4
-#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE_WIDTH 4
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
-#define SIM_FCFG1_NVMSIZE_SHIFT 28
-#define SIM_FCFG1_NVMSIZE_WIDTH 4
-#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
-#define SIM_FCFG2_MAXADDR1_SHIFT 16
-#define SIM_FCFG2_MAXADDR1_WIDTH 7
-#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
-#define SIM_FCFG2_PFLSH_MASK 0x800000u
-#define SIM_FCFG2_PFLSH_SHIFT 23
-#define SIM_FCFG2_PFLSH_WIDTH 1
-#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_PFLSH_SHIFT))&SIM_FCFG2_PFLSH_MASK)
-#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR0_SHIFT 24
-#define SIM_FCFG2_MAXADDR0_WIDTH 7
-#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
-#define SIM_FCFG2_SWAPPFLSH_MASK 0x80000000u
-#define SIM_FCFG2_SWAPPFLSH_SHIFT 31
-#define SIM_FCFG2_SWAPPFLSH_WIDTH 1
-#define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_SWAPPFLSH_SHIFT))&SIM_FCFG2_SWAPPFLSH_MASK)
-/* UIDH Bit Fields */
-#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDH_UID_SHIFT 0
-#define SIM_UIDH_UID_WIDTH 32
-#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID_WIDTH 32
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID_WIDTH 32
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID_WIDTH 32
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
+#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
+#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT (31U)
+#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT (24U)
+#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
+#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
+#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK (0x300U)
+#define SIM_SOPT2_FBSL_SHIFT (8U)
+#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK (0x800U)
+#define SIM_SOPT2_PTD7PAD_SHIFT (11U)
+#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
+#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
+#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK (0x10000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT (18U)
+#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
+#define SIM_SOPT2_SDHCSRC_SHIFT (28U)
+#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
+#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
+#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
+#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
+#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
+#define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
+#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
+#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
+#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
+#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
+#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
+#define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
+#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
+#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
+#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
+#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
+#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
+#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
+#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
+#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
+#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
+#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
+#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK (0xFU)
+#define SIM_SDID_PINID_SHIFT (0U)
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK (0x70U)
+#define SIM_SDID_FAMID_SHIFT (4U)
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK (0xF80U)
+#define SIM_SDID_DIEID_SHIFT (7U)
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK (0xF000U)
+#define SIM_SDID_REVID_SHIFT (12U)
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+
+/*! @name SCGC1 - System Clock Gating Control Register 1 */
+#define SIM_SCGC1_I2C2_MASK (0x40U)
+#define SIM_SCGC1_I2C2_SHIFT (6U)
+#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_UART4_MASK (0x400U)
+#define SIM_SCGC1_UART4_SHIFT (10U)
+#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART5_MASK (0x800U)
+#define SIM_SCGC1_UART5_SHIFT (11U)
+#define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
+
+/*! @name SCGC2 - System Clock Gating Control Register 2 */
+#define SIM_SCGC2_DAC0_MASK (0x1000U)
+#define SIM_SCGC2_DAC0_SHIFT (12U)
+#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK (0x2000U)
+#define SIM_SCGC2_DAC1_SHIFT (13U)
+#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
+
+/*! @name SCGC3 - System Clock Gating Control Register 3 */
+#define SIM_SCGC3_SPI2_MASK (0x1000U)
+#define SIM_SCGC3_SPI2_SHIFT (12U)
+#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK (0x20000U)
+#define SIM_SCGC3_SDHC_SHIFT (17U)
+#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK (0x1000000U)
+#define SIM_SCGC3_FTM2_SHIFT (24U)
+#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK (0x2000000U)
+#define SIM_SCGC3_FTM3_SHIFT (25U)
+#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK (0x8000000U)
+#define SIM_SCGC3_ADC1_SHIFT (27U)
+#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM_MASK (0x2U)
+#define SIM_SCGC4_EWM_SHIFT (1U)
+#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK (0x4U)
+#define SIM_SCGC4_CMT_SHIFT (2U)
+#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT (6U)
+#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT (7U)
+#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK (0x400U)
+#define SIM_SCGC4_UART0_SHIFT (10U)
+#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK (0x800U)
+#define SIM_SCGC4_UART1_SHIFT (11U)
+#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT (12U)
+#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK (0x2000U)
+#define SIM_SCGC4_UART3_SHIFT (13U)
+#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT (18U)
+#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_CMP_MASK (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT (19U)
+#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT (20U)
+#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR_MASK (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT (0U)
+#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_PORTA_MASK (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT (9U)
+#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTB_MASK (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT (10U)
+#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTC_MASK (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT (11U)
+#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTD_MASK (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT (12U)
+#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTE_MASK (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT (13U)
+#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTF_MASK (0x1U)
+#define SIM_SCGC6_FTF_SHIFT (0U)
+#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT (1U)
+#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
+#define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
+#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_SPI0_MASK (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT (12U)
+#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK (0x2000U)
+#define SIM_SCGC6_SPI1_SHIFT (13U)
+#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT (15U)
+#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT (18U)
+#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK (0x200000U)
+#define SIM_SCGC6_USBDCD_SHIFT (21U)
+#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK (0x400000U)
+#define SIM_SCGC6_PDB_SHIFT (22U)
+#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT (23U)
+#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK (0x1000000U)
+#define SIM_SCGC6_FTM0_SHIFT (24U)
+#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK (0x2000000U)
+#define SIM_SCGC6_FTM1_SHIFT (25U)
+#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK (0x4000000U)
+#define SIM_SCGC6_FTM2_SHIFT (26U)
+#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT (27U)
+#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT (29U)
+#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT (31U)
+#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_FLEXBUS_MASK (0x1U)
+#define SIM_SCGC7_FLEXBUS_SHIFT (0U)
+#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK (0x2U)
+#define SIM_SCGC7_DMA_SHIFT (1U)
+#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK (0x4U)
+#define SIM_SCGC7_MPU_SHIFT (2U)
+#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
+#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
+#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
+#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
+#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
+#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK (0xF00U)
+#define SIM_FCFG1_DEPART_SHIFT (8U)
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
+#define SIM_FCFG1_EESIZE_SHIFT (16U)
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT (24U)
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
+#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK (0x800000U)
+#define SIM_FCFG2_PFLSH_SHIFT (23U)
+#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+#define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
+#define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
+#define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
+
+/*! @name UIDH - Unique Identification Register High */
+#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT (0U)
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT (0U)
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT (0U)
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT (0U)
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
/*!
* @}
@@ -13736,52 +9053,11 @@ typedef struct {
#define SIM_BASE (0x40047000u)
/** Peripheral SIM base pointer */
#define SIM ((SIM_Type *)SIM_BASE)
-#define SIM_BASE_PTR (SIM)
/** Array initializer of SIM peripheral base addresses */
#define SIM_BASE_ADDRS { SIM_BASE }
/** Array initializer of SIM peripheral base pointers */
#define SIM_BASE_PTRS { SIM }
-/* ----------------------------------------------------------------------------
- -- SIM - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
- * @{
- */
-
-
-/* SIM - Register instance definitions */
-/* SIM */
-#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
-#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
-#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
-#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
-#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
-#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
-#define SIM_SDID SIM_SDID_REG(SIM)
-#define SIM_SCGC1 SIM_SCGC1_REG(SIM)
-#define SIM_SCGC2 SIM_SCGC2_REG(SIM)
-#define SIM_SCGC3 SIM_SCGC3_REG(SIM)
-#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
-#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
-#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
-#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
-#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
-#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
-#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
-#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
-#define SIM_UIDH SIM_UIDH_REG(SIM)
-#define SIM_UIDMH SIM_UIDMH_REG(SIM)
-#define SIM_UIDML SIM_UIDML_REG(SIM)
-#define SIM_UIDL SIM_UIDL_REG(SIM)
-
-/*!
- * @}
- */ /* end of group SIM_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SIM_Peripheral_Access_Layer */
@@ -13802,28 +9078,7 @@ typedef struct {
__IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
__IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
__I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type, *SMC_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register accessors */
-#define SMC_PMPROT_REG(base) ((base)->PMPROT)
-#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
-#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
-#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
+} SMC_Type;
/* ----------------------------------------------------------------------------
-- SMC Register Masks
@@ -13834,54 +9089,47 @@ typedef struct {
* @{
*/
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_AVLLS_WIDTH 1
-#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_ALLS_WIDTH 1
-#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-#define SMC_PMPROT_AVLP_WIDTH 1
-#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM_WIDTH 3
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_STOPA_WIDTH 1
-#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM_WIDTH 2
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-#define SMC_PMCTRL_LPWUI_MASK 0x80u
-#define SMC_PMCTRL_LPWUI_SHIFT 7
-#define SMC_PMCTRL_LPWUI_WIDTH 1
-#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_LPWUI_SHIFT))&SMC_PMCTRL_LPWUI_MASK)
-/* VLLSCTRL Bit Fields */
-#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
-#define SMC_VLLSCTRL_VLLSM_SHIFT 0
-#define SMC_VLLSCTRL_VLLSM_WIDTH 3
-#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
-#define SMC_VLLSCTRL_RAM2PO_MASK 0x10u
-#define SMC_VLLSCTRL_RAM2PO_SHIFT 4
-#define SMC_VLLSCTRL_RAM2PO_WIDTH 1
-#define SMC_VLLSCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_RAM2PO_SHIFT))&SMC_VLLSCTRL_RAM2PO_MASK)
-#define SMC_VLLSCTRL_PORPO_MASK 0x20u
-#define SMC_VLLSCTRL_PORPO_SHIFT 5
-#define SMC_VLLSCTRL_PORPO_WIDTH 1
-#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_PORPO_SHIFT))&SMC_VLLSCTRL_PORPO_MASK)
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT_WIDTH 8
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT (1U)
+#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT (3U)
+#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT (5U)
+#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT (0U)
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT (3U)
+#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT (5U)
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK (0x80U)
+#define SMC_PMCTRL_LPWUI_SHIFT (7U)
+#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
+
+/*! @name VLLSCTRL - VLLS Control Register */
+#define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
+#define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_RAM2PO_MASK (0x10U)
+#define SMC_VLLSCTRL_RAM2PO_SHIFT (4U)
+#define SMC_VLLSCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_RAM2PO_SHIFT)) & SMC_VLLSCTRL_RAM2PO_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK (0x20U)
+#define SMC_VLLSCTRL_PORPO_SHIFT (5U)
+#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
/*!
* @}
@@ -13893,34 +9141,11 @@ typedef struct {
#define SMC_BASE (0x4007E000u)
/** Peripheral SMC base pointer */
#define SMC ((SMC_Type *)SMC_BASE)
-#define SMC_BASE_PTR (SMC)
/** Array initializer of SMC peripheral base addresses */
#define SMC_BASE_ADDRS { SMC_BASE }
/** Array initializer of SMC peripheral base pointers */
#define SMC_BASE_PTRS { SMC }
-/* ----------------------------------------------------------------------------
- -- SMC - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
- * @{
- */
-
-
-/* SMC - Register instance definitions */
-/* SMC */
-#define SMC_PMPROT SMC_PMPROT_REG(SMC)
-#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
-#define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
-#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
-
-/*!
- * @}
- */ /* end of group SMC_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group SMC_Peripheral_Access_Layer */
@@ -13961,43 +9186,7 @@ typedef struct {
__I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
__I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
__I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
-} SPI_Type, *SPI_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
- * @{
- */
-
-
-/* SPI - Register accessors */
-#define SPI_MCR_REG(base) ((base)->MCR)
-#define SPI_TCR_REG(base) ((base)->TCR)
-#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
-#define SPI_CTAR_COUNT 2
-#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
-#define SPI_CTAR_SLAVE_COUNT 1
-#define SPI_SR_REG(base) ((base)->SR)
-#define SPI_RSER_REG(base) ((base)->RSER)
-#define SPI_PUSHR_REG(base) ((base)->PUSHR)
-#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
-#define SPI_POPR_REG(base) ((base)->POPR)
-#define SPI_TXFR0_REG(base) ((base)->TXFR0)
-#define SPI_TXFR1_REG(base) ((base)->TXFR1)
-#define SPI_TXFR2_REG(base) ((base)->TXFR2)
-#define SPI_TXFR3_REG(base) ((base)->TXFR3)
-#define SPI_RXFR0_REG(base) ((base)->RXFR0)
-#define SPI_RXFR1_REG(base) ((base)->RXFR1)
-#define SPI_RXFR2_REG(base) ((base)->RXFR2)
-#define SPI_RXFR3_REG(base) ((base)->RXFR3)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
+} SPI_Type;
/* ----------------------------------------------------------------------------
-- SPI Register Masks
@@ -14008,311 +9197,262 @@ typedef struct {
* @{
*/
-/* MCR Bit Fields */
-#define SPI_MCR_HALT_MASK 0x1u
-#define SPI_MCR_HALT_SHIFT 0
-#define SPI_MCR_HALT_WIDTH 1
-#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
-#define SPI_MCR_SMPL_PT_MASK 0x300u
-#define SPI_MCR_SMPL_PT_SHIFT 8
-#define SPI_MCR_SMPL_PT_WIDTH 2
-#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK 0x400u
-#define SPI_MCR_CLR_RXF_SHIFT 10
-#define SPI_MCR_CLR_RXF_WIDTH 1
-#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
-#define SPI_MCR_CLR_TXF_MASK 0x800u
-#define SPI_MCR_CLR_TXF_SHIFT 11
-#define SPI_MCR_CLR_TXF_WIDTH 1
-#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
-#define SPI_MCR_DIS_RXF_MASK 0x1000u
-#define SPI_MCR_DIS_RXF_SHIFT 12
-#define SPI_MCR_DIS_RXF_WIDTH 1
-#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
-#define SPI_MCR_DIS_TXF_MASK 0x2000u
-#define SPI_MCR_DIS_TXF_SHIFT 13
-#define SPI_MCR_DIS_TXF_WIDTH 1
-#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
-#define SPI_MCR_MDIS_MASK 0x4000u
-#define SPI_MCR_MDIS_SHIFT 14
-#define SPI_MCR_MDIS_WIDTH 1
-#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
-#define SPI_MCR_DOZE_MASK 0x8000u
-#define SPI_MCR_DOZE_SHIFT 15
-#define SPI_MCR_DOZE_WIDTH 1
-#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
-#define SPI_MCR_PCSIS_MASK 0x3F0000u
-#define SPI_MCR_PCSIS_SHIFT 16
-#define SPI_MCR_PCSIS_WIDTH 6
-#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK 0x1000000u
-#define SPI_MCR_ROOE_SHIFT 24
-#define SPI_MCR_ROOE_WIDTH 1
-#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
-#define SPI_MCR_PCSSE_MASK 0x2000000u
-#define SPI_MCR_PCSSE_SHIFT 25
-#define SPI_MCR_PCSSE_WIDTH 1
-#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
-#define SPI_MCR_MTFE_MASK 0x4000000u
-#define SPI_MCR_MTFE_SHIFT 26
-#define SPI_MCR_MTFE_WIDTH 1
-#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
-#define SPI_MCR_FRZ_MASK 0x8000000u
-#define SPI_MCR_FRZ_SHIFT 27
-#define SPI_MCR_FRZ_WIDTH 1
-#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
-#define SPI_MCR_DCONF_MASK 0x30000000u
-#define SPI_MCR_DCONF_SHIFT 28
-#define SPI_MCR_DCONF_WIDTH 2
-#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
-#define SPI_MCR_CONT_SCKE_SHIFT 30
-#define SPI_MCR_CONT_SCKE_WIDTH 1
-#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
-#define SPI_MCR_MSTR_MASK 0x80000000u
-#define SPI_MCR_MSTR_SHIFT 31
-#define SPI_MCR_MSTR_WIDTH 1
-#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
-/* TCR Bit Fields */
-#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
-#define SPI_TCR_SPI_TCNT_SHIFT 16
-#define SPI_TCR_SPI_TCNT_WIDTH 16
-#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
-/* CTAR Bit Fields */
-#define SPI_CTAR_BR_MASK 0xFu
-#define SPI_CTAR_BR_SHIFT 0
-#define SPI_CTAR_BR_WIDTH 4
-#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK 0xF0u
-#define SPI_CTAR_DT_SHIFT 4
-#define SPI_CTAR_DT_WIDTH 4
-#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK 0xF00u
-#define SPI_CTAR_ASC_SHIFT 8
-#define SPI_CTAR_ASC_WIDTH 4
-#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK 0xF000u
-#define SPI_CTAR_CSSCK_SHIFT 12
-#define SPI_CTAR_CSSCK_WIDTH 4
-#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK 0x30000u
-#define SPI_CTAR_PBR_SHIFT 16
-#define SPI_CTAR_PBR_WIDTH 2
-#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK 0xC0000u
-#define SPI_CTAR_PDT_SHIFT 18
-#define SPI_CTAR_PDT_WIDTH 2
-#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK 0x300000u
-#define SPI_CTAR_PASC_SHIFT 20
-#define SPI_CTAR_PASC_WIDTH 2
-#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK 0xC00000u
-#define SPI_CTAR_PCSSCK_SHIFT 22
-#define SPI_CTAR_PCSSCK_WIDTH 2
-#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK 0x1000000u
-#define SPI_CTAR_LSBFE_SHIFT 24
-#define SPI_CTAR_LSBFE_WIDTH 1
-#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
-#define SPI_CTAR_CPHA_MASK 0x2000000u
-#define SPI_CTAR_CPHA_SHIFT 25
-#define SPI_CTAR_CPHA_WIDTH 1
-#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
-#define SPI_CTAR_CPOL_MASK 0x4000000u
-#define SPI_CTAR_CPOL_SHIFT 26
-#define SPI_CTAR_CPOL_WIDTH 1
-#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
-#define SPI_CTAR_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_FMSZ_SHIFT 27
-#define SPI_CTAR_FMSZ_WIDTH 4
-#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK 0x80000000u
-#define SPI_CTAR_DBR_SHIFT 31
-#define SPI_CTAR_DBR_WIDTH 1
-#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
-/* CTAR_SLAVE Bit Fields */
-#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
-#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
-#define SPI_CTAR_SLAVE_CPHA_WIDTH 1
-#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
-#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
-#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
-#define SPI_CTAR_SLAVE_CPOL_WIDTH 1
-#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
-#define SPI_CTAR_SLAVE_FMSZ_MASK 0x78000000u
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
-#define SPI_CTAR_SLAVE_FMSZ_WIDTH 4
-#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
-/* SR Bit Fields */
-#define SPI_SR_POPNXTPTR_MASK 0xFu
-#define SPI_SR_POPNXTPTR_SHIFT 0
-#define SPI_SR_POPNXTPTR_WIDTH 4
-#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK 0xF0u
-#define SPI_SR_RXCTR_SHIFT 4
-#define SPI_SR_RXCTR_WIDTH 4
-#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK 0xF00u
-#define SPI_SR_TXNXTPTR_SHIFT 8
-#define SPI_SR_TXNXTPTR_WIDTH 4
-#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK 0xF000u
-#define SPI_SR_TXCTR_SHIFT 12
-#define SPI_SR_TXCTR_WIDTH 4
-#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK 0x20000u
-#define SPI_SR_RFDF_SHIFT 17
-#define SPI_SR_RFDF_WIDTH 1
-#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
-#define SPI_SR_RFOF_MASK 0x80000u
-#define SPI_SR_RFOF_SHIFT 19
-#define SPI_SR_RFOF_WIDTH 1
-#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
-#define SPI_SR_TFFF_MASK 0x2000000u
-#define SPI_SR_TFFF_SHIFT 25
-#define SPI_SR_TFFF_WIDTH 1
-#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
-#define SPI_SR_TFUF_MASK 0x8000000u
-#define SPI_SR_TFUF_SHIFT 27
-#define SPI_SR_TFUF_WIDTH 1
-#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
-#define SPI_SR_EOQF_MASK 0x10000000u
-#define SPI_SR_EOQF_SHIFT 28
-#define SPI_SR_EOQF_WIDTH 1
-#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
-#define SPI_SR_TXRXS_MASK 0x40000000u
-#define SPI_SR_TXRXS_SHIFT 30
-#define SPI_SR_TXRXS_WIDTH 1
-#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
-#define SPI_SR_TCF_MASK 0x80000000u
-#define SPI_SR_TCF_SHIFT 31
-#define SPI_SR_TCF_WIDTH 1
-#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
-/* RSER Bit Fields */
-#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
-#define SPI_RSER_RFDF_DIRS_SHIFT 16
-#define SPI_RSER_RFDF_DIRS_WIDTH 1
-#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
-#define SPI_RSER_RFDF_RE_MASK 0x20000u
-#define SPI_RSER_RFDF_RE_SHIFT 17
-#define SPI_RSER_RFDF_RE_WIDTH 1
-#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
-#define SPI_RSER_RFOF_RE_MASK 0x80000u
-#define SPI_RSER_RFOF_RE_SHIFT 19
-#define SPI_RSER_RFOF_RE_WIDTH 1
-#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
-#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
-#define SPI_RSER_TFFF_DIRS_SHIFT 24
-#define SPI_RSER_TFFF_DIRS_WIDTH 1
-#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
-#define SPI_RSER_TFFF_RE_MASK 0x2000000u
-#define SPI_RSER_TFFF_RE_SHIFT 25
-#define SPI_RSER_TFFF_RE_WIDTH 1
-#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
-#define SPI_RSER_TFUF_RE_MASK 0x8000000u
-#define SPI_RSER_TFUF_RE_SHIFT 27
-#define SPI_RSER_TFUF_RE_WIDTH 1
-#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
-#define SPI_RSER_EOQF_RE_MASK 0x10000000u
-#define SPI_RSER_EOQF_RE_SHIFT 28
-#define SPI_RSER_EOQF_RE_WIDTH 1
-#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
-#define SPI_RSER_TCF_RE_MASK 0x80000000u
-#define SPI_RSER_TCF_RE_SHIFT 31
-#define SPI_RSER_TCF_RE_WIDTH 1
-#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
-/* PUSHR Bit Fields */
-#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
-#define SPI_PUSHR_TXDATA_SHIFT 0
-#define SPI_PUSHR_TXDATA_WIDTH 16
-#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK 0x3F0000u
-#define SPI_PUSHR_PCS_SHIFT 16
-#define SPI_PUSHR_PCS_WIDTH 6
-#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK 0x4000000u
-#define SPI_PUSHR_CTCNT_SHIFT 26
-#define SPI_PUSHR_CTCNT_WIDTH 1
-#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
-#define SPI_PUSHR_EOQ_MASK 0x8000000u
-#define SPI_PUSHR_EOQ_SHIFT 27
-#define SPI_PUSHR_EOQ_WIDTH 1
-#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
-#define SPI_PUSHR_CTAS_MASK 0x70000000u
-#define SPI_PUSHR_CTAS_SHIFT 28
-#define SPI_PUSHR_CTAS_WIDTH 3
-#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK 0x80000000u
-#define SPI_PUSHR_CONT_SHIFT 31
-#define SPI_PUSHR_CONT_WIDTH 1
-#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
-/* PUSHR_SLAVE Bit Fields */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
-#define SPI_PUSHR_SLAVE_TXDATA_WIDTH 32
-#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
-/* POPR Bit Fields */
-#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_POPR_RXDATA_SHIFT 0
-#define SPI_POPR_RXDATA_WIDTH 32
-#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
-/* TXFR0 Bit Fields */
-#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR0_TXDATA_SHIFT 0
-#define SPI_TXFR0_TXDATA_WIDTH 16
-#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR0_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
-/* TXFR1 Bit Fields */
-#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR1_TXDATA_SHIFT 0
-#define SPI_TXFR1_TXDATA_WIDTH 16
-#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR1_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
-/* TXFR2 Bit Fields */
-#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR2_TXDATA_SHIFT 0
-#define SPI_TXFR2_TXDATA_WIDTH 16
-#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR2_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
-/* TXFR3 Bit Fields */
-#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
-#define SPI_TXFR3_TXDATA_SHIFT 0
-#define SPI_TXFR3_TXDATA_WIDTH 16
-#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
-#define SPI_TXFR3_TXCMD_TXDATA_WIDTH 16
-#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
-/* RXFR0 Bit Fields */
-#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR0_RXDATA_SHIFT 0
-#define SPI_RXFR0_RXDATA_WIDTH 32
-#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
-/* RXFR1 Bit Fields */
-#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR1_RXDATA_SHIFT 0
-#define SPI_RXFR1_RXDATA_WIDTH 32
-#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
-/* RXFR2 Bit Fields */
-#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR2_RXDATA_SHIFT 0
-#define SPI_RXFR2_RXDATA_WIDTH 32
-#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
-/* RXFR3 Bit Fields */
-#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
-#define SPI_RXFR3_RXDATA_SHIFT 0
-#define SPI_RXFR3_RXDATA_WIDTH 32
-#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+/*! @name MCR - Module Configuration Register */
+#define SPI_MCR_HALT_MASK (0x1U)
+#define SPI_MCR_HALT_SHIFT (0U)
+#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT (8U)
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT (10U)
+#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT (11U)
+#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT (12U)
+#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT (13U)
+#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK (0x4000U)
+#define SPI_MCR_MDIS_SHIFT (14U)
+#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK (0x8000U)
+#define SPI_MCR_DOZE_SHIFT (15U)
+#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT (16U)
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT (24U)
+#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT (25U)
+#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT (26U)
+#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT (27U)
+#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT (28U)
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT (30U)
+#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT (31U)
+#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+
+/*! @name TCR - Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT (16U)
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK (0xFU)
+#define SPI_CTAR_BR_SHIFT (0U)
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK (0xF0U)
+#define SPI_CTAR_DT_SHIFT (4U)
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK (0xF00U)
+#define SPI_CTAR_ASC_SHIFT (8U)
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT (12U)
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK (0x30000U)
+#define SPI_CTAR_PBR_SHIFT (16U)
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT (18U)
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK (0x300000U)
+#define SPI_CTAR_PASC_SHIFT (20U)
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT (22U)
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT (24U)
+#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT (25U)
+#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT (26U)
+#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT (27U)
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT (31U)
+#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
+#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
+#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT (1U)
+
+/*! @name SR - Status Register */
+#define SPI_SR_POPNXTPTR_MASK (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT (0U)
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK (0xF0U)
+#define SPI_SR_RXCTR_SHIFT (4U)
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT (8U)
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK (0xF000U)
+#define SPI_SR_TXCTR_SHIFT (12U)
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK (0x20000U)
+#define SPI_SR_RFDF_SHIFT (17U)
+#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK (0x80000U)
+#define SPI_SR_RFOF_SHIFT (19U)
+#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK (0x2000000U)
+#define SPI_SR_TFFF_SHIFT (25U)
+#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK (0x8000000U)
+#define SPI_SR_TFUF_SHIFT (27U)
+#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK (0x10000000U)
+#define SPI_SR_EOQF_SHIFT (28U)
+#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT (30U)
+#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK (0x80000000U)
+#define SPI_SR_TCF_SHIFT (31U)
+#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
+#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT (17U)
+#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT (19U)
+#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
+#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT (25U)
+#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT (27U)
+#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT (28U)
+#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT (31U)
+#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT (16U)
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT (26U)
+#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT (27U)
+#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT (28U)
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT (31U)
+#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+
+/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+
+/*! @name POPR - POP RX FIFO Register */
+#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT (0U)
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+
+/*! @name TXFR0 - Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT (0U)
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT (0U)
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT (0U)
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT (0U)
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*! @name RXFR0 - Receive FIFO Registers */
+#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT (0U)
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+
+/*! @name RXFR1 - Receive FIFO Registers */
+#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT (0U)
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+
+/*! @name RXFR2 - Receive FIFO Registers */
+#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT (0U)
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+
+/*! @name RXFR3 - Receive FIFO Registers */
+#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT (0U)
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+
/*!
* @}
@@ -14324,17 +9464,14 @@ typedef struct {
#define SPI0_BASE (0x4002C000u)
/** Peripheral SPI0 base pointer */
#define SPI0 ((SPI_Type *)SPI0_BASE)
-#define SPI0_BASE_PTR (SPI0)
/** Peripheral SPI1 base address */
#define SPI1_BASE (0x4002D000u)
/** Peripheral SPI1 base pointer */
#define SPI1 ((SPI_Type *)SPI1_BASE)
-#define SPI1_BASE_PTR (SPI1)
/** Peripheral SPI2 base address */
#define SPI2_BASE (0x400AC000u)
/** Peripheral SPI2 base pointer */
#define SPI2 ((SPI_Type *)SPI2_BASE)
-#define SPI2_BASE_PTR (SPI2)
/** Array initializer of SPI peripheral base addresses */
#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
/** Array initializer of SPI peripheral base pointers */
@@ -14342,91 +9479,255 @@ typedef struct {
/** Interrupt vectors for the SPI peripheral type */
#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
/* ----------------------------------------------------------------------------
- -- SPI - Register accessor macros
+ -- SYSMPU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
- * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
* @{
*/
-
-/* SPI - Register instance definitions */
-/* SPI0 */
-#define SPI0_MCR SPI_MCR_REG(SPI0)
-#define SPI0_TCR SPI_TCR_REG(SPI0)
-#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
-#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
-#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
-#define SPI0_SR SPI_SR_REG(SPI0)
-#define SPI0_RSER SPI_RSER_REG(SPI0)
-#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
-#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
-#define SPI0_POPR SPI_POPR_REG(SPI0)
-#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
-#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
-#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
-#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
-#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
-#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
-#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
-#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
-/* SPI1 */
-#define SPI1_MCR SPI_MCR_REG(SPI1)
-#define SPI1_TCR SPI_TCR_REG(SPI1)
-#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
-#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
-#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
-#define SPI1_SR SPI_SR_REG(SPI1)
-#define SPI1_RSER SPI_RSER_REG(SPI1)
-#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
-#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
-#define SPI1_POPR SPI_POPR_REG(SPI1)
-#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
-#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
-#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
-#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
-#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
-#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
-#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
-#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
-/* SPI2 */
-#define SPI2_MCR SPI_MCR_REG(SPI2)
-#define SPI2_TCR SPI_TCR_REG(SPI2)
-#define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
-#define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
-#define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
-#define SPI2_SR SPI_SR_REG(SPI2)
-#define SPI2_RSER SPI_RSER_REG(SPI2)
-#define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
-#define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
-#define SPI2_POPR SPI_POPR_REG(SPI2)
-#define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
-#define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
-#define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
-#define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
-#define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
-#define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
-#define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
-#define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
-
-/* SPI - Register array accessors */
-#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
-#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
-#define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
-#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
-#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
-#define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
-
-/*!
- * @}
- */ /* end of group SPI_Register_Accessor_Macros */
-
-
-/*!
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
+/** SYSMPU - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ struct { /* offset: 0x10, array step: 0x8 */
+ __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+ __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+ } SP[5];
+ uint8_t RESERVED_1[968];
+ __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+ uint8_t RESERVED_2[832];
+ __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} SYSMPU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SYSMPU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+#define SYSMPU_CESR_VLD_MASK (0x1U)
+#define SYSMPU_CESR_VLD_SHIFT (0U)
+#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_NRGD_MASK (0xF00U)
+#define SYSMPU_CESR_NRGD_SHIFT (8U)
+#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NSP_MASK (0xF000U)
+#define SYSMPU_CESR_NSP_SHIFT (12U)
+#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_HRL_MASK (0xF0000U)
+#define SYSMPU_CESR_HRL_SHIFT (16U)
+#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
+#define SYSMPU_CESR_SPERR_SHIFT (27U)
+#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+
+/*! @name EAR - Error Address Register, slave port n */
+#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
+#define SYSMPU_EAR_EADDR_SHIFT (0U)
+#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+
+/* The count of SYSMPU_EAR */
+#define SYSMPU_EAR_COUNT (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+#define SYSMPU_EDR_ERW_MASK (0x1U)
+#define SYSMPU_EDR_ERW_SHIFT (0U)
+#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_EATTR_MASK (0xEU)
+#define SYSMPU_EDR_EATTR_SHIFT (1U)
+#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EMN_MASK (0xF0U)
+#define SYSMPU_EDR_EMN_SHIFT (4U)
+#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EPID_MASK (0xFF00U)
+#define SYSMPU_EDR_EPID_SHIFT (8U)
+#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
+#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
+#define SYSMPU_EDR_EACD_SHIFT (16U)
+#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+
+/* The count of SYSMPU_EDR */
+#define SYSMPU_EDR_COUNT (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+#define SYSMPU_WORD_VLD_MASK (0x1U)
+#define SYSMPU_WORD_VLD_SHIFT (0U)
+#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_M0UM_MASK (0x7U)
+#define SYSMPU_WORD_M0UM_SHIFT (0U)
+#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_M0SM_MASK (0x18U)
+#define SYSMPU_WORD_M0SM_SHIFT (3U)
+#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_M0PE_MASK (0x20U)
+#define SYSMPU_WORD_M0PE_SHIFT (5U)
+#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
+#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
+#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
+#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
+#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
+#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
+#define SYSMPU_WORD_M1UM_SHIFT (6U)
+#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1SM_MASK (0x600U)
+#define SYSMPU_WORD_M1SM_SHIFT (9U)
+#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M1PE_MASK (0x800U)
+#define SYSMPU_WORD_M1PE_SHIFT (11U)
+#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
+#define SYSMPU_WORD_M2UM_MASK (0x7000U)
+#define SYSMPU_WORD_M2UM_SHIFT (12U)
+#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2SM_MASK (0x18000U)
+#define SYSMPU_WORD_M2SM_SHIFT (15U)
+#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
+#define SYSMPU_WORD_PIDMASK_SHIFT (16U)
+#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
+#define SYSMPU_WORD_M2PE_MASK (0x20000U)
+#define SYSMPU_WORD_M2PE_SHIFT (17U)
+#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
+#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
+#define SYSMPU_WORD_M3UM_SHIFT (18U)
+#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3SM_MASK (0x600000U)
+#define SYSMPU_WORD_M3SM_SHIFT (21U)
+#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M3PE_MASK (0x800000U)
+#define SYSMPU_WORD_M3PE_SHIFT (23U)
+#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
+#define SYSMPU_WORD_PID_MASK (0xFF000000U)
+#define SYSMPU_WORD_PID_SHIFT (24U)
+#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
+#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
+#define SYSMPU_WORD_M4WE_SHIFT (24U)
+#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
+#define SYSMPU_WORD_M4RE_SHIFT (25U)
+#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
+#define SYSMPU_WORD_M5WE_SHIFT (26U)
+#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
+#define SYSMPU_WORD_M5RE_SHIFT (27U)
+#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
+#define SYSMPU_WORD_M6WE_SHIFT (28U)
+#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
+#define SYSMPU_WORD_M6RE_SHIFT (29U)
+#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
+#define SYSMPU_WORD_M7WE_SHIFT (30U)
+#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
+#define SYSMPU_WORD_M7RE_SHIFT (31U)
+#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT (12U)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT2 (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
+#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
+#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
+#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
+#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
+#define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
+#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
+#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
+#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
+#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
+#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
+#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
+#define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
+#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
+#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
+#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
+#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
+#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
+#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
+#define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
+#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
+#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
+#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
+#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
+#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
+#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
+#define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
+#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
+#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
+#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
+#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
+#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
+#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
+#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
+#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
+#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
+#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
+#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
+#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
+#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
+#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
+#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
+#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
+#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
+#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+
+/* The count of SYSMPU_RGDAAC */
+#define SYSMPU_RGDAAC_COUNT (12U)
+
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Register_Masks */
+
+
+/* SYSMPU - Peripheral instance base addresses */
+/** Peripheral SYSMPU base address */
+#define SYSMPU_BASE (0x4000D000u)
+/** Peripheral SYSMPU base pointer */
+#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
+/** Array initializer of SYSMPU peripheral base addresses */
+#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
+/** Array initializer of SYSMPU peripheral base pointers */
+#define SYSMPU_BASE_PTRS { SYSMPU }
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
@@ -14487,62 +9788,7 @@ typedef struct {
};
__IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
__IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
-} UART_Type, *UART_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register accessors */
-#define UART_BDH_REG(base) ((base)->BDH)
-#define UART_BDL_REG(base) ((base)->BDL)
-#define UART_C1_REG(base) ((base)->C1)
-#define UART_C2_REG(base) ((base)->C2)
-#define UART_S1_REG(base) ((base)->S1)
-#define UART_S2_REG(base) ((base)->S2)
-#define UART_C3_REG(base) ((base)->C3)
-#define UART_D_REG(base) ((base)->D)
-#define UART_MA1_REG(base) ((base)->MA1)
-#define UART_MA2_REG(base) ((base)->MA2)
-#define UART_C4_REG(base) ((base)->C4)
-#define UART_C5_REG(base) ((base)->C5)
-#define UART_ED_REG(base) ((base)->ED)
-#define UART_MODEM_REG(base) ((base)->MODEM)
-#define UART_IR_REG(base) ((base)->IR)
-#define UART_PFIFO_REG(base) ((base)->PFIFO)
-#define UART_CFIFO_REG(base) ((base)->CFIFO)
-#define UART_SFIFO_REG(base) ((base)->SFIFO)
-#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
-#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
-#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
-#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
-#define UART_C7816_REG(base) ((base)->C7816)
-#define UART_IE7816_REG(base) ((base)->IE7816)
-#define UART_IS7816_REG(base) ((base)->IS7816)
-#define UART_WP7816_REG(base) ((base)->WP7816)
-#define UART_WN7816_REG(base) ((base)->WN7816)
-#define UART_WF7816_REG(base) ((base)->WF7816)
-#define UART_ET7816_REG(base) ((base)->ET7816)
-#define UART_TL7816_REG(base) ((base)->TL7816)
-#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
-#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
-#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
-#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
-#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
-#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
-#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
-#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
+} UART_Type;
/* ----------------------------------------------------------------------------
-- UART Register Masks
@@ -14553,504 +9799,427 @@ typedef struct {
* @{
*/
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR_WIDTH 5
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_RXEDGIE_WIDTH 1
-#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-#define UART_BDH_LBKDIE_WIDTH 1
-#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR_WIDTH 8
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PT_WIDTH 1
-#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_PE_WIDTH 1
-#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_ILT_WIDTH 1
-#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_WAKE_WIDTH 1
-#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_M_WIDTH 1
-#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_RSRC_WIDTH 1
-#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_UARTSWAI_WIDTH 1
-#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-#define UART_C1_LOOPS_WIDTH 1
-#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_SBK_WIDTH 1
-#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RWU_WIDTH 1
-#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_RE_WIDTH 1
-#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_TE_WIDTH 1
-#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_ILIE_WIDTH 1
-#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_RIE_WIDTH 1
-#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TCIE_WIDTH 1
-#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-#define UART_C2_TIE_WIDTH 1
-#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_PF_WIDTH 1
-#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_FE_WIDTH 1
-#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_NF_WIDTH 1
-#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_OR_WIDTH 1
-#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_IDLE_WIDTH 1
-#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_RDRF_WIDTH 1
-#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TC_WIDTH 1
-#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-#define UART_S1_TDRE_WIDTH 1
-#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_RAF_WIDTH 1
-#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_LBKDE_WIDTH 1
-#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_BRK13_WIDTH 1
-#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RWUID_WIDTH 1
-#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_RXINV_WIDTH 1
-#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
-#define UART_S2_MSBF_MASK 0x20u
-#define UART_S2_MSBF_SHIFT 5
-#define UART_S2_MSBF_WIDTH 1
-#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_RXEDGIF_WIDTH 1
-#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-#define UART_S2_LBKDIF_WIDTH 1
-#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_PEIE_WIDTH 1
-#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_FEIE_WIDTH 1
-#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_NEIE_WIDTH 1
-#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_ORIE_WIDTH 1
-#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXINV_WIDTH 1
-#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_TXDIR_WIDTH 1
-#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_T8_WIDTH 1
-#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-#define UART_C3_R8_WIDTH 1
-#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
-/* D Bit Fields */
-#define UART_D_RT_MASK 0xFFu
-#define UART_D_RT_SHIFT 0
-#define UART_D_RT_WIDTH 8
-#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
-/* MA1 Bit Fields */
-#define UART_MA1_MA_MASK 0xFFu
-#define UART_MA1_MA_SHIFT 0
-#define UART_MA1_MA_WIDTH 8
-#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UART_MA2_MA_MASK 0xFFu
-#define UART_MA2_MA_SHIFT 0
-#define UART_MA2_MA_WIDTH 8
-#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UART_C4_BRFA_MASK 0x1Fu
-#define UART_C4_BRFA_SHIFT 0
-#define UART_C4_BRFA_WIDTH 5
-#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK 0x20u
-#define UART_C4_M10_SHIFT 5
-#define UART_C4_M10_WIDTH 1
-#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
-#define UART_C4_MAEN2_MASK 0x40u
-#define UART_C4_MAEN2_SHIFT 6
-#define UART_C4_MAEN2_WIDTH 1
-#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
-#define UART_C4_MAEN1_MASK 0x80u
-#define UART_C4_MAEN1_SHIFT 7
-#define UART_C4_MAEN1_WIDTH 1
-#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
-/* C5 Bit Fields */
-#define UART_C5_RDMAS_MASK 0x20u
-#define UART_C5_RDMAS_SHIFT 5
-#define UART_C5_RDMAS_WIDTH 1
-#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
-#define UART_C5_TDMAS_MASK 0x80u
-#define UART_C5_TDMAS_SHIFT 7
-#define UART_C5_TDMAS_WIDTH 1
-#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
-/* ED Bit Fields */
-#define UART_ED_PARITYE_MASK 0x40u
-#define UART_ED_PARITYE_SHIFT 6
-#define UART_ED_PARITYE_WIDTH 1
-#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
-#define UART_ED_NOISY_MASK 0x80u
-#define UART_ED_NOISY_SHIFT 7
-#define UART_ED_NOISY_WIDTH 1
-#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
-/* MODEM Bit Fields */
-#define UART_MODEM_TXCTSE_MASK 0x1u
-#define UART_MODEM_TXCTSE_SHIFT 0
-#define UART_MODEM_TXCTSE_WIDTH 1
-#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
-#define UART_MODEM_TXRTSE_MASK 0x2u
-#define UART_MODEM_TXRTSE_SHIFT 1
-#define UART_MODEM_TXRTSE_WIDTH 1
-#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
-#define UART_MODEM_TXRTSPOL_MASK 0x4u
-#define UART_MODEM_TXRTSPOL_SHIFT 2
-#define UART_MODEM_TXRTSPOL_WIDTH 1
-#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
-#define UART_MODEM_RXRTSE_MASK 0x8u
-#define UART_MODEM_RXRTSE_SHIFT 3
-#define UART_MODEM_RXRTSE_WIDTH 1
-#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
-/* IR Bit Fields */
-#define UART_IR_TNP_MASK 0x3u
-#define UART_IR_TNP_SHIFT 0
-#define UART_IR_TNP_WIDTH 2
-#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK 0x4u
-#define UART_IR_IREN_SHIFT 2
-#define UART_IR_IREN_WIDTH 1
-#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
-/* PFIFO Bit Fields */
-#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
-#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
-#define UART_PFIFO_RXFIFOSIZE_WIDTH 3
-#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK 0x8u
-#define UART_PFIFO_RXFE_SHIFT 3
-#define UART_PFIFO_RXFE_WIDTH 1
-#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
-#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
-#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
-#define UART_PFIFO_TXFIFOSIZE_WIDTH 3
-#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK 0x80u
-#define UART_PFIFO_TXFE_SHIFT 7
-#define UART_PFIFO_TXFE_WIDTH 1
-#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
-/* CFIFO Bit Fields */
-#define UART_CFIFO_RXUFE_MASK 0x1u
-#define UART_CFIFO_RXUFE_SHIFT 0
-#define UART_CFIFO_RXUFE_WIDTH 1
-#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
-#define UART_CFIFO_TXOFE_MASK 0x2u
-#define UART_CFIFO_TXOFE_SHIFT 1
-#define UART_CFIFO_TXOFE_WIDTH 1
-#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
-#define UART_CFIFO_RXOFE_MASK 0x4u
-#define UART_CFIFO_RXOFE_SHIFT 2
-#define UART_CFIFO_RXOFE_WIDTH 1
-#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
-#define UART_CFIFO_RXFLUSH_MASK 0x40u
-#define UART_CFIFO_RXFLUSH_SHIFT 6
-#define UART_CFIFO_RXFLUSH_WIDTH 1
-#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
-#define UART_CFIFO_TXFLUSH_MASK 0x80u
-#define UART_CFIFO_TXFLUSH_SHIFT 7
-#define UART_CFIFO_TXFLUSH_WIDTH 1
-#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
-/* SFIFO Bit Fields */
-#define UART_SFIFO_RXUF_MASK 0x1u
-#define UART_SFIFO_RXUF_SHIFT 0
-#define UART_SFIFO_RXUF_WIDTH 1
-#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
-#define UART_SFIFO_TXOF_MASK 0x2u
-#define UART_SFIFO_TXOF_SHIFT 1
-#define UART_SFIFO_TXOF_WIDTH 1
-#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
-#define UART_SFIFO_RXOF_MASK 0x4u
-#define UART_SFIFO_RXOF_SHIFT 2
-#define UART_SFIFO_RXOF_WIDTH 1
-#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
-#define UART_SFIFO_RXEMPT_MASK 0x40u
-#define UART_SFIFO_RXEMPT_SHIFT 6
-#define UART_SFIFO_RXEMPT_WIDTH 1
-#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
-#define UART_SFIFO_TXEMPT_MASK 0x80u
-#define UART_SFIFO_TXEMPT_SHIFT 7
-#define UART_SFIFO_TXEMPT_WIDTH 1
-#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
-/* TWFIFO Bit Fields */
-#define UART_TWFIFO_TXWATER_MASK 0xFFu
-#define UART_TWFIFO_TXWATER_SHIFT 0
-#define UART_TWFIFO_TXWATER_WIDTH 8
-#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
-/* TCFIFO Bit Fields */
-#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
-#define UART_TCFIFO_TXCOUNT_SHIFT 0
-#define UART_TCFIFO_TXCOUNT_WIDTH 8
-#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
-/* RWFIFO Bit Fields */
-#define UART_RWFIFO_RXWATER_MASK 0xFFu
-#define UART_RWFIFO_RXWATER_SHIFT 0
-#define UART_RWFIFO_RXWATER_WIDTH 8
-#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
-/* RCFIFO Bit Fields */
-#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
-#define UART_RCFIFO_RXCOUNT_SHIFT 0
-#define UART_RCFIFO_RXCOUNT_WIDTH 8
-#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
-/* C7816 Bit Fields */
-#define UART_C7816_ISO_7816E_MASK 0x1u
-#define UART_C7816_ISO_7816E_SHIFT 0
-#define UART_C7816_ISO_7816E_WIDTH 1
-#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
-#define UART_C7816_TTYPE_MASK 0x2u
-#define UART_C7816_TTYPE_SHIFT 1
-#define UART_C7816_TTYPE_WIDTH 1
-#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
-#define UART_C7816_INIT_MASK 0x4u
-#define UART_C7816_INIT_SHIFT 2
-#define UART_C7816_INIT_WIDTH 1
-#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
-#define UART_C7816_ANACK_MASK 0x8u
-#define UART_C7816_ANACK_SHIFT 3
-#define UART_C7816_ANACK_WIDTH 1
-#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
-#define UART_C7816_ONACK_MASK 0x10u
-#define UART_C7816_ONACK_SHIFT 4
-#define UART_C7816_ONACK_WIDTH 1
-#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
-/* IE7816 Bit Fields */
-#define UART_IE7816_RXTE_MASK 0x1u
-#define UART_IE7816_RXTE_SHIFT 0
-#define UART_IE7816_RXTE_WIDTH 1
-#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
-#define UART_IE7816_TXTE_MASK 0x2u
-#define UART_IE7816_TXTE_SHIFT 1
-#define UART_IE7816_TXTE_WIDTH 1
-#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
-#define UART_IE7816_GTVE_MASK 0x4u
-#define UART_IE7816_GTVE_SHIFT 2
-#define UART_IE7816_GTVE_WIDTH 1
-#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
-#define UART_IE7816_ADTE_MASK 0x8u
-#define UART_IE7816_ADTE_SHIFT 3
-#define UART_IE7816_ADTE_WIDTH 1
-#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_ADTE_SHIFT))&UART_IE7816_ADTE_MASK)
-#define UART_IE7816_INITDE_MASK 0x10u
-#define UART_IE7816_INITDE_SHIFT 4
-#define UART_IE7816_INITDE_WIDTH 1
-#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
-#define UART_IE7816_BWTE_MASK 0x20u
-#define UART_IE7816_BWTE_SHIFT 5
-#define UART_IE7816_BWTE_WIDTH 1
-#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
-#define UART_IE7816_CWTE_MASK 0x40u
-#define UART_IE7816_CWTE_SHIFT 6
-#define UART_IE7816_CWTE_WIDTH 1
-#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
-#define UART_IE7816_WTE_MASK 0x80u
-#define UART_IE7816_WTE_SHIFT 7
-#define UART_IE7816_WTE_WIDTH 1
-#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
-/* IS7816 Bit Fields */
-#define UART_IS7816_RXT_MASK 0x1u
-#define UART_IS7816_RXT_SHIFT 0
-#define UART_IS7816_RXT_WIDTH 1
-#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
-#define UART_IS7816_TXT_MASK 0x2u
-#define UART_IS7816_TXT_SHIFT 1
-#define UART_IS7816_TXT_WIDTH 1
-#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
-#define UART_IS7816_GTV_MASK 0x4u
-#define UART_IS7816_GTV_SHIFT 2
-#define UART_IS7816_GTV_WIDTH 1
-#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
-#define UART_IS7816_ADT_MASK 0x8u
-#define UART_IS7816_ADT_SHIFT 3
-#define UART_IS7816_ADT_WIDTH 1
-#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_ADT_SHIFT))&UART_IS7816_ADT_MASK)
-#define UART_IS7816_INITD_MASK 0x10u
-#define UART_IS7816_INITD_SHIFT 4
-#define UART_IS7816_INITD_WIDTH 1
-#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
-#define UART_IS7816_BWT_MASK 0x20u
-#define UART_IS7816_BWT_SHIFT 5
-#define UART_IS7816_BWT_WIDTH 1
-#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
-#define UART_IS7816_CWT_MASK 0x40u
-#define UART_IS7816_CWT_SHIFT 6
-#define UART_IS7816_CWT_WIDTH 1
-#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
-#define UART_IS7816_WT_MASK 0x80u
-#define UART_IS7816_WT_SHIFT 7
-#define UART_IS7816_WT_WIDTH 1
-#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
-/* WP7816 Bit Fields */
-#define UART_WP7816_WTX_MASK 0xFFu
-#define UART_WP7816_WTX_SHIFT 0
-#define UART_WP7816_WTX_WIDTH 8
-#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
-/* WN7816 Bit Fields */
-#define UART_WN7816_GTN_MASK 0xFFu
-#define UART_WN7816_GTN_SHIFT 0
-#define UART_WN7816_GTN_WIDTH 8
-#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
-/* WF7816 Bit Fields */
-#define UART_WF7816_GTFD_MASK 0xFFu
-#define UART_WF7816_GTFD_SHIFT 0
-#define UART_WF7816_GTFD_WIDTH 8
-#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
-/* ET7816 Bit Fields */
-#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
-#define UART_ET7816_RXTHRESHOLD_SHIFT 0
-#define UART_ET7816_RXTHRESHOLD_WIDTH 4
-#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
-#define UART_ET7816_TXTHRESHOLD_SHIFT 4
-#define UART_ET7816_TXTHRESHOLD_WIDTH 4
-#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
-/* TL7816 Bit Fields */
-#define UART_TL7816_TLEN_MASK 0xFFu
-#define UART_TL7816_TLEN_SHIFT 0
-#define UART_TL7816_TLEN_WIDTH 8
-#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
-/* AP7816A_T0 Bit Fields */
-#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
-#define UART_AP7816A_T0_ADTI_H_SHIFT 0
-#define UART_AP7816A_T0_ADTI_H_WIDTH 8
-#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
-/* AP7816B_T0 Bit Fields */
-#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
-#define UART_AP7816B_T0_ADTI_L_SHIFT 0
-#define UART_AP7816B_T0_ADTI_L_WIDTH 8
-#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
-/* WP7816A_T0 Bit Fields */
-#define UART_WP7816A_T0_WI_H_MASK 0xFFu
-#define UART_WP7816A_T0_WI_H_SHIFT 0
-#define UART_WP7816A_T0_WI_H_WIDTH 8
-#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
-/* WP7816B_T0 Bit Fields */
-#define UART_WP7816B_T0_WI_L_MASK 0xFFu
-#define UART_WP7816B_T0_WI_L_SHIFT 0
-#define UART_WP7816B_T0_WI_L_WIDTH 8
-#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
-/* WP7816A_T1 Bit Fields */
-#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
-#define UART_WP7816A_T1_BWI_H_SHIFT 0
-#define UART_WP7816A_T1_BWI_H_WIDTH 8
-#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
-/* WP7816B_T1 Bit Fields */
-#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
-#define UART_WP7816B_T1_BWI_L_SHIFT 0
-#define UART_WP7816B_T1_BWI_L_WIDTH 8
-#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
-/* WGP7816_T1 Bit Fields */
-#define UART_WGP7816_T1_BGI_MASK 0xFu
-#define UART_WGP7816_T1_BGI_SHIFT 0
-#define UART_WGP7816_T1_BGI_WIDTH 4
-#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
-#define UART_WGP7816_T1_CWI1_MASK 0xF0u
-#define UART_WGP7816_T1_CWI1_SHIFT 4
-#define UART_WGP7816_T1_CWI1_WIDTH 4
-#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
-/* WP7816C_T1 Bit Fields */
-#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
-#define UART_WP7816C_T1_CWI2_SHIFT 0
-#define UART_WP7816C_T1_CWI2_WIDTH 5
-#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+/*! @name BDH - UART Baud Rate Registers: High */
+#define UART_BDH_SBR_MASK (0x1FU)
+#define UART_BDH_SBR_SHIFT (0U)
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT (6U)
+#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK (0x80U)
+#define UART_BDH_LBKDIE_SHIFT (7U)
+#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+#define UART_BDL_SBR_MASK (0xFFU)
+#define UART_BDL_SBR_SHIFT (0U)
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK (0x1U)
+#define UART_C1_PT_SHIFT (0U)
+#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK (0x2U)
+#define UART_C1_PE_SHIFT (1U)
+#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK (0x4U)
+#define UART_C1_ILT_SHIFT (2U)
+#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK (0x8U)
+#define UART_C1_WAKE_SHIFT (3U)
+#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK (0x10U)
+#define UART_C1_M_SHIFT (4U)
+#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK (0x20U)
+#define UART_C1_RSRC_SHIFT (5U)
+#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK (0x40U)
+#define UART_C1_UARTSWAI_SHIFT (6U)
+#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK (0x80U)
+#define UART_C1_LOOPS_SHIFT (7U)
+#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK (0x1U)
+#define UART_C2_SBK_SHIFT (0U)
+#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK (0x2U)
+#define UART_C2_RWU_SHIFT (1U)
+#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK (0x4U)
+#define UART_C2_RE_SHIFT (2U)
+#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK (0x8U)
+#define UART_C2_TE_SHIFT (3U)
+#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK (0x10U)
+#define UART_C2_ILIE_SHIFT (4U)
+#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK (0x20U)
+#define UART_C2_RIE_SHIFT (5U)
+#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK (0x40U)
+#define UART_C2_TCIE_SHIFT (6U)
+#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK (0x80U)
+#define UART_C2_TIE_SHIFT (7U)
+#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK (0x1U)
+#define UART_S1_PF_SHIFT (0U)
+#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK (0x2U)
+#define UART_S1_FE_SHIFT (1U)
+#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK (0x4U)
+#define UART_S1_NF_SHIFT (2U)
+#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK (0x8U)
+#define UART_S1_OR_SHIFT (3U)
+#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK (0x10U)
+#define UART_S1_IDLE_SHIFT (4U)
+#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK (0x20U)
+#define UART_S1_RDRF_SHIFT (5U)
+#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK (0x40U)
+#define UART_S1_TC_SHIFT (6U)
+#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK (0x80U)
+#define UART_S1_TDRE_SHIFT (7U)
+#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK (0x1U)
+#define UART_S2_RAF_SHIFT (0U)
+#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK (0x2U)
+#define UART_S2_LBKDE_SHIFT (1U)
+#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK (0x4U)
+#define UART_S2_BRK13_SHIFT (2U)
+#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK (0x8U)
+#define UART_S2_RWUID_SHIFT (3U)
+#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK (0x10U)
+#define UART_S2_RXINV_SHIFT (4U)
+#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK (0x20U)
+#define UART_S2_MSBF_SHIFT (5U)
+#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK (0x40U)
+#define UART_S2_RXEDGIF_SHIFT (6U)
+#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK (0x80U)
+#define UART_S2_LBKDIF_SHIFT (7U)
+#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK (0x1U)
+#define UART_C3_PEIE_SHIFT (0U)
+#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK (0x2U)
+#define UART_C3_FEIE_SHIFT (1U)
+#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK (0x4U)
+#define UART_C3_NEIE_SHIFT (2U)
+#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK (0x8U)
+#define UART_C3_ORIE_SHIFT (3U)
+#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK (0x10U)
+#define UART_C3_TXINV_SHIFT (4U)
+#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK (0x20U)
+#define UART_C3_TXDIR_SHIFT (5U)
+#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK (0x40U)
+#define UART_C3_T8_SHIFT (6U)
+#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK (0x80U)
+#define UART_C3_R8_SHIFT (7U)
+#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_RT_MASK (0xFFU)
+#define UART_D_RT_SHIFT (0U)
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART_MA1_MA_MASK (0xFFU)
+#define UART_MA1_MA_SHIFT (0U)
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART_MA2_MA_MASK (0xFFU)
+#define UART_MA2_MA_SHIFT (0U)
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_BRFA_MASK (0x1FU)
+#define UART_C4_BRFA_SHIFT (0U)
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK (0x20U)
+#define UART_C4_M10_SHIFT (5U)
+#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK (0x40U)
+#define UART_C4_MAEN2_SHIFT (6U)
+#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK (0x80U)
+#define UART_C4_MAEN1_SHIFT (7U)
+#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART_C5_RDMAS_MASK (0x20U)
+#define UART_C5_RDMAS_SHIFT (5U)
+#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK (0x80U)
+#define UART_C5_TDMAS_SHIFT (7U)
+#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+
+/*! @name ED - UART Extended Data Register */
+#define UART_ED_PARITYE_MASK (0x40U)
+#define UART_ED_PARITYE_SHIFT (6U)
+#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK (0x80U)
+#define UART_ED_NOISY_SHIFT (7U)
+#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+
+/*! @name MODEM - UART Modem Register */
+#define UART_MODEM_TXCTSE_MASK (0x1U)
+#define UART_MODEM_TXCTSE_SHIFT (0U)
+#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK (0x2U)
+#define UART_MODEM_TXRTSE_SHIFT (1U)
+#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK (0x4U)
+#define UART_MODEM_TXRTSPOL_SHIFT (2U)
+#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK (0x8U)
+#define UART_MODEM_RXRTSE_SHIFT (3U)
+#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+
+/*! @name IR - UART Infrared Register */
+#define UART_IR_TNP_MASK (0x3U)
+#define UART_IR_TNP_SHIFT (0U)
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK (0x4U)
+#define UART_IR_IREN_SHIFT (2U)
+#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+
+/*! @name PFIFO - UART FIFO Parameters */
+#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK (0x8U)
+#define UART_PFIFO_RXFE_SHIFT (3U)
+#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK (0x80U)
+#define UART_PFIFO_TXFE_SHIFT (7U)
+#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+
+/*! @name CFIFO - UART FIFO Control Register */
+#define UART_CFIFO_RXUFE_MASK (0x1U)
+#define UART_CFIFO_RXUFE_SHIFT (0U)
+#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK (0x2U)
+#define UART_CFIFO_TXOFE_SHIFT (1U)
+#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK (0x4U)
+#define UART_CFIFO_RXOFE_SHIFT (2U)
+#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK (0x40U)
+#define UART_CFIFO_RXFLUSH_SHIFT (6U)
+#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK (0x80U)
+#define UART_CFIFO_TXFLUSH_SHIFT (7U)
+#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+
+/*! @name SFIFO - UART FIFO Status Register */
+#define UART_SFIFO_RXUF_MASK (0x1U)
+#define UART_SFIFO_RXUF_SHIFT (0U)
+#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK (0x2U)
+#define UART_SFIFO_TXOF_SHIFT (1U)
+#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK (0x4U)
+#define UART_SFIFO_RXOF_SHIFT (2U)
+#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK (0x40U)
+#define UART_SFIFO_RXEMPT_SHIFT (6U)
+#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK (0x80U)
+#define UART_SFIFO_TXEMPT_SHIFT (7U)
+#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+#define UART_TWFIFO_TXWATER_MASK (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT (0U)
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+#define UART_RWFIFO_RXWATER_MASK (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT (0U)
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+
+/*! @name C7816 - UART 7816 Control Register */
+#define UART_C7816_ISO_7816E_MASK (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT (0U)
+#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK (0x2U)
+#define UART_C7816_TTYPE_SHIFT (1U)
+#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK (0x4U)
+#define UART_C7816_INIT_SHIFT (2U)
+#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK (0x8U)
+#define UART_C7816_ANACK_SHIFT (3U)
+#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK (0x10U)
+#define UART_C7816_ONACK_SHIFT (4U)
+#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+#define UART_IE7816_RXTE_MASK (0x1U)
+#define UART_IE7816_RXTE_SHIFT (0U)
+#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK (0x2U)
+#define UART_IE7816_TXTE_SHIFT (1U)
+#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK (0x4U)
+#define UART_IE7816_GTVE_SHIFT (2U)
+#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+#define UART_IE7816_ADTE_MASK (0x8U)
+#define UART_IE7816_ADTE_SHIFT (3U)
+#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
+#define UART_IE7816_INITDE_MASK (0x10U)
+#define UART_IE7816_INITDE_SHIFT (4U)
+#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK (0x20U)
+#define UART_IE7816_BWTE_SHIFT (5U)
+#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK (0x40U)
+#define UART_IE7816_CWTE_SHIFT (6U)
+#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK (0x80U)
+#define UART_IE7816_WTE_SHIFT (7U)
+#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+#define UART_IS7816_RXT_MASK (0x1U)
+#define UART_IS7816_RXT_SHIFT (0U)
+#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK (0x2U)
+#define UART_IS7816_TXT_SHIFT (1U)
+#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK (0x4U)
+#define UART_IS7816_GTV_SHIFT (2U)
+#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+#define UART_IS7816_ADT_MASK (0x8U)
+#define UART_IS7816_ADT_SHIFT (3U)
+#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
+#define UART_IS7816_INITD_MASK (0x10U)
+#define UART_IS7816_INITD_SHIFT (4U)
+#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK (0x20U)
+#define UART_IS7816_BWT_SHIFT (5U)
+#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK (0x40U)
+#define UART_IS7816_CWT_SHIFT (6U)
+#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK (0x80U)
+#define UART_IS7816_WT_SHIFT (7U)
+#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+
+/*! @name WP7816 - UART 7816 Wait Parameter Register */
+#define UART_WP7816_WTX_MASK (0xFFU)
+#define UART_WP7816_WTX_SHIFT (0U)
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+#define UART_WN7816_GTN_MASK (0xFFU)
+#define UART_WN7816_GTN_SHIFT (0U)
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+#define UART_WF7816_GTFD_MASK (0xFFU)
+#define UART_WF7816_GTFD_SHIFT (0U)
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+#define UART_TL7816_TLEN_MASK (0xFFU)
+#define UART_TL7816_TLEN_SHIFT (0U)
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+
+/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
+#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
+#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
+
+/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
+#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
+#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
+
+/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
+#define UART_WP7816A_T0_WI_H_SHIFT (0U)
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
+
+/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
+#define UART_WP7816B_T0_WI_L_SHIFT (0U)
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
+
+/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
+#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
+
+/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
+#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
+
+/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
+#define UART_WGP7816_T1_BGI_MASK (0xFU)
+#define UART_WGP7816_T1_BGI_SHIFT (0U)
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
+#define UART_WGP7816_T1_CWI1_SHIFT (4U)
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
+
+/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
+#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
+#define UART_WP7816C_T1_CWI2_SHIFT (0U)
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
+
/*!
* @}
@@ -15062,32 +10231,26 @@ typedef struct {
#define UART0_BASE (0x4006A000u)
/** Peripheral UART0 base pointer */
#define UART0 ((UART_Type *)UART0_BASE)
-#define UART0_BASE_PTR (UART0)
/** Peripheral UART1 base address */
#define UART1_BASE (0x4006B000u)
/** Peripheral UART1 base pointer */
#define UART1 ((UART_Type *)UART1_BASE)
-#define UART1_BASE_PTR (UART1)
/** Peripheral UART2 base address */
#define UART2_BASE (0x4006C000u)
/** Peripheral UART2 base pointer */
#define UART2 ((UART_Type *)UART2_BASE)
-#define UART2_BASE_PTR (UART2)
/** Peripheral UART3 base address */
#define UART3_BASE (0x4006D000u)
/** Peripheral UART3 base pointer */
#define UART3 ((UART_Type *)UART3_BASE)
-#define UART3_BASE_PTR (UART3)
/** Peripheral UART4 base address */
#define UART4_BASE (0x400EA000u)
/** Peripheral UART4 base pointer */
#define UART4 ((UART_Type *)UART4_BASE)
-#define UART4_BASE_PTR (UART4)
/** Peripheral UART5 base address */
#define UART5_BASE (0x400EB000u)
/** Peripheral UART5 base pointer */
#define UART5 ((UART_Type *)UART5_BASE)
-#define UART5_BASE_PTR (UART5)
/** Array initializer of UART peripheral base addresses */
#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
/** Array initializer of UART peripheral base pointers */
@@ -15096,177 +10259,6 @@ typedef struct {
#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
-/* ----------------------------------------------------------------------------
- -- UART - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
- * @{
- */
-
-
-/* UART - Register instance definitions */
-/* UART0 */
-#define UART0_BDH UART_BDH_REG(UART0)
-#define UART0_BDL UART_BDL_REG(UART0)
-#define UART0_C1 UART_C1_REG(UART0)
-#define UART0_C2 UART_C2_REG(UART0)
-#define UART0_S1 UART_S1_REG(UART0)
-#define UART0_S2 UART_S2_REG(UART0)
-#define UART0_C3 UART_C3_REG(UART0)
-#define UART0_D UART_D_REG(UART0)
-#define UART0_MA1 UART_MA1_REG(UART0)
-#define UART0_MA2 UART_MA2_REG(UART0)
-#define UART0_C4 UART_C4_REG(UART0)
-#define UART0_C5 UART_C5_REG(UART0)
-#define UART0_ED UART_ED_REG(UART0)
-#define UART0_MODEM UART_MODEM_REG(UART0)
-#define UART0_IR UART_IR_REG(UART0)
-#define UART0_PFIFO UART_PFIFO_REG(UART0)
-#define UART0_CFIFO UART_CFIFO_REG(UART0)
-#define UART0_SFIFO UART_SFIFO_REG(UART0)
-#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
-#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
-#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
-#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
-#define UART0_C7816 UART_C7816_REG(UART0)
-#define UART0_IE7816 UART_IE7816_REG(UART0)
-#define UART0_IS7816 UART_IS7816_REG(UART0)
-#define UART0_WP7816 UART_WP7816_REG(UART0)
-#define UART0_WN7816 UART_WN7816_REG(UART0)
-#define UART0_WF7816 UART_WF7816_REG(UART0)
-#define UART0_ET7816 UART_ET7816_REG(UART0)
-#define UART0_TL7816 UART_TL7816_REG(UART0)
-#define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
-#define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
-#define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
-#define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
-#define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
-#define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
-#define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
-#define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
-/* UART1 */
-#define UART1_BDH UART_BDH_REG(UART1)
-#define UART1_BDL UART_BDL_REG(UART1)
-#define UART1_C1 UART_C1_REG(UART1)
-#define UART1_C2 UART_C2_REG(UART1)
-#define UART1_S1 UART_S1_REG(UART1)
-#define UART1_S2 UART_S2_REG(UART1)
-#define UART1_C3 UART_C3_REG(UART1)
-#define UART1_D UART_D_REG(UART1)
-#define UART1_MA1 UART_MA1_REG(UART1)
-#define UART1_MA2 UART_MA2_REG(UART1)
-#define UART1_C4 UART_C4_REG(UART1)
-#define UART1_C5 UART_C5_REG(UART1)
-#define UART1_ED UART_ED_REG(UART1)
-#define UART1_MODEM UART_MODEM_REG(UART1)
-#define UART1_IR UART_IR_REG(UART1)
-#define UART1_PFIFO UART_PFIFO_REG(UART1)
-#define UART1_CFIFO UART_CFIFO_REG(UART1)
-#define UART1_SFIFO UART_SFIFO_REG(UART1)
-#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
-#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
-#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
-#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
-/* UART2 */
-#define UART2_BDH UART_BDH_REG(UART2)
-#define UART2_BDL UART_BDL_REG(UART2)
-#define UART2_C1 UART_C1_REG(UART2)
-#define UART2_C2 UART_C2_REG(UART2)
-#define UART2_S1 UART_S1_REG(UART2)
-#define UART2_S2 UART_S2_REG(UART2)
-#define UART2_C3 UART_C3_REG(UART2)
-#define UART2_D UART_D_REG(UART2)
-#define UART2_MA1 UART_MA1_REG(UART2)
-#define UART2_MA2 UART_MA2_REG(UART2)
-#define UART2_C4 UART_C4_REG(UART2)
-#define UART2_C5 UART_C5_REG(UART2)
-#define UART2_ED UART_ED_REG(UART2)
-#define UART2_MODEM UART_MODEM_REG(UART2)
-#define UART2_IR UART_IR_REG(UART2)
-#define UART2_PFIFO UART_PFIFO_REG(UART2)
-#define UART2_CFIFO UART_CFIFO_REG(UART2)
-#define UART2_SFIFO UART_SFIFO_REG(UART2)
-#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
-#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
-#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
-#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
-/* UART3 */
-#define UART3_BDH UART_BDH_REG(UART3)
-#define UART3_BDL UART_BDL_REG(UART3)
-#define UART3_C1 UART_C1_REG(UART3)
-#define UART3_C2 UART_C2_REG(UART3)
-#define UART3_S1 UART_S1_REG(UART3)
-#define UART3_S2 UART_S2_REG(UART3)
-#define UART3_C3 UART_C3_REG(UART3)
-#define UART3_D UART_D_REG(UART3)
-#define UART3_MA1 UART_MA1_REG(UART3)
-#define UART3_MA2 UART_MA2_REG(UART3)
-#define UART3_C4 UART_C4_REG(UART3)
-#define UART3_C5 UART_C5_REG(UART3)
-#define UART3_ED UART_ED_REG(UART3)
-#define UART3_MODEM UART_MODEM_REG(UART3)
-#define UART3_IR UART_IR_REG(UART3)
-#define UART3_PFIFO UART_PFIFO_REG(UART3)
-#define UART3_CFIFO UART_CFIFO_REG(UART3)
-#define UART3_SFIFO UART_SFIFO_REG(UART3)
-#define UART3_TWFIFO UART_TWFIFO_REG(UART3)
-#define UART3_TCFIFO UART_TCFIFO_REG(UART3)
-#define UART3_RWFIFO UART_RWFIFO_REG(UART3)
-#define UART3_RCFIFO UART_RCFIFO_REG(UART3)
-/* UART4 */
-#define UART4_BDH UART_BDH_REG(UART4)
-#define UART4_BDL UART_BDL_REG(UART4)
-#define UART4_C1 UART_C1_REG(UART4)
-#define UART4_C2 UART_C2_REG(UART4)
-#define UART4_S1 UART_S1_REG(UART4)
-#define UART4_S2 UART_S2_REG(UART4)
-#define UART4_C3 UART_C3_REG(UART4)
-#define UART4_D UART_D_REG(UART4)
-#define UART4_MA1 UART_MA1_REG(UART4)
-#define UART4_MA2 UART_MA2_REG(UART4)
-#define UART4_C4 UART_C4_REG(UART4)
-#define UART4_C5 UART_C5_REG(UART4)
-#define UART4_ED UART_ED_REG(UART4)
-#define UART4_MODEM UART_MODEM_REG(UART4)
-#define UART4_IR UART_IR_REG(UART4)
-#define UART4_PFIFO UART_PFIFO_REG(UART4)
-#define UART4_CFIFO UART_CFIFO_REG(UART4)
-#define UART4_SFIFO UART_SFIFO_REG(UART4)
-#define UART4_TWFIFO UART_TWFIFO_REG(UART4)
-#define UART4_TCFIFO UART_TCFIFO_REG(UART4)
-#define UART4_RWFIFO UART_RWFIFO_REG(UART4)
-#define UART4_RCFIFO UART_RCFIFO_REG(UART4)
-/* UART5 */
-#define UART5_BDH UART_BDH_REG(UART5)
-#define UART5_BDL UART_BDL_REG(UART5)
-#define UART5_C1 UART_C1_REG(UART5)
-#define UART5_C2 UART_C2_REG(UART5)
-#define UART5_S1 UART_S1_REG(UART5)
-#define UART5_S2 UART_S2_REG(UART5)
-#define UART5_C3 UART_C3_REG(UART5)
-#define UART5_D UART_D_REG(UART5)
-#define UART5_MA1 UART_MA1_REG(UART5)
-#define UART5_MA2 UART_MA2_REG(UART5)
-#define UART5_C4 UART_C4_REG(UART5)
-#define UART5_C5 UART_C5_REG(UART5)
-#define UART5_ED UART_ED_REG(UART5)
-#define UART5_MODEM UART_MODEM_REG(UART5)
-#define UART5_IR UART_IR_REG(UART5)
-#define UART5_PFIFO UART_PFIFO_REG(UART5)
-#define UART5_CFIFO UART_CFIFO_REG(UART5)
-#define UART5_SFIFO UART_SFIFO_REG(UART5)
-#define UART5_TWFIFO UART_TWFIFO_REG(UART5)
-#define UART5_TCFIFO UART_TCFIFO_REG(UART5)
-#define UART5_RWFIFO UART_RWFIFO_REG(UART5)
-#define UART5_RCFIFO UART_RCFIFO_REG(UART5)
-
-/*!
- * @}
- */ /* end of group UART_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group UART_Peripheral_Access_Layer */
@@ -15340,53 +10332,7 @@ typedef struct {
__IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
uint8_t RESERVED_25[7];
__IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
-} USB_Type, *USB_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register accessors */
-#define USB_PERID_REG(base) ((base)->PERID)
-#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
-#define USB_REV_REG(base) ((base)->REV)
-#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
-#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
-#define USB_OTGICR_REG(base) ((base)->OTGICR)
-#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
-#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
-#define USB_ISTAT_REG(base) ((base)->ISTAT)
-#define USB_INTEN_REG(base) ((base)->INTEN)
-#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
-#define USB_ERREN_REG(base) ((base)->ERREN)
-#define USB_STAT_REG(base) ((base)->STAT)
-#define USB_CTL_REG(base) ((base)->CTL)
-#define USB_ADDR_REG(base) ((base)->ADDR)
-#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
-#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
-#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
-#define USB_TOKEN_REG(base) ((base)->TOKEN)
-#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
-#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
-#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
-#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
-#define USB_ENDPT_COUNT 16
-#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
-#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
-#define USB_CONTROL_REG(base) ((base)->CONTROL)
-#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
-#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
+} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
@@ -15397,414 +10343,350 @@ typedef struct {
* @{
*/
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID_WIDTH 6
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID_WIDTH 6
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV_WIDTH 8
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-#define USB_ADDINFO_IEHOST_WIDTH 1
-#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_AVBUSCHG_WIDTH 1
-#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_AVBUSCHG_SHIFT))&USB_OTGISTAT_AVBUSCHG_MASK)
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_B_SESS_CHG_WIDTH 1
-#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_B_SESS_CHG_SHIFT))&USB_OTGISTAT_B_SESS_CHG_MASK)
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_SESSVLDCHG_WIDTH 1
-#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_SESSVLDCHG_SHIFT))&USB_OTGISTAT_SESSVLDCHG_MASK)
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_LINE_STATE_CHG_WIDTH 1
-#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_ONEMSEC_WIDTH 1
-#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-#define USB_OTGISTAT_IDCHG_WIDTH 1
-#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_IDCHG_SHIFT))&USB_OTGISTAT_IDCHG_MASK)
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_AVBUSEN_WIDTH 1
-#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_AVBUSEN_SHIFT))&USB_OTGICR_AVBUSEN_MASK)
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_BSESSEN_WIDTH 1
-#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_BSESSEN_SHIFT))&USB_OTGICR_BSESSEN_MASK)
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_SESSVLDEN_WIDTH 1
-#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_SESSVLDEN_SHIFT))&USB_OTGICR_SESSVLDEN_MASK)
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_LINESTATEEN_WIDTH 1
-#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_ONEMSECEN_WIDTH 1
-#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-#define USB_OTGICR_IDEN_WIDTH 1
-#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_IDEN_SHIFT))&USB_OTGICR_IDEN_MASK)
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_AVBUSVLD_WIDTH 1
-#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_AVBUSVLD_SHIFT))&USB_OTGSTAT_AVBUSVLD_MASK)
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_BSESSEND_WIDTH 1
-#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_BSESSEND_SHIFT))&USB_OTGSTAT_BSESSEND_MASK)
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_SESS_VLD_WIDTH 1
-#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_SESS_VLD_SHIFT))&USB_OTGSTAT_SESS_VLD_MASK)
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_LINESTATESTABLE_WIDTH 1
-#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ONEMSECEN_WIDTH 1
-#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-#define USB_OTGSTAT_ID_WIDTH 1
-#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ID_SHIFT))&USB_OTGSTAT_ID_MASK)
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_OTGEN_WIDTH 1
-#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DMLOW_WIDTH 1
-#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPLOW_WIDTH 1
-#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-#define USB_OTGCTL_DPHIGH_WIDTH 1
-#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_USBRST_WIDTH 1
-#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_ERROR_WIDTH 1
-#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_SOFTOK_WIDTH 1
-#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_TOKDNE_WIDTH 1
-#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_SLEEP_WIDTH 1
-#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_RESUME_WIDTH 1
-#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_ATTACH_WIDTH 1
-#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-#define USB_ISTAT_STALL_WIDTH 1
-#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_USBRSTEN_WIDTH 1
-#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_ERROREN_WIDTH 1
-#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_SOFTOKEN_WIDTH 1
-#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_TOKDNEEN_WIDTH 1
-#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_SLEEPEN_WIDTH 1
-#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_RESUMEEN_WIDTH 1
-#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_ATTACHEN_WIDTH 1
-#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-#define USB_INTEN_STALLEN_WIDTH 1
-#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_PIDERR_WIDTH 1
-#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC5EOF_WIDTH 1
-#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_CRC16_WIDTH 1
-#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_DFN8_WIDTH 1
-#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_BTOERR_WIDTH 1
-#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_DMAERR_WIDTH 1
-#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-#define USB_ERRSTAT_BTSERR_WIDTH 1
-#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_PIDERREN_WIDTH 1
-#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC5EOFEN_WIDTH 1
-#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_CRC16EN_WIDTH 1
-#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_DFN8EN_WIDTH 1
-#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_BTOERREN_WIDTH 1
-#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_DMAERREN_WIDTH 1
-#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-#define USB_ERREN_BTSERREN_WIDTH 1
-#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_ODD_WIDTH 1
-#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_TX_WIDTH 1
-#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP_WIDTH 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_USBENSOFEN_WIDTH 1
-#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_ODDRST_WIDTH 1
-#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_RESUME_WIDTH 1
-#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_HOSTMODEEN_WIDTH 1
-#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_RESET_WIDTH 1
-#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH 1
-#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_SE0_WIDTH 1
-#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-#define USB_CTL_JSTATE_WIDTH 1
-#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR_WIDTH 7
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-#define USB_ADDR_LSEN_WIDTH 1
-#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA_WIDTH 7
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM_WIDTH 8
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM_WIDTH 3
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT_WIDTH 4
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID_WIDTH 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT_WIDTH 8
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA_WIDTH 8
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA_WIDTH 8
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPHSHK_WIDTH 1
-#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPSTALL_WIDTH 1
-#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPTXEN_WIDTH 1
-#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPRXEN_WIDTH 1
-#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_EPCTLDIS_WIDTH 1
-#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_RETRYDIS_WIDTH 1
-#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-#define USB_ENDPT_HOSTWOHUB_WIDTH 1
-#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_PDE_WIDTH 1
-#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-#define USB_USBCTRL_SUSP_WIDTH 1
-#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DMPD_WIDTH 1
-#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPD_WIDTH 1
-#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-#define USB_OBSERVE_DPPU_WIDTH 1
-#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-#define USB_CONTROL_DPPULLUPNONOTG_WIDTH 1
-#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_USB_RESUME_INT_WIDTH 1
-#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_SYNC_DET_WIDTH 1
-#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESMEN_WIDTH 1
-#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-#define USB_USBTRC0_USBRESET_WIDTH 1
-#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
-/* USBFRMADJUST Bit Fields */
-#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
-#define USB_USBFRMADJUST_ADJ_SHIFT 0
-#define USB_USBFRMADJUST_ADJ_WIDTH 8
-#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK (0x3FU)
+#define USB_PERID_ID_SHIFT (0U)
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK (0x3FU)
+#define USB_IDCOMP_NID_SHIFT (0U)
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK (0xFFU)
+#define USB_REV_REV_SHIFT (0U)
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT (0U)
+#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
+#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
+#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
+#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
+#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
+#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
+#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
+#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+#define USB_OTGISTAT_IDCHG_MASK (0x80U)
+#define USB_OTGISTAT_IDCHG_SHIFT (7U)
+#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_AVBUSEN_MASK (0x1U)
+#define USB_OTGICR_AVBUSEN_SHIFT (0U)
+#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
+#define USB_OTGICR_BSESSEN_MASK (0x4U)
+#define USB_OTGICR_BSESSEN_SHIFT (2U)
+#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
+#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
+#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
+#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
+#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
+#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
+#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+#define USB_OTGICR_IDEN_MASK (0x80U)
+#define USB_OTGICR_IDEN_SHIFT (7U)
+#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
+#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
+#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
+#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
+#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
+#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
+#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
+#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
+#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
+#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
+#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+#define USB_OTGSTAT_ID_MASK (0x80U)
+#define USB_OTGSTAT_ID_SHIFT (7U)
+#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT (2U)
+#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT (4U)
+#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT (5U)
+#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT (7U)
+#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK (0x1U)
+#define USB_ISTAT_USBRST_SHIFT (0U)
+#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK (0x2U)
+#define USB_ISTAT_ERROR_SHIFT (1U)
+#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT (2U)
+#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT (3U)
+#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT (4U)
+#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK (0x20U)
+#define USB_ISTAT_RESUME_SHIFT (5U)
+#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT (6U)
+#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK (0x80U)
+#define USB_ISTAT_STALL_SHIFT (7U)
+#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT (0U)
+#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK (0x2U)
+#define USB_INTEN_ERROREN_SHIFT (1U)
+#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT (2U)
+#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT (3U)
+#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT (4U)
+#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT (5U)
+#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT (6U)
+#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK (0x80U)
+#define USB_INTEN_STALLEN_SHIFT (7U)
+#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT (0U)
+#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
+#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT (2U)
+#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT (3U)
+#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT (4U)
+#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT (5U)
+#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT (7U)
+#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT (0U)
+#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
+#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT (2U)
+#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT (3U)
+#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT (4U)
+#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT (5U)
+#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT (7U)
+#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK (0x4U)
+#define USB_STAT_ODD_SHIFT (2U)
+#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK (0x8U)
+#define USB_STAT_TX_SHIFT (3U)
+#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK (0xF0U)
+#define USB_STAT_ENDP_SHIFT (4U)
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT (0U)
+#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK (0x2U)
+#define USB_CTL_ODDRST_SHIFT (1U)
+#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK (0x4U)
+#define USB_CTL_RESUME_SHIFT (2U)
+#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT (3U)
+#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK (0x10U)
+#define USB_CTL_RESET_SHIFT (4U)
+#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK (0x40U)
+#define USB_CTL_SE0_SHIFT (6U)
+#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK (0x80U)
+#define USB_CTL_JSTATE_SHIFT (7U)
+#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK (0x7FU)
+#define USB_ADDR_ADDR_SHIFT (0U)
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK (0x80U)
+#define USB_ADDR_LSEN_SHIFT (7U)
+#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT (0U)
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT (0U)
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT (4U)
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT (0U)
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT (0U)
+#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT (1U)
+#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT (2U)
+#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT (3U)
+#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
+#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT (6U)
+#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
+#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_PDE_MASK (0x40U)
+#define USB_USBCTRL_PDE_SHIFT (6U)
+#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT (7U)
+#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT (4U)
+#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT (6U)
+#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT (7U)
+#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
+#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
+#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT (7U)
+#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
/*!
* @}
@@ -15816,7 +10698,6 @@ typedef struct {
#define USB0_BASE (0x40072000u)
/** Peripheral USB0 base pointer */
#define USB0 ((USB_Type *)USB0_BASE)
-#define USB0_BASE_PTR (USB0)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { USB0_BASE }
/** Array initializer of USB peripheral base pointers */
@@ -15824,70 +10705,6 @@ typedef struct {
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS { USB0_IRQn }
-/* ----------------------------------------------------------------------------
- -- USB - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
- * @{
- */
-
-
-/* USB - Register instance definitions */
-/* USB0 */
-#define USB0_PERID USB_PERID_REG(USB0)
-#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
-#define USB0_REV USB_REV_REG(USB0)
-#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
-#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
-#define USB0_OTGICR USB_OTGICR_REG(USB0)
-#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
-#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
-#define USB0_ISTAT USB_ISTAT_REG(USB0)
-#define USB0_INTEN USB_INTEN_REG(USB0)
-#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
-#define USB0_ERREN USB_ERREN_REG(USB0)
-#define USB0_STAT USB_STAT_REG(USB0)
-#define USB0_CTL USB_CTL_REG(USB0)
-#define USB0_ADDR USB_ADDR_REG(USB0)
-#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
-#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
-#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
-#define USB0_TOKEN USB_TOKEN_REG(USB0)
-#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
-#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
-#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
-#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
-#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
-#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
-#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
-#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
-#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
-#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
-#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
-#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
-#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
-#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
-#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
-#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
-#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
-#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
-#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
-#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
-#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
-#define USB0_CONTROL USB_CONTROL_REG(USB0)
-#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
-#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
-
-/* USB - Register array accessors */
-#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
-
-/*!
- * @}
- */ /* end of group USB_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
@@ -15914,31 +10731,7 @@ typedef struct {
__IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
__IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
};
-} USBDCD_Type, *USBDCD_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- USBDCD - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
- * @{
- */
-
-
-/* USBDCD - Register accessors */
-#define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
-#define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
-#define USBDCD_STATUS_REG(base) ((base)->STATUS)
-#define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
-#define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
-#define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
-#define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
-
-/*!
- * @}
- */ /* end of group USBDCD_Register_Accessor_Macros */
-
+} USBDCD_Type;
/* ----------------------------------------------------------------------------
-- USBDCD Register Masks
@@ -15949,97 +10742,83 @@ typedef struct {
* @{
*/
-/* CONTROL Bit Fields */
-#define USBDCD_CONTROL_IACK_MASK 0x1u
-#define USBDCD_CONTROL_IACK_SHIFT 0
-#define USBDCD_CONTROL_IACK_WIDTH 1
-#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IACK_SHIFT))&USBDCD_CONTROL_IACK_MASK)
-#define USBDCD_CONTROL_IF_MASK 0x100u
-#define USBDCD_CONTROL_IF_SHIFT 8
-#define USBDCD_CONTROL_IF_WIDTH 1
-#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IF_SHIFT))&USBDCD_CONTROL_IF_MASK)
-#define USBDCD_CONTROL_IE_MASK 0x10000u
-#define USBDCD_CONTROL_IE_SHIFT 16
-#define USBDCD_CONTROL_IE_WIDTH 1
-#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_IE_SHIFT))&USBDCD_CONTROL_IE_MASK)
-#define USBDCD_CONTROL_BC12_MASK 0x20000u
-#define USBDCD_CONTROL_BC12_SHIFT 17
-#define USBDCD_CONTROL_BC12_WIDTH 1
-#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_BC12_SHIFT))&USBDCD_CONTROL_BC12_MASK)
-#define USBDCD_CONTROL_START_MASK 0x1000000u
-#define USBDCD_CONTROL_START_SHIFT 24
-#define USBDCD_CONTROL_START_WIDTH 1
-#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_START_SHIFT))&USBDCD_CONTROL_START_MASK)
-#define USBDCD_CONTROL_SR_MASK 0x2000000u
-#define USBDCD_CONTROL_SR_SHIFT 25
-#define USBDCD_CONTROL_SR_WIDTH 1
-#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CONTROL_SR_SHIFT))&USBDCD_CONTROL_SR_MASK)
-/* CLOCK Bit Fields */
-#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
-#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
-#define USBDCD_CLOCK_CLOCK_UNIT_WIDTH 1
-#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_UNIT_SHIFT))&USBDCD_CLOCK_CLOCK_UNIT_MASK)
-#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
-#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
-#define USBDCD_CLOCK_CLOCK_SPEED_WIDTH 10
-#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
-/* STATUS Bit Fields */
-#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
-#define USBDCD_STATUS_SEQ_RES_SHIFT 16
-#define USBDCD_STATUS_SEQ_RES_WIDTH 2
-#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
-#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
-#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
-#define USBDCD_STATUS_SEQ_STAT_WIDTH 2
-#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
-#define USBDCD_STATUS_ERR_MASK 0x100000u
-#define USBDCD_STATUS_ERR_SHIFT 20
-#define USBDCD_STATUS_ERR_WIDTH 1
-#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ERR_SHIFT))&USBDCD_STATUS_ERR_MASK)
-#define USBDCD_STATUS_TO_MASK 0x200000u
-#define USBDCD_STATUS_TO_SHIFT 21
-#define USBDCD_STATUS_TO_WIDTH 1
-#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_TO_SHIFT))&USBDCD_STATUS_TO_MASK)
-#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
-#define USBDCD_STATUS_ACTIVE_SHIFT 22
-#define USBDCD_STATUS_ACTIVE_WIDTH 1
-#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_ACTIVE_SHIFT))&USBDCD_STATUS_ACTIVE_MASK)
-/* TIMER0 Bit Fields */
-#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
-#define USBDCD_TIMER0_TUNITCON_SHIFT 0
-#define USBDCD_TIMER0_TUNITCON_WIDTH 12
-#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
-#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
-#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
-#define USBDCD_TIMER0_TSEQ_INIT_WIDTH 10
-#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
-/* TIMER1 Bit Fields */
-#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
-#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
-#define USBDCD_TIMER1_TVDPSRC_ON_WIDTH 10
-#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
-#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
-#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
-#define USBDCD_TIMER1_TDCD_DBNC_WIDTH 10
-#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
-/* TIMER2_BC11 Bit Fields */
-#define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
-#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
-#define USBDCD_TIMER2_BC11_CHECK_DM_WIDTH 4
-#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON_WIDTH 10
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
-/* TIMER2_BC12 Bit Fields */
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON_WIDTH 10
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_WIDTH 10
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+/*! @name CONTROL - Control register */
+#define USBDCD_CONTROL_IACK_MASK (0x1U)
+#define USBDCD_CONTROL_IACK_SHIFT (0U)
+#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK (0x100U)
+#define USBDCD_CONTROL_IF_SHIFT (8U)
+#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK (0x10000U)
+#define USBDCD_CONTROL_IE_SHIFT (16U)
+#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK (0x20000U)
+#define USBDCD_CONTROL_BC12_SHIFT (17U)
+#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK (0x1000000U)
+#define USBDCD_CONTROL_START_SHIFT (24U)
+#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK (0x2000000U)
+#define USBDCD_CONTROL_SR_SHIFT (25U)
+#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
+
+/*! @name CLOCK - Clock register */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
+#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+
+/*! @name STATUS - Status register */
+#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
+#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
+#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK (0x100000U)
+#define USBDCD_STATUS_ERR_SHIFT (20U)
+#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK (0x200000U)
+#define USBDCD_STATUS_TO_SHIFT (21U)
+#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
+#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
+#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
+
+/*! @name TIMER0 - TIMER0 register */
+#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
+#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+
+/*! @name TIMER1 - TIMER1 register */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+
+/*! @name TIMER2_BC11 - TIMER2_BC11 register */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
+#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+
+/*! @name TIMER2_BC12 - TIMER2_BC12 register */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
/*!
* @}
@@ -16051,7 +10830,6 @@ typedef struct {
#define USBDCD_BASE (0x40035000u)
/** Peripheral USBDCD base pointer */
#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
-#define USBDCD_BASE_PTR (USBDCD)
/** Array initializer of USBDCD peripheral base addresses */
#define USBDCD_BASE_ADDRS { USBDCD_BASE }
/** Array initializer of USBDCD peripheral base pointers */
@@ -16059,31 +10837,6 @@ typedef struct {
/** Interrupt vectors for the USBDCD peripheral type */
#define USBDCD_IRQS { USBDCD_IRQn }
-/* ----------------------------------------------------------------------------
- -- USBDCD - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
- * @{
- */
-
-
-/* USBDCD - Register instance definitions */
-/* USBDCD */
-#define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
-#define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
-#define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
-#define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
-#define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
-#define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
-#define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
-
-/*!
- * @}
- */ /* end of group USBDCD_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group USBDCD_Peripheral_Access_Layer */
@@ -16102,26 +10855,7 @@ typedef struct {
typedef struct {
__IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
__IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type, *VREF_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register accessors */
-#define VREF_TRM_REG(base) ((base)->TRM)
-#define VREF_SC_REG(base) ((base)->SC)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
+} VREF_Type;
/* ----------------------------------------------------------------------------
-- VREF Register Masks
@@ -16132,36 +10866,31 @@ typedef struct {
* @{
*/
-/* TRM Bit Fields */
-#define VREF_TRM_TRIM_MASK 0x3Fu
-#define VREF_TRM_TRIM_SHIFT 0
-#define VREF_TRM_TRIM_WIDTH 6
-#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
-#define VREF_TRM_CHOPEN_MASK 0x40u
-#define VREF_TRM_CHOPEN_SHIFT 6
-#define VREF_TRM_CHOPEN_WIDTH 1
-#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_CHOPEN_SHIFT))&VREF_TRM_CHOPEN_MASK)
-/* SC Bit Fields */
-#define VREF_SC_MODE_LV_MASK 0x3u
-#define VREF_SC_MODE_LV_SHIFT 0
-#define VREF_SC_MODE_LV_WIDTH 2
-#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
-#define VREF_SC_VREFST_MASK 0x4u
-#define VREF_SC_VREFST_SHIFT 2
-#define VREF_SC_VREFST_WIDTH 1
-#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFST_SHIFT))&VREF_SC_VREFST_MASK)
-#define VREF_SC_ICOMPEN_MASK 0x20u
-#define VREF_SC_ICOMPEN_SHIFT 5
-#define VREF_SC_ICOMPEN_WIDTH 1
-#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_ICOMPEN_SHIFT))&VREF_SC_ICOMPEN_MASK)
-#define VREF_SC_REGEN_MASK 0x40u
-#define VREF_SC_REGEN_SHIFT 6
-#define VREF_SC_REGEN_WIDTH 1
-#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_REGEN_SHIFT))&VREF_SC_REGEN_MASK)
-#define VREF_SC_VREFEN_MASK 0x80u
-#define VREF_SC_VREFEN_SHIFT 7
-#define VREF_SC_VREFEN_WIDTH 1
-#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_VREFEN_SHIFT))&VREF_SC_VREFEN_MASK)
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK (0x3FU)
+#define VREF_TRM_TRIM_SHIFT (0U)
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT (6U)
+#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK (0x3U)
+#define VREF_SC_MODE_LV_SHIFT (0U)
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK (0x4U)
+#define VREF_SC_VREFST_SHIFT (2U)
+#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT (5U)
+#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK (0x40U)
+#define VREF_SC_REGEN_SHIFT (6U)
+#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK (0x80U)
+#define VREF_SC_VREFEN_SHIFT (7U)
+#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+
/*!
* @}
@@ -16173,32 +10902,11 @@ typedef struct {
#define VREF_BASE (0x40074000u)
/** Peripheral VREF base pointer */
#define VREF ((VREF_Type *)VREF_BASE)
-#define VREF_BASE_PTR (VREF)
/** Array initializer of VREF peripheral base addresses */
#define VREF_BASE_ADDRS { VREF_BASE }
/** Array initializer of VREF peripheral base pointers */
#define VREF_BASE_PTRS { VREF }
-/* ----------------------------------------------------------------------------
- -- VREF - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
- * @{
- */
-
-
-/* VREF - Register instance definitions */
-/* VREF */
-#define VREF_TRM VREF_TRM_REG(VREF)
-#define VREF_SC VREF_SC_REG(VREF)
-
-/*!
- * @}
- */ /* end of group VREF_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group VREF_Peripheral_Access_Layer */
@@ -16227,36 +10935,7 @@ typedef struct {
__IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
__IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
__IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
-} WDOG_Type, *WDOG_MemMapPtr;
-
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register accessors */
-#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
-#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
-#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
-#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
-#define WDOG_WINH_REG(base) ((base)->WINH)
-#define WDOG_WINL_REG(base) ((base)->WINL)
-#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
-#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
-#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
-#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
-#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
-#define WDOG_PRESC_REG(base) ((base)->PRESC)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
+} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
@@ -16267,110 +10946,99 @@ typedef struct {
* @{
*/
-/* STCTRLH Bit Fields */
-#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
-#define WDOG_STCTRLH_WDOGEN_SHIFT 0
-#define WDOG_STCTRLH_WDOGEN_WIDTH 1
-#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
-#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
-#define WDOG_STCTRLH_CLKSRC_SHIFT 1
-#define WDOG_STCTRLH_CLKSRC_WIDTH 1
-#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
-#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
-#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
-#define WDOG_STCTRLH_IRQRSTEN_WIDTH 1
-#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
-#define WDOG_STCTRLH_WINEN_MASK 0x8u
-#define WDOG_STCTRLH_WINEN_SHIFT 3
-#define WDOG_STCTRLH_WINEN_WIDTH 1
-#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
-#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
-#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
-#define WDOG_STCTRLH_ALLOWUPDATE_WIDTH 1
-#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
-#define WDOG_STCTRLH_DBGEN_MASK 0x20u
-#define WDOG_STCTRLH_DBGEN_SHIFT 5
-#define WDOG_STCTRLH_DBGEN_WIDTH 1
-#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
-#define WDOG_STCTRLH_STOPEN_MASK 0x40u
-#define WDOG_STCTRLH_STOPEN_SHIFT 6
-#define WDOG_STCTRLH_STOPEN_WIDTH 1
-#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
-#define WDOG_STCTRLH_WAITEN_MASK 0x80u
-#define WDOG_STCTRLH_WAITEN_SHIFT 7
-#define WDOG_STCTRLH_WAITEN_WIDTH 1
-#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
-#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
-#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
-#define WDOG_STCTRLH_TESTWDOG_WIDTH 1
-#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
-#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
-#define WDOG_STCTRLH_TESTSEL_SHIFT 11
-#define WDOG_STCTRLH_TESTSEL_WIDTH 1
-#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
-#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
-#define WDOG_STCTRLH_BYTESEL_SHIFT 12
-#define WDOG_STCTRLH_BYTESEL_WIDTH 2
-#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
-#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
-#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
-#define WDOG_STCTRLH_DISTESTWDOG_WIDTH 1
-#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
-/* STCTRLL Bit Fields */
-#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
-#define WDOG_STCTRLL_INTFLG_SHIFT 15
-#define WDOG_STCTRLL_INTFLG_WIDTH 1
-#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
-/* TOVALH Bit Fields */
-#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
-#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
-#define WDOG_TOVALH_TOVALHIGH_WIDTH 16
-#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
-/* TOVALL Bit Fields */
-#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
-#define WDOG_TOVALL_TOVALLOW_SHIFT 0
-#define WDOG_TOVALL_TOVALLOW_WIDTH 16
-#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
-/* WINH Bit Fields */
-#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
-#define WDOG_WINH_WINHIGH_SHIFT 0
-#define WDOG_WINH_WINHIGH_WIDTH 16
-#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
-/* WINL Bit Fields */
-#define WDOG_WINL_WINLOW_MASK 0xFFFFu
-#define WDOG_WINL_WINLOW_SHIFT 0
-#define WDOG_WINL_WINLOW_WIDTH 16
-#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
-/* REFRESH Bit Fields */
-#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
-#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
-#define WDOG_REFRESH_WDOGREFRESH_WIDTH 16
-#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
-/* UNLOCK Bit Fields */
-#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
-#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
-#define WDOG_UNLOCK_WDOGUNLOCK_WIDTH 16
-#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
-/* TMROUTH Bit Fields */
-#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
-#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
-#define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH 16
-#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
-/* TMROUTL Bit Fields */
-#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
-#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
-#define WDOG_TMROUTL_TIMEROUTLOW_WIDTH 16
-#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
-/* RSTCNT Bit Fields */
-#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
-#define WDOG_RSTCNT_RSTCNT_SHIFT 0
-#define WDOG_RSTCNT_RSTCNT_WIDTH 16
-#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
-/* PRESC Bit Fields */
-#define WDOG_PRESC_PRESCVAL_MASK 0x700u
-#define WDOG_PRESC_PRESCVAL_SHIFT 8
-#define WDOG_PRESC_PRESCVAL_WIDTH 3
-#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
+#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
+#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
+#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT (3U)
+#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
+#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
+#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
+#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
+#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
+#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
+#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
+#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
+#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+
+/*! @name WINH - Watchdog Window Register High */
+#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT (0U)
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+
+/*! @name WINL - Watchdog Window Register Low */
+#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT (0U)
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+
+/*! @name REFRESH - Watchdog Refresh register */
+#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+
+/*! @name UNLOCK - Watchdog Unlock register */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+
+/*! @name RSTCNT - Watchdog Reset Count register */
+#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+
+/*! @name PRESC - Watchdog Prescaler register */
+#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
/*!
* @}
@@ -16382,7 +11050,6 @@ typedef struct {
#define WDOG_BASE (0x40052000u)
/** Peripheral WDOG base pointer */
#define WDOG ((WDOG_Type *)WDOG_BASE)
-#define WDOG_BASE_PTR (WDOG)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { WDOG_BASE }
/** Array initializer of WDOG peripheral base pointers */
@@ -16390,36 +11057,6 @@ typedef struct {
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS { WDOG_EWM_IRQn }
-/* ----------------------------------------------------------------------------
- -- WDOG - Register accessor macros
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
- * @{
- */
-
-
-/* WDOG - Register instance definitions */
-/* WDOG */
-#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
-#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
-#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
-#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
-#define WDOG_WINH WDOG_WINH_REG(WDOG)
-#define WDOG_WINL WDOG_WINL_REG(WDOG)
-#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
-#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
-#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
-#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
-#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
-#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
-
-/*!
- * @}
- */ /* end of group WDOG_Register_Accessor_Macros */
-
-
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
@@ -16447,29 +11084,66 @@ typedef struct {
/* ----------------------------------------------------------------------------
- -- Backward Compatibility
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
-#define PTA_BASE_PTR GPIOA_BASE_PTR
+#define DSPI0 SPI0
+#define DSPI1 SPI1
+#define DSPI2 SPI2
+#define FLEXCAN0 CAN0
#define PTA_BASE GPIOA_BASE
#define PTA GPIOA
-#define PTB_BASE_PTR GPIOB_BASE_PTR
#define PTB_BASE GPIOB_BASE
#define PTB GPIOB
-#define PTC_BASE_PTR GPIOC_BASE_PTR
#define PTC_BASE GPIOC_BASE
#define PTC GPIOC
-#define PTD_BASE_PTR GPIOD_BASE_PTR
#define PTD_BASE GPIOD_BASE
#define PTD GPIOD
-#define PTE_BASE_PTR GPIOE_BASE_PTR
#define PTE_BASE GPIOE_BASE
#define PTE GPIOE
+#define DMAMUX0 DMAMUX
#define SIM_SCGC6_FTFL_MASK SIM_SCGC6_FTF_MASK
#define SIM_SCGC6_FTFL_SHIFT SIM_SCGC6_FTF_SHIFT
#define MCG_S_LOLS_MASK MCG_S_LOLS0_MASK
@@ -16481,24 +11155,15 @@ typedef struct {
#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
-#define Watchdog_IRQn WDOG_EWM_IRQn
-#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
-#define LPTimer_IRQn LPTMR0_IRQn
-#define LPTimer_IRQHandler LPTMR0_IRQHandler
-#define LLW_IRQn LLWU_IRQn
-#define LLW_IRQHandler LLWU_IRQHandler
-
-#define OSC0 OSC
+#define Watchdog_IRQn WDOG_EWM_IRQn
+#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
+#define LPTimer_IRQn LPTMR0_IRQn
+#define LPTimer_IRQHandler LPTMR0_IRQHandler
+#define LLW_IRQn LLWU_IRQn
+#define LLW_IRQHandler LLWU_IRQHandler
+
/*!
* @}
- */ /* end of group Backward_Compatibility_Symbols */
-
+ */ /* end of group SDK_Compatibility_Symbols */
-#else /* #if !defined(MK22FA12_H_) */
- /* There is already included the same memory map. Check if it is compatible (has the same major version) */
- #if (MCU_MEM_MAP_VERSION != 0x0100u)
- #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
- #warning There are included two not compatible versions of memory maps. Please check possible differences.
- #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
- #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
-#endif /* #if !defined(MK22FA12_H_) */
+#endif /* _MK22FA12_H_ */
--
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