From 2d980c545dc012d6b5df43cef4a7060987530b29 Mon Sep 17 00:00:00 2001
From: Vincent Dupont <vincent@otakeys.com>
Date: Thu, 8 Jun 2017 18:32:09 +0200
Subject: [PATCH] boards/nucleo144-f207: convert to stmclk
---
boards/nucleo144-f207/include/periph_conf.h | 27 ++++++++++-----------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/boards/nucleo144-f207/include/periph_conf.h b/boards/nucleo144-f207/include/periph_conf.h
index 114df36f18..0d5b00cce9 100644
--- a/boards/nucleo144-f207/include/periph_conf.h
+++ b/boards/nucleo144-f207/include/periph_conf.h
@@ -31,22 +31,21 @@ extern "C" {
* @name Clock system configuration
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (120000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
-#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
-#define CLOCK_PLL_P (2U)
-#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 120MHz */
+#define CLOCK_CORECLOCK (120000000U)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
--
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