diff --git a/boards/bluepill/Makefile b/boards/bluepill/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f8fcbb53a06595771dae356338a7bf2c0673734d
--- /dev/null
+++ b/boards/bluepill/Makefile
@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/bluepill/Makefile.dep b/boards/bluepill/Makefile.dep
new file mode 100644
index 0000000000000000000000000000000000000000..5472bf8b8d8fd463a18815c0f10e5d348f90fe51
--- /dev/null
+++ b/boards/bluepill/Makefile.dep
@@ -0,0 +1,3 @@
+ifneq (,$(filter saul_default,$(USEMODULE)))
+ USEMODULE += saul_gpio
+endif
diff --git a/boards/bluepill/Makefile.features b/boards/bluepill/Makefile.features
new file mode 100644
index 0000000000000000000000000000000000000000..16e76886f0efd1dda1e8337c98fc0971c4476c11
--- /dev/null
+++ b/boards/bluepill/Makefile.features
@@ -0,0 +1,14 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+FEATURES_PROVIDED += periph_adc
+
+# Various other features (if any)
+FEATURES_PROVIDED += cpp
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m3_2
diff --git a/boards/bluepill/Makefile.include b/boards/bluepill/Makefile.include
new file mode 100644
index 0000000000000000000000000000000000000000..b666f26bc5d4f0928e4b8c6b83497af5a04cafe8
--- /dev/null
+++ b/boards/bluepill/Makefile.include
@@ -0,0 +1,13 @@
+## the cpu to build for
+export CPU = stm32f1
+export CPU_MODEL = stm32f103c8
+
+# define the default port depending on the host OS
+PORT_LINUX ?= /dev/ttyUSB0
+PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
+
+# setup serial terminal
+include $(RIOTMAKE)/tools/serial.inc.mk
+
+# this board uses openocd
+include $(RIOTMAKE)/tools/openocd.inc.mk
diff --git a/boards/bluepill/board.c b/boards/bluepill/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..4ee5a315bf976c9af2ebaa3f0a6ae19db4a19fa6
--- /dev/null
+++ b/boards/bluepill/board.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2015 TriaGnoSys GmbH
+ * 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_bluepill
+ * @{
+ *
+ * @file
+ * @brief Board specific implementations for the bluepill board
+ *
+ * @author VÃctor Ariño <victor.arino@triagnosys.com>
+ * @author Sören Tempel <tempel@uni-bremen.de>
+ * @author Tristan Bruns <tbruns@uni-bremen.de>
+ * @author Alexander Kurth <kurth1@uni-bremen.de>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+
+void board_init(void)
+{
+ cpu_init();
+ gpio_init(LED0_PIN, GPIO_OUT);
+}
diff --git a/boards/bluepill/dist/openocd.cfg b/boards/bluepill/dist/openocd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a93406dfb5fc43d546d27ee6b008dcccd5464c0f
--- /dev/null
+++ b/boards/bluepill/dist/openocd.cfg
@@ -0,0 +1,7 @@
+source [find interface/stlink-v2.cfg]
+transport select hla_swd
+
+source [find target/stm32f1x.cfg]
+reset_config none separate
+
+$_TARGETNAME configure -rtos auto
diff --git a/boards/bluepill/include/board.h b/boards/bluepill/include/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..f0b6d7c89aa4761192d2d80e3f7de793266894b6
--- /dev/null
+++ b/boards/bluepill/include/board.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2015 TriaGnoSys GmbH
+ * 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup boards_bluepill Bluepill board
+ * @ingroup boards
+ * @brief Support for the stm32f103c8 based bluepill board.
+ *
+ * This board can be bought very cheaply on sides like eBay or
+ * AliExpress. Although the MCU nominally has 64 KiB ROM, most of them
+ * have 128 KiB ROM. For more information see:
+ * http://wiki.stm32duino.com/index.php?title=Blue_Pill
+ *
+ * @{
+ *
+ * @file
+ * @brief Peripheral MCU configuration for the bluepill board
+ *
+ * @author VÃctor Ariño <victor.arino@triagnosys.com>
+ * @author Sören Tempel <tempel@uni-bremen.de>
+ * @author Tristan Bruns <tbruns@uni-bremen.de>
+ * @author Alexander Kurth <kurth1@uni-bremen.de>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Macros for controlling the on-board LED.
+ * @{
+ */
+#define LED0_PORT GPIOC
+#define LED0_PIN GPIO_PIN(PORT_C, 13)
+#define LED0_MASK (1 << 13)
+
+#define LED0_ON (LED0_PORT->BSRR = LED0_MASK)
+#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 16))
+#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
+/** @} */
+
+/**
+ * @brief Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+/**
+ * @brief Use the 2nd UART for STDIO on this board
+ */
+#define UART_STDIO_DEV UART_DEV(1)
+
+/**
+ * @name xtimer configuration
+ * @{
+ */
+#define XTIMER_WIDTH (16)
+#define XTIMER_BACKOFF 5
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */
diff --git a/boards/bluepill/include/gpio_params.h b/boards/bluepill/include/gpio_params.h
new file mode 100644
index 0000000000000000000000000000000000000000..f72ebdaeee250ca9766a36f9171db83e83fbe985
--- /dev/null
+++ b/boards/bluepill/include/gpio_params.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2017 HAW Hamburg
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_stm32f130c8t6
+ * @{
+ *
+ * @file
+ * @brief Board specific configuration of direct mapped GPIOs
+ *
+ * @author Sebastian Meiling <s@mlng.net>
+ */
+
+#ifndef GPIO_PARAMS_H
+#define GPIO_PARAMS_H
+
+#include "board.h"
+#include "saul/periph.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief GPIO pin configuration
+ */
+static const saul_gpio_params_t saul_gpio_params[] =
+{
+ {
+ .name = "LED",
+ .pin = LED0_PIN,
+ .mode = GPIO_OUT
+ },
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO_PARAMS_H */
+/** @} */
diff --git a/boards/bluepill/include/periph_conf.h b/boards/bluepill/include/periph_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..5cc9e7d12a6a723464e0969205d0281c5487d31e
--- /dev/null
+++ b/boards/bluepill/include/periph_conf.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2015 TriaGnoSys GmbH
+ * 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_bluepill
+ * @{
+ *
+ * @file
+ * @brief Peripheral MCU configuration for the bluepill board
+ *
+ * @author VÃctor Ariño <victor.arino@triagnosys.com>
+ * @author Sören Tempel <tempel@uni-bremen.de>
+ * @author Tristan Bruns <tbruns@uni-bremen.de>
+ * @author Alexander Kurth <kurth1@uni-bremen.de>
+ *
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @{
+ */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1U)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
+/** @} */
+
+/**
+ * @name ADC configuration
+ * @{
+ */
+#define ADC_CONFIG { \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 0), .chan = 0 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 1), .chan = 1 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 2), .chan = 2 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 3), .chan = 3 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 4), .chan = 4 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 5), .chan = 5 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 6), .chan = 6 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_A, 7), .chan = 7 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, \
+ { .dev = 0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, \
+}
+
+#define ADC_NUMOF 10
+/** @} */
+
+/**
+ * @name Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+ {
+ .dev = TIM2,
+ .max = 0x0000ffff,
+ .rcc_mask = RCC_APB1ENR_TIM2EN,
+ .bus = APB1,
+ .irqn = TIM2_IRQn
+ },
+ {
+ .dev = TIM3,
+ .max = 0x0000ffff,
+ .rcc_mask = RCC_APB1ENR_TIM3EN,
+ .bus = APB1,
+ .irqn = TIM3_IRQn
+ },
+ {
+ .dev = TIM4,
+ .max = 0x0000ffff,
+ .rcc_mask = RCC_APB1ENR_TIM4EN,
+ .bus = APB1,
+ .irqn = TIM4_IRQn
+ }
+};
+
+#define TIMER_0_ISR isr_tim2
+#define TIMER_1_ISR isr_tim3
+#define TIMER_2_ISR isr_tim4
+
+#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @name UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+ {
+ .dev = USART1,
+ .rcc_mask = RCC_APB2ENR_USART1EN,
+ .rx_pin = GPIO_PIN(PORT_A, 10),
+ .tx_pin = GPIO_PIN(PORT_A, 9),
+ .bus = APB2,
+ .irqn = USART1_IRQn
+ },
+ {
+ .dev = USART2,
+ .rcc_mask = RCC_APB1ENR_USART2EN,
+ .rx_pin = GPIO_PIN(PORT_A, 3),
+ .tx_pin = GPIO_PIN(PORT_A, 2),
+ .bus = APB1,
+ .irqn = USART2_IRQn
+ },
+ {
+ .dev = USART3,
+ .rcc_mask = RCC_APB1ENR_USART3EN,
+ .rx_pin = GPIO_PIN(PORT_B, 11),
+ .tx_pin = GPIO_PIN(PORT_B, 10),
+ .bus = APB1,
+ .irqn = USART3_IRQn
+ }
+};
+
+#define UART_0_ISR (isr_usart1)
+#define UART_1_ISR (isr_usart2)
+#define UART_2_ISR (isr_usart3)
+
+#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @name PWM configuration
+ * @{
+ */
+static const pwm_conf_t pwm_config[] = {
+ {
+ .dev = TIM1,
+ .rcc_mask = RCC_APB2ENR_TIM1EN,
+ .chan = { { .pin = GPIO_PIN(PORT_A, 8), .cc_chan = 0 },
+ { .pin = GPIO_PIN(PORT_A, 9), .cc_chan = 1 },
+ { .pin = GPIO_PIN(PORT_A, 10), .cc_chan = 2 },
+ { .pin = GPIO_PIN(PORT_A, 11), .cc_chan = 3 } },
+ .af = GPIO_AF_OUT_PP,
+ .bus = APB2
+ }
+};
+
+#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
+/** @} */
+
+/**
+ * @name SPI configuration
+ *
+ * @note The spi_divtable is auto-generated from
+ * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+ { /* for APB1 @ 36000000Hz */
+ 7, /* -> 140625Hz */
+ 6, /* -> 281250Hz */
+ 4, /* -> 1125000Hz */
+ 2, /* -> 4500000Hz */
+ 1 /* -> 9000000Hz */
+ },
+ { /* for APB2 @ 72000000Hz */
+ 7, /* -> 281250Hz */
+ 7, /* -> 281250Hz */
+ 5, /* -> 1125000Hz */
+ 3, /* -> 4500000Hz */
+ 2 /* -> 9000000Hz */
+ }
+};
+
+static const spi_conf_t spi_config[] = {
+ {
+ .dev = SPI1,
+ .mosi_pin = GPIO_PIN(PORT_A, 7),
+ .miso_pin = GPIO_PIN(PORT_A, 6),
+ .sclk_pin = GPIO_PIN(PORT_A, 5),
+ .cs_pin = GPIO_PIN(PORT_A, 4),
+ .rccmask = RCC_APB2ENR_SPI1EN,
+ .apbbus = APB2
+ },
+ {
+ .dev = SPI2,
+ .mosi_pin = GPIO_PIN(PORT_B, 15),
+ .miso_pin = GPIO_PIN(PORT_B, 14),
+ .sclk_pin = GPIO_PIN(PORT_B, 13),
+ .cs_pin = GPIO_PIN(PORT_B, 12),
+ .rccmask = RCC_APB1ENR_SPI2EN,
+ .apbbus = APB1
+ }
+};
+
+#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
diff --git a/cpu/stm32f1/include/cpu_conf.h b/cpu/stm32f1/include/cpu_conf.h
index 4e95bad86fe96f5b5e50ba18701acec410171947..3e06a3040f36bef1c0ca2adf53212cced43487fd 100644
--- a/cpu/stm32f1/include/cpu_conf.h
+++ b/cpu/stm32f1/include/cpu_conf.h
@@ -25,7 +25,7 @@
#include "cpu_conf_common.h"
-#if defined(CPU_MODEL_STM32F103CB) || defined(CPU_MODEL_STM32F103RB)
+#if defined(CPU_MODEL_STM32F103C8) || defined(CPU_MODEL_STM32F103CB) || defined(CPU_MODEL_STM32F103RB)
#include "vendor/stm32f103xb.h"
#elif defined(CPU_MODEL_STM32F103RE)
#include "vendor/stm32f103xe.h"
diff --git a/examples/dtls-echo/Makefile b/examples/dtls-echo/Makefile
index 4380dd665c860a0101eb6b162ddb78cc0da3b8e2..26aeb758467ad2cdbbe8630dfb52f4900b666e02 100644
--- a/examples/dtls-echo/Makefile
+++ b/examples/dtls-echo/Makefile
@@ -12,7 +12,7 @@ BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno chronos \
msb-430 msb-430h telosb waspmote-pro wsn430-v1_3b wsn430-v1_4 \
z1
-BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 calliope-mini \
+BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 bluepill calliope-mini \
cc2650-launchpad cc2650stk maple-mini \
microbit nrf51dongle nrf6310 nucleo32-f031 \
nucleo32-f042 nucleo32-f303 nucleo32-l031 nucleo-f030 \
diff --git a/examples/gnrc_border_router/Makefile b/examples/gnrc_border_router/Makefile
index 9b2df0637c88c128239502a5dcac11287965bdca..99a63aecd8f0b9ecbc2ac133c4ef1986b858a64a 100644
--- a/examples/gnrc_border_router/Makefile
+++ b/examples/gnrc_border_router/Makefile
@@ -7,7 +7,7 @@ BOARD ?= samr21-xpro
# This has to be the absolute path to the RIOT base directory:
RIOTBASE ?= $(CURDIR)/../..
-BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 calliope-mini \
+BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 bluepill calliope-mini \
cc2650-launchpad cc2650stk maple-mini \
microbit msb-430 msb-430h nrf51dongle nrf6310 \
nucleo32-f031 nucleo32-f042 nucleo32-f303 nucleo32-l031 \
diff --git a/examples/javascript/Makefile b/examples/javascript/Makefile
index 21848e6638f5a9c2515af2106640a0cf3fe6a0bb..54718a83594931b3b38855008078427aac4506de 100644
--- a/examples/javascript/Makefile
+++ b/examples/javascript/Makefile
@@ -4,7 +4,7 @@ APPLICATION = riot_javascript
# default BOARD environment
BOARD ?= native
-BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 calliope-mini \
+BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 bluepill calliope-mini \
cc2650-launchpad cc2650stk maple-mini \
microbit nrf51dongle nrf6310 nucleo-f030 nucleo-f070 \
nucleo-f072 nucleo-f103 nucleo-f302 nucleo-f334 nucleo-f410 \
diff --git a/tests/gnrc_netif2/Makefile b/tests/gnrc_netif2/Makefile
index 92e7d4ea0b6de668064ef91ac8336c29d6559832..ebe8ef8156de660613c93f284babcd13fb24645f 100644
--- a/tests/gnrc_netif2/Makefile
+++ b/tests/gnrc_netif2/Makefile
@@ -2,7 +2,7 @@
APPLICATION = gnrc_ipv6_nib
include ../Makefile.tests_common
-BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 calliope-mini \
+BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 bluepill calliope-mini \
cc2650-launchpad cc2650stk chronos maple-mini \
microbit msb-430 msb-430h nrf51dongle nrf6310 \
nucleo-f030 nucleo-f070 nucleo-f072 nucleo-f103 \
diff --git a/tests/thread_cooperation/Makefile b/tests/thread_cooperation/Makefile
index 2e2606a2eb39fa465b0cdafa396fda4b8a0c3c60..e6ae2ac31134b6048e028cb8a9651b94abc7c618 100644
--- a/tests/thread_cooperation/Makefile
+++ b/tests/thread_cooperation/Makefile
@@ -1,7 +1,7 @@
APPLICATION = thread_cooperation
include ../Makefile.tests_common
-BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 calliope-mini \
+BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 bluepill calliope-mini \
cc2650-launchpad cc2650stk chronos \
maple-mini mbed_lpc1768 microbit msb-430 msb-430h nrf51dongle \
nrf6310 nucleo32-f031 nucleo32-f042 nucleo32-f303 \
diff --git a/tests/unittests/Makefile b/tests/unittests/Makefile
index ebe2b3f6553e2fa65c382f4c19611c299c1ecdb2..d435e04839a8475b984f4d0fc2f34be5680c24f5 100644
--- a/tests/unittests/Makefile
+++ b/tests/unittests/Makefile
@@ -9,6 +9,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon \
arduino-uno \
arduino-zero \
b-l072z-lrwan1 \
+ bluepill \
calliope-mini \
cc2538dk \
cc2650-launchpad \