diff --git a/cpu/sam3/include/periph_cpu.h b/cpu/sam3/include/periph_cpu.h
index ffdabe961bc13934b631d138b25feebb529e4059..a584a8635af43a8b542186340cedc5869bee1357 100644
--- a/cpu/sam3/include/periph_cpu.h
+++ b/cpu/sam3/include/periph_cpu.h
@@ -149,6 +149,14 @@ typedef struct {
     uint8_t irqn;           /**< interrupt number of the device */
 } uart_conf_t;
 
+/**
+ * @brief   Configure the given GPIO pin to be used with the given MUX setting
+ *
+ * @param[in] pin           GPIO pin to configure
+ * @param[in] mux           MUX setting to use
+ */
+void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/cpu/sam3/periph/gpio.c b/cpu/sam3/periph/gpio.c
index 7043054b46e383eb23879d8527dd433216e4a3e8..bf79bfd4943c0d158b0ea33bbeb5c1a120834b8f 100644
--- a/cpu/sam3/periph/gpio.c
+++ b/cpu/sam3/periph/gpio.c
@@ -242,6 +242,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
     return 0;
 }
 
+void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
+{
+    /* power on the corresponding port */
+    PMC->PMC_PCER0 = (1 << (_port_num(pin) + 11));
+    /* give peripheral control over the pin */
+    _port(pin)->PIO_PDR = (1 << _pin_num(pin));
+    /* and configure the MUX */
+    _port(pin)->PIO_ABSR &= ~(1 << _pin_num(pin));
+    _port(pin)->PIO_ABSR |=  (mux << _pin_num(pin));
+}
+
 void gpio_irq_enable(gpio_t pin)
 {
     NVIC_EnableIRQ((1 << (_port_num(pin) + PIOA_IRQn)));