From 38c7d11f8c2982fd4058fae493841e38e9bee7fc Mon Sep 17 00:00:00 2001
From: Hauke Petersen <hauke.petersen@fu-berlin.de>
Date: Tue, 13 Dec 2016 15:49:57 +0100
Subject: [PATCH] cpu/sam3: add gpio_init_mux() function
---
cpu/sam3/include/periph_cpu.h | 8 ++++++++
cpu/sam3/periph/gpio.c | 11 +++++++++++
2 files changed, 19 insertions(+)
diff --git a/cpu/sam3/include/periph_cpu.h b/cpu/sam3/include/periph_cpu.h
index ffdabe961b..a584a8635a 100644
--- a/cpu/sam3/include/periph_cpu.h
+++ b/cpu/sam3/include/periph_cpu.h
@@ -149,6 +149,14 @@ typedef struct {
uint8_t irqn; /**< interrupt number of the device */
} uart_conf_t;
+/**
+ * @brief Configure the given GPIO pin to be used with the given MUX setting
+ *
+ * @param[in] pin GPIO pin to configure
+ * @param[in] mux MUX setting to use
+ */
+void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
+
#ifdef __cplusplus
}
#endif
diff --git a/cpu/sam3/periph/gpio.c b/cpu/sam3/periph/gpio.c
index 7043054b46..bf79bfd494 100644
--- a/cpu/sam3/periph/gpio.c
+++ b/cpu/sam3/periph/gpio.c
@@ -242,6 +242,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
return 0;
}
+void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
+{
+ /* power on the corresponding port */
+ PMC->PMC_PCER0 = (1 << (_port_num(pin) + 11));
+ /* give peripheral control over the pin */
+ _port(pin)->PIO_PDR = (1 << _pin_num(pin));
+ /* and configure the MUX */
+ _port(pin)->PIO_ABSR &= ~(1 << _pin_num(pin));
+ _port(pin)->PIO_ABSR |= (mux << _pin_num(pin));
+}
+
void gpio_irq_enable(gpio_t pin)
{
NVIC_EnableIRQ((1 << (_port_num(pin) + PIOA_IRQn)));
--
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