diff --git a/boards/nucleo-f103/Makefile b/boards/nucleo-f103/Makefile
new file mode 100755
index 0000000000000000000000000000000000000000..f8fcbb53a06595771dae356338a7bf2c0673734d
--- /dev/null
+++ b/boards/nucleo-f103/Makefile
@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/nucleo-f103/Makefile.features b/boards/nucleo-f103/Makefile.features
new file mode 100755
index 0000000000000000000000000000000000000000..792dc9fcb29ca46f3459db45941dcad2c6ee4b4e
--- /dev/null
+++ b/boards/nucleo-f103/Makefile.features
@@ -0,0 +1,13 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Various other features (if any)
+FEATURES_PROVIDED += cpp
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m3_1
diff --git a/boards/nucleo-f103/Makefile.include b/boards/nucleo-f103/Makefile.include
new file mode 100755
index 0000000000000000000000000000000000000000..56acab42742c910a2ffad21481a6b5cb31a52c78
--- /dev/null
+++ b/boards/nucleo-f103/Makefile.include
@@ -0,0 +1,16 @@
+## the cpu to build for
+export CPU = stm32f1
+export CPU_MODEL = stm32f103rb
+
+#define the default port depending on the host OS
+PORT_LINUX ?= /dev/ttyUSB0
+PORT_DARWIN ?= $(shell ls -1 /dev/tty.usbmodem* | head -n 1)
+
+# setup serial terminal
+include $(RIOTBOARD)/Makefile.include.serial
+
+# this board uses openocd
+include $(RIOTBOARD)/Makefile.include.openocd
+
+# include cortex defaults
+include $(RIOTBOARD)/Makefile.include.cortexm_common
diff --git a/boards/nucleo-f103/board.c b/boards/nucleo-f103/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..5385d5cd40977ae190c659134c18ec0cc21658d0
--- /dev/null
+++ b/boards/nucleo-f103/board.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2015 TriaGnoSys GmbH
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo-f103
+ * @{
+ *
+ * @file
+ * @brief Board specific implementations for the nucleo-f103 board
+ *
+ * @author VÃctor Ariño <victor.arino@triagnosys.com>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "cpu.h"
+#include "periph/gpio.h"
+
+static void leds_init(void);
+
+void board_init(void)
+{
+ /* initialize the CPU */
+ cpu_init();
+
+ /* initialize the boards LEDs */
+ leds_init();
+
+ /* pin remapping: in order to use the MCU peripherals with the Arduino
+ * compatible connectors. Some peripherals need to be remapped here. */
+ RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
+ AFIO->MAPR |= AFIO_MAPR_I2C1_REMAP;
+}
+
+/**
+ * @brief Initialize the boards on-board LEDs
+ *
+ * The green LED is connected to pin PA5
+ */
+static void leds_init(void)
+{
+ RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
+ GPIOA->CR[0] &= ~(0x0f << 20);
+ GPIOA->CR[0] |= (0x03 << 20);
+ GPIOA->BRR = (1 << 5);
+}
diff --git a/boards/nucleo-f103/dist/openocd.cfg b/boards/nucleo-f103/dist/openocd.cfg
new file mode 100755
index 0000000000000000000000000000000000000000..e6d5040e502f5b022ed4d863b0935f02e1377059
--- /dev/null
+++ b/boards/nucleo-f103/dist/openocd.cfg
@@ -0,0 +1 @@
+source [find board/st_nucleo_f1.cfg]
diff --git a/boards/nucleo-f103/include/board.h b/boards/nucleo-f103/include/board.h
new file mode 100755
index 0000000000000000000000000000000000000000..c1e3e473daf47124ad487792552397610ab91737
--- /dev/null
+++ b/boards/nucleo-f103/include/board.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2015 TriaGnoSys GmbH
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup boards_nucleo-f103 Nucleo-F103
+ * @ingroup boards
+ * @brief Board specific files for the nucleo-f103 board
+ * @{
+ *
+ * @file
+ * @brief Board specific definitions for the nucleo-f103 board
+ *
+ * @author VÃctor Ariño <victor.arino@triagnosys.com>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include <stdint.h>
+
+#include "cpu.h"
+#include "periph_conf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Define the nominal CPU core clock in this board
+ */
+#define F_CPU CLOCK_CORECLOCK
+
+/**
+ * @name Define the UART to be used as stdio and its baudrate
+ * @{
+ */
+#define STDIO UART_1
+#define STDIO_BAUDRATE (115200U)
+#define STDIO_RX_BUFSIZE (64U)
+/** @} */
+
+/**
+ * @name LED pin definitions
+ * @{
+ */
+#define LED_GREEN_GPIO GPIO_PIN(PORT_A, 5)
+/** @} */
+
+/**
+ * @name Macros for controlling the on-board LEDs.
+ * @{
+ */
+#define LED_RED_ON
+#define LED_RED_OFF
+#define LED_RED_TOGGLE
+
+#define LED_GREEN_ON (GPIOA->BSRR = (1 << 5))
+#define LED_GREEN_OFF (GPIOA->BRR = (1 << 5))
+#define LED_GREEN_TOGGLE (GPIOA->ODR ^= (1 << 5))
+
+#define LED_ORANGE_ON
+#define LED_ORANGE_OFF
+#define LED_ORANGE_TOGGLE
+/** @} */
+
+/**
+ * @name Buttons
+ * @{
+ */
+#define BUTTON_USER_GPIO GPIO_PIN(PORT_C, 13)
+/** @} */
+
+/**
+ * @name xtimer configuration
+ * @{
+ */
+#define XTIMER TIMER_0
+#define XTIMER_CHAN 0
+#define XTIMER_SHIFT 0
+#define XTIMER_MASK 0 /* llt 32-bit since combined */
+#define XTIMER_BACKOFF 5
+/** @} */
+
+/**
+ * @brief Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
+/** @} */
diff --git a/boards/nucleo-f103/include/periph_conf.h b/boards/nucleo-f103/include/periph_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..5d7e30f14e6f7bc051b1976510b2bf33b7acba86
--- /dev/null
+++ b/boards/nucleo-f103/include/periph_conf.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2015 TriaGnoSys GmbH
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo-f103
+ * @{
+ *
+ * @file
+ * @brief Peripheral MCU configuration for the nucleo-f103 board
+ *
+ * @author VÃctor Ariño <victor.arino@triagnosys.com>
+ */
+
+#ifndef PERIPH_CONF_H_
+#define PERIPH_CONF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+#define CLOCK_HSE (8000000U) /* external oscillator */
+#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
+
+/* the actual PLL values are automatically generated */
+#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE /* not divided */
+#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
+
+/* AHB, APB1, APB2 dividers */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36 MHz (!) */
+
+/* Flash latency */
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2 /* for >= 72 MHz */
+/** @} */
+
+/**
+ * @brief Timer configuration
+ * @{
+ */
+#define TIMER_NUMOF (1U)
+#define TIMER_0_EN 1
+#define TIMER_1_EN 0
+
+/* Timer 0 configuration */
+#define TIMER_0_DEV_0 TIM2
+#define TIMER_0_DEV_1 TIM3
+#define TIMER_0_PRESCALER (CLOCK_CORECLOCK / 1000000U)
+#define TIMER_0_MAX_VALUE (0xffff)
+#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
+#define TIMER_0_ISR_0 isr_tim2
+#define TIMER_0_ISR_1 isr_tim3
+#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
+#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
+#define TIMER_0_IRQ_PRIO 1
+#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
+
+/* Timer 1 configuration */
+#define TIMER_1_DEV_0 TIM4
+#define TIMER_1_DEV_1 TIM5
+#define TIMER_1_PRESCALER (36000U)
+#define TIMER_1_MAX_VALUE (0xffff)
+#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
+#define TIMER_1_ISR_0 isr_tim4
+#define TIMER_1_ISR_1 isr_tim5
+#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
+#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
+#define TIMER_1_IRQ_PRIO 1
+#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
+/** @} */
+
+/**
+ * @brief UART configuration
+ * @{
+ */
+#define UART_NUMOF (3U)
+#define UART_0_EN 0
+#define UART_1_EN 1
+#define UART_2_EN 0
+#define UART_IRQ_PRIO 1
+
+/* UART 0 device configuration */
+#define UART_0_DEV USART1
+#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
+#define UART_0_IRQ USART1_IRQn
+#define UART_0_ISR isr_usart1
+#define UART_0_BUS_FREQ CLOCK_CORECLOCK
+/* UART 0 pin configuration */
+#define UART_0_RX_PIN GPIO_PIN(PORT_A, 10)
+#define UART_0_TX_PIN GPIO_PIN(PORT_A, 9)
+
+/* UART 1 device configuration */
+#define UART_1_DEV USART2
+#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
+#define UART_1_IRQ USART2_IRQn
+#define UART_1_ISR isr_usart2
+#define UART_1_BUS_FREQ CLOCK_CORECLOCK / 2
+/* UART 1 pin configuration */
+#define UART_1_RX_PIN GPIO_PIN(PORT_A, 3)
+#define UART_1_TX_PIN GPIO_PIN(PORT_A, 2)
+
+/* UART 2 device configuration */
+#define UART_2_DEV USART3
+#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
+#define UART_2_IRQ USART3_IRQn
+#define UART_2_ISR isr_usart3
+#define UART_2_BUS_FREQ CLOCK_CORECLOCK / 2
+/* UART 2 pin configuration */
+#define UART_2_RX_PIN GPIO_PIN(PORT_B, 11)
+#define UART_2_TX_PIN GPIO_PIN(PORT_B, 10)
+/** @} */
+
+/**
+ * @name I2C configuration
+ * @{
+ */
+#define I2C_NUMOF (2U)
+#define I2C_0_EN 1
+#define I2C_1_EN 0
+#define I2C_IRQ_PRIO 1
+#define I2C_APBCLK (36000000U)
+
+/* I2C 0 device configuration */
+#define I2C_0_DEV I2C1
+#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
+#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define I2C_0_EVT_IRQ I2C1_EV_IRQn
+#define I2C_0_EVT_ISR isr_i2c1_ev
+#define I2C_0_ERR_IRQ I2C1_ER_IRQn
+#define I2C_0_ERR_ISR isr_i2c1_er
+/* I2C 0 pin configuration */
+#define I2C_0_SCL_PIN GPIO_PIN(PORT_B, 8) /* remapped */
+#define I2C_0_SDA_PIN GPIO_PIN(PORT_B, 9) /* remapped */
+
+/* I2C 1 device configuration */
+#define I2C_1_DEV I2C2
+#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
+#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define I2C_1_EVT_IRQ I2C2_EV_IRQn
+#define I2C_1_EVT_ISR isr_i2c2_ev
+#define I2C_1_ERR_IRQ I2C2_ER_IRQn
+#define I2C_1_ERR_ISR isr_i2c2_er
+/* I2C 1 pin configuration */
+#define I2C_1_SCL_PIN GPIO_PIN(PORT_B, 10)
+#define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11)
+/** @} */
+
+/**
+ * @name SPI configuration
+ * @{
+ */
+#define SPI_NUMOF (2U)
+#define SPI_0_EN 1
+#define SPI_1_EN 0
+#define SPI_IRQ_PRIO 1
+
+/* SPI 0 device config */
+#define SPI_0_DEV SPI1
+#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
+#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
+#define SPI_0_IRQ SPI1_IRQn
+#define SPI_0_IRQ_HANDLER isr_spi1
+#define SPI_0_BUS_DIV 1
+
+/* SPI 0 pin configuration */
+#define SPI_0_CLK_PIN GPIO_PIN(PORT_A, 5)
+#define SPI_0_MISO_PIN GPIO_PIN(PORT_A, 6)
+#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A, 7)
+
+/* SPI 1 device config */
+#define SPI_1_DEV SPI2
+#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
+#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
+#define SPI_1_IRQ SPI2_IRQn
+#define SPI_1_IRQ_HANDLER isr_spi2
+#define SPI_1_BUS_DIV 1
+/* SPI 1 pin configuration */
+#define SPI_1_CLK_PIN GPIO_PIN(PORT_B, 13)
+#define SPI_1_MISO_PIN GPIO_PIN(PORT_B, 14)
+#define SPI_1_MOSI_PIN GPIO_PIN(PORT_B, 15)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H_ */
diff --git a/examples/gnrc_border_router/Makefile b/examples/gnrc_border_router/Makefile
index 1ceec259feec8057c00ef7524d553c1599363a01..cbbe76ffa531d7818559c58c5b6cc0d72ce09d35 100644
--- a/examples/gnrc_border_router/Makefile
+++ b/examples/gnrc_border_router/Makefile
@@ -8,9 +8,9 @@ BOARD ?= samr21-xpro
RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := airfy-beacon msb-430 msb-430h pca10000 pca10005 \
- nrf51dongle nrf6310 nucleo-f334 spark-core \
- stm32f0discovery telosb weio wsn430-v1_3b \
- wsn430-v1_4 yunjia-nrf51822 z1
+ nrf51dongle nrf6310 nucleo-f103 nucleo-f334 \
+ spark-core stm32f0discovery telosb \
+ weio wsn430-v1_3b wsn430-v1_4 yunjia-nrf51822 z1
ifeq (,$(SLIP_UART))
# set default (last available UART)
diff --git a/examples/gnrc_networking/Makefile b/examples/gnrc_networking/Makefile
index 30bb5eeb276a326d5e2471b4b5491c1d7f9a9afd..b73bb4d081df9b25809a30bc62b9c2923b6831af 100644
--- a/examples/gnrc_networking/Makefile
+++ b/examples/gnrc_networking/Makefile
@@ -8,7 +8,7 @@ BOARD ?= native
RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := airfy-beacon chronos msb-430 msb-430h nrf51dongle \
- nrf6310 nucleo-f334 pca10000 pca10005 spark-core \
+ nrf6310 nucleo-f103 nucleo-f334 pca10000 pca10005 spark-core \
stm32f0discovery telosb weio wsn430-v1_3b wsn430-v1_4 \
yunjia-nrf51822 z1
diff --git a/examples/gnrc_tftp/Makefile b/examples/gnrc_tftp/Makefile
index b92f8e951c83b361e7959bfe8c6aa841cc9b574c..3c06fc1f2e41bdb7cdd775030791247c8c4eaa47 100644
--- a/examples/gnrc_tftp/Makefile
+++ b/examples/gnrc_tftp/Makefile
@@ -8,9 +8,9 @@ BOARD ?= native
RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := airfy-beacon chronos msb-430 msb-430h nrf51dongle \
- nrf6310 nucleo-f334 pca10000 pca10005 spark-core \
- stm32f0discovery telosb weio wsn430-v1_3b wsn430-v1_4 \
- yunjia-nrf51822 z1
+ nrf6310 nucleo-f103 nucleo-f334 pca10000 pca10005 \
+ spark-core stm32f0discovery telosb weio wsn430-v1_3b \
+ wsn430-v1_4 yunjia-nrf51822 z1
# Include packages that pull up and auto-init the link layer.
# NOTE: 6LoWPAN will be included if IEEE802.15.4 devices are present
diff --git a/tests/pkg_cmsis-dsp/Makefile b/tests/pkg_cmsis-dsp/Makefile
index 19e0f9d8cee0fe826e89af3d0c99a5ea55387580..7bc2d0145fde558adcfd513326833e53170e3d56 100644
--- a/tests/pkg_cmsis-dsp/Makefile
+++ b/tests/pkg_cmsis-dsp/Makefile
@@ -14,6 +14,7 @@ BOARD_WHITELIST := \
msbiot \
mulle \
nucleo-f091 \
+ nucleo-f103 \
nucleo-f303 \
nucleo-f334 \
nucleo-f401 \
diff --git a/tests/thread_cooperation/Makefile b/tests/thread_cooperation/Makefile
index c1e283f0ffe642617daadc0b7359af9edab82c13..0fcdce844a10c0382858a5a8ca728b8a26cd87de 100644
--- a/tests/thread_cooperation/Makefile
+++ b/tests/thread_cooperation/Makefile
@@ -3,8 +3,8 @@ include ../Makefile.tests_common
BOARD_INSUFFICIENT_MEMORY := chronos msb-430 msb-430h mbed_lpc1768 \
stm32f0discovery pca10000 pca10005 \
- yunjia-nrf51822 spark-core airfy-beacon nucleo-f334 \
- nrf51dongle nrf6310 weio
+ yunjia-nrf51822 spark-core airfy-beacon nucleo-f103 \
+ nucleo-f334 nrf51dongle nrf6310 weio
DISABLE_MODULE += auto_init
diff --git a/tests/unittests/Makefile b/tests/unittests/Makefile
index 4b15672eeb64867247346e12a6e2eb1f33a34f2b..5d9d7c49a03550ac85688834f6e68b2d820fc217 100644
--- a/tests/unittests/Makefile
+++ b/tests/unittests/Makefile
@@ -3,9 +3,9 @@ include ../Makefile.tests_common
BOARD_INSUFFICIENT_MEMORY := airfy-beacon chronos msb-430 msb-430h pca10000 \
pca10005 spark-core stm32f0discovery \
- telosb wsn430-v1_3b wsn430-v1_4 z1 nucleo-f334 \
- yunjia-nrf51822 samr21-xpro arduino-mega2560 \
- airfy-beacon nrf51dongle nrf6310 weio
+ telosb wsn430-v1_3b wsn430-v1_4 z1 nucleo-f103 \
+ nucleo-f334 yunjia-nrf51822 samr21-xpro \
+ arduino-mega2560 airfy-beacon nrf51dongle nrf6310 weio
USEMODULE += embunit