From 541fc7f93f4d55f44cd1f18070baa8fff8b9c7e8 Mon Sep 17 00:00:00 2001
From: Alexandre Abadie <alexandre.abadie@inria.fr>
Date: Wed, 2 Jan 2019 14:13:32 +0100
Subject: [PATCH] boards/stm32: add f2 common clock configuration
---
.../stm32/include/f2/cfg_clock_120_8_1.h | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 boards/common/stm32/include/f2/cfg_clock_120_8_1.h
diff --git a/boards/common/stm32/include/f2/cfg_clock_120_8_1.h b/boards/common/stm32/include/f2/cfg_clock_120_8_1.h
new file mode 100644
index 0000000000..fbdf7e1caf
--- /dev/null
+++ b/boards/common/stm32/include/f2/cfg_clock_120_8_1.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016-2017 OTA keys S.A.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_common_stm32
+ * @{
+ *
+ * @file
+ * @brief Configure STM32F2 clock to 120MHz using PLL
+ *
+ * @author Vincent Dupont <vincent@otakeys.com>
+ * @author Aurelien Gonce <aurelien.gonce@altran.fr>
+ * @author Toon Stegen <toon.stegen@altran.com>
+ */
+
+#ifndef F2_CFG_CLOCK_120_8_1_H
+#define F2_CFG_CLOCK_120_8_1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @{
+ */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 120MHz */
+#define CLOCK_CORECLOCK (120000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (120)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (5)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* F2_CFG_CLOCK_120_8_1_H */
+/** @} */
--
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