diff --git a/boards/nucleo32-f031/Makefile b/boards/nucleo32-f031/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f8fcbb53a06595771dae356338a7bf2c0673734d
--- /dev/null
+++ b/boards/nucleo32-f031/Makefile
@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/nucleo32-f031/Makefile.dep b/boards/nucleo32-f031/Makefile.dep
new file mode 100644
index 0000000000000000000000000000000000000000..5472bf8b8d8fd463a18815c0f10e5d348f90fe51
--- /dev/null
+++ b/boards/nucleo32-f031/Makefile.dep
@@ -0,0 +1,3 @@
+ifneq (,$(filter saul_default,$(USEMODULE)))
+ USEMODULE += saul_gpio
+endif
diff --git a/boards/nucleo32-f031/Makefile.features b/boards/nucleo32-f031/Makefile.features
new file mode 100644
index 0000000000000000000000000000000000000000..5ff6b01c43ad4b14ce35e5000d66bb32e61c26b1
--- /dev/null
+++ b/boards/nucleo32-f031/Makefile.features
@@ -0,0 +1,13 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_adc
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Various common features of Nucleo boards
+FEATURES_PROVIDED += cpp
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m0_1
diff --git a/boards/nucleo32-f031/Makefile.include b/boards/nucleo32-f031/Makefile.include
new file mode 100644
index 0000000000000000000000000000000000000000..df3e18ba4e2d9cefd1a0dcbda80f63c6e1380794
--- /dev/null
+++ b/boards/nucleo32-f031/Makefile.include
@@ -0,0 +1,13 @@
+## the cpu to build for
+export CPU = stm32f0
+export CPU_MODEL = stm32f031k6
+
+# define the default port depending on the host OS
+PORT_LINUX ?= /dev/ttyACM0
+PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
+
+# setup serial terminal
+include $(RIOTBOARD)/Makefile.include.serial
+
+# this board uses openocd
+include $(RIOTBOARD)/Makefile.include.openocd
diff --git a/boards/nucleo32-f031/board.c b/boards/nucleo32-f031/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..18c172353c6fcb066e4474928820a7c49e042a49
--- /dev/null
+++ b/boards/nucleo32-f031/board.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2017 Inria
+ * 2016 OTA keys
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo32-f031
+ * @{
+ *
+ * @file
+ * @brief Board specific implementations for the nucleo32-f031 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Vincent Dupont <vincent@otakeys.com>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+
+void board_init(void)
+{
+ /* initialize the CPU */
+ cpu_init();
+
+ /* initialize the boards LEDs */
+ gpio_init(LED0_PIN, GPIO_OUT);
+}
diff --git a/boards/nucleo32-f031/dist/openocd.cfg b/boards/nucleo32-f031/dist/openocd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4f0cfb3a023bba8d0d9df75647452a24c138a121
--- /dev/null
+++ b/boards/nucleo32-f031/dist/openocd.cfg
@@ -0,0 +1 @@
+source [find board/st_nucleo_f0.cfg]
diff --git a/boards/nucleo32-f031/include/board.h b/boards/nucleo32-f031/include/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..6623bba63966b5f2bac9d16af7f8590cf8707e8a
--- /dev/null
+++ b/boards/nucleo32-f031/include/board.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Inria
+ * 2017 OTA keys
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup boards_nucleo32-f031 Nucleo32-F031
+ * @ingroup boards
+ * @brief Board specific files for the nucleo32-f031 board
+ * @{
+ *
+ * @file
+ * @brief Board specific definitions for the nucleo32-f031 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Vincent Dupont <vincent@otakeys.com>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Macros for controlling the on-board LED.
+ * @{
+ */
+#define LED0_PIN GPIO_PIN(PORT_B, 3)
+
+#define LED0_MASK (1 << 3)
+
+#define LED0_ON (GPIOB->BSRR = LED0_MASK)
+#define LED0_OFF (GPIOB->BRR = LED0_MASK)
+#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
+/** @} */
+
+/**
+ * @brief Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
+/** @} */
diff --git a/boards/nucleo32-f031/include/gpio_params.h b/boards/nucleo32-f031/include/gpio_params.h
new file mode 100644
index 0000000000000000000000000000000000000000..9e3745f08b1df51987bf29dae60c2b18797b62cb
--- /dev/null
+++ b/boards/nucleo32-f031/include/gpio_params.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2017 Inria
+ * 2017 OTA keys
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo32-f031
+ * @{
+ *
+ * @file
+ * @brief Board specific configuration of direct mapped GPIOs
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Vincent Dupont <vincent@otakeys.com>
+ */
+
+#ifndef GPIO_PARAMS_H
+#define GPIO_PARAMS_H
+
+#include "board.h"
+#include "saul/periph.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief GPIO pin configuration
+ */
+static const saul_gpio_params_t saul_gpio_params[] =
+{
+ {
+ .name = "LED(green)",
+ .pin = LED0_PIN,
+ .mode = GPIO_OUT
+ },
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO_PARAMS_H */
+/** @} */
diff --git a/boards/nucleo32-f031/include/periph_conf.h b/boards/nucleo32-f031/include/periph_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..497ba0ed72718e166d73d55352aff0cf18ced8f7
--- /dev/null
+++ b/boards/nucleo32-f031/include/periph_conf.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2017 Inria
+ * 2017 OTA keys
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo32-f031
+ * @{
+ *
+ * @file
+ * @brief Peripheral MCU configuration for the nucleo32-f031 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Vincent Dupont <vincent@otakeys.com>
+ */
+
+#ifndef PERIPH_CONF_H_
+#define PERIPH_CONF_H_
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+#define CLOCK_HSI (8000000U) /* internal oscillator */
+#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
+
+/* the actual PLL values are automatically generated */
+#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI)
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+/** @} */
+
+/**
+ * @brief Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+ {
+ .dev = TIM2,
+ .max = 0xffffffff,
+ .rcc_mask = RCC_APB1ENR_TIM2EN,
+ .bus = APB1,
+ .irqn = TIM2_IRQn
+ }
+};
+
+#define TIMER_0_ISR isr_tim2
+
+#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @brief UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+ {
+ .dev = USART1,
+ .rcc_mask = RCC_APB2ENR_USART1EN,
+ .rx_pin = GPIO_PIN(PORT_A, 15),
+ .tx_pin = GPIO_PIN(PORT_A, 2),
+ .rx_af = GPIO_AF1,
+ .tx_af = GPIO_AF1,
+ .bus = APB2,
+ .irqn = USART1_IRQn
+ }
+};
+
+#define UART_0_ISR (isr_usart1)
+
+#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @brief PWM configuration
+ * @{
+ */
+static const pwm_conf_t pwm_config[] = {
+ {
+ .dev = TIM1,
+ .rcc_mask = RCC_APB2ENR_TIM1EN,
+ .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 } },
+ .af = GPIO_AF2,
+ .bus = APB2
+ },
+ {
+ .dev = TIM14,
+ .rcc_mask = RCC_APB1ENR_TIM14EN,
+ .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 } },
+ .af = GPIO_AF0,
+ .bus = APB1
+ },
+ {
+ .dev = TIM3,
+ .rcc_mask = RCC_APB1ENR_TIM3EN,
+ .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 } },
+ .af = GPIO_AF1,
+ .bus = APB1
+ },
+};
+
+#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
+/** @} */
+
+/**
+ * @name RTC configuration
+ * @{
+ */
+/**
+ * Nucleo-f031 does not have any LSE, current RTC driver does not support LSI as
+ * clock source, so disabling RTC.
+ */
+#define RTC_NUMOF (0U)
+/** @} */
+
+/**
+ * @brief ADC configuration
+ * @{
+ */
+#define ADC_CONFIG { \
+ { GPIO_PIN(PORT_A, 0), 0 }, \
+ { GPIO_PIN(PORT_A, 1), 1 }, \
+ { GPIO_PIN(PORT_A, 3), 3 }, \
+ { GPIO_PIN(PORT_A, 4), 4 }, \
+ { GPIO_PIN(PORT_A, 7), 7 } \
+}
+
+#define ADC_NUMOF (5)
+/** @} */
+
+/**
+ * @brief DAC configuration
+ * @{
+ */
+#define DAC_NUMOF (0)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H_ */
+/** @} */