From 7d31bb43f169a8fd9e6c9eb12d80119394e8773d Mon Sep 17 00:00:00 2001
From: Alexandre Abadie <alexandre.abadie@inria.fr>
Date: Tue, 26 Feb 2019 10:34:08 +0100
Subject: [PATCH] boards/stm32/f4: factorize common clock configuration (168/8)
MIME-Version: 1.0
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A common configuration file is introduced for stm32f4 with core clock
at 168MHz with HSE at 8MHz, 2 configuration files are introduced to²:
distinguish between clock configuration with and without LSE.
---
.../stm32/include/f4/cfg_clock_168_8_0.h | 41 +++++++++++++
.../stm32/include/f4/cfg_clock_168_8_1.h | 33 ++---------
.../stm32/include/f4/cfg_clock_168_8_common.h | 59 +++++++++++++++++++
3 files changed, 106 insertions(+), 27 deletions(-)
create mode 100644 boards/common/stm32/include/f4/cfg_clock_168_8_0.h
create mode 100644 boards/common/stm32/include/f4/cfg_clock_168_8_common.h
diff --git a/boards/common/stm32/include/f4/cfg_clock_168_8_0.h b/boards/common/stm32/include/f4/cfg_clock_168_8_0.h
new file mode 100644
index 0000000000..b82256c7fd
--- /dev/null
+++ b/boards/common/stm32/include/f4/cfg_clock_168_8_0.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2018 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_common_stm32
+ * @{
+ *
+ * @file
+ * @brief Configure STM32F4 clock to 168MHz using PLL and without LSE
+ *
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef F4_CFG_CLOCK_168_8_0_H
+#define F4_CFG_CLOCK_168_8_0_H
+
+#include "f4/cfg_clock_168_8_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LSE clock settings
+ *
+ * 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz)
+ */
+#define CLOCK_LSE (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* F4_CFG_CLOCK_168_8_0_H */
+/** @} */
diff --git a/boards/common/stm32/include/f4/cfg_clock_168_8_1.h b/boards/common/stm32/include/f4/cfg_clock_168_8_1.h
index c974287456..5707c0ea0d 100644
--- a/boards/common/stm32/include/f4/cfg_clock_168_8_1.h
+++ b/boards/common/stm32/include/f4/cfg_clock_168_8_1.h
@@ -11,7 +11,7 @@
* @{
*
* @file
- * @brief Configure STM32F4 clock to 168MHz using PLL
+ * @brief Configure STM32F4 clock to 168MHz using PLL with LSE
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
@@ -19,40 +19,19 @@
#ifndef F4_CFG_CLOCK_168_8_1_H
#define F4_CFG_CLOCK_168_8_1_H
+#include "f4/cfg_clock_168_8_common.h"
+
#ifdef __cplusplus
extern "C" {
#endif
/**
- * @name Clock settings
+ * @brief LSE clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
+ * 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz)
*/
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 168MHz */
-#define CLOCK_CORECLOCK (168000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (168)
-#define CLOCK_PLL_P (2)
-#define CLOCK_PLL_Q (7)
-/** @} */
#ifdef __cplusplus
}
diff --git a/boards/common/stm32/include/f4/cfg_clock_168_8_common.h b/boards/common/stm32/include/f4/cfg_clock_168_8_common.h
new file mode 100644
index 0000000000..11b9ac18db
--- /dev/null
+++ b/boards/common/stm32/include/f4/cfg_clock_168_8_common.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2018 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_common_stm32
+ * @{
+ *
+ * @file
+ * @brief Configure STM32F4 clock to 168MHz using PLL
+ *
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef F4_CFG_CLOCK_168_8_COMMON_H
+#define F4_CFG_CLOCK_168_8_COMMON_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @{
+ */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 168MHz */
+#define CLOCK_CORECLOCK (168000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (168)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (7)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* F4_CFG_CLOCK_168_8_COMMON_H */
+/** @} */
--
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