diff --git a/Makefile.dep b/Makefile.dep
index 3443339744960e1b283534271dc32eccffc7ae56..71c21be140b4af5c29236ad4d7a34f6556b978dd 100644
--- a/Makefile.dep
+++ b/Makefile.dep
@@ -11,7 +11,7 @@ ifneq (,$(filter ng_nomac,$(USEMODULE)))
endif
ifneq (,$(filter ng_at86rf2%,$(USEMODULE)))
- USEMODULE += ng_at86rf2xx
+ USEMODULE += at86rf2xx
USEMODULE += ieee802154
endif
diff --git a/boards/iot-lab_M3/include/ng_at86rf2xx_params.h b/boards/iot-lab_M3/include/at86rf2xx_params.h
similarity index 89%
rename from boards/iot-lab_M3/include/ng_at86rf2xx_params.h
rename to boards/iot-lab_M3/include/at86rf2xx_params.h
index b9f01637ecc935b3a85ccba55696c35c31a4a4c3..559c9b6f9ec693a6a9fc84c174e928222729992e 100644
--- a/boards/iot-lab_M3/include/ng_at86rf2xx_params.h
+++ b/boards/iot-lab_M3/include/at86rf2xx_params.h
@@ -16,8 +16,8 @@
* @author Kaspar Schleiser <kaspar@schleiser.de>
*/
-#ifndef NG_AT86RF2XX_PARAMS_H_
-#define NG_AT86RF2XX_PARAMS_H_
+#ifndef AT86RF2XX_PARAMS_H_
+#define AT86RF2XX_PARAMS_H_
#ifdef __cplusplus
extern "C" {
@@ -42,5 +42,5 @@ static const at86rf2xx_params_t at86rf2xx_params[] =
#ifdef __cplusplus
}
#endif
-#endif /* NG_AT86RF2XX_PARAMS_H */
+#endif /* AT86RF2XX_PARAMS_H_ */
/** @} */
diff --git a/boards/mulle/include/ng_at86rf2xx_params.h b/boards/mulle/include/at86rf2xx_params.h
similarity index 90%
rename from boards/mulle/include/ng_at86rf2xx_params.h
rename to boards/mulle/include/at86rf2xx_params.h
index 9cecea9bf4e36fd68f82525619514f1a84f49e97..2a6e20700ac5a70f71398972556565dc460764b8 100644
--- a/boards/mulle/include/ng_at86rf2xx_params.h
+++ b/boards/mulle/include/at86rf2xx_params.h
@@ -18,8 +18,8 @@
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
-#ifndef NG_AT86RF2XX_PARAMS_H_
-#define NG_AT86RF2XX_PARAMS_H_
+#ifndef AT86RF2XX_PARAMS_H_
+#define AT86RF2XX_PARAMS_H_
#ifdef __cplusplus
extern "C" {
@@ -44,5 +44,5 @@ static const at86rf2xx_params_t at86rf2xx_params[] =
#ifdef __cplusplus
}
#endif
-#endif /* NG_AT86RF2XX_PARAMS_H */
+#endif /* AT86RF2XX_PARAMS_H */
/** @} */
diff --git a/boards/samr21-xpro/include/ng_at86rf2xx_params.h b/boards/samr21-xpro/include/at86rf2xx_params.h
similarity index 90%
rename from boards/samr21-xpro/include/ng_at86rf2xx_params.h
rename to boards/samr21-xpro/include/at86rf2xx_params.h
index b4ae732e18682fcdd834c7744a0c5c2bd59c2ce4..fc231b47ca1ca60228e7fe5fc9014d8c8d037415 100644
--- a/boards/samr21-xpro/include/ng_at86rf2xx_params.h
+++ b/boards/samr21-xpro/include/at86rf2xx_params.h
@@ -16,8 +16,8 @@
* @author Kaspar Schleiser <kaspar@schleiser.de>
*/
-#ifndef NG_AT86RF2XX_PARAMS_H_
-#define NG_AT86RF2XX_PARAMS_H_
+#ifndef AT86RF2XX_PARAMS_H_
+#define AT86RF2XX_PARAMS_H_
#ifdef __cplusplus
extern "C" {
@@ -42,5 +42,5 @@ static const at86rf2xx_params_t at86rf2xx_params[] =
#ifdef __cplusplus
}
#endif
-#endif /* NG_AT86RF2XX_PARAMS_H */
+#endif /* AT86RF2XX_PARAMS_H_ */
/** @} */
diff --git a/drivers/Makefile.include b/drivers/Makefile.include
index 6125961bde984b44c163298bda7744cec0cfd7e2..e15584f92d04bbceefdd4dea4e5f1b3c9a8d567d 100644
--- a/drivers/Makefile.include
+++ b/drivers/Makefile.include
@@ -1,8 +1,8 @@
ifneq (,$(filter dht,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/dht/include
endif
-ifneq (,$(filter ng_at86rf2xx,$(USEMODULE)))
- USEMODULE_INCLUDES += $(RIOTBASE)/drivers/ng_at86rf2xx/include
+ifneq (,$(filter at86rf2xx,$(USEMODULE)))
+ USEMODULE_INCLUDES += $(RIOTBASE)/drivers/at86rf2xx/include
endif
ifneq (,$(filter kw2xrf,$(USEMODULE)))
USEMODULE_INCLUDES += $(RIOTBASE)/drivers/kw2xrf/include
diff --git a/drivers/ng_at86rf2xx/Makefile b/drivers/at86rf2xx/Makefile
similarity index 100%
rename from drivers/ng_at86rf2xx/Makefile
rename to drivers/at86rf2xx/Makefile
diff --git a/drivers/ng_at86rf2xx/ng_at86rf2xx.c b/drivers/at86rf2xx/at86rf2xx.c
similarity index 54%
rename from drivers/ng_at86rf2xx/ng_at86rf2xx.c
rename to drivers/at86rf2xx/at86rf2xx.c
index 75497d249b67a1dcccbfe1675d13703c376635ce..be5ba88b93231effc3e9a6391c262a72ffd29bd4 100644
--- a/drivers/ng_at86rf2xx/ng_at86rf2xx.c
+++ b/drivers/at86rf2xx/at86rf2xx.c
@@ -8,7 +8,7 @@
*/
/**
- * @ingroup drivers_ng_at86rf2xx
+ * @ingroup drivers_at86rf2xx
* @{
*
* @file
@@ -28,9 +28,9 @@
#include "byteorder.h"
#include "net/ieee802154.h"
#include "net/ng_netbase.h"
-#include "ng_at86rf2xx_registers.h"
-#include "ng_at86rf2xx_internal.h"
-#include "ng_at86rf2xx_netdev.h"
+#include "at86rf2xx_registers.h"
+#include "at86rf2xx_internal.h"
+#include "at86rf2xx_netdev.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
@@ -42,18 +42,18 @@
static void _irq_handler(void *arg)
{
msg_t msg;
- ng_at86rf2xx_t *dev = (ng_at86rf2xx_t *) arg;
+ at86rf2xx_t *dev = (at86rf2xx_t *) arg;
/* tell driver thread about the interrupt */
msg.type = NG_NETDEV_MSG_TYPE_EVENT;
msg_send(&msg, dev->mac_pid);
}
-int ng_at86rf2xx_init(ng_at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed,
- gpio_t cs_pin, gpio_t int_pin,
- gpio_t sleep_pin, gpio_t reset_pin)
+int at86rf2xx_init(at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed,
+ gpio_t cs_pin, gpio_t int_pin,
+ gpio_t sleep_pin, gpio_t reset_pin)
{
- dev->driver = &ng_at86rf2xx_driver;
+ dev->driver = &at86rf2xx_driver;
/* initialize device descriptor */
dev->spi = spi;
@@ -61,7 +61,7 @@ int ng_at86rf2xx_init(ng_at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed,
dev->int_pin = int_pin;
dev->sleep_pin = sleep_pin;
dev->reset_pin = reset_pin;
- dev->idle_state = NG_AT86RF2XX_STATE_TRX_OFF;
+ dev->idle_state = AT86RF2XX_STATE_TRX_OFF;
/* initialise SPI */
spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, spi_speed);
@@ -75,18 +75,18 @@ int ng_at86rf2xx_init(ng_at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed,
gpio_init_int(dev->int_pin, GPIO_NOPULL, GPIO_RISING, _irq_handler, dev);
/* test if the SPI is set up correctly and the device is responding */
- if (ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__PART_NUM) !=
- NG_AT86RF2XX_PARTNUM) {
- DEBUG("[ng_at86rf2xx] error: unable to read correct part number\n");
+ if (at86rf2xx_reg_read(dev, AT86RF2XX_REG__PART_NUM) !=
+ AT86RF2XX_PARTNUM) {
+ DEBUG("[at86rf2xx] error: unable to read correct part number\n");
return -1;
}
/* reset device to default values and put it into RX state */
- ng_at86rf2xx_reset(dev);
+ at86rf2xx_reset(dev);
return 0;
}
-void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev)
+void at86rf2xx_reset(at86rf2xx_t *dev)
{
#if CPUID_ID_LEN
uint8_t cpuid[CPUID_ID_LEN];
@@ -101,7 +101,7 @@ void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev)
gpio_set(dev->reset_pin);
/* Reset state machine to ensure a known state */
- ng_at86rf2xx_reset_state_machine(dev);
+ at86rf2xx_reset_state_machine(dev);
/* reset options and sequence number */
dev->seq_nr = 0;
@@ -125,23 +125,23 @@ void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev)
cpuid[0] |= 0x02;
/* copy and set long address */
memcpy(&addr_long, cpuid, 8);
- ng_at86rf2xx_set_addr_long(dev, NTOHLL(addr_long.uint64.u64));
- ng_at86rf2xx_set_addr_short(dev, NTOHS(addr_long.uint16[0].u16));
+ at86rf2xx_set_addr_long(dev, NTOHLL(addr_long.uint64.u64));
+ at86rf2xx_set_addr_short(dev, NTOHS(addr_long.uint16[0].u16));
#else
- ng_at86rf2xx_set_addr_long(dev, NG_AT86RF2XX_DEFAULT_ADDR_LONG);
- ng_at86rf2xx_set_addr_short(dev, NG_AT86RF2XX_DEFAULT_ADDR_SHORT);
+ at86rf2xx_set_addr_long(dev, AT86RF2XX_DEFAULT_ADDR_LONG);
+ at86rf2xx_set_addr_short(dev, AT86RF2XX_DEFAULT_ADDR_SHORT);
#endif
/* set default PAN id */
- ng_at86rf2xx_set_pan(dev, NG_AT86RF2XX_DEFAULT_PANID);
+ at86rf2xx_set_pan(dev, AT86RF2XX_DEFAULT_PANID);
/* set default channel */
- ng_at86rf2xx_set_chan(dev, NG_AT86RF2XX_DEFAULT_CHANNEL);
+ at86rf2xx_set_chan(dev, AT86RF2XX_DEFAULT_CHANNEL);
/* set default TX power */
- ng_at86rf2xx_set_txpower(dev, NG_AT86RF2XX_DEFAULT_TXPOWER);
+ at86rf2xx_set_txpower(dev, AT86RF2XX_DEFAULT_TXPOWER);
/* set default options */
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_AUTOACK, true);
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_CSMA, true);
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_RX_START, false);
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_RX_END, true);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_AUTOACK, true);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_CSMA, true);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_START, false);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_END, true);
/* set default protocol */
#ifdef MODULE_NG_SIXLOWPAN
dev->proto = NG_NETTYPE_SIXLOWPAN;
@@ -149,44 +149,44 @@ void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev)
dev->proto = NG_NETTYPE_UNDEF;
#endif
/* enable safe mode (protect RX FIFO until reading data starts) */
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_CTRL_2,
- NG_AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_2,
+ AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE);
#ifdef MODULE_NG_AT86RF212B
- ng_at86rf2xx_set_freq(dev,NG_AT86RF2XX_FREQ_915MHZ);
+ at86rf2xx_set_freq(dev, AT86RF2XX_FREQ_915MHZ);
#endif
/* don't populate masked interrupt flags to IRQ_STATUS register */
- uint8_t tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__TRX_CTRL_1);
- tmp &= ~(NG_AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_CTRL_1, tmp);
+ uint8_t tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_1);
+ tmp &= ~(AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_1, tmp);
/* enable interrupts */
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK,
- NG_AT86RF2XX_IRQ_STATUS_MASK__TRX_END);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__IRQ_MASK,
+ AT86RF2XX_IRQ_STATUS_MASK__TRX_END);
/* clear interrupt flags */
- ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__IRQ_STATUS);
+ at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_STATUS);
/* go into RX state */
- ng_at86rf2xx_set_state(dev, NG_AT86RF2XX_STATE_RX_AACK_ON);
+ at86rf2xx_set_state(dev, AT86RF2XX_STATE_RX_AACK_ON);
- DEBUG("ng_at86rf2xx_reset(): reset complete.\n");
+ DEBUG("at86rf2xx_reset(): reset complete.\n");
}
-bool ng_at86rf2xx_cca(ng_at86rf2xx_t *dev)
+bool at86rf2xx_cca(at86rf2xx_t *dev)
{
uint8_t tmp;
uint8_t status;
/* trigger CCA measurment */
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__PHY_CC_CCA);
- tmp &= NG_AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__PHY_CC_CCA, tmp);
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__PHY_CC_CCA);
+ tmp &= AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__PHY_CC_CCA, tmp);
/* wait for result to be ready */
do {
- status = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__TRX_STATUS);
- } while (!(status & NG_AT86RF2XX_TRX_STATUS_MASK__CCA_DONE));
+ status = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_STATUS);
+ } while (!(status & AT86RF2XX_TRX_STATUS_MASK__CCA_DONE));
/* return according to measurement */
- if (status & NG_AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS) {
+ if (status & AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS) {
return true;
}
else {
@@ -194,65 +194,65 @@ bool ng_at86rf2xx_cca(ng_at86rf2xx_t *dev)
}
}
-size_t ng_at86rf2xx_send(ng_at86rf2xx_t *dev, uint8_t *data, size_t len)
+size_t at86rf2xx_send(at86rf2xx_t *dev, uint8_t *data, size_t len)
{
/* check data length */
- if (len > NG_AT86RF2XX_MAX_PKT_LENGTH) {
- DEBUG("[ng_at86rf2xx] Error: data to send exceeds max packet size\n");
+ if (len > AT86RF2XX_MAX_PKT_LENGTH) {
+ DEBUG("[at86rf2xx] Error: data to send exceeds max packet size\n");
return 0;
}
- ng_at86rf2xx_tx_prepare(dev);
- ng_at86rf2xx_tx_load(dev, data, len, 0);
- ng_at86rf2xx_tx_exec(dev);
+ at86rf2xx_tx_prepare(dev);
+ at86rf2xx_tx_load(dev, data, len, 0);
+ at86rf2xx_tx_exec(dev);
return len;
}
-void ng_at86rf2xx_tx_prepare(ng_at86rf2xx_t *dev)
+void at86rf2xx_tx_prepare(at86rf2xx_t *dev)
{
uint8_t state;
/* make sure ongoing transmissions are finished */
do {
- state = ng_at86rf2xx_get_status(dev);
+ state = at86rf2xx_get_status(dev);
}
- while (state == NG_AT86RF2XX_STATE_BUSY_RX_AACK ||
- state == NG_AT86RF2XX_STATE_BUSY_TX_ARET);
- if (state != NG_AT86RF2XX_STATE_TX_ARET_ON) {
+ while (state == AT86RF2XX_STATE_BUSY_RX_AACK ||
+ state == AT86RF2XX_STATE_BUSY_TX_ARET);
+ if (state != AT86RF2XX_STATE_TX_ARET_ON) {
dev->idle_state = state;
}
- ng_at86rf2xx_set_state(dev, NG_AT86RF2XX_STATE_TX_ARET_ON);
+ at86rf2xx_set_state(dev, AT86RF2XX_STATE_TX_ARET_ON);
dev->frame_len = IEEE802154_FCS_LEN;
}
-size_t ng_at86rf2xx_tx_load(ng_at86rf2xx_t *dev, uint8_t *data,
- size_t len, size_t offset)
+size_t at86rf2xx_tx_load(at86rf2xx_t *dev, uint8_t *data,
+ size_t len, size_t offset)
{
dev->frame_len += (uint8_t)len;
- ng_at86rf2xx_sram_write(dev, offset + 1, data, len);
+ at86rf2xx_sram_write(dev, offset + 1, data, len);
return offset + len;
}
-void ng_at86rf2xx_tx_exec(ng_at86rf2xx_t *dev)
+void at86rf2xx_tx_exec(at86rf2xx_t *dev)
{
/* write frame length field in FIFO */
- ng_at86rf2xx_sram_write(dev, 0, &(dev->frame_len), 1);
+ at86rf2xx_sram_write(dev, 0, &(dev->frame_len), 1);
/* trigger sending of pre-loaded frame */
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_STATE,
- NG_AT86RF2XX_TRX_STATE__TX_START);
- if (dev->event_cb && (dev->options & NG_AT86RF2XX_OPT_TELL_TX_START)) {
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_STATE,
+ AT86RF2XX_TRX_STATE__TX_START);
+ if (dev->event_cb && (dev->options & AT86RF2XX_OPT_TELL_TX_START)) {
dev->event_cb(NETDEV_EVENT_TX_STARTED, NULL);
}
}
-size_t ng_at86rf2xx_rx_len(ng_at86rf2xx_t *dev)
+size_t at86rf2xx_rx_len(at86rf2xx_t *dev)
{
uint8_t res;
- ng_at86rf2xx_fb_read(dev, &res, 1);
+ at86rf2xx_fb_read(dev, &res, 1);
return (size_t)(res - 2); /* extract the PHR and LQI field */
}
-void ng_at86rf2xx_rx_read(ng_at86rf2xx_t *dev, uint8_t *data, size_t len,
- size_t offset)
+void at86rf2xx_rx_read(at86rf2xx_t *dev, uint8_t *data, size_t len,
+ size_t offset)
{
/* when reading from SRAM, the different chips from the AT86RF2xx family
* behave differently: the AT86F233, the AT86RF232 and the ATRF86212B return
@@ -262,8 +262,8 @@ void ng_at86rf2xx_rx_read(ng_at86rf2xx_t *dev, uint8_t *data, size_t len,
* the first data byte at position 0.
*/
#ifndef MODULE_NG_AT86RF231
- ng_at86rf2xx_sram_read(dev, offset + 1, data, len);
+ at86rf2xx_sram_read(dev, offset + 1, data, len);
#else
- ng_at86rf2xx_sram_read(dev, offset, data, len);
+ at86rf2xx_sram_read(dev, offset, data, len);
#endif
}
diff --git a/drivers/at86rf2xx/at86rf2xx_getset.c b/drivers/at86rf2xx/at86rf2xx_getset.c
new file mode 100644
index 0000000000000000000000000000000000000000..ea5eb7061ab12c2df86d6d6431b7b8b119ddabdd
--- /dev/null
+++ b/drivers/at86rf2xx/at86rf2xx_getset.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup drivers_at86rf2xx
+ * @{
+ *
+ * @file
+ * @brief Getter and setter functions for the AT86RF2xx drivers
+ *
+ * @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author Baptiste Clenet <bapclenet@gmail.com>
+ *
+ * @}
+ */
+
+#include "at86rf2xx.h"
+#include "at86rf2xx_internal.h"
+#include "at86rf2xx_registers.h"
+#include "periph/spi.h"
+
+#define ENABLE_DEBUG (0)
+#include "debug.h"
+
+#ifdef MODULE_NG_AT86RF212B
+/* See: Table 9-15. Recommended Mapping of TX Power, Frequency Band, and
+ * PHY_TX_PWR (register 0x05), AT86RF212B data sheet. */
+static const uint8_t dbm_to_tx_pow_868[] = {0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
+ 0x17, 0x15, 0x14, 0x13, 0x12, 0x11,
+ 0x10, 0x0f, 0x31, 0x30, 0x2f, 0x94,
+ 0x93, 0x91, 0x90, 0x29, 0x49, 0x48,
+ 0x47, 0xad, 0xcd, 0xcc, 0xcb, 0xea,
+ 0xe9, 0xe8, 0xe7, 0xe6, 0xe4, 0x80,
+ 0xa0};
+static const uint8_t dbm_to_tx_pow_915[] = {0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x17,
+ 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
+ 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b,
+ 0x09, 0x91, 0x08, 0x07, 0x05, 0x27,
+ 0x04, 0x03, 0x02, 0x01, 0x00, 0x86,
+ 0x40, 0x84, 0x83, 0x82, 0x80, 0xc1,
+ 0xc0};
+int16_t tx_pow_to_dbm(at86rf2xx_freq_t freq, uint8_t reg) {
+ for(int i = 0; i < 37; i++){
+ if(freq == AT86RF2XX_FREQ_868MHZ){
+ if (dbm_to_tx_pow_868[i] == reg) {
+ return i -25;
+ }
+ } else if (freq == AT86RF2XX_FREQ_915MHZ){
+ if (dbm_to_tx_pow_915[i] == reg) {
+ return i -25;
+ }
+ }
+ }
+ return 0;
+}
+
+#elif MODULE_NG_AT86RF233
+static const int16_t tx_pow_to_dbm[] = {4, 4, 3, 3, 2, 2, 1,
+ 0, -1, -2, -3, -4, -6, -8, -12, -17};
+static const uint8_t dbm_to_tx_pow[] = {0x0f, 0x0f, 0x0f, 0x0e, 0x0e, 0x0e,
+ 0x0e, 0x0d, 0x0d, 0x0d, 0x0c, 0x0c,
+ 0x0b, 0x0b, 0x0a, 0x09, 0x08, 0x07,
+ 0x06, 0x05, 0x03,0x00};
+#else
+static const int16_t tx_pow_to_dbm[] = {3, 3, 2, 2, 1, 1, 0,
+ -1, -2, -3, -4, -5, -7, -9, -12, -17};
+static const uint8_t dbm_to_tx_pow[] = {0x0f, 0x0f, 0x0f, 0x0e, 0x0e, 0x0e,
+ 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
+ 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
+ 0x05, 0x03, 0x00};
+#endif
+
+uint16_t at86rf2xx_get_addr_short(at86rf2xx_t *dev)
+{
+ return (dev->addr_short[0] << 8) | dev->addr_short[1];
+}
+
+void at86rf2xx_set_addr_short(at86rf2xx_t *dev, uint16_t addr)
+{
+ dev->addr_short[0] = addr >> 8;
+ dev->addr_short[1] = addr & 0xff;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__SHORT_ADDR_0,
+ dev->addr_short[0]);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__SHORT_ADDR_1,
+ dev->addr_short[1]);
+}
+
+uint64_t at86rf2xx_get_addr_long(at86rf2xx_t *dev)
+{
+ uint64_t addr;
+ uint8_t *ap = (uint8_t *)(&addr);
+ for (int i = 0; i < 8; i++) {
+ ap[i] = dev->addr_long[7 - i];
+ }
+ return addr;
+}
+
+void at86rf2xx_set_addr_long(at86rf2xx_t *dev, uint64_t addr)
+{
+ for (int i = 0; i < 8; i++) {
+ dev->addr_long[i] = (addr >> ((7 - i) * 8));
+ at86rf2xx_reg_write(dev, (AT86RF2XX_REG__IEEE_ADDR_0 + i),
+ dev->addr_long[i]);
+ }
+}
+
+uint8_t at86rf2xx_get_chan(at86rf2xx_t *dev)
+{
+ return dev->chan;
+}
+
+void at86rf2xx_set_chan(at86rf2xx_t *dev, uint8_t channel)
+{
+ uint8_t tmp;
+
+ if (channel < AT86RF2XX_MIN_CHANNEL
+ || channel > AT86RF2XX_MAX_CHANNEL) {
+ return;
+ }
+ dev->chan = channel;
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__PHY_CC_CCA);
+ tmp &= ~(AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL);
+ tmp |= (channel & AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__PHY_CC_CCA, tmp);
+}
+
+#ifdef MODULE_NG_AT86RF212B
+at86rf2xx_freq_t at86rf2xx_get_freq(at86rf2xx_t *dev)
+{
+ return dev->freq;
+}
+
+void at86rf2xx_set_freq(at86rf2xx_t *dev, at86rf2xx_freq_t freq)
+{
+ uint8_t trx_ctrl2 = 0, rf_ctrl0 = 0;
+ trx_ctrl2 = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_2);
+ trx_ctrl2 &= ~(AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE);
+ rf_ctrl0 = at86rf2xx_reg_read(dev, AT86RF2XX_REG__RF_CTRL_0);
+ /* Erase previous conf for GC_TX_OFFS */
+ rf_ctrl0 &= ~AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS;
+
+ trx_ctrl2 |= AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE;
+ rf_ctrl0 |= AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB;
+
+ switch(freq) {
+ case AT86RF2XX_FREQ_915MHZ:
+ if (dev->chan == 0) {
+ at86rf2xx_set_chan(dev,AT86RF2XX_DEFAULT_CHANNEL);
+ } else {
+ at86rf2xx_set_chan(dev,dev->chan);
+ }
+ break;
+
+ case AT86RF2XX_FREQ_868MHZ:
+ /* Channel = 0 for 868MHz means 868.3MHz, only one available */
+ at86rf2xx_set_chan(dev,0x00);
+ break;
+
+ default:
+ DEBUG("at86rf2xx: Trying to set unknown frequency 0x%lx\n",
+ (unsigned long) freq);
+ return;
+ }
+ dev->freq = freq;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_2, trx_ctrl2);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__RF_CTRL_0, rf_ctrl0);
+}
+#endif
+
+uint16_t at86rf2xx_get_pan(at86rf2xx_t *dev)
+{
+ return dev->pan;
+}
+
+void at86rf2xx_set_pan(at86rf2xx_t *dev, uint16_t pan)
+{
+ dev->pan = pan;
+ DEBUG("pan0: %u, pan1: %u\n", (uint8_t)pan, pan >> 8);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__PAN_ID_0, (uint8_t)pan);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__PAN_ID_1, (pan >> 8));
+}
+
+int16_t at86rf2xx_get_txpower(at86rf2xx_t *dev)
+{
+#ifdef MODULE_NG_AT86RF212B
+ uint8_t txpower = at86rf2xx_reg_read(dev, AT86RF2XX_REG__PHY_TX_PWR);
+ DEBUG("txpower value: %x\n", txpower);
+ return tx_pow_to_dbm(dev->freq, txpower);
+#else
+ uint8_t txpower = at86rf2xx_reg_read(dev, AT86RF2XX_REG__PHY_TX_PWR)
+ & AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR;
+ return tx_pow_to_dbm[txpower];
+#endif
+}
+
+void at86rf2xx_set_txpower(at86rf2xx_t *dev, int16_t txpower)
+{
+#ifdef MODULE_NG_AT86RF212B
+ txpower += 25;
+#else
+ txpower += 17;
+#endif
+ if (txpower < 0) {
+ txpower = 0;
+#ifdef MODULE_NG_AT86RF212B
+ }
+ else if (txpower > 36) {
+ txpower = 36;
+#elif MODULE_NG_AT86RF233
+ }
+ else if (txpower > 21) {
+ txpower = 21;
+#else
+ }
+ else if (txpower > 20) {
+ txpower = 20;
+#endif
+ }
+#ifdef MODULE_NG_AT86RF212B
+ if (dev->freq == AT86RF2XX_FREQ_915MHZ) {
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__PHY_TX_PWR,
+ dbm_to_tx_pow_915[txpower]);
+ }
+ else if (dev->freq == AT86RF2XX_FREQ_868MHZ) {
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__PHY_TX_PWR,
+ dbm_to_tx_pow_868[txpower]);
+ }
+ else {
+ return;
+ }
+#else
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__PHY_TX_PWR,
+ dbm_to_tx_pow[txpower]);
+#endif
+}
+
+uint8_t at86rf2xx_get_max_retries(at86rf2xx_t *dev)
+{
+ return (at86rf2xx_reg_read(dev, AT86RF2XX_REG__XAH_CTRL_0) >> 4);
+}
+
+void at86rf2xx_set_max_retries(at86rf2xx_t *dev, uint8_t max)
+{
+ max = (max > 7) ? 7 : max;
+ uint8_t tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__XAH_CTRL_0);
+ tmp &= ~(AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES);
+ tmp |= (max << 4);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__XAH_CTRL_0, tmp);
+}
+
+void at86rf2xx_set_option(at86rf2xx_t *dev, uint16_t option, bool state)
+{
+ uint8_t tmp;
+
+ DEBUG("set option %i to %i\n", option, state);
+
+ /* set option field */
+ if (state) {
+ dev->options |= option;
+ /* trigger option specific actions */
+ switch (option) {
+ case AT86RF2XX_OPT_CSMA:
+ DEBUG("[at86rf2xx] opt: enabling CSMA mode (NOT IMPLEMENTED)\n");
+ /* TODO: en/disable csma */
+ break;
+ case AT86RF2XX_OPT_PROMISCUOUS:
+ DEBUG("[at86rf2xx] opt: enabling PROMISCUOUS mode\n");
+ /* disable auto ACKs in promiscuous mode */
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__CSMA_SEED_1);
+ tmp |= AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__CSMA_SEED_1, tmp);
+ /* enable promiscuous mode */
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__XAH_CTRL_1);
+ tmp |= AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__XAH_CTRL_1, tmp);
+ break;
+ case AT86RF2XX_OPT_AUTOACK:
+ DEBUG("[at86rf2xx] opt: enabling auto ACKs\n");
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__CSMA_SEED_1);
+ tmp &= ~(AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__CSMA_SEED_1, tmp);
+ break;
+ case AT86RF2XX_OPT_TELL_RX_START:
+ DEBUG("[at86rf2xx] opt: enabling SFD IRQ\n");
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_MASK);
+ tmp |= AT86RF2XX_IRQ_STATUS_MASK__RX_START;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__IRQ_MASK, tmp);
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+ else {
+ dev->options &= ~(option);
+ /* trigger option specific actions */
+ switch (option) {
+ case AT86RF2XX_OPT_CSMA:
+ DEBUG("[at86rf2xx] opt: disabling CSMA mode (NOT IMPLEMENTED)\n");
+ /* TODO: en/disable csma */
+ break;
+ case AT86RF2XX_OPT_PROMISCUOUS:
+ DEBUG("[at86rf2xx] opt: disabling PROMISCUOUS mode\n");
+ /* disable promiscuous mode */
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__XAH_CTRL_1);
+ tmp &= ~(AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__XAH_CTRL_1, tmp);
+ /* re-enable AUTOACK only if the option is set */
+ if (dev->options & AT86RF2XX_OPT_AUTOACK) {
+ tmp = at86rf2xx_reg_read(dev,
+ AT86RF2XX_REG__CSMA_SEED_1);
+ tmp &= ~(AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK);
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__CSMA_SEED_1,
+ tmp);
+ }
+ break;
+ case AT86RF2XX_OPT_AUTOACK:
+ DEBUG("[at86rf2xx] opt: disabling auto ACKs\n");
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__CSMA_SEED_1);
+ tmp |= AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__CSMA_SEED_1, tmp);
+ break;
+ case AT86RF2XX_OPT_TELL_RX_START:
+ DEBUG("[at86rf2xx] opt: disabling SFD IRQ\n");
+ tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_MASK);
+ tmp &= ~AT86RF2XX_IRQ_STATUS_MASK__RX_START;
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__IRQ_MASK, tmp);
+ break;
+ default:
+ /* do nothing */
+ break;
+ }
+ }
+}
+
+static inline void _set_state(at86rf2xx_t *dev, uint8_t state)
+{
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_STATE, state);
+ while (at86rf2xx_get_status(dev) != state);
+}
+
+static inline void _force_trx_off(at86rf2xx_t *dev)
+{
+ at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_STATE, AT86RF2XX_TRX_STATE__FORCE_TRX_OFF);
+ while (at86rf2xx_get_status(dev) != AT86RF2XX_STATE_TRX_OFF);
+}
+
+void at86rf2xx_set_state(at86rf2xx_t *dev, uint8_t state)
+{
+ uint8_t old_state = at86rf2xx_get_status(dev);
+
+ if (state == old_state) {
+ return;
+ }
+ /* make sure there is no ongoing transmission, or state transition already
+ * in progress */
+ while (old_state == AT86RF2XX_STATE_BUSY_RX_AACK ||
+ old_state == AT86RF2XX_STATE_BUSY_TX_ARET ||
+ old_state == AT86RF2XX_STATE_IN_PROGRESS) {
+ old_state = at86rf2xx_get_status(dev);
+ }
+
+ /* we need to go via PLL_ON if we are moving between RX_AACK_ON <-> TX_ARET_ON */
+ if ((old_state == AT86RF2XX_STATE_RX_AACK_ON &&
+ state == AT86RF2XX_STATE_TX_ARET_ON) ||
+ (old_state == AT86RF2XX_STATE_TX_ARET_ON &&
+ state == AT86RF2XX_STATE_RX_AACK_ON)) {
+ _set_state(dev, AT86RF2XX_STATE_PLL_ON);
+ }
+ /* check if we need to wake up from sleep mode */
+ else if (old_state == AT86RF2XX_STATE_SLEEP) {
+ DEBUG("at86rf2xx: waking up from sleep mode\n");
+ gpio_clear(dev->sleep_pin);
+ while (at86rf2xx_get_status(dev) != AT86RF2XX_STATE_TRX_OFF);
+ }
+
+ if (state == AT86RF2XX_STATE_SLEEP) {
+ /* First go to TRX_OFF */
+ _force_trx_off(dev);
+ /* Go to SLEEP mode from TRX_OFF */
+ gpio_set(dev->sleep_pin);
+ } else {
+ _set_state(dev, state);
+ }
+}
+
+void at86rf2xx_reset_state_machine(at86rf2xx_t *dev)
+{
+ uint8_t old_state;
+
+ /* Wake up */
+ gpio_clear(dev->sleep_pin);
+
+ /* Wait for any state transitions to complete before forcing TRX_OFF */
+ do {
+ old_state = at86rf2xx_get_status(dev);
+ } while (old_state == AT86RF2XX_STATE_IN_PROGRESS);
+
+ _force_trx_off(dev);
+}
diff --git a/drivers/ng_at86rf2xx/ng_at86rf2xx_internal.c b/drivers/at86rf2xx/at86rf2xx_internal.c
similarity index 53%
rename from drivers/ng_at86rf2xx/ng_at86rf2xx_internal.c
rename to drivers/at86rf2xx/at86rf2xx_internal.c
index 95511009a8638c30b827e85edec24d1b781ddcfd..c18d5c576e940d2ba92260f6a3e1c04a86e0f881 100644
--- a/drivers/ng_at86rf2xx/ng_at86rf2xx_internal.c
+++ b/drivers/at86rf2xx/at86rf2xx_internal.c
@@ -8,7 +8,7 @@
*/
/**
- * @ingroup drivers_ng_at86rf2xx
+ * @ingroup drivers_at86rf2xx
* @{
*
* @file
@@ -24,30 +24,30 @@
#include "periph/spi.h"
#include "periph/gpio.h"
-#include "ng_at86rf2xx_internal.h"
-#include "ng_at86rf2xx_registers.h"
+#include "at86rf2xx_internal.h"
+#include "at86rf2xx_registers.h"
-void ng_at86rf2xx_reg_write(const ng_at86rf2xx_t *dev,
- const uint8_t addr,
- const uint8_t value)
+void at86rf2xx_reg_write(const at86rf2xx_t *dev,
+ const uint8_t addr,
+ const uint8_t value)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
- NG_AT86RF2XX_ACCESS_REG | NG_AT86RF2XX_ACCESS_WRITE | addr,
+ AT86RF2XX_ACCESS_REG | AT86RF2XX_ACCESS_WRITE | addr,
value, 0);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
-uint8_t ng_at86rf2xx_reg_read(const ng_at86rf2xx_t *dev, const uint8_t addr)
+uint8_t at86rf2xx_reg_read(const at86rf2xx_t *dev, const uint8_t addr)
{
char value;
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
- NG_AT86RF2XX_ACCESS_REG | NG_AT86RF2XX_ACCESS_READ | addr,
+ AT86RF2XX_ACCESS_REG | AT86RF2XX_ACCESS_READ | addr,
0, &value);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
@@ -55,52 +55,52 @@ uint8_t ng_at86rf2xx_reg_read(const ng_at86rf2xx_t *dev, const uint8_t addr)
return (uint8_t)value;
}
-void ng_at86rf2xx_sram_read(const ng_at86rf2xx_t *dev,
- const uint8_t offset,
- uint8_t *data,
- const size_t len)
+void at86rf2xx_sram_read(const at86rf2xx_t *dev,
+ const uint8_t offset,
+ uint8_t *data,
+ const size_t len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
- NG_AT86RF2XX_ACCESS_SRAM | NG_AT86RF2XX_ACCESS_READ,
+ AT86RF2XX_ACCESS_SRAM | AT86RF2XX_ACCESS_READ,
(char)offset, NULL);
- spi_transfer_bytes(dev->spi, NULL, (char*)data, len);
+ spi_transfer_bytes(dev->spi, NULL, (char *)data, len);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
-void ng_at86rf2xx_sram_write(const ng_at86rf2xx_t *dev,
- const uint8_t offset,
- const uint8_t *data,
- const size_t len)
+void at86rf2xx_sram_write(const at86rf2xx_t *dev,
+ const uint8_t offset,
+ const uint8_t *data,
+ const size_t len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
- NG_AT86RF2XX_ACCESS_SRAM | NG_AT86RF2XX_ACCESS_WRITE,
+ AT86RF2XX_ACCESS_SRAM | AT86RF2XX_ACCESS_WRITE,
(char)offset, NULL);
- spi_transfer_bytes(dev->spi, (char*)data, NULL, len);
+ spi_transfer_bytes(dev->spi, (char *)data, NULL, len);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
-void ng_at86rf2xx_fb_read(const ng_at86rf2xx_t *dev,
- uint8_t *data,
- const size_t len)
+void at86rf2xx_fb_read(const at86rf2xx_t *dev,
+ uint8_t *data,
+ const size_t len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_byte(dev->spi,
- NG_AT86RF2XX_ACCESS_FB | NG_AT86RF2XX_ACCESS_READ,
+ AT86RF2XX_ACCESS_FB | AT86RF2XX_ACCESS_READ,
NULL);
spi_transfer_bytes(dev->spi, NULL, (char *)data, len);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
-uint8_t ng_at86rf2xx_get_status(const ng_at86rf2xx_t *dev)
+uint8_t at86rf2xx_get_status(const at86rf2xx_t *dev)
{
- return (ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__TRX_STATUS)
- & NG_AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS);
+ return (at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_STATUS)
+ & AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS);
}
diff --git a/drivers/ng_at86rf2xx/ng_at86rf2xx_netdev.c b/drivers/at86rf2xx/at86rf2xx_netdev.c
similarity index 71%
rename from drivers/ng_at86rf2xx/ng_at86rf2xx_netdev.c
rename to drivers/at86rf2xx/at86rf2xx_netdev.c
index 009bb39da68ceb336405588a118ac4fed70417e4..3be39058f54aa09a727cf7151a00b82c637a5319 100644
--- a/drivers/ng_at86rf2xx/ng_at86rf2xx_netdev.c
+++ b/drivers/at86rf2xx/at86rf2xx_netdev.c
@@ -7,7 +7,7 @@
*/
/**
- * @ingroup drivers_ng_at86rf2xx
+ * @ingroup drivers_at86rf2xx
* @{
*
* @file
@@ -22,10 +22,10 @@
#include "net/eui64.h"
#include "net/ieee802154.h"
#include "net/ng_netbase.h"
-#include "ng_at86rf2xx.h"
-#include "ng_at86rf2xx_netdev.h"
-#include "ng_at86rf2xx_internal.h"
-#include "ng_at86rf2xx_registers.h"
+#include "at86rf2xx.h"
+#include "at86rf2xx_netdev.h"
+#include "at86rf2xx_internal.h"
+#include "at86rf2xx_registers.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
@@ -33,7 +33,7 @@
#define _MAX_MHR_OVERHEAD (25)
/* TODO: generalize and move to (gnrc_)ieee802154 */
-static size_t _make_data_frame_hdr(ng_at86rf2xx_t *dev, uint8_t *buf,
+static size_t _make_data_frame_hdr(at86rf2xx_t *dev, uint8_t *buf,
ng_netif_hdr_t *hdr)
{
int pos = 0;
@@ -45,7 +45,7 @@ static size_t _make_data_frame_hdr(ng_at86rf2xx_t *dev, uint8_t *buf,
/* if AUTOACK is enabled, then we also expect ACKs for this packet */
if (!(hdr->flags & NG_NETIF_HDR_FLAGS_BROADCAST) &&
!(hdr->flags & NG_NETIF_HDR_FLAGS_MULTICAST) &&
- (dev->options & NG_AT86RF2XX_OPT_AUTOACK)) {
+ (dev->options & AT86RF2XX_OPT_AUTOACK)) {
buf[0] |= IEEE802154_FCF_ACK_REQ;
}
@@ -80,7 +80,7 @@ static size_t _make_data_frame_hdr(ng_at86rf2xx_t *dev, uint8_t *buf,
}
/* fill in source PAN ID (if applicable */
- if (dev->options & NG_AT86RF2XX_OPT_USE_SRC_PAN) {
+ if (dev->options & AT86RF2XX_OPT_USE_SRC_PAN) {
buf[pos++] = (uint8_t)((dev->pan) & 0xff);
buf[pos++] = (uint8_t)((dev->pan) >> 8);
} else {
@@ -88,7 +88,7 @@ static size_t _make_data_frame_hdr(ng_at86rf2xx_t *dev, uint8_t *buf,
}
/* fill in source address */
- if (dev->options & NG_AT86RF2XX_OPT_SRC_ADDR_LONG) {
+ if (dev->options & AT86RF2XX_OPT_SRC_ADDR_LONG) {
buf[1] |= IEEE802154_FCF_SRC_ADDR_LONG;
memcpy(&(buf[pos]), dev->addr_long, 8);
pos += 8;
@@ -211,7 +211,7 @@ static ng_pktsnip_t *_make_netif_hdr(uint8_t *mhr)
static int _send(ng_netdev_t *netdev, ng_pktsnip_t *pkt)
{
- ng_at86rf2xx_t *dev = (ng_at86rf2xx_t *)netdev;
+ at86rf2xx_t *dev = (at86rf2xx_t *)netdev;
ng_pktsnip_t *snip;
uint8_t mhr[IEEE802154_MAX_HDR_LEN];
size_t len;
@@ -227,30 +227,30 @@ static int _send(ng_netdev_t *netdev, ng_pktsnip_t *pkt)
/* create 802.15.4 header */
len = _make_data_frame_hdr(dev, mhr, (ng_netif_hdr_t *)pkt->data);
if (len == 0) {
- DEBUG("[ng_at86rf2xx] error: unable to create 802.15.4 header\n");
+ DEBUG("[at86rf2xx] error: unable to create 802.15.4 header\n");
ng_pktbuf_release(pkt);
return -ENOMSG;
}
/* check if packet (header + payload + FCS) fits into FIFO */
snip = pkt->next;
- if ((ng_pkt_len(snip) + len + 2) > NG_AT86RF2XX_MAX_PKT_LENGTH) {
- printf("[ng_at86rf2xx] error: packet too large (%u byte) to be send\n",
+ if ((ng_pkt_len(snip) + len + 2) > AT86RF2XX_MAX_PKT_LENGTH) {
+ printf("[at86rf2xx] error: packet too large (%u byte) to be send\n",
ng_pkt_len(snip) + len + 2);
ng_pktbuf_release(pkt);
return -EOVERFLOW;
}
- ng_at86rf2xx_tx_prepare(dev);
+ at86rf2xx_tx_prepare(dev);
/* put header into FIFO */
- len = ng_at86rf2xx_tx_load(dev, mhr, len, 0);
+ len = at86rf2xx_tx_load(dev, mhr, len, 0);
/* load packet data into FIFO */
while (snip) {
- len = ng_at86rf2xx_tx_load(dev, snip->data, snip->size, len);
+ len = at86rf2xx_tx_load(dev, snip->data, snip->size, len);
snip = snip->next;
}
/* send data out directly if pre-loading id disabled */
- if (!(dev->options & NG_AT86RF2XX_OPT_PRELOADING)) {
- ng_at86rf2xx_tx_exec(dev);
+ if (!(dev->options & AT86RF2XX_OPT_PRELOADING)) {
+ at86rf2xx_tx_exec(dev);
}
/* release packet */
ng_pktbuf_release(pkt);
@@ -258,7 +258,7 @@ static int _send(ng_netdev_t *netdev, ng_pktsnip_t *pkt)
return (int)len;
}
-static void _receive_data(ng_at86rf2xx_t *dev)
+static void _receive_data(at86rf2xx_t *dev)
{
uint8_t mhr[IEEE802154_MAX_HDR_LEN];
size_t pkt_len, hdr_len;
@@ -266,7 +266,7 @@ static void _receive_data(ng_at86rf2xx_t *dev)
ng_netif_hdr_t *netif;
/* get the size of the received packet (unlocks frame buffer protection) */
- pkt_len = ng_at86rf2xx_rx_len(dev);
+ pkt_len = at86rf2xx_rx_len(dev);
/* abort here already if no event callback is registered */
if (!dev->event_cb) {
@@ -274,66 +274,66 @@ static void _receive_data(ng_at86rf2xx_t *dev)
}
/* in raw mode, just read the binary dump into the packet buffer */
- if (dev->options & NG_AT86RF2XX_OPT_RAWDUMP) {
+ if (dev->options & AT86RF2XX_OPT_RAWDUMP) {
payload = ng_pktbuf_add(NULL, NULL, pkt_len, NG_NETTYPE_UNDEF);
if (payload == NULL ) {
- DEBUG("[ng_at86rf2xx] error: unable to allocate RAW data\n");
+ DEBUG("[at86rf2xx] error: unable to allocate RAW data\n");
return;
}
- ng_at86rf2xx_rx_read(dev, payload->data, pkt_len, 0);
+ at86rf2xx_rx_read(dev, payload->data, pkt_len, 0);
dev->event_cb(NETDEV_EVENT_RX_COMPLETE, payload);
return;
}
/* get FCF field and compute 802.15.4 header length */
- ng_at86rf2xx_rx_read(dev, mhr, 2, 0);
+ at86rf2xx_rx_read(dev, mhr, 2, 0);
hdr_len = _get_frame_hdr_len(mhr);
if (hdr_len == 0) {
- DEBUG("[ng_at86rf2xx] error: unable parse incoming frame header\n");
+ DEBUG("[at86rf2xx] error: unable parse incoming frame header\n");
return;
}
/* read the rest of the header and parse the netif header from it */
- ng_at86rf2xx_rx_read(dev, &(mhr[2]), hdr_len - 2, 2);
+ at86rf2xx_rx_read(dev, &(mhr[2]), hdr_len - 2, 2);
hdr = _make_netif_hdr(mhr);
if (hdr == NULL) {
- DEBUG("[ng_at86rf2xx] error: unable to allocate netif header\n");
+ DEBUG("[at86rf2xx] error: unable to allocate netif header\n");
return;
}
/* fill missing fields in netif header */
netif = (ng_netif_hdr_t *)hdr->data;
netif->if_pid = dev->mac_pid;
- ng_at86rf2xx_rx_read(dev, &(netif->lqi), 1, pkt_len);
- netif->rssi = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__PHY_ED_LEVEL);
+ at86rf2xx_rx_read(dev, &(netif->lqi), 1, pkt_len);
+ netif->rssi = at86rf2xx_reg_read(dev, AT86RF2XX_REG__PHY_ED_LEVEL);
/* allocate payload */
payload = ng_pktbuf_add(hdr, NULL, (pkt_len - hdr_len), dev->proto);
if (payload == NULL) {
- DEBUG("[ng_at86rf2xx] error: unable to allocate incoming payload\n");
+ DEBUG("[at86rf2xx] error: unable to allocate incoming payload\n");
ng_pktbuf_release(hdr);
return;
}
/* copy payload */
- ng_at86rf2xx_rx_read(dev, payload->data, payload->size, hdr_len);
+ at86rf2xx_rx_read(dev, payload->data, payload->size, hdr_len);
/* finish up and send data to upper layers */
dev->event_cb(NETDEV_EVENT_RX_COMPLETE, payload);
}
-static int _set_state(ng_at86rf2xx_t *dev, netopt_state_t state)
+static int _set_state(at86rf2xx_t *dev, netopt_state_t state)
{
switch (state) {
case NETOPT_STATE_SLEEP:
- ng_at86rf2xx_set_state(dev, NG_AT86RF2XX_STATE_TRX_OFF);
+ at86rf2xx_set_state(dev, AT86RF2XX_STATE_TRX_OFF);
break;
case NETOPT_STATE_IDLE:
- ng_at86rf2xx_set_state(dev, NG_AT86RF2XX_STATE_RX_AACK_ON);
+ at86rf2xx_set_state(dev, AT86RF2XX_STATE_RX_AACK_ON);
break;
case NETOPT_STATE_TX:
- if (dev->options & NG_AT86RF2XX_OPT_PRELOADING) {
- ng_at86rf2xx_tx_exec(dev);
+ if (dev->options & AT86RF2XX_OPT_PRELOADING) {
+ at86rf2xx_tx_exec(dev);
}
break;
case NETOPT_STATE_RESET:
- ng_at86rf2xx_reset(dev);
+ at86rf2xx_reset(dev);
break;
default:
return -ENOTSUP;
@@ -341,17 +341,17 @@ static int _set_state(ng_at86rf2xx_t *dev, netopt_state_t state)
return sizeof(netopt_state_t);
}
-netopt_state_t _get_state(ng_at86rf2xx_t *dev)
+netopt_state_t _get_state(at86rf2xx_t *dev)
{
- switch (ng_at86rf2xx_get_status(dev)) {
- case NG_AT86RF2XX_STATE_SLEEP:
+ switch (at86rf2xx_get_status(dev)) {
+ case AT86RF2XX_STATE_SLEEP:
return NETOPT_STATE_SLEEP;
- case NG_AT86RF2XX_STATE_BUSY_RX_AACK:
+ case AT86RF2XX_STATE_BUSY_RX_AACK:
return NETOPT_STATE_RX;
- case NG_AT86RF2XX_STATE_BUSY_TX_ARET:
- case NG_AT86RF2XX_STATE_TX_ARET_ON:
+ case AT86RF2XX_STATE_BUSY_TX_ARET:
+ case AT86RF2XX_STATE_TX_ARET_ON:
return NETOPT_STATE_TX;
- case NG_AT86RF2XX_STATE_RX_AACK_ON:
+ case AT86RF2XX_STATE_RX_AACK_ON:
default:
return NETOPT_STATE_IDLE;
}
@@ -362,7 +362,7 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
if (device == NULL) {
return -ENODEV;
}
- ng_at86rf2xx_t *dev = (ng_at86rf2xx_t *) device;
+ at86rf2xx_t *dev = (at86rf2xx_t *) device;
switch (opt) {
@@ -370,14 +370,14 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
if (max_len < sizeof(uint16_t)) {
return -EOVERFLOW;
}
- *((uint16_t *)val) = ng_at86rf2xx_get_addr_short(dev);
+ *((uint16_t *)val) = at86rf2xx_get_addr_short(dev);
return sizeof(uint16_t);
case NETOPT_ADDRESS_LONG:
if (max_len < sizeof(uint64_t)) {
return -EOVERFLOW;
}
- *((uint64_t *)val) = ng_at86rf2xx_get_addr_long(dev);
+ *((uint64_t *)val) = at86rf2xx_get_addr_long(dev);
return sizeof(uint64_t);
case NETOPT_ADDR_LEN:
@@ -391,7 +391,7 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
if (max_len < sizeof(uint16_t)) {
return -EOVERFLOW;
}
- if (dev->options & NG_AT86RF2XX_OPT_SRC_ADDR_LONG) {
+ if (dev->options & AT86RF2XX_OPT_SRC_ADDR_LONG) {
*((uint16_t *)val) = 8;
}
else {
@@ -410,12 +410,12 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
if (max_len < sizeof(eui64_t)) {
return -EOVERFLOW;
}
- if (dev->options & NG_AT86RF2XX_OPT_SRC_ADDR_LONG) {
- uint64_t addr = ng_at86rf2xx_get_addr_long(dev);
+ if (dev->options & AT86RF2XX_OPT_SRC_ADDR_LONG) {
+ uint64_t addr = at86rf2xx_get_addr_long(dev);
ieee802154_get_iid(val, (uint8_t *)&addr, 8);
}
else {
- uint16_t addr = ng_at86rf2xx_get_addr_short(dev);
+ uint16_t addr = at86rf2xx_get_addr_short(dev);
ieee802154_get_iid(val, (uint8_t *)&addr, 2);
}
return sizeof(eui64_t);
@@ -432,21 +432,21 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
return -EOVERFLOW;
}
((uint8_t *)val)[1] = 0;
- ((uint8_t *)val)[0] = ng_at86rf2xx_get_chan(dev);
+ ((uint8_t *)val)[0] = at86rf2xx_get_chan(dev);
return sizeof(uint16_t);
case NETOPT_TX_POWER:
if (max_len < sizeof(int16_t)) {
return -EOVERFLOW;
}
- *((uint16_t *)val) = ng_at86rf2xx_get_txpower(dev);
+ *((uint16_t *)val) = at86rf2xx_get_txpower(dev);
return sizeof(uint16_t);
case NETOPT_MAX_PACKET_SIZE:
if (max_len < sizeof(int16_t)) {
return -EOVERFLOW;
}
- *((uint16_t *)val) = NG_AT86RF2XX_MAX_PKT_LENGTH - _MAX_MHR_OVERHEAD;
+ *((uint16_t *)val) = AT86RF2XX_MAX_PKT_LENGTH - _MAX_MHR_OVERHEAD;
return sizeof(uint16_t);
case NETOPT_STATE:
@@ -457,7 +457,7 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
break;
case NETOPT_PRELOADING:
- if (dev->options & NG_AT86RF2XX_OPT_PRELOADING) {
+ if (dev->options & AT86RF2XX_OPT_PRELOADING) {
*((netopt_enable_t *)val) = NETOPT_ENABLE;
}
else {
@@ -466,7 +466,7 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
return sizeof(netopt_enable_t);
case NETOPT_AUTOACK:
- if (dev->options & NG_AT86RF2XX_OPT_AUTOACK) {
+ if (dev->options & AT86RF2XX_OPT_AUTOACK) {
*((netopt_enable_t *)val) = NETOPT_ENABLE;
}
else {
@@ -478,11 +478,11 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
if (max_len < sizeof(uint8_t)) {
return -EOVERFLOW;
}
- *((uint8_t *)val) = ng_at86rf2xx_get_max_retries(dev);
+ *((uint8_t *)val) = at86rf2xx_get_max_retries(dev);
return sizeof(uint8_t);
case NETOPT_PROMISCUOUSMODE:
- if (dev->options & NG_AT86RF2XX_OPT_PROMISCUOUS) {
+ if (dev->options & AT86RF2XX_OPT_PROMISCUOUS) {
*((netopt_enable_t *)val) = NETOPT_ENABLE;
}
else {
@@ -491,7 +491,7 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
return sizeof(netopt_enable_t);
case NETOPT_RAWMODE:
- if (dev->options & NG_AT86RF2XX_OPT_RAWDUMP) {
+ if (dev->options & AT86RF2XX_OPT_RAWDUMP) {
*((netopt_enable_t *)val) = NETOPT_ENABLE;
}
else {
@@ -500,7 +500,7 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
return sizeof(netopt_enable_t);
case NETOPT_IS_CHANNEL_CLR:
- if (ng_at86rf2xx_cca(dev)) {
+ if (at86rf2xx_cca(dev)) {
*((netopt_enable_t *)val) = NETOPT_ENABLE;
}
else {
@@ -510,22 +510,22 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
case NETOPT_RX_START_IRQ:
*((netopt_enable_t *)val) =
- !!(dev->options & NG_AT86RF2XX_OPT_TELL_RX_START);
+ !!(dev->options & AT86RF2XX_OPT_TELL_RX_START);
return sizeof(netopt_enable_t);
case NETOPT_RX_END_IRQ:
*((netopt_enable_t *)val) =
- !!(dev->options & NG_AT86RF2XX_OPT_TELL_RX_END);
+ !!(dev->options & AT86RF2XX_OPT_TELL_RX_END);
return sizeof(netopt_enable_t);
case NETOPT_TX_START_IRQ:
*((netopt_enable_t *)val) =
- !!(dev->options & NG_AT86RF2XX_OPT_TELL_TX_START);
+ !!(dev->options & AT86RF2XX_OPT_TELL_TX_START);
return sizeof(netopt_enable_t);
case NETOPT_TX_END_IRQ:
*((netopt_enable_t *)val) =
- !!(dev->options & NG_AT86RF2XX_OPT_TELL_TX_END);
+ !!(dev->options & AT86RF2XX_OPT_TELL_TX_END);
return sizeof(netopt_enable_t);
default:
@@ -537,7 +537,7 @@ static int _get(ng_netdev_t *device, netopt_t opt, void *val, size_t max_len)
static int _set(ng_netdev_t *device, netopt_t opt, void *val, size_t len)
{
- ng_at86rf2xx_t *dev = (ng_at86rf2xx_t *) device;
+ at86rf2xx_t *dev = (at86rf2xx_t *) device;
if (dev == NULL) {
return -ENODEV;
@@ -548,14 +548,14 @@ static int _set(ng_netdev_t *device, netopt_t opt, void *val, size_t len)
if (len > sizeof(uint16_t)) {
return -EOVERFLOW;
}
- ng_at86rf2xx_set_addr_short(dev, *((uint16_t*)val));
+ at86rf2xx_set_addr_short(dev, *((uint16_t*)val));
return sizeof(uint16_t);
case NETOPT_ADDRESS_LONG:
if (len > sizeof(uint64_t)) {
return -EOVERFLOW;
}
- ng_at86rf2xx_set_addr_long(dev, *((uint64_t*)val));
+ at86rf2xx_set_addr_long(dev, *((uint64_t*)val));
return sizeof(uint64_t);
case NETOPT_SRC_LEN:
@@ -563,12 +563,12 @@ static int _set(ng_netdev_t *device, netopt_t opt, void *val, size_t len)
return -EOVERFLOW;
}
if (*((uint16_t *)val) == 2) {
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_SRC_ADDR_LONG,
- false);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_SRC_ADDR_LONG,
+ false);
}
else if (*((uint16_t *)val) == 8) {
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_SRC_ADDR_LONG,
- true);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_SRC_ADDR_LONG,
+ true);
}
else {
return -ENOTSUP;
@@ -579,7 +579,7 @@ static int _set(ng_netdev_t *device, netopt_t opt, void *val, size_t len)
if (len > sizeof(uint16_t)) {
return -EOVERFLOW;
}
- ng_at86rf2xx_set_pan(dev, *((uint16_t *)val));
+ at86rf2xx_set_pan(dev, *((uint16_t *)val));
return sizeof(uint16_t);
case NETOPT_CHANNEL:
@@ -587,18 +587,18 @@ static int _set(ng_netdev_t *device, netopt_t opt, void *val, size_t len)
return -EINVAL;
}
uint8_t chan = ((uint8_t *)val)[0];
- if (chan < NG_AT86RF2XX_MIN_CHANNEL ||
- chan > NG_AT86RF2XX_MAX_CHANNEL) {
+ if (chan < AT86RF2XX_MIN_CHANNEL ||
+ chan > AT86RF2XX_MAX_CHANNEL) {
return -ENOTSUP;
}
- ng_at86rf2xx_set_chan(dev, chan);
+ at86rf2xx_set_chan(dev, chan);
return sizeof(uint16_t);
case NETOPT_TX_POWER:
if (len > sizeof(int16_t)) {
return -EOVERFLOW;
}
- ng_at86rf2xx_set_txpower(dev, *((int16_t *)val));
+ at86rf2xx_set_txpower(dev, *((int16_t *)val));
return sizeof(uint16_t);
case NETOPT_STATE:
@@ -608,50 +608,50 @@ static int _set(ng_netdev_t *device, netopt_t opt, void *val, size_t len)
return _set_state(dev, *((netopt_state_t *)val));
case NETOPT_AUTOACK:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_AUTOACK,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_AUTOACK,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
case NETOPT_RETRANS:
if (len > sizeof(uint8_t)) {
return -EOVERFLOW;
}
- ng_at86rf2xx_set_max_retries(dev, *((uint8_t *)val));
+ at86rf2xx_set_max_retries(dev, *((uint8_t *)val));
return sizeof(uint8_t);
case NETOPT_PRELOADING:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_PRELOADING,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_PRELOADING,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
case NETOPT_PROMISCUOUSMODE:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_PROMISCUOUS,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_PROMISCUOUS,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
case NETOPT_RAWMODE:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_RAWDUMP,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_RAWDUMP,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
case NETOPT_RX_START_IRQ:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_RX_START,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_START,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
case NETOPT_RX_END_IRQ:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_RX_END,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_END,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
case NETOPT_TX_START_IRQ:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_TX_START,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_TX_START,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
case NETOPT_TX_END_IRQ:
- ng_at86rf2xx_set_option(dev, NG_AT86RF2XX_OPT_TELL_TX_END,
- ((bool *)val)[0]);
+ at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_TX_END,
+ ((bool *)val)[0]);
return sizeof(netopt_enable_t);
default:
@@ -689,38 +689,38 @@ static int _rem_event_cb(ng_netdev_t *dev, ng_netdev_event_cb_t cb)
static void _isr_event(ng_netdev_t *device, uint32_t event_type)
{
- ng_at86rf2xx_t *dev = (ng_at86rf2xx_t *) device;
+ at86rf2xx_t *dev = (at86rf2xx_t *) device;
uint8_t irq_mask;
uint8_t state;
/* read (consume) device status */
- irq_mask = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__IRQ_STATUS);
+ irq_mask = at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_STATUS);
- state = ng_at86rf2xx_get_status(dev);
+ state = at86rf2xx_get_status(dev);
- if (irq_mask & NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START) {
+ if (irq_mask & AT86RF2XX_IRQ_STATUS_MASK__RX_START) {
dev->event_cb(NETDEV_EVENT_RX_STARTED, NULL);
- DEBUG("[ng_at86rf2xx] EVT - RX_START\n");
+ DEBUG("[at86rf2xx] EVT - RX_START\n");
}
- if (irq_mask & NG_AT86RF2XX_IRQ_STATUS_MASK__TRX_END) {
- if (state == NG_AT86RF2XX_STATE_RX_AACK_ON || state == NG_AT86RF2XX_STATE_BUSY_RX_AACK) {
- DEBUG("[ng_at86rf2xx] EVT - RX_END\n");
- if (!(dev->options & NG_AT86RF2XX_OPT_TELL_RX_END)) {
+ if (irq_mask & AT86RF2XX_IRQ_STATUS_MASK__TRX_END) {
+ if (state == AT86RF2XX_STATE_RX_AACK_ON || state == AT86RF2XX_STATE_BUSY_RX_AACK) {
+ DEBUG("[at86rf2xx] EVT - RX_END\n");
+ if (!(dev->options & AT86RF2XX_OPT_TELL_RX_END)) {
return;
}
_receive_data(dev);
}
- else if (state == NG_AT86RF2XX_STATE_TX_ARET_ON) {
- ng_at86rf2xx_set_state(dev, dev->idle_state);
- if (dev->event_cb && (dev->options & NG_AT86RF2XX_OPT_TELL_TX_END)) {
+ else if (state == AT86RF2XX_STATE_TX_ARET_ON) {
+ at86rf2xx_set_state(dev, dev->idle_state);
+ if (dev->event_cb && (dev->options & AT86RF2XX_OPT_TELL_TX_END)) {
dev->event_cb(NETDEV_EVENT_TX_COMPLETE, NULL);
}
- DEBUG("[ng_at86rf2xx] EVT - TX_END\n");
+ DEBUG("[at86rf2xx] EVT - TX_END\n");
}
}
}
-const ng_netdev_driver_t ng_at86rf2xx_driver = {
+const ng_netdev_driver_t at86rf2xx_driver = {
.send_data = _send,
.add_event_callback = _add_event_cb,
.rem_event_callback = _rem_event_cb,
diff --git a/drivers/ng_at86rf2xx/include/ng_at86rf2xx_internal.h b/drivers/at86rf2xx/include/at86rf2xx_internal.h
similarity index 71%
rename from drivers/ng_at86rf2xx/include/ng_at86rf2xx_internal.h
rename to drivers/at86rf2xx/include/at86rf2xx_internal.h
index c5e8ca424cfb2ffdcf52f1c5323db3382d026965..b32b2a4066225c18e7939ccb13fd85c7cefcdded 100644
--- a/drivers/ng_at86rf2xx/include/ng_at86rf2xx_internal.h
+++ b/drivers/at86rf2xx/include/at86rf2xx_internal.h
@@ -8,7 +8,7 @@
*/
/**
- * @ingroup drivers_ng_at86rf2xx
+ * @ingroup drivers_at86rf2xx
* @{
*
* @file
@@ -19,12 +19,12 @@
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
-#ifndef NG_AT86RF2XX_INTERNAL_H_
-#define NG_AT86RF2XX_INTERNAL_H_
+#ifndef AT86RF2XX_INTERNAL_H_
+#define AT86RF2XX_INTERNAL_H_
#include <stdint.h>
-#include "ng_at86rf2xx.h"
+#include "at86rf2xx.h"
#ifdef __cplusplus
@@ -39,7 +39,7 @@ extern "C" {
*
* @return the value of the specified register
*/
-uint8_t ng_at86rf2xx_reg_read(const ng_at86rf2xx_t *dev, const uint8_t addr);
+uint8_t at86rf2xx_reg_read(const at86rf2xx_t *dev, const uint8_t addr);
/**
* @brief Write to a register at address `addr` from device `dev`.
@@ -48,8 +48,8 @@ uint8_t ng_at86rf2xx_reg_read(const ng_at86rf2xx_t *dev, const uint8_t addr);
* @param[in] addr address of the register to write
* @param[in] value value to write to the given register
*/
-void ng_at86rf2xx_reg_write(const ng_at86rf2xx_t *dev, const uint8_t addr,
- const uint8_t value);
+void at86rf2xx_reg_write(const at86rf2xx_t *dev, const uint8_t addr,
+ const uint8_t value);
/**
* @brief Read a chunk of data from the SRAM of the given device
@@ -59,10 +59,10 @@ void ng_at86rf2xx_reg_write(const ng_at86rf2xx_t *dev, const uint8_t addr,
* @param[out] data buffer to read data into
* @param[in] len number of bytes to read from SRAM
*/
-void ng_at86rf2xx_sram_read(const ng_at86rf2xx_t *dev,
- const uint8_t offset,
- uint8_t *data,
- const size_t len);
+void at86rf2xx_sram_read(const at86rf2xx_t *dev,
+ const uint8_t offset,
+ uint8_t *data,
+ const size_t len);
/**
* @brief Write a chunk of data into the SRAM of the given device
@@ -72,10 +72,10 @@ void ng_at86rf2xx_sram_read(const ng_at86rf2xx_t *dev,
* @param[in] data data to copy into SRAM
* @param[in] len number of bytes to write to SRAM
*/
-void ng_at86rf2xx_sram_write(const ng_at86rf2xx_t *dev,
- const uint8_t offset,
- const uint8_t *data,
- const size_t len);
+void at86rf2xx_sram_write(const at86rf2xx_t *dev,
+ const uint8_t offset,
+ const uint8_t *data,
+ const size_t len);
/**
* @brief Read the internal frame buffer of the given device
@@ -87,8 +87,8 @@ void ng_at86rf2xx_sram_write(const ng_at86rf2xx_t *dev,
* @param[out] data buffer to copy the data to
* @param[in] len number of bytes to read from the frame buffer
*/
-void ng_at86rf2xx_fb_read(const ng_at86rf2xx_t *dev,
- uint8_t *data, const size_t len);
+void at86rf2xx_fb_read(const at86rf2xx_t *dev,
+ uint8_t *data, const size_t len);
/**
* @brief Convenience function for reading the status of the given device
@@ -97,11 +97,11 @@ void ng_at86rf2xx_fb_read(const ng_at86rf2xx_t *dev,
*
* @return internal status of the given device
*/
-uint8_t ng_at86rf2xx_get_status(const ng_at86rf2xx_t *dev);
+uint8_t at86rf2xx_get_status(const at86rf2xx_t *dev);
#ifdef __cplusplus
}
#endif
-#endif /* NG_AT86RF2XX_INTERNAL_H_ */
+#endif /* AT86RF2XX_INTERNAL_H_ */
/** @} */
diff --git a/drivers/ng_at86rf2xx/include/ng_at86rf2xx_netdev.h b/drivers/at86rf2xx/include/at86rf2xx_netdev.h
similarity index 74%
rename from drivers/ng_at86rf2xx/include/ng_at86rf2xx_netdev.h
rename to drivers/at86rf2xx/include/at86rf2xx_netdev.h
index 2085fb3e6e3c24850fbb9e8f8d642d17582a0a7c..304046a6866980ec59a32dcded642023da35d9ee 100644
--- a/drivers/ng_at86rf2xx/include/ng_at86rf2xx_netdev.h
+++ b/drivers/at86rf2xx/include/at86rf2xx_netdev.h
@@ -7,7 +7,7 @@
*/
/**
- * @ingroup drivers_ng_at86rf2xx
+ * @ingroup drivers_at86rf2xx
* @{
*
* @file
@@ -16,8 +16,8 @@
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
-#ifndef NG_AT86RF2XX_NETDEV_H_
-#define NG_AT86RF2XX_NETDEV_H_
+#ifndef AT86RF2XX_NETDEV_H_
+#define AT86RF2XX_NETDEV_H_
#include "net/ng_netdev.h"
@@ -28,11 +28,11 @@ extern "C" {
/**
* @brief Reference to the netdev device driver struct
*/
-extern const ng_netdev_driver_t ng_at86rf2xx_driver;
+extern const ng_netdev_driver_t at86rf2xx_driver;
#ifdef __cplusplus
}
#endif
-#endif /* NG_AT86RF2XX_NETDEV_H_ */
+#endif /* AT86RF2XX_NETDEV_H_ */
/** @} */
diff --git a/drivers/at86rf2xx/include/at86rf2xx_registers.h b/drivers/at86rf2xx/include/at86rf2xx_registers.h
new file mode 100644
index 0000000000000000000000000000000000000000..e55d9290150190bb8706267c69dc088a5e93f907
--- /dev/null
+++ b/drivers/at86rf2xx/include/at86rf2xx_registers.h
@@ -0,0 +1,341 @@
+/*
+ * Copyright (C) 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr>
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup drivers_at86rf2xx
+ * @{
+ *
+ * @file
+ * @brief Register and command definitions for AT86RF2xx devices
+ *
+ * @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
+ * @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author Kaspar Schleiser <kaspar@schleiser.de>
+ */
+
+#ifndef AT86RF2XX_REGISTERS_H_
+#define AT86RF2XX_REGISTERS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Constant part numbers of the AT86RF2xx device family
+ * @{
+ */
+#define NG_AT86RF212B_PARTNUM (0x07)
+#define NG_AT86RF231_PARTNUM (0x03)
+#define NG_AT86RF232_PARTNUM (0x0a)
+#define NG_AT86RF233_PARTNUM (0x0b)
+/** @} */
+
+/**
+ * @brief Assign the part number for the device we are building the driver for
+ * @{
+ */
+#ifdef MODULE_NG_AT86RF212B
+#define AT86RF2XX_PARTNUM NG_AT86RF212B_PARTNUM
+#elif MODULE_NG_AT86RF232
+#define AT86RF2XX_PARTNUM NG_AT86RF232_PARTNUM
+#elif MODULE_NG_AT86RF233
+#define AT86RF2XX_PARTNUM NG_AT86RF233_PARTNUM
+#else /* MODULE_NG_AT86RF231 as default device */
+#define AT86RF2XX_PARTNUM NG_AT86RF231_PARTNUM
+#endif
+/** @} */
+
+/**
+ * @brief SPI access specifiers
+ * @{
+ */
+#define AT86RF2XX_ACCESS_REG (0x80)
+#define AT86RF2XX_ACCESS_FB (0x20)
+#define AT86RF2XX_ACCESS_SRAM (0x00)
+#define AT86RF2XX_ACCESS_READ (0x00)
+#define AT86RF2XX_ACCESS_WRITE (0x40)
+/** @} */
+
+/**
+ * @brief Register addresses
+ * @{
+ */
+#define AT86RF2XX_REG__TRX_STATUS (0x01)
+#define AT86RF2XX_REG__TRX_STATE (0x02)
+#define AT86RF2XX_REG__TRX_CTRL_0 (0x03)
+#define AT86RF2XX_REG__TRX_CTRL_1 (0x04)
+#define AT86RF2XX_REG__PHY_TX_PWR (0x05)
+#define AT86RF2XX_REG__PHY_RSSI (0x06)
+#define AT86RF2XX_REG__PHY_ED_LEVEL (0x07)
+#define AT86RF2XX_REG__PHY_CC_CCA (0x08)
+#define AT86RF2XX_REG__CCA_THRES (0x09)
+#define AT86RF2XX_REG__RX_CTRL (0x0A)
+#define AT86RF2XX_REG__SFD_VALUE (0x0B)
+#define AT86RF2XX_REG__TRX_CTRL_2 (0x0C)
+#define AT86RF2XX_REG__ANT_DIV (0x0D)
+#define AT86RF2XX_REG__IRQ_MASK (0x0E)
+#define AT86RF2XX_REG__IRQ_STATUS (0x0F)
+#define AT86RF2XX_REG__VREG_CTRL (0x10)
+#define AT86RF2XX_REG__BATMON (0x11)
+#define AT86RF2XX_REG__XOSC_CTRL (0x12)
+#define AT86RF2XX_REG__CC_CTRL_1 (0x14)
+#define AT86RF2XX_REG__RX_SYN (0x15)
+#ifdef MODULE_NG_AT86RF212B
+#define AT86RF2XX_REG__RF_CTRL_0 (0x16)
+#endif
+#define AT86RF2XX_REG__XAH_CTRL_1 (0x17)
+#define AT86RF2XX_REG__FTN_CTRL (0x18)
+#define AT86RF2XX_REG__PLL_CF (0x1A)
+#define AT86RF2XX_REG__PLL_DCU (0x1B)
+#define AT86RF2XX_REG__PART_NUM (0x1C)
+#define AT86RF2XX_REG__VERSION_NUM (0x1D)
+#define AT86RF2XX_REG__MAN_ID_0 (0x1E)
+#define AT86RF2XX_REG__MAN_ID_1 (0x1F)
+#define AT86RF2XX_REG__SHORT_ADDR_0 (0x20)
+#define AT86RF2XX_REG__SHORT_ADDR_1 (0x21)
+#define AT86RF2XX_REG__PAN_ID_0 (0x22)
+#define AT86RF2XX_REG__PAN_ID_1 (0x23)
+#define AT86RF2XX_REG__IEEE_ADDR_0 (0x24)
+#define AT86RF2XX_REG__IEEE_ADDR_1 (0x25)
+#define AT86RF2XX_REG__IEEE_ADDR_2 (0x26)
+#define AT86RF2XX_REG__IEEE_ADDR_3 (0x27)
+#define AT86RF2XX_REG__IEEE_ADDR_4 (0x28)
+#define AT86RF2XX_REG__IEEE_ADDR_5 (0x29)
+#define AT86RF2XX_REG__IEEE_ADDR_6 (0x2A)
+#define AT86RF2XX_REG__IEEE_ADDR_7 (0x2B)
+#define AT86RF2XX_REG__XAH_CTRL_0 (0x2C)
+#define AT86RF2XX_REG__CSMA_SEED_0 (0x2D)
+#define AT86RF2XX_REG__CSMA_SEED_1 (0x2E)
+#define AT86RF2XX_REG__CSMA_BE (0x2F)
+#define AT86RF2XX_REG__TST_CTRL_DIGI (0x36)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the TRX_CTRL_0 register
+ * @{
+ */
+#define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO (0xC0)
+#define AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO_CLKM (0x30)
+#define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL (0x08)
+#define AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL (0x07)
+
+#define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO (0x00)
+#define AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM (0x10)
+#define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL (0x08)
+#define AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_CTRL (0x01)
+
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF (0x00)
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__1MHz (0x01)
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__2MHz (0x02)
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__4MHz (0x03)
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__8MHz (0x04)
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__16MHz (0x05)
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__250kHz (0x06)
+#define AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__62_5kHz (0x07)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the TRX_CTRL_1 register
+ * @{
+ */
+#define AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN (0x80)
+#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN (0x40)
+#define AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON (0x20)
+#define AT86RF2XX_TRX_CTRL_1_MASK__RX_BL_CTRL (0x10)
+#define AT86RF2XX_TRX_CTRL_1_MASK__SPI_CMD_MODE (0x0C)
+#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE (0x02)
+#define AT86RF2XX_TRX_CTRL_1_MASK__IRQ_POLARITY (0x01)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the TRX_CTRL_2 register
+ * @{
+ */
+#define AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE (0x80)
+#define AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE (0x3F)
+#define AT86RF2XX_TRX_CTRL_2_MASK__TRX_OFF_AVDD_EN (0x40)
+#define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN (0x20)
+#define AT86RF2XX_TRX_CTRL_2_MASK__ALT_SPECTRUM (0x10)
+#define AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK (0x08)
+#define AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE (0x04)
+#define AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE (0x03)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the IRQ_STATUS register
+ * @{
+ */
+#define AT86RF2XX_IRQ_STATUS_MASK__BAT_LOW (0x80)
+#define AT86RF2XX_IRQ_STATUS_MASK__TRX_UR (0x40)
+#define AT86RF2XX_IRQ_STATUS_MASK__AMI (0x20)
+#define AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE (0x10)
+#define AT86RF2XX_IRQ_STATUS_MASK__TRX_END (0x08)
+#define AT86RF2XX_IRQ_STATUS_MASK__RX_START (0x04)
+#define AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK (0x02)
+#define AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK (0x01)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the TRX_STATUS register
+ * @{
+ */
+#define AT86RF2XX_TRX_STATUS_MASK__CCA_DONE (0x80)
+#define AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS (0x40)
+#define AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS (0x1F)
+
+#define AT86RF2XX_TRX_STATUS__P_ON (0x00)
+#define AT86RF2XX_TRX_STATUS__BUSY_RX (0x01)
+#define AT86RF2XX_TRX_STATUS__BUSY_TX (0x02)
+#define AT86RF2XX_TRX_STATUS__RX_ON (0x06)
+#define AT86RF2XX_TRX_STATUS__TRX_OFF (0x08)
+#define AT86RF2XX_TRX_STATUS__PLL_ON (0x09)
+#define AT86RF2XX_TRX_STATUS__SLEEP (0x0F)
+#define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK (0x11)
+#define AT86RF2XX_TRX_STATUS__BUSY_TX_ARET (0x12)
+#define AT86RF2XX_TRX_STATUS__RX_AACK_ON (0x16)
+#define AT86RF2XX_TRX_STATUS__TX_ARET_ON (0x19)
+#define AT86RF2XX_TRX_STATUS__RX_ON_NOCLK (0x1C)
+#define AT86RF2XX_TRX_STATUS__RX_AACK_ON_NOCLK (0x1D)
+#define AT86RF2XX_TRX_STATUS__BUSY_RX_AACK_NOCLK (0x1E)
+#define AT86RF2XX_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS (0x1F)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the TRX_STATE register
+ * @{
+ */
+#define AT86RF2XX_TRX_STATE_MASK__TRAC (0xe0)
+
+#define AT86RF2XX_TRX_STATE__NOP (0x00)
+#define AT86RF2XX_TRX_STATE__TX_START (0x02)
+#define AT86RF2XX_TRX_STATE__FORCE_TRX_OFF (0x03)
+#define AT86RF2XX_TRX_STATE__FORCE_PLL_ON (0x04)
+#define AT86RF2XX_TRX_STATE__RX_ON (0x06)
+#define AT86RF2XX_TRX_STATE__TRX_OFF (0x08)
+#define AT86RF2XX_TRX_STATE__PLL_ON (0x09)
+#define AT86RF2XX_TRX_STATE__RX_AACK_ON (0x16)
+#define AT86RF2XX_TRX_STATE__TX_ARET_ON (0x19)
+#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS (0x00)
+#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_DATA_PENDING (0x20)
+#define AT86RF2XX_TRX_STATE__TRAC_SUCCESS_WAIT_FOR_ACK (0x40)
+#define AT86RF2XX_TRX_STATE__TRAC_CHANNEL_ACCESS_FAILURE (0x60)
+#define AT86RF2XX_TRX_STATE__TRAC_NO_ACK (0xa0)
+#define AT86RF2XX_TRX_STATE__TRAC_INVALID (0xe0)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the PHY_CCA register
+ * @{
+ */
+#define AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST (0x80)
+#define AT86RF2XX_PHY_CC_CCA_MASK__CCA_MODE (0x60)
+#define AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL (0x1F)
+
+#define AT86RF2XX_PHY_CC_CCA_DEFAULT__CCA_MODE (0x20)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the PHY_TX_PWR register
+ * @{
+ */
+#ifdef MODULE_NG_AT86RF212B
+#define AT86RF2XX_PHY_TX_PWR_MASK__PA_BOOST (0x80)
+#define AT86RF2XX_PHY_TX_PWR_MASK__GC_PA (0x60)
+#define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x1F)
+#elif MODULE_NG_AT86RF231
+#define AT86RF2XX_PHY_TX_PWR_MASK__PA_BUF_LT (0xC0)
+#define AT86RF2XX_PHY_TX_PWR_MASK__PA_LT (0x30)
+#define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
+#else
+#define AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
+#endif
+#define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT (0xC0)
+#define AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT (0x00)
+#define AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR (0x00)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the PHY_RSSI register
+ * @{
+ */
+#define AT86RF2XX_PHY_RSSI_MASK__RX_CRC_VALID (0x80)
+#define AT86RF2XX_PHY_RSSI_MASK__RND_VALUE (0x60)
+#define AT86RF2XX_PHY_RSSI_MASK__RSSI (0x1F)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the XOSC_CTRL register
+ * @{
+ */
+#define AT86RF2XX_XOSC_CTRL__XTAL_MODE_CRYSTAL (0xF0)
+#define AT86RF2XX_XOSC_CTRL__XTAL_MODE_EXTERNAL (0xF0)
+/** @} */
+
+/**
+ * @brief Timing values
+ * @{
+ */
+#define AT86RF2XX_TIMING__VCC_TO_P_ON (330)
+#define AT86RF2XX_TIMING__SLEEP_TO_TRX_OFF (380)
+#define AT86RF2XX_TIMING__TRX_OFF_TO_PLL_ON (110)
+#define AT86RF2XX_TIMING__TRX_OFF_TO_RX_ON (110)
+#define AT86RF2XX_TIMING__PLL_ON_TO_BUSY_TX (16)
+#define AT86RF2XX_TIMING__RESET (100)
+#define AT86RF2XX_TIMING__RESET_TO_TRX_OFF (37)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the XAH_CTRL_0 register
+ * @{
+ */
+#define AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES (0xF0)
+#define AT86RF2XX_XAH_CTRL_0__MAX_CSMA_RETRIES (0x0E)
+#define AT86RF2XX_XAH_CTRL_0__SLOTTED_OPERATION (0x01)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the XAH_CTRL_1 register
+ * @{
+ */
+#define AT86RF2XX_XAH_CTRL_1__AACK_FLTR_RES_FT (0x20)
+#define AT86RF2XX_XAH_CTRL_1__AACK_UPLD_RES_FT (0x10)
+#define AT86RF2XX_XAH_CTRL_1__AACK_ACK_TIME (0x04)
+#define AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE (0x02)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the CSMA_SEED_1 register
+ * @{
+ */
+#define AT86RF2XX_CSMA_SEED_1__AACK_SET_PD (0x20)
+#define AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK (0x10)
+#define AT86RF2XX_CSMA_SEED_1__AACK_I_AM_COORD (0x08)
+/** @} */
+
+/**
+ * @brief Bitfield definitions for the RF_CTRL_0 register
+ * @{
+ */
+#ifdef MODULE_NG_AT86RF212B
+#define AT86RF2XX_RF_CTRL_0_MASK__PA_LT (0xC0)
+#define AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS (0x03)
+
+#define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__0DB (0x01)
+#define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__1DB (0x02)
+#define AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB (0x03)
+#endif
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AT86RF2XX_REGISTERS_H_ */
+/** @} */
diff --git a/drivers/include/ng_at86rf2xx.h b/drivers/include/at86rf2xx.h
similarity index 72%
rename from drivers/include/ng_at86rf2xx.h
rename to drivers/include/at86rf2xx.h
index 66e6230f206a11d7567686e693a030869a78beb8..56db698b97598aae7491190a7384fb51d8dbf982 100644
--- a/drivers/include/ng_at86rf2xx.h
+++ b/drivers/include/at86rf2xx.h
@@ -7,7 +7,7 @@
*/
/**
- * @defgroup drivers_ng_at86rf2xx AT86RF2xx based drivers
+ * @defgroup drivers_at86rf2xx AT86RF2xx based drivers
* @ingroup drivers
*
* This module contains drivers for radio devices in Atmel's AT86RF2xx series.
@@ -23,8 +23,8 @@
* @author Kaspar Schleiser <kaspar@schleiser.de>
*/
-#ifndef NG_AT86RF2XX_H_
-#define NG_AT86RF2XX_H_
+#ifndef AT86RF2XX_H_
+#define AT86RF2XX_H_
#include <stdint.h>
@@ -32,7 +32,7 @@
#include "periph/spi.h"
#include "periph/gpio.h"
#include "net/ng_netdev.h"
-#include "ng_at86rf2xx.h"
+#include "at86rf2xx.h"
#ifdef __cplusplus
extern "C" {
@@ -41,14 +41,14 @@ extern "C" {
/**
* @brief Maximum possible packet size in byte
*/
-#define NG_AT86RF2XX_MAX_PKT_LENGTH (127)
+#define AT86RF2XX_MAX_PKT_LENGTH (127)
/**
* @brief Default addresses used if the CPUID module is not present
* @{
*/
-#define NG_AT86RF2XX_DEFAULT_ADDR_SHORT (0x0230)
-#define NG_AT86RF2XX_DEFAULT_ADDR_LONG (0x1222334455667788)
+#define AT86RF2XX_DEFAULT_ADDR_SHORT (0x0230)
+#define AT86RF2XX_DEFAULT_ADDR_LONG (0x1222334455667788)
/** @} */
/**
@@ -57,13 +57,13 @@ extern "C" {
*/
#ifdef MODULE_NG_AT86RF212B
/* the AT86RF212B has a sub-1GHz radio */
-#define NG_AT86RF2XX_MIN_CHANNEL (0)
-#define NG_AT86RF2XX_MAX_CHANNEL (10)
-#define NG_AT86RF2XX_DEFAULT_CHANNEL (5)
+#define AT86RF2XX_MIN_CHANNEL (0)
+#define AT86RF2XX_MAX_CHANNEL (10)
+#define AT86RF2XX_DEFAULT_CHANNEL (5)
#else
-#define NG_AT86RF2XX_MIN_CHANNEL (11U)
-#define NG_AT86RF2XX_MAX_CHANNEL (26U)
-#define NG_AT86RF2XX_DEFAULT_CHANNEL (26U)
+#define AT86RF2XX_MIN_CHANNEL (11U)
+#define AT86RF2XX_MAX_CHANNEL (26U)
+#define AT86RF2XX_DEFAULT_CHANNEL (26U)
#endif
/** @} */
@@ -72,49 +72,49 @@ extern "C" {
*
* @todo Read some global network stack specific configuration value
*/
-#define NG_AT86RF2XX_DEFAULT_PANID (0x0023)
+#define AT86RF2XX_DEFAULT_PANID (0x0023)
/**
* @brief Default TX power (0dBm)
*/
-#define NG_AT86RF2XX_DEFAULT_TXPOWER (0U)
+#define AT86RF2XX_DEFAULT_TXPOWER (0U)
/**
* @brief Flags for device internal states (see datasheet)
* @{
*/
-#define NG_AT86RF2XX_STATE_TRX_OFF (0x08) /**< idle */
-#define NG_AT86RF2XX_STATE_PLL_ON (0x09) /**< ready to transmit */
-#define NG_AT86RF2XX_STATE_SLEEP (0x0f) /**< sleep mode */
-#define NG_AT86RF2XX_STATE_BUSY_RX_AACK (0x11) /**< busy receiving data */
-#define NG_AT86RF2XX_STATE_BUSY_TX_ARET (0x12) /**< busy transmitting data */
-#define NG_AT86RF2XX_STATE_RX_AACK_ON (0x16) /**< wait for incoming data */
-#define NG_AT86RF2XX_STATE_TX_ARET_ON (0x19) /**< ready for sending data */
-#define NG_AT86RF2XX_STATE_IN_PROGRESS (0x1f) /**< ongoing state conversion */
+#define AT86RF2XX_STATE_TRX_OFF (0x08) /**< idle */
+#define AT86RF2XX_STATE_PLL_ON (0x09) /**< ready to transmit */
+#define AT86RF2XX_STATE_SLEEP (0x0f) /**< sleep mode */
+#define AT86RF2XX_STATE_BUSY_RX_AACK (0x11) /**< busy receiving data */
+#define AT86RF2XX_STATE_BUSY_TX_ARET (0x12) /**< busy transmitting data */
+#define AT86RF2XX_STATE_RX_AACK_ON (0x16) /**< wait for incoming data */
+#define AT86RF2XX_STATE_TX_ARET_ON (0x19) /**< ready for sending data */
+#define AT86RF2XX_STATE_IN_PROGRESS (0x1f) /**< ongoing state conversion */
/** @} */
/**
* @brief Internal device option flags
* @{
*/
-#define NG_AT86RF2XX_OPT_AUTOACK (0x0001) /**< auto ACKs active */
-#define NG_AT86RF2XX_OPT_CSMA (0x0002) /**< CSMA active */
-#define NG_AT86RF2XX_OPT_PROMISCUOUS (0x0004) /**< promiscuous mode
+#define AT86RF2XX_OPT_AUTOACK (0x0001) /**< auto ACKs active */
+#define AT86RF2XX_OPT_CSMA (0x0002) /**< CSMA active */
+#define AT86RF2XX_OPT_PROMISCUOUS (0x0004) /**< promiscuous mode
* active */
-#define NG_AT86RF2XX_OPT_PRELOADING (0x0008) /**< preloading enabled */
-#define NG_AT86RF2XX_OPT_TELL_TX_START (0x0010) /**< notify MAC layer on TX
+#define AT86RF2XX_OPT_PRELOADING (0x0008) /**< preloading enabled */
+#define AT86RF2XX_OPT_TELL_TX_START (0x0010) /**< notify MAC layer on TX
* start */
-#define NG_AT86RF2XX_OPT_TELL_TX_END (0x0020) /**< notify MAC layer on TX
+#define AT86RF2XX_OPT_TELL_TX_END (0x0020) /**< notify MAC layer on TX
* finished */
-#define NG_AT86RF2XX_OPT_TELL_RX_START (0x0040) /**< notify MAC layer on RX
+#define AT86RF2XX_OPT_TELL_RX_START (0x0040) /**< notify MAC layer on RX
* start */
-#define NG_AT86RF2XX_OPT_TELL_RX_END (0x0080) /**< notify MAC layer on RX
+#define AT86RF2XX_OPT_TELL_RX_END (0x0080) /**< notify MAC layer on RX
* finished */
-#define NG_AT86RF2XX_OPT_RAWDUMP (0x0100) /**< pass RAW frame data to
+#define AT86RF2XX_OPT_RAWDUMP (0x0100) /**< pass RAW frame data to
* upper layer */
-#define NG_AT86RF2XX_OPT_SRC_ADDR_LONG (0x0200) /**< send data using long
+#define AT86RF2XX_OPT_SRC_ADDR_LONG (0x0200) /**< send data using long
* source address */
-#define NG_AT86RF2XX_OPT_USE_SRC_PAN (0x0400) /**< do not compress source
+#define AT86RF2XX_OPT_USE_SRC_PAN (0x0400) /**< do not compress source
* PAN ID */
/** @} */
@@ -123,9 +123,9 @@ extern "C" {
* @{
*/
typedef enum {
- NG_AT86RF2XX_FREQ_915MHZ, /**< frequency 915MHz enabled */
- NG_AT86RF2XX_FREQ_868MHZ, /**< frequency 868MHz enabled */
-} ng_at86rf2xx_freq_t;
+ AT86RF2XX_FREQ_915MHZ, /**< frequency 915MHz enabled */
+ AT86RF2XX_FREQ_868MHZ, /**< frequency 868MHz enabled */
+} at86rf2xx_freq_t;
/** @} */
/**
@@ -149,13 +149,13 @@ typedef struct {
uint16_t pan; /**< currently used PAN ID */
uint8_t chan; /**< currently used channel */
#ifdef MODULE_NG_AT86RF212B
- ng_at86rf2xx_freq_t freq; /**< currently used frequency */
+ at86rf2xx_freq_t freq; /**< currently used frequency */
#endif
uint8_t addr_short[2]; /**< the radio's short address */
uint8_t addr_long[8]; /**< the radio's long address */
uint16_t options; /**< state of used options */
uint8_t idle_state; /**< state to return to after sending */
-} ng_at86rf2xx_t;
+} at86rf2xx_t;
/**
* @brief struct holding all params needed for device initialization
@@ -183,16 +183,16 @@ typedef struct at86rf2xx_params {
* @return 0 on success
* @return <0 on error
*/
-int ng_at86rf2xx_init(ng_at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed,
- gpio_t cs_pin, gpio_t int_pin,
- gpio_t sleep_pin, gpio_t reset_pin);
+int at86rf2xx_init(at86rf2xx_t *dev, spi_t spi, spi_speed_t spi_speed,
+ gpio_t cs_pin, gpio_t int_pin,
+ gpio_t sleep_pin, gpio_t reset_pin);
/**
* @brief Trigger a hardware reset and configure radio with default values
*
* @param[in] dev device to reset
*/
-void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev);
+void at86rf2xx_reset(at86rf2xx_t *dev);
/**
* @brief Trigger a clear channel assessment
@@ -202,7 +202,7 @@ void ng_at86rf2xx_reset(ng_at86rf2xx_t *dev);
* @return true if channel is clear
* @return false if channel is busy
*/
-bool ng_at86rf2xx_cca(ng_at86rf2xx_t *dev);
+bool at86rf2xx_cca(at86rf2xx_t *dev);
/**
* @brief Get the short address of the given device
@@ -211,7 +211,7 @@ bool ng_at86rf2xx_cca(ng_at86rf2xx_t *dev);
*
* @return the currently set (2-byte) short address
*/
-uint16_t ng_at86rf2xx_get_addr_short(ng_at86rf2xx_t *dev);
+uint16_t at86rf2xx_get_addr_short(at86rf2xx_t *dev);
/**
* @brief Set the short address of the given device
@@ -219,7 +219,7 @@ uint16_t ng_at86rf2xx_get_addr_short(ng_at86rf2xx_t *dev);
* @param[in] dev device to write to
* @param[in] addr (2-byte) short address to set
*/
-void ng_at86rf2xx_set_addr_short(ng_at86rf2xx_t *dev, uint16_t addr);
+void at86rf2xx_set_addr_short(at86rf2xx_t *dev, uint16_t addr);
/**
* @brief Get the configured long address of the given device
@@ -228,7 +228,7 @@ void ng_at86rf2xx_set_addr_short(ng_at86rf2xx_t *dev, uint16_t addr);
*
* @return the currently set (8-byte) long address
*/
-uint64_t ng_at86rf2xx_get_addr_long(ng_at86rf2xx_t *dev);
+uint64_t at86rf2xx_get_addr_long(at86rf2xx_t *dev);
/**
* @brief Set the long address of the given device
@@ -236,7 +236,7 @@ uint64_t ng_at86rf2xx_get_addr_long(ng_at86rf2xx_t *dev);
* @param[in] dev device to write to
* @param[in] addr (8-byte) long address to set
*/
-void ng_at86rf2xx_set_addr_long(ng_at86rf2xx_t *dev, uint64_t addr);
+void at86rf2xx_set_addr_long(at86rf2xx_t *dev, uint64_t addr);
/**
* @brief Get the configured channel of the given device
@@ -245,7 +245,7 @@ void ng_at86rf2xx_set_addr_long(ng_at86rf2xx_t *dev, uint64_t addr);
*
* @return the currently set channel
*/
-uint8_t ng_at86rf2xx_get_chan(ng_at86rf2xx_t *dev);
+uint8_t at86rf2xx_get_chan(at86rf2xx_t *dev);
/**
* @brief Set the channel of the given device
@@ -253,7 +253,7 @@ uint8_t ng_at86rf2xx_get_chan(ng_at86rf2xx_t *dev);
* @param[in] dev device to write to
* @param[in] chan channel to set
*/
-void ng_at86rf2xx_set_chan(ng_at86rf2xx_t *dev, uint8_t chan);
+void at86rf2xx_set_chan(at86rf2xx_t *dev, uint8_t chan);
#ifdef MODULE_NG_AT86RF212B
/**
@@ -263,7 +263,7 @@ void ng_at86rf2xx_set_chan(ng_at86rf2xx_t *dev, uint8_t chan);
*
* @return the currently set frequency
*/
-ng_at86rf2xx_freq_t ng_at86rf2xx_get_freq(ng_at86rf2xx_t *dev);
+at86rf2xx_freq_t at86rf2xx_get_freq(at86rf2xx_t *dev);
/**
* @brief Set the frequency of the given device
@@ -271,7 +271,7 @@ ng_at86rf2xx_freq_t ng_at86rf2xx_get_freq(ng_at86rf2xx_t *dev);
* @param[in] dev device to write to
* @param[in] chan frequency to set
*/
-void ng_at86rf2xx_set_freq(ng_at86rf2xx_t *dev, ng_at86rf2xx_freq_t freq);
+void at86rf2xx_set_freq(at86rf2xx_t *dev, at86rf2xx_freq_t freq);
#endif
/**
@@ -281,7 +281,7 @@ void ng_at86rf2xx_set_freq(ng_at86rf2xx_t *dev, ng_at86rf2xx_freq_t freq);
*
* @return the currently set PAN ID
*/
-uint16_t ng_at86rf2xx_get_pan(ng_at86rf2xx_t *dev);
+uint16_t at86rf2xx_get_pan(at86rf2xx_t *dev);
/**
* @brief Set the PAN ID of the given device
@@ -289,7 +289,7 @@ uint16_t ng_at86rf2xx_get_pan(ng_at86rf2xx_t *dev);
* @param[in] dev device to write to
* @param[in] pan PAN ID to set
*/
-void ng_at86rf2xx_set_pan(ng_at86rf2xx_t *dev, uint16_t pan);
+void at86rf2xx_set_pan(at86rf2xx_t *dev, uint16_t pan);
/**
* @brief Get the configured transmission power of the given device [in dBm]
@@ -298,7 +298,7 @@ void ng_at86rf2xx_set_pan(ng_at86rf2xx_t *dev, uint16_t pan);
*
* @return configured transmission power in dBm
*/
-int16_t ng_at86rf2xx_get_txpower(ng_at86rf2xx_t *dev);
+int16_t at86rf2xx_get_txpower(at86rf2xx_t *dev);
/**
* @brief Set the transmission power of the given device [in dBm]
@@ -311,7 +311,7 @@ int16_t ng_at86rf2xx_get_txpower(ng_at86rf2xx_t *dev);
* @param[in] dev device to write to
* @param[in] txpower transmission power in dBm
*/
-void ng_at86rf2xx_set_txpower(ng_at86rf2xx_t *dev, int16_t txpower);
+void at86rf2xx_set_txpower(at86rf2xx_t *dev, int16_t txpower);
/**
* @brief Get the maximum number of retransmissions
@@ -320,7 +320,7 @@ void ng_at86rf2xx_set_txpower(ng_at86rf2xx_t *dev, int16_t txpower);
*
* @return configured number of retransmissions
*/
-uint8_t ng_at86rf2xx_get_max_retries(ng_at86rf2xx_t *dev);
+uint8_t at86rf2xx_get_max_retries(at86rf2xx_t *dev);
/**
* @brief Set the maximum number of retransmissions
@@ -332,7 +332,7 @@ uint8_t ng_at86rf2xx_get_max_retries(ng_at86rf2xx_t *dev);
* @param[in] dev device to write to
* @param[in] max the maximum number of retransmissions
*/
-void ng_at86rf2xx_set_max_retries(ng_at86rf2xx_t *dev, uint8_t max);
+void at86rf2xx_set_max_retries(at86rf2xx_t *dev, uint8_t max);
/**
* @brief Enable or disable driver specific options
@@ -341,7 +341,7 @@ void ng_at86rf2xx_set_max_retries(ng_at86rf2xx_t *dev, uint8_t max);
* @param[in] option option to enable/disable
* @param[in] state true for enable, false for disable
*/
-void ng_at86rf2xx_set_option(ng_at86rf2xx_t *dev, uint16_t option, bool state);
+void at86rf2xx_set_option(at86rf2xx_t *dev, uint16_t option, bool state);
/**
* @brief Set the state of the given device (trigger a state change)
@@ -349,7 +349,7 @@ void ng_at86rf2xx_set_option(ng_at86rf2xx_t *dev, uint16_t option, bool state);
* @param[in] dev device to change state of
* @param[in] state the targeted new state
*/
-void ng_at86rf2xx_set_state(ng_at86rf2xx_t *dev, uint8_t state);
+void at86rf2xx_set_state(at86rf2xx_t *dev, uint8_t state);
/**
* @brief Reset the internal state machine to TRX_OFF mode.
@@ -360,7 +360,7 @@ void ng_at86rf2xx_set_state(ng_at86rf2xx_t *dev, uint8_t state);
*
* @param[in] dev device to operate on
*/
-void ng_at86rf2xx_reset_state_machine(ng_at86rf2xx_t *dev);
+void at86rf2xx_reset_state_machine(at86rf2xx_t *dev);
/**
* @brief Convenience function for simply sending data
@@ -374,7 +374,7 @@ void ng_at86rf2xx_reset_state_machine(ng_at86rf2xx_t *dev);
* @return number of bytes that were actually send
* @return 0 on error
*/
-size_t ng_at86rf2xx_send(ng_at86rf2xx_t *dev, uint8_t *data, size_t len);
+size_t at86rf2xx_send(at86rf2xx_t *dev, uint8_t *data, size_t len);
/**
* @brief Prepare for sending of data
@@ -384,7 +384,7 @@ size_t ng_at86rf2xx_send(ng_at86rf2xx_t *dev, uint8_t *data, size_t len);
*
* @param[in] dev device to prepare for sending
*/
-void ng_at86rf2xx_tx_prepare(ng_at86rf2xx_t *dev);
+void at86rf2xx_tx_prepare(at86rf2xx_t *dev);
/**
* @brief Load chunks of data into the transmit buffer of the given device
@@ -396,15 +396,15 @@ void ng_at86rf2xx_tx_prepare(ng_at86rf2xx_t *dev);
*
* @return offset + number of bytes written
*/
-size_t ng_at86rf2xx_tx_load(ng_at86rf2xx_t *dev, uint8_t *data, size_t len,
- size_t offset);
+size_t at86rf2xx_tx_load(at86rf2xx_t *dev, uint8_t *data, size_t len,
+ size_t offset);
/**
* @brief Trigger sending of data previously loaded into transmit buffer
*
* @param[in] dev device to trigger
*/
-void ng_at86rf2xx_tx_exec(ng_at86rf2xx_t *dev);
+void at86rf2xx_tx_exec(at86rf2xx_t *dev);
/**
* @brief Read the length of a received packet
@@ -413,7 +413,7 @@ void ng_at86rf2xx_tx_exec(ng_at86rf2xx_t *dev);
*
* @return overall length of a received packet in byte
*/
-size_t ng_at86rf2xx_rx_len(ng_at86rf2xx_t *dev);
+size_t at86rf2xx_rx_len(at86rf2xx_t *dev);
/**
* @brief Read a chunk of data from the receive buffer of the given device
@@ -423,12 +423,12 @@ size_t ng_at86rf2xx_rx_len(ng_at86rf2xx_t *dev);
* @param[in] len number of bytes to read from device
* @param[in] offset offset in the receive buffer
*/
-void ng_at86rf2xx_rx_read(ng_at86rf2xx_t *dev, uint8_t *data, size_t len,
- size_t offset);
+void at86rf2xx_rx_read(at86rf2xx_t *dev, uint8_t *data, size_t len,
+ size_t offset);
#ifdef __cplusplus
}
#endif
-#endif /* NG_AT86RF2XX_H_ */
+#endif /* AT86RF2XX_H_ */
/** @} */
diff --git a/drivers/ng_at86rf2xx/include/ng_at86rf2xx_registers.h b/drivers/ng_at86rf2xx/include/ng_at86rf2xx_registers.h
deleted file mode 100644
index 94c328a6dacb9bee87569da4df2917f273b993af..0000000000000000000000000000000000000000
--- a/drivers/ng_at86rf2xx/include/ng_at86rf2xx_registers.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * Copyright (C) 2013 Alaeddine Weslati <alaeddine.weslati@inria.fr>
- * Copyright (C) 2015 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser
- * General Public License v2.1. See the file LICENSE in the top level
- * directory for more details.
- */
-
-/**
- * @ingroup drivers_ng_at86rf2xx
- * @{
- *
- * @file
- * @brief Register and command definitions for AT86RF2xx devices
- *
- * @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
- * @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
- * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
- * @author Kaspar Schleiser <kaspar@schleiser.de>
- */
-
-#ifndef NG_AT86RF2XX_REGISTERS_H_
-#define NG_AT86RF2XX_REGISTERS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Constant part numbers of the AT86RF2xx device family
- * @{
- */
-#define NG_AT86RF212B_PARTNUM (0x07)
-#define NG_AT86RF231_PARTNUM (0x03)
-#define NG_AT86RF232_PARTNUM (0x0a)
-#define NG_AT86RF233_PARTNUM (0x0b)
-/** @} */
-
-/**
- * @brief Assign the part number for the device we are building the driver for
- * @{
- */
-#ifdef MODULE_NG_AT86RF212B
-#define NG_AT86RF2XX_PARTNUM NG_AT86RF212B_PARTNUM
-#elif MODULE_NG_AT86RF232
-#define NG_AT86RF2XX_PARTNUM NG_AT86RF232_PARTNUM
-#elif MODULE_NG_AT86RF233
-#define NG_AT86RF2XX_PARTNUM NG_AT86RF233_PARTNUM
-#else /* MODULE_NG_AT86RF231 as default device */
-#define NG_AT86RF2XX_PARTNUM NG_AT86RF231_PARTNUM
-#endif
-/** @} */
-
-/**
- * @brief SPI access specifiers
- * @{
- */
-#define NG_AT86RF2XX_ACCESS_REG (0x80)
-#define NG_AT86RF2XX_ACCESS_FB (0x20)
-#define NG_AT86RF2XX_ACCESS_SRAM (0x00)
-#define NG_AT86RF2XX_ACCESS_READ (0x00)
-#define NG_AT86RF2XX_ACCESS_WRITE (0x40)
-/** @} */
-
-/**
- * @brief Register addresses
- * @{
- */
-#define NG_AT86RF2XX_REG__TRX_STATUS (0x01)
-#define NG_AT86RF2XX_REG__TRX_STATE (0x02)
-#define NG_AT86RF2XX_REG__TRX_CTRL_0 (0x03)
-#define NG_AT86RF2XX_REG__TRX_CTRL_1 (0x04)
-#define NG_AT86RF2XX_REG__PHY_TX_PWR (0x05)
-#define NG_AT86RF2XX_REG__PHY_RSSI (0x06)
-#define NG_AT86RF2XX_REG__PHY_ED_LEVEL (0x07)
-#define NG_AT86RF2XX_REG__PHY_CC_CCA (0x08)
-#define NG_AT86RF2XX_REG__CCA_THRES (0x09)
-#define NG_AT86RF2XX_REG__RX_CTRL (0x0A)
-#define NG_AT86RF2XX_REG__SFD_VALUE (0x0B)
-#define NG_AT86RF2XX_REG__TRX_CTRL_2 (0x0C)
-#define NG_AT86RF2XX_REG__ANT_DIV (0x0D)
-#define NG_AT86RF2XX_REG__IRQ_MASK (0x0E)
-#define NG_AT86RF2XX_REG__IRQ_STATUS (0x0F)
-#define NG_AT86RF2XX_REG__VREG_CTRL (0x10)
-#define NG_AT86RF2XX_REG__BATMON (0x11)
-#define NG_AT86RF2XX_REG__XOSC_CTRL (0x12)
-#define NG_AT86RF2XX_REG__CC_CTRL_1 (0x14)
-#define NG_AT86RF2XX_REG__RX_SYN (0x15)
-#ifdef MODULE_NG_AT86RF212B
-#define NG_AT86RF2XX_REG__RF_CTRL_0 (0x16)
-#endif
-#define NG_AT86RF2XX_REG__XAH_CTRL_1 (0x17)
-#define NG_AT86RF2XX_REG__FTN_CTRL (0x18)
-#define NG_AT86RF2XX_REG__PLL_CF (0x1A)
-#define NG_AT86RF2XX_REG__PLL_DCU (0x1B)
-#define NG_AT86RF2XX_REG__PART_NUM (0x1C)
-#define NG_AT86RF2XX_REG__VERSION_NUM (0x1D)
-#define NG_AT86RF2XX_REG__MAN_ID_0 (0x1E)
-#define NG_AT86RF2XX_REG__MAN_ID_1 (0x1F)
-#define NG_AT86RF2XX_REG__SHORT_ADDR_0 (0x20)
-#define NG_AT86RF2XX_REG__SHORT_ADDR_1 (0x21)
-#define NG_AT86RF2XX_REG__PAN_ID_0 (0x22)
-#define NG_AT86RF2XX_REG__PAN_ID_1 (0x23)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_0 (0x24)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_1 (0x25)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_2 (0x26)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_3 (0x27)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_4 (0x28)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_5 (0x29)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_6 (0x2A)
-#define NG_AT86RF2XX_REG__IEEE_ADDR_7 (0x2B)
-#define NG_AT86RF2XX_REG__XAH_CTRL_0 (0x2C)
-#define NG_AT86RF2XX_REG__CSMA_SEED_0 (0x2D)
-#define NG_AT86RF2XX_REG__CSMA_SEED_1 (0x2E)
-#define NG_AT86RF2XX_REG__CSMA_BE (0x2F)
-#define NG_AT86RF2XX_REG__TST_CTRL_DIGI (0x36)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the TRX_CTRL_0 register
- * @{
- */
-#define NG_AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO (0xC0)
-#define NG_AT86RF2XX_TRX_CTRL_0_MASK__PAD_IO_CLKM (0x30)
-#define NG_AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL (0x08)
-#define NG_AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL (0x07)
-
-#define NG_AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO (0x00)
-#define NG_AT86RF2XX_TRX_CTRL_0_DEFAULT__PAD_IO_CLKM (0x10)
-#define NG_AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_SHA_SEL (0x08)
-#define NG_AT86RF2XX_TRX_CTRL_0_DEFAULT__CLKM_CTRL (0x01)
-
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF (0x00)
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__1MHz (0x01)
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__2MHz (0x02)
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__4MHz (0x03)
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__8MHz (0x04)
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__16MHz (0x05)
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__250kHz (0x06)
-#define NG_AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__62_5kHz (0x07)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the TRX_CTRL_1 register
- * @{
- */
-#define NG_AT86RF2XX_TRX_CTRL_1_MASK__PA_EXT_EN (0x80)
-#define NG_AT86RF2XX_TRX_CTRL_1_MASK__IRQ_2_EXT_EN (0x40)
-#define NG_AT86RF2XX_TRX_CTRL_1_MASK__TX_AUTO_CRC_ON (0x20)
-#define NG_AT86RF2XX_TRX_CTRL_1_MASK__RX_BL_CTRL (0x10)
-#define NG_AT86RF2XX_TRX_CTRL_1_MASK__SPI_CMD_MODE (0x0C)
-#define NG_AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE (0x02)
-#define NG_AT86RF2XX_TRX_CTRL_1_MASK__IRQ_POLARITY (0x01)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the TRX_CTRL_2 register
- * @{
- */
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE (0x80)
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE (0x3F)
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__TRX_OFF_AVDD_EN (0x40)
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_SCRAM_EN (0x20)
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__ALT_SPECTRUM (0x10)
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__BPSK_OQPSK (0x08)
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE (0x04)
-#define NG_AT86RF2XX_TRX_CTRL_2_MASK__OQPSK_DATA_RATE (0x03)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the IRQ_STATUS register
- * @{
- */
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__BAT_LOW (0x80)
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__TRX_UR (0x40)
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__AMI (0x20)
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__CCA_ED_DONE (0x10)
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__TRX_END (0x08)
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START (0x04)
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__PLL_UNLOCK (0x02)
-#define NG_AT86RF2XX_IRQ_STATUS_MASK__PLL_LOCK (0x01)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the TRX_STATUS register
- * @{
- */
-#define NG_AT86RF2XX_TRX_STATUS_MASK__CCA_DONE (0x80)
-#define NG_AT86RF2XX_TRX_STATUS_MASK__CCA_STATUS (0x40)
-#define NG_AT86RF2XX_TRX_STATUS_MASK__TRX_STATUS (0x1F)
-
-#define NG_AT86RF2XX_TRX_STATUS__P_ON (0x00)
-#define NG_AT86RF2XX_TRX_STATUS__BUSY_RX (0x01)
-#define NG_AT86RF2XX_TRX_STATUS__BUSY_TX (0x02)
-#define NG_AT86RF2XX_TRX_STATUS__RX_ON (0x06)
-#define NG_AT86RF2XX_TRX_STATUS__TRX_OFF (0x08)
-#define NG_AT86RF2XX_TRX_STATUS__PLL_ON (0x09)
-#define NG_AT86RF2XX_TRX_STATUS__SLEEP (0x0F)
-#define NG_AT86RF2XX_TRX_STATUS__BUSY_RX_AACK (0x11)
-#define NG_AT86RF2XX_TRX_STATUS__BUSY_TX_ARET (0x12)
-#define NG_AT86RF2XX_TRX_STATUS__RX_AACK_ON (0x16)
-#define NG_AT86RF2XX_TRX_STATUS__TX_ARET_ON (0x19)
-#define NG_AT86RF2XX_TRX_STATUS__RX_ON_NOCLK (0x1C)
-#define NG_AT86RF2XX_TRX_STATUS__RX_AACK_ON_NOCLK (0x1D)
-#define NG_AT86RF2XX_TRX_STATUS__BUSY_RX_AACK_NOCLK (0x1E)
-#define NG_AT86RF2XX_TRX_STATUS__STATE_TRANSITION_IN_PROGRESS (0x1F)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the TRX_STATE register
- * @{
- */
-#define NG_AT86RF2XX_TRX_STATE_MASK__TRAC (0xe0)
-
-#define NG_AT86RF2XX_TRX_STATE__NOP (0x00)
-#define NG_AT86RF2XX_TRX_STATE__TX_START (0x02)
-#define NG_AT86RF2XX_TRX_STATE__FORCE_TRX_OFF (0x03)
-#define NG_AT86RF2XX_TRX_STATE__FORCE_PLL_ON (0x04)
-#define NG_AT86RF2XX_TRX_STATE__RX_ON (0x06)
-#define NG_AT86RF2XX_TRX_STATE__TRX_OFF (0x08)
-#define NG_AT86RF2XX_TRX_STATE__PLL_ON (0x09)
-#define NG_AT86RF2XX_TRX_STATE__RX_AACK_ON (0x16)
-#define NG_AT86RF2XX_TRX_STATE__TX_ARET_ON (0x19)
-#define NG_AT86RF2XX_TRX_STATE__TRAC_SUCCESS (0x00)
-#define NG_AT86RF2XX_TRX_STATE__TRAC_SUCCESS_DATA_PENDING (0x20)
-#define NG_AT86RF2XX_TRX_STATE__TRAC_SUCCESS_WAIT_FOR_ACK (0x40)
-#define NG_AT86RF2XX_TRX_STATE__TRAC_CHANNEL_ACCESS_FAILURE (0x60)
-#define NG_AT86RF2XX_TRX_STATE__TRAC_NO_ACK (0xa0)
-#define NG_AT86RF2XX_TRX_STATE__TRAC_INVALID (0xe0)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the PHY_CCA register
- * @{
- */
-#define NG_AT86RF2XX_PHY_CC_CCA_MASK__CCA_REQUEST (0x80)
-#define NG_AT86RF2XX_PHY_CC_CCA_MASK__CCA_MODE (0x60)
-#define NG_AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL (0x1F)
-
-#define NG_AT86RF2XX_PHY_CC_CCA_DEFAULT__CCA_MODE (0x20)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the PHY_TX_PWR register
- * @{
- */
-#ifdef MODULE_NG_AT86RF212B
-#define NG_AT86RF2XX_PHY_TX_PWR_MASK__PA_BOOST (0x80)
-#define NG_AT86RF2XX_PHY_TX_PWR_MASK__GC_PA (0x60)
-#define NG_AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x1F)
-#elif MODULE_NG_AT86RF231
-#define NG_AT86RF2XX_PHY_TX_PWR_MASK__PA_BUF_LT (0xC0)
-#define NG_AT86RF2XX_PHY_TX_PWR_MASK__PA_LT (0x30)
-#define NG_AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
-#else
-#define NG_AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR (0x0F)
-#endif
-#define NG_AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_BUF_LT (0xC0)
-#define NG_AT86RF2XX_PHY_TX_PWR_DEFAULT__PA_LT (0x00)
-#define NG_AT86RF2XX_PHY_TX_PWR_DEFAULT__TX_PWR (0x00)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the PHY_RSSI register
- * @{
- */
-#define NG_AT86RF2XX_PHY_RSSI_MASK__RX_CRC_VALID (0x80)
-#define NG_AT86RF2XX_PHY_RSSI_MASK__RND_VALUE (0x60)
-#define NG_AT86RF2XX_PHY_RSSI_MASK__RSSI (0x1F)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the XOSC_CTRL register
- * @{
- */
-#define NG_AT86RF2XX_XOSC_CTRL__XTAL_MODE_CRYSTAL (0xF0)
-#define NG_AT86RF2XX_XOSC_CTRL__XTAL_MODE_EXTERNAL (0xF0)
-/** @} */
-
-/**
- * @brief Timing values
- * @{
- */
-#define NG_AT86RF2XX_TIMING__VCC_TO_P_ON (330)
-#define NG_AT86RF2XX_TIMING__SLEEP_TO_TRX_OFF (380)
-#define NG_AT86RF2XX_TIMING__TRX_OFF_TO_PLL_ON (110)
-#define NG_AT86RF2XX_TIMING__TRX_OFF_TO_RX_ON (110)
-#define NG_AT86RF2XX_TIMING__PLL_ON_TO_BUSY_TX (16)
-#define NG_AT86RF2XX_TIMING__RESET (100)
-#define NG_AT86RF2XX_TIMING__RESET_TO_TRX_OFF (37)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the XAH_CTRL_0 register
- * @{
- */
-#define NG_AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES (0xF0)
-#define NG_AT86RF2XX_XAH_CTRL_0__MAX_CSMA_RETRIES (0x0E)
-#define NG_AT86RF2XX_XAH_CTRL_0__SLOTTED_OPERATION (0x01)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the XAH_CTRL_1 register
- * @{
- */
-#define NG_AT86RF2XX_XAH_CTRL_1__AACK_FLTR_RES_FT (0x20)
-#define NG_AT86RF2XX_XAH_CTRL_1__AACK_UPLD_RES_FT (0x10)
-#define NG_AT86RF2XX_XAH_CTRL_1__AACK_ACK_TIME (0x04)
-#define NG_AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE (0x02)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the CSMA_SEED_1 register
- * @{
- */
-#define NG_AT86RF2XX_CSMA_SEED_1__AACK_SET_PD (0x20)
-#define NG_AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK (0x10)
-#define NG_AT86RF2XX_CSMA_SEED_1__AACK_I_AM_COORD (0x08)
-/** @} */
-
-/**
- * @brief Bitfield definitions for the RF_CTRL_0 register
- * @{
- */
-#ifdef MODULE_NG_AT86RF212B
-#define NG_AT86RF2XX_RF_CTRL_0_MASK__PA_LT (0xC0)
-#define NG_AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS (0x03)
-
-#define NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__0DB (0x01)
-#define NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__1DB (0x02)
-#define NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB (0x03)
-#endif
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* NG_AT86RF2XX_REGISTERS_H_ */
-/** @} */
diff --git a/drivers/ng_at86rf2xx/ng_at86rf2xx_getset.c b/drivers/ng_at86rf2xx/ng_at86rf2xx_getset.c
deleted file mode 100644
index 3cee746e3464d52038729b6029d9e131a002db01..0000000000000000000000000000000000000000
--- a/drivers/ng_at86rf2xx/ng_at86rf2xx_getset.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/*
- * Copyright (C) 2015 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser
- * General Public License v2.1. See the file LICENSE in the top level
- * directory for more details.
- */
-
-/**
- * @ingroup drivers_ng_at86rf2xx
- * @{
- *
- * @file
- * @brief Getter and setter functions for the AT86RF2xx drivers
- *
- * @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
- * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
- * @author Baptiste Clenet <bapclenet@gmail.com>
- *
- * @}
- */
-
-#include "ng_at86rf2xx.h"
-#include "ng_at86rf2xx_internal.h"
-#include "ng_at86rf2xx_registers.h"
-#include "periph/spi.h"
-
-#define ENABLE_DEBUG (0)
-#include "debug.h"
-
-#ifdef MODULE_NG_AT86RF212B
-/* See: Table 9-15. Recommended Mapping of TX Power, Frequency Band, and
- * PHY_TX_PWR (register 0x05), AT86RF212B data sheet. */
-static const uint8_t dbm_to_tx_pow_868[] = {0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
- 0x17, 0x15, 0x14, 0x13, 0x12, 0x11,
- 0x10, 0x0f, 0x31, 0x30, 0x2f, 0x94,
- 0x93, 0x91, 0x90, 0x29, 0x49, 0x48,
- 0x47, 0xad, 0xcd, 0xcc, 0xcb, 0xea,
- 0xe9, 0xe8, 0xe7, 0xe6, 0xe4, 0x80,
- 0xa0};
-static const uint8_t dbm_to_tx_pow_915[] = {0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x17,
- 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
- 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b,
- 0x09, 0x91, 0x08, 0x07, 0x05, 0x27,
- 0x04, 0x03, 0x02, 0x01, 0x00, 0x86,
- 0x40, 0x84, 0x83, 0x82, 0x80, 0xc1,
- 0xc0};
-int16_t tx_pow_to_dbm(ng_at86rf2xx_freq_t freq, uint8_t reg) {
- for(int i = 0; i < 37; i++){
- if(freq == NG_AT86RF2XX_FREQ_868MHZ){
- if (dbm_to_tx_pow_868[i] == reg) {
- return i -25;
- }
- } else if (freq == NG_AT86RF2XX_FREQ_915MHZ){
- if (dbm_to_tx_pow_915[i] == reg) {
- return i -25;
- }
- }
- }
- return 0;
-}
-
-#elif MODULE_NG_AT86RF233
-static const int16_t tx_pow_to_dbm[] = {4, 4, 3, 3, 2, 2, 1,
- 0, -1, -2, -3, -4, -6, -8, -12, -17};
-static const uint8_t dbm_to_tx_pow[] = {0x0f, 0x0f, 0x0f, 0x0e, 0x0e, 0x0e,
- 0x0e, 0x0d, 0x0d, 0x0d, 0x0c, 0x0c,
- 0x0b, 0x0b, 0x0a, 0x09, 0x08, 0x07,
- 0x06, 0x05, 0x03,0x00};
-#else
-static const int16_t tx_pow_to_dbm[] = {3, 3, 2, 2, 1, 1, 0,
- -1, -2, -3, -4, -5, -7, -9, -12, -17};
-static const uint8_t dbm_to_tx_pow[] = {0x0f, 0x0f, 0x0f, 0x0e, 0x0e, 0x0e,
- 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b,
- 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
- 0x05, 0x03, 0x00};
-#endif
-
-uint16_t ng_at86rf2xx_get_addr_short(ng_at86rf2xx_t *dev)
-{
- return (dev->addr_short[0] << 8) | dev->addr_short[1];
-}
-
-void ng_at86rf2xx_set_addr_short(ng_at86rf2xx_t *dev, uint16_t addr)
-{
- dev->addr_short[0] = addr >> 8;
- dev->addr_short[1] = addr & 0xff;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__SHORT_ADDR_0,
- dev->addr_short[0]);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__SHORT_ADDR_1,
- dev->addr_short[1]);
-}
-
-uint64_t ng_at86rf2xx_get_addr_long(ng_at86rf2xx_t *dev)
-{
- uint64_t addr;
- uint8_t *ap = (uint8_t *)(&addr);
- for (int i = 0; i < 8; i++) {
- ap[i] = dev->addr_long[7 - i];
- }
- return addr;
-}
-
-void ng_at86rf2xx_set_addr_long(ng_at86rf2xx_t *dev, uint64_t addr)
-{
- for (int i = 0; i < 8; i++) {
- dev->addr_long[i] = (addr >> ((7 - i) * 8));
- ng_at86rf2xx_reg_write(dev, (NG_AT86RF2XX_REG__IEEE_ADDR_0 + i),
- dev->addr_long[i]);
- }
-}
-
-uint8_t ng_at86rf2xx_get_chan(ng_at86rf2xx_t *dev)
-{
- return dev->chan;
-}
-
-void ng_at86rf2xx_set_chan(ng_at86rf2xx_t *dev, uint8_t channel)
-{
- uint8_t tmp;
-
- if (channel < NG_AT86RF2XX_MIN_CHANNEL
- || channel > NG_AT86RF2XX_MAX_CHANNEL) {
- return;
- }
- dev->chan = channel;
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__PHY_CC_CCA);
- tmp &= ~(NG_AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL);
- tmp |= (channel & NG_AT86RF2XX_PHY_CC_CCA_MASK__CHANNEL);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__PHY_CC_CCA, tmp);
-}
-
-#ifdef MODULE_NG_AT86RF212B
-ng_at86rf2xx_freq_t ng_at86rf2xx_get_freq(ng_at86rf2xx_t *dev)
-{
- return dev->freq;
-}
-
-void ng_at86rf2xx_set_freq(ng_at86rf2xx_t *dev, ng_at86rf2xx_freq_t freq)
-{
- uint8_t trx_ctrl2 = 0, rf_ctrl0 = 0;
- trx_ctrl2 = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__TRX_CTRL_2);
- trx_ctrl2 &= ~(NG_AT86RF2XX_TRX_CTRL_2_MASK__FREQ_MODE);
- rf_ctrl0 = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__RF_CTRL_0);
- /* Erase previous conf for GC_TX_OFFS */
- rf_ctrl0 &= ~NG_AT86RF2XX_RF_CTRL_0_MASK__GC_TX_OFFS;
-
- trx_ctrl2 |= NG_AT86RF2XX_TRX_CTRL_2_MASK__SUB_MODE;
- rf_ctrl0 |= NG_AT86RF2XX_RF_CTRL_0_GC_TX_OFFS__2DB;
-
- switch(freq) {
- case NG_AT86RF2XX_FREQ_915MHZ:
- if (dev->chan == 0) {
- ng_at86rf2xx_set_chan(dev,NG_AT86RF2XX_DEFAULT_CHANNEL);
- } else {
- ng_at86rf2xx_set_chan(dev,dev->chan);
- }
- break;
-
- case NG_AT86RF2XX_FREQ_868MHZ:
- /* Channel = 0 for 868MHz means 868.3MHz, only one available */
- ng_at86rf2xx_set_chan(dev,0x00);
- break;
-
- default:
- DEBUG("ng_at86rf2xx: Trying to set unknown frequency 0x%lx\n",
- (unsigned long) freq);
- return;
- }
- dev->freq = freq;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_CTRL_2, trx_ctrl2);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__RF_CTRL_0, rf_ctrl0);
-}
-#endif
-
-uint16_t ng_at86rf2xx_get_pan(ng_at86rf2xx_t *dev)
-{
- return dev->pan;
-}
-
-void ng_at86rf2xx_set_pan(ng_at86rf2xx_t *dev, uint16_t pan)
-{
- dev->pan = pan;
- DEBUG("pan0: %u, pan1: %u\n", (uint8_t)pan, pan >> 8);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__PAN_ID_0, (uint8_t)pan);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__PAN_ID_1, (pan >> 8));
-}
-
-int16_t ng_at86rf2xx_get_txpower(ng_at86rf2xx_t *dev)
-{
-#ifdef MODULE_NG_AT86RF212B
- uint8_t txpower = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__PHY_TX_PWR);
- DEBUG("txpower value: %x\n", txpower);
- return tx_pow_to_dbm(dev->freq, txpower);
-#else
- uint8_t txpower = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__PHY_TX_PWR)
- & NG_AT86RF2XX_PHY_TX_PWR_MASK__TX_PWR;
- return tx_pow_to_dbm[txpower];
-#endif
-}
-
-void ng_at86rf2xx_set_txpower(ng_at86rf2xx_t *dev, int16_t txpower)
-{
-#ifdef MODULE_NG_AT86RF212B
- txpower += 25;
-#else
- txpower += 17;
-#endif
- if (txpower < 0) {
- txpower = 0;
-#ifdef MODULE_NG_AT86RF212B
- } else if (txpower > 36) {
- txpower = 36;
-#elif MODULE_NG_AT86RF233
- } else if (txpower > 21) {
- txpower = 21;
-#else
- } else if (txpower > 20) {
- txpower = 20;
-#endif
- }
-#ifdef MODULE_NG_AT86RF212B
- if (dev->freq == NG_AT86RF2XX_FREQ_915MHZ) {
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__PHY_TX_PWR,
- dbm_to_tx_pow_915[txpower]);
- } else if (dev->freq == NG_AT86RF2XX_FREQ_868MHZ) {
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__PHY_TX_PWR,
- dbm_to_tx_pow_868[txpower]);
- } else {
- return;
- }
-#else
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__PHY_TX_PWR,
- dbm_to_tx_pow[txpower]);
-#endif
-}
-
-uint8_t ng_at86rf2xx_get_max_retries(ng_at86rf2xx_t *dev)
-{
- return (ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__XAH_CTRL_0) >> 4);
-}
-
-void ng_at86rf2xx_set_max_retries(ng_at86rf2xx_t *dev, uint8_t max)
-{
- max = (max > 7) ? 7 : max;
- uint8_t tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__XAH_CTRL_0);
- tmp &= ~(NG_AT86RF2XX_XAH_CTRL_0__MAX_FRAME_RETRIES);
- tmp |= (max << 4);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__XAH_CTRL_0, tmp);
-}
-
-void ng_at86rf2xx_set_option(ng_at86rf2xx_t *dev, uint16_t option, bool state)
-{
- uint8_t tmp;
-
- DEBUG("set option %i to %i\n", option, state);
-
- /* set option field */
- if (state) {
- dev->options |= option;
- /* trigger option specific actions */
- switch (option) {
- case NG_AT86RF2XX_OPT_CSMA:
- DEBUG("[ng_at86rf2xx] opt: enabling CSMA mode (NOT IMPLEMENTED)\n");
- /* TODO: en/disable csma */
- break;
- case NG_AT86RF2XX_OPT_PROMISCUOUS:
- DEBUG("[ng_at86rf2xx] opt: enabling PROMISCUOUS mode\n");
- /* disable auto ACKs in promiscuous mode */
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__CSMA_SEED_1);
- tmp |= NG_AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__CSMA_SEED_1, tmp);
- /* enable promiscuous mode */
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__XAH_CTRL_1);
- tmp |= NG_AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__XAH_CTRL_1, tmp);
- break;
- case NG_AT86RF2XX_OPT_AUTOACK:
- DEBUG("[ng_at86rf2xx] opt: enabling auto ACKs\n");
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__CSMA_SEED_1);
- tmp &= ~(NG_AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__CSMA_SEED_1, tmp);
- break;
- case NG_AT86RF2XX_OPT_TELL_RX_START:
- DEBUG("[ng_at86rf2xx] opt: enabling SFD IRQ\n");
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__IRQ_MASK);
- tmp |= NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK, tmp);
- break;
- default:
- /* do nothing */
- break;
- }
- }
- else {
- dev->options &= ~(option);
- /* trigger option specific actions */
- switch (option) {
- case NG_AT86RF2XX_OPT_CSMA:
- DEBUG("[ng_at86rf2xx] opt: disabling CSMA mode (NOT IMPLEMENTED)\n");
- /* TODO: en/disable csma */
- break;
- case NG_AT86RF2XX_OPT_PROMISCUOUS:
- DEBUG("[ng_at86rf2xx] opt: disabling PROMISCUOUS mode\n");
- /* disable promiscuous mode */
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__XAH_CTRL_1);
- tmp &= ~(NG_AT86RF2XX_XAH_CTRL_1__AACK_PROM_MODE);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__XAH_CTRL_1, tmp);
- /* re-enable AUTOACK only if the option is set */
- if (dev->options & NG_AT86RF2XX_OPT_AUTOACK) {
- tmp = ng_at86rf2xx_reg_read(dev,
- NG_AT86RF2XX_REG__CSMA_SEED_1);
- tmp &= ~(NG_AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK);
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__CSMA_SEED_1,
- tmp);
- }
- break;
- case NG_AT86RF2XX_OPT_AUTOACK:
- DEBUG("[ng_at86rf2xx] opt: disabling auto ACKs\n");
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__CSMA_SEED_1);
- tmp |= NG_AT86RF2XX_CSMA_SEED_1__AACK_DIS_ACK;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__CSMA_SEED_1, tmp);
- break;
- case NG_AT86RF2XX_OPT_TELL_RX_START:
- DEBUG("[ng_at86rf2xx] opt: disabling SFD IRQ\n");
- tmp = ng_at86rf2xx_reg_read(dev, NG_AT86RF2XX_REG__IRQ_MASK);
- tmp &= ~NG_AT86RF2XX_IRQ_STATUS_MASK__RX_START;
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__IRQ_MASK, tmp);
- break;
- default:
- /* do nothing */
- break;
- }
- }
-}
-
-static inline void _set_state(ng_at86rf2xx_t *dev, uint8_t state)
-{
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_STATE, state);
- while (ng_at86rf2xx_get_status(dev) != state);
-}
-
-static inline void _force_trx_off(ng_at86rf2xx_t *dev)
-{
- ng_at86rf2xx_reg_write(dev, NG_AT86RF2XX_REG__TRX_STATE, NG_AT86RF2XX_TRX_STATE__FORCE_TRX_OFF);
- while (ng_at86rf2xx_get_status(dev) != NG_AT86RF2XX_STATE_TRX_OFF);
-}
-
-void ng_at86rf2xx_set_state(ng_at86rf2xx_t *dev, uint8_t state)
-{
- uint8_t old_state = ng_at86rf2xx_get_status(dev);
-
- if (state == old_state) {
- return;
- }
- /* make sure there is no ongoing transmission, or state transition already
- * in progress */
- while (old_state == NG_AT86RF2XX_STATE_BUSY_RX_AACK ||
- old_state == NG_AT86RF2XX_STATE_BUSY_TX_ARET ||
- old_state == NG_AT86RF2XX_STATE_IN_PROGRESS) {
- old_state = ng_at86rf2xx_get_status(dev);
- }
-
- /* we need to go via PLL_ON if we are moving between RX_AACK_ON <-> TX_ARET_ON */
- if ((old_state == NG_AT86RF2XX_STATE_RX_AACK_ON &&
- state == NG_AT86RF2XX_STATE_TX_ARET_ON) ||
- (old_state == NG_AT86RF2XX_STATE_TX_ARET_ON &&
- state == NG_AT86RF2XX_STATE_RX_AACK_ON)) {
- _set_state(dev, NG_AT86RF2XX_STATE_PLL_ON);
- }
- /* check if we need to wake up from sleep mode */
- else if (old_state == NG_AT86RF2XX_STATE_SLEEP) {
- DEBUG("at86rf2xx: waking up from sleep mode\n");
- gpio_clear(dev->sleep_pin);
- while (ng_at86rf2xx_get_status(dev) != NG_AT86RF2XX_STATE_TRX_OFF);
- }
-
- if (state == NG_AT86RF2XX_STATE_SLEEP) {
- /* First go to TRX_OFF */
- _force_trx_off(dev);
- /* Go to SLEEP mode from TRX_OFF */
- gpio_set(dev->sleep_pin);
- } else {
- _set_state(dev, state);
- }
-}
-
-void ng_at86rf2xx_reset_state_machine(ng_at86rf2xx_t *dev)
-{
- uint8_t old_state;
-
- /* Wake up */
- gpio_clear(dev->sleep_pin);
-
- /* Wait for any state transitions to complete before forcing TRX_OFF */
- do {
- old_state = ng_at86rf2xx_get_status(dev);
- } while (old_state == NG_AT86RF2XX_STATE_IN_PROGRESS);
-
- _force_trx_off(dev);
-}
diff --git a/sys/auto_init/auto_init.c b/sys/auto_init/auto_init.c
index e9c17eceef596dba3682b5dae5b1194a854c23b9..ff9f88658de73b08955552bf5d38d06a716c8515 100644
--- a/sys/auto_init/auto_init.c
+++ b/sys/auto_init/auto_init.c
@@ -162,9 +162,9 @@ void auto_init(void)
/* initialize network devices */
#ifdef MODULE_AUTO_INIT_NG_NETIF
-#ifdef MODULE_NG_AT86RF2XX
- extern void auto_init_ng_at86rf2xx(void);
- auto_init_ng_at86rf2xx();
+#ifdef MODULE_AT86RF2XX
+ extern void auto_init_at86rf2xx(void);
+ auto_init_at86rf2xx();
#endif
#ifdef MODULE_XBEE
diff --git a/sys/auto_init/netif/auto_init_ng_at86rf2xx.c b/sys/auto_init/netif/auto_init_ng_at86rf2xx.c
index 02a48761686ca58c9956c4ae50992f1b9540567d..a605e3660ad95be4535473705cc998345c7a88a7 100644
--- a/sys/auto_init/netif/auto_init_ng_at86rf2xx.c
+++ b/sys/auto_init/netif/auto_init_ng_at86rf2xx.c
@@ -17,14 +17,14 @@
* @author Kaspar Schleiser <kaspar@schleiser.de>
*/
-#ifdef MODULE_NG_AT86RF2XX
+#ifdef MODULE_AT86RF2XX
#include "board.h"
#include "net/ng_nomac.h"
#include "net/ng_netbase.h"
-#include "ng_at86rf2xx.h"
-#include "ng_at86rf2xx_params.h"
+#include "at86rf2xx.h"
+#include "at86rf2xx_params.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
@@ -38,34 +38,34 @@
#define AT86RF2XX_NUM (sizeof(at86rf2xx_params)/sizeof(at86rf2xx_params[0]))
-static ng_at86rf2xx_t ng_at86rf2xx_devs[AT86RF2XX_NUM];
+static at86rf2xx_t at86rf2xx_devs[AT86RF2XX_NUM];
static char _nomac_stacks[AT86RF2XX_MAC_STACKSIZE][AT86RF2XX_NUM];
-void auto_init_ng_at86rf2xx(void)
+void auto_init_at86rf2xx(void)
{
for (int i = 0; i < AT86RF2XX_NUM; i++) {
DEBUG("Initializing AT86RF2xx radio at SPI_%i\n", i);
const at86rf2xx_params_t *p = &at86rf2xx_params[i];
- int res = ng_at86rf2xx_init(&ng_at86rf2xx_devs[i],
- p->spi,
- p->spi_speed,
- p->cs_pin,
- p->int_pin,
- p->sleep_pin,
- p->reset_pin);
+ int res = at86rf2xx_init(&at86rf2xx_devs[i],
+ p->spi,
+ p->spi_speed,
+ p->cs_pin,
+ p->int_pin,
+ p->sleep_pin,
+ p->reset_pin);
if (res < 0) {
DEBUG("Error initializing AT86RF2xx radio device!");
}
else {
ng_nomac_init(_nomac_stacks[i],
- AT86RF2XX_MAC_STACKSIZE, AT86RF2XX_MAC_PRIO,
- "at86rfxx", (ng_netdev_t *)&ng_at86rf2xx_devs[i]);
+ AT86RF2XX_MAC_STACKSIZE, AT86RF2XX_MAC_PRIO,
+ "at86rfxx", (ng_netdev_t *)&at86rf2xx_devs[i]);
}
}
}
#else
typedef int dont_be_pedantic;
-#endif /* MODULE_NG_AT86RF2XX */
+#endif /* MODULE_AT86RF2XX */
/** @} */
diff --git a/tests/driver_at86rf2xx/Makefile b/tests/driver_at86rf2xx/Makefile
index 71d58cbbdfa108e52348e58b417fcb6b18cc13f5..7a443d9df62c9f66208c740e8773d854bbabef41 100644
--- a/tests/driver_at86rf2xx/Makefile
+++ b/tests/driver_at86rf2xx/Makefile
@@ -24,7 +24,7 @@ else
endif
ifneq (true,$(USE_BOARD_PARAMETERS))
- # This adds . to include path so generic ng_at86rf2xx_params.h gets picked
+ # This adds . to include path so generic at86rf2xx_params.h gets picked
# up. All boards actually having such a device on board should define
# USE_BOARD_PARAMETERS=true above to skip this step, as the board provides
# this header.
diff --git a/tests/driver_at86rf2xx/ng_at86rf2xx_params.h b/tests/driver_at86rf2xx/at86rf2xx_params.h
similarity index 93%
rename from tests/driver_at86rf2xx/ng_at86rf2xx_params.h
rename to tests/driver_at86rf2xx/at86rf2xx_params.h
index 4eaf70222ff75d83f32333a0821b25f7262db502..ae89a65e0d9fb1de2c85c75c27fef5ba9a900afd 100644
--- a/tests/driver_at86rf2xx/ng_at86rf2xx_params.h
+++ b/tests/driver_at86rf2xx/at86rf2xx_params.h
@@ -20,8 +20,8 @@
extern "C" {
#endif
-#ifndef NG_AT86RF2XX_PARAMS_H
-#define NG_AT86RF2XX_PARAMS_H
+#ifndef AT86RF2XX_PARAMS_H
+#define AT86RF2XX_PARAMS_H
/**
* @brief make sure the SPI port and the needed GPIO pins are defined
@@ -66,5 +66,5 @@ static const at86rf2xx_params_t at86rf2xx_params[] =
#ifdef __cplusplus
}
#endif
-#endif /* NG_AT86RF2XX_PARAMS_H */
+#endif /* AT86RF2XX_PARAMS_H */
/** @} */
diff --git a/tests/driver_at86rf2xx/auto_init_ng_netif/netif_app.c b/tests/driver_at86rf2xx/auto_init_ng_netif/netif_app.c
index ac1d3a7ad4d474e596ae1d6b9619301f394a24f4..644992b053f7fbc627bb1053beaafe2eb731a4ce 100644
--- a/tests/driver_at86rf2xx/auto_init_ng_netif/netif_app.c
+++ b/tests/driver_at86rf2xx/auto_init_ng_netif/netif_app.c
@@ -21,7 +21,7 @@
#include <stdio.h>
#include "kernel.h"
-#include "ng_at86rf2xx.h"
+#include "at86rf2xx.h"
#include "net/ng_nomac.h"
#include "net/ng_netbase.h"
@@ -56,7 +56,7 @@
/**
* @brief Allocate the AT86RF2xx device descriptor
*/
-static ng_at86rf2xx_t dev;
+static at86rf2xx_t dev;
/**
* @brief Stack for the nomac thread
@@ -71,9 +71,9 @@ void auto_init_ng_netif(void)
/* initialize the AT86RF2xx device */
printf("Initializing the AT86RF2xx radio at SPI_%i... \n", ATRF_SPI);
- res = ng_at86rf2xx_init(&dev, ATRF_SPI, ATRF_SPI_SPEED,
- ATRF_CS, ATRF_INT,
- ATRF_SLEEP, ATRF_RESET);
+ res = at86rf2xx_init(&dev, ATRF_SPI, ATRF_SPI_SPEED,
+ ATRF_CS, ATRF_INT,
+ ATRF_SLEEP, ATRF_RESET);
if (res < 0) {
puts("Error initializing AT86RF2xx radio device");
return;