From a2d9d9a3f90afcfc5348960ef27000dedc2165f0 Mon Sep 17 00:00:00 2001
From: Hauke Petersen <hauke.petersen@fu-berlin.de>
Date: Tue, 24 Jan 2017 14:37:51 +0100
Subject: [PATCH] boards/maple-mini: adapted SPI configuration
---
boards/maple-mini/include/periph_conf.h | 74 +++++++++++++++----------
1 file changed, 45 insertions(+), 29 deletions(-)
diff --git a/boards/maple-mini/include/periph_conf.h b/boards/maple-mini/include/periph_conf.h
index f48e95cacc..a8998b99ee 100644
--- a/boards/maple-mini/include/periph_conf.h
+++ b/boards/maple-mini/include/periph_conf.h
@@ -163,39 +163,55 @@ static const uart_conf_t uart_config[] = {
#define I2C_1_SDA_PIN GPIO_PIN(PORT_B, 11) /* D0 */
/** @} */
+/**
+ * @brief Shared SPI clock div table
+ *
+ * @note The spi_divtable is auto-generated from
+ * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ */
+static const uint8_t spi_divtable[2][5] = {
+ { /* for APB1 @ 36000000Hz */
+ 7, /* -> 140625Hz */
+ 6, /* -> 281250Hz */
+ 4, /* -> 1125000Hz */
+ 2, /* -> 4500000Hz */
+ 1 /* -> 9000000Hz */
+ },
+ { /* for APB2 @ 72000000Hz */
+ 7, /* -> 281250Hz */
+ 7, /* -> 281250Hz */
+ 5, /* -> 1125000Hz */
+ 3, /* -> 4500000Hz */
+ 2 /* -> 9000000Hz */
+ }
+};
+
/**
* @name SPI configuration
* @{
*/
-#define SPI_NUMOF (2U)
-#define SPI_0_EN 1
-#define SPI_1_EN 0
-#define SPI_IRQ_PRIO 1
-
-/* SPI 0 device config */
-#define SPI_0_DEV SPI1
-#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
-#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
-#define SPI_0_IRQ SPI1_IRQn
-#define SPI_0_IRQ_HANDLER isr_spi1
-#define SPI_0_BUS_DIV 1
-
-/* SPI 0 pin configuration */
-#define SPI_0_CLK_PIN GPIO_PIN(PORT_A, 5) /* D6 */
-#define SPI_0_MISO_PIN GPIO_PIN(PORT_A, 6) /* D5 */
-#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A, 7) /* D4 */
-
-/* SPI 1 device config */
-#define SPI_1_DEV SPI2
-#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI2EN)
-#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN)
-#define SPI_1_IRQ SPI2_IRQn
-#define SPI_1_IRQ_HANDLER isr_spi2
-#define SPI_1_BUS_DIV 1
-/* SPI 1 pin configuration */
-#define SPI_1_CLK_PIN GPIO_PIN(PORT_B, 13) /* D30 */
-#define SPI_1_MISO_PIN GPIO_PIN(PORT_B, 14) /* D29 */
-#define SPI_1_MOSI_PIN GPIO_PIN(PORT_B, 15) /* D28 */
+static const spi_conf_t spi_config[] = {
+ {
+ .dev = SPI1,
+ .mosi_pin = GPIO_PIN(PORT_A, 7),
+ .miso_pin = GPIO_PIN(PORT_A, 6),
+ .sclk_pin = GPIO_PIN(PORT_A, 5),
+ .cs_pin = GPIO_UNDEF,
+ .rccmask = RCC_APB2ENR_SPI1EN,
+ .apbbus = APB2
+ },
+ {
+ .dev = SPI2,
+ .mosi_pin = GPIO_PIN(PORT_B, 15),
+ .miso_pin = GPIO_PIN(PORT_B, 14),
+ .sclk_pin = GPIO_PIN(PORT_B, 13),
+ .cs_pin = GPIO_UNDEF,
+ .rccmask = RCC_APB1ENR_SPI2EN,
+ .apbbus = APB1
+ }
+};
+
+#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
#ifdef __cplusplus
--
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