diff --git a/boards/nucleo-f030/include/periph_conf.h b/boards/nucleo-f030/include/periph_conf.h
index 934e880b38205053848853d7bb36ccde7dc7abee..8140c29f1581b04b56ef37d65fd72d53cd7f31ce 100644
--- a/boards/nucleo-f030/include/periph_conf.h
+++ b/boards/nucleo-f030/include/periph_conf.h
@@ -28,10 +28,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f070/include/periph_conf.h b/boards/nucleo-f070/include/periph_conf.h
index 65d1e4ee18e168b138329ec22b041dd77775f439..d70f79f06649e7309bfbd51588adf9e9ea25d95f 100644
--- a/boards/nucleo-f070/include/periph_conf.h
+++ b/boards/nucleo-f070/include/periph_conf.h
@@ -28,10 +28,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f072/include/periph_conf.h b/boards/nucleo-f072/include/periph_conf.h
index 722d5f29413ffb24a44117f1f4a25dbd31bd81cf..af7c238fffab256cc5bbdd982469c77ab95bab56 100644
--- a/boards/nucleo-f072/include/periph_conf.h
+++ b/boards/nucleo-f072/include/periph_conf.h
@@ -27,10 +27,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f091/include/periph_conf.h b/boards/nucleo-f091/include/periph_conf.h
index 7387e5f7d61285664c432c9abf2e181840e74afa..376c0705a8810fc23263965c38905854e0111fe4 100644
--- a/boards/nucleo-f091/include/periph_conf.h
+++ b/boards/nucleo-f091/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f103/include/periph_conf.h b/boards/nucleo-f103/include/periph_conf.h
index 88e8251501ab947c9ee8166005e68905f82ff76c..ab21ac0c828babf44b407d1b0047431462e4d048 100644
--- a/boards/nucleo-f103/include/periph_conf.h
+++ b/boards/nucleo-f103/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f302/include/periph_conf.h b/boards/nucleo-f302/include/periph_conf.h
index 9e9f6cff84710a12abe850d76d66d7e2e39b45cf..144aeed6703ba8ca275c089dbf70a2a6ba4ad265 100755
--- a/boards/nucleo-f302/include/periph_conf.h
+++ b/boards/nucleo-f302/include/periph_conf.h
@@ -30,23 +30,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo-f303/include/periph_conf.h b/boards/nucleo-f303/include/periph_conf.h
index 1998a9294a575f6263b4cf6350d7ef5b3b4d3f21..4ad384a7d134c3265c6f4eb378a4b238170a7ee1 100755
--- a/boards/nucleo-f303/include/periph_conf.h
+++ b/boards/nucleo-f303/include/periph_conf.h
@@ -28,23 +28,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo-f334/include/periph_conf.h b/boards/nucleo-f334/include/periph_conf.h
index 1660d784d0fd943bfc3e65c5938b7d07146581bb..7ceae49b80cddcf793c5e8c62c4f7fdf71e5f195 100644
--- a/boards/nucleo-f334/include/periph_conf.h
+++ b/boards/nucleo-f334/include/periph_conf.h
@@ -27,23 +27,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
- **/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+ */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo144-f303/include/periph_conf.h b/boards/nucleo144-f303/include/periph_conf.h
index 4d8c5a2a9ba61e0d9531ba510366e77f9e6d038c..4b91f7f449739d6f37cc3a67d9dc69a18b910009 100644
--- a/boards/nucleo144-f303/include/periph_conf.h
+++ b/boards/nucleo144-f303/include/periph_conf.h
@@ -26,23 +26,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo32-f031/include/periph_conf.h b/boards/nucleo32-f031/include/periph_conf.h
index 74b2e8ceab1680b8a0a83297a3157abc191cb8a2..53f027a03592e2dac749d2be50fe2b24b5608585 100644
--- a/boards/nucleo32-f031/include/periph_conf.h
+++ b/boards/nucleo32-f031/include/periph_conf.h
@@ -27,10 +27,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo32-f042/include/periph_conf.h b/boards/nucleo32-f042/include/periph_conf.h
index c609b29b8abeb94d039b081e6f4b2247a5b63f86..d4fb690b39512df569c6f8e59e8af629faf2ecbb 100644
--- a/boards/nucleo32-f042/include/periph_conf.h
+++ b/boards/nucleo32-f042/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo32-f303/include/periph_conf.h b/boards/nucleo32-f303/include/periph_conf.h
index 703f0af2efdd3156577e60ec576d7328fd7c444b..e4f8afcd4e3fd2c3d9a3fefa6b86efbf9418bce4 100644
--- a/boards/nucleo32-f303/include/periph_conf.h
+++ b/boards/nucleo32-f303/include/periph_conf.h
@@ -26,23 +26,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSI (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (64000000U) /* desired core clock frequency */
-
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI)
-/* the actual PLL values are automatically generated */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (64000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (0U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (0)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (2)
+#define CLOCK_PLL_MUL (16)
/** @} */
/**
diff --git a/boards/stm32f0discovery/include/periph_conf.h b/boards/stm32f0discovery/include/periph_conf.h
index 41a86b772ade71ecbb1c8cd37fe7afd78df5432f..d382678891e73f0ee842474ff1710de6be7c3f73 100644
--- a/boards/stm32f0discovery/include/periph_conf.h
+++ b/boards/stm32f0discovery/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/stm32f3discovery/include/periph_conf.h b/boards/stm32f3discovery/include/periph_conf.h
index 8036a92e840c5548738de9c0d03b4b652a4653ab..c4842774e49fabfbee0b1bbcf19095ab8917e409 100644
--- a/boards/stm32f3discovery/include/periph_conf.h
+++ b/boards/stm32f3discovery/include/periph_conf.h
@@ -26,23 +26,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**