From a4b25ad4dc3dd0dc2f7093b34be8ee05fffb7249 Mon Sep 17 00:00:00 2001
From: Vincent Dupont <vincent@otakeys.com>
Date: Sun, 27 Aug 2017 18:26:05 +0200
Subject: [PATCH] boards/nucleo-f3xx: adapt clock config
---
boards/nucleo-f030/include/periph_conf.h | 6 ++--
boards/nucleo-f070/include/periph_conf.h | 6 ++--
boards/nucleo-f072/include/periph_conf.h | 6 ++--
boards/nucleo-f091/include/periph_conf.h | 6 ++--
boards/nucleo-f103/include/periph_conf.h | 6 ++--
boards/nucleo-f302/include/periph_conf.h | 33 ++++++++++-------
boards/nucleo-f303/include/periph_conf.h | 33 ++++++++++-------
boards/nucleo-f334/include/periph_conf.h | 35 ++++++++++++-------
boards/nucleo144-f303/include/periph_conf.h | 33 ++++++++++-------
boards/nucleo32-f031/include/periph_conf.h | 6 ++--
boards/nucleo32-f042/include/periph_conf.h | 6 ++--
boards/nucleo32-f303/include/periph_conf.h | 33 ++++++++++-------
boards/stm32f0discovery/include/periph_conf.h | 6 ++--
boards/stm32f3discovery/include/periph_conf.h | 33 ++++++++++-------
14 files changed, 151 insertions(+), 97 deletions(-)
diff --git a/boards/nucleo-f030/include/periph_conf.h b/boards/nucleo-f030/include/periph_conf.h
index 934e880b38..8140c29f15 100644
--- a/boards/nucleo-f030/include/periph_conf.h
+++ b/boards/nucleo-f030/include/periph_conf.h
@@ -28,10 +28,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f070/include/periph_conf.h b/boards/nucleo-f070/include/periph_conf.h
index 65d1e4ee18..d70f79f066 100644
--- a/boards/nucleo-f070/include/periph_conf.h
+++ b/boards/nucleo-f070/include/periph_conf.h
@@ -28,10 +28,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f072/include/periph_conf.h b/boards/nucleo-f072/include/periph_conf.h
index 722d5f2941..af7c238fff 100644
--- a/boards/nucleo-f072/include/periph_conf.h
+++ b/boards/nucleo-f072/include/periph_conf.h
@@ -27,10 +27,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f091/include/periph_conf.h b/boards/nucleo-f091/include/periph_conf.h
index 7387e5f7d6..376c0705a8 100644
--- a/boards/nucleo-f091/include/periph_conf.h
+++ b/boards/nucleo-f091/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f103/include/periph_conf.h b/boards/nucleo-f103/include/periph_conf.h
index 88e8251501..ab21ac0c82 100644
--- a/boards/nucleo-f103/include/periph_conf.h
+++ b/boards/nucleo-f103/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo-f302/include/periph_conf.h b/boards/nucleo-f302/include/periph_conf.h
index 9e9f6cff84..144aeed670 100755
--- a/boards/nucleo-f302/include/periph_conf.h
+++ b/boards/nucleo-f302/include/periph_conf.h
@@ -30,23 +30,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo-f303/include/periph_conf.h b/boards/nucleo-f303/include/periph_conf.h
index 1998a9294a..4ad384a7d1 100755
--- a/boards/nucleo-f303/include/periph_conf.h
+++ b/boards/nucleo-f303/include/periph_conf.h
@@ -28,23 +28,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo-f334/include/periph_conf.h b/boards/nucleo-f334/include/periph_conf.h
index 1660d784d0..7ceae49b80 100644
--- a/boards/nucleo-f334/include/periph_conf.h
+++ b/boards/nucleo-f334/include/periph_conf.h
@@ -27,23 +27,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
- **/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+ */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo144-f303/include/periph_conf.h b/boards/nucleo144-f303/include/periph_conf.h
index 4d8c5a2a9b..4b91f7f449 100644
--- a/boards/nucleo144-f303/include/periph_conf.h
+++ b/boards/nucleo144-f303/include/periph_conf.h
@@ -26,23 +26,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
diff --git a/boards/nucleo32-f031/include/periph_conf.h b/boards/nucleo32-f031/include/periph_conf.h
index 74b2e8ceab..53f027a035 100644
--- a/boards/nucleo32-f031/include/periph_conf.h
+++ b/boards/nucleo32-f031/include/periph_conf.h
@@ -27,10 +27,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo32-f042/include/periph_conf.h b/boards/nucleo32-f042/include/periph_conf.h
index c609b29b8a..d4fb690b39 100644
--- a/boards/nucleo32-f042/include/periph_conf.h
+++ b/boards/nucleo32-f042/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/nucleo32-f303/include/periph_conf.h b/boards/nucleo32-f303/include/periph_conf.h
index 703f0af2ef..e4f8afcd4e 100644
--- a/boards/nucleo32-f303/include/periph_conf.h
+++ b/boards/nucleo32-f303/include/periph_conf.h
@@ -26,23 +26,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSI (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (64000000U) /* desired core clock frequency */
-
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI)
-/* the actual PLL values are automatically generated */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (64000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (0U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (0)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (2)
+#define CLOCK_PLL_MUL (16)
/** @} */
/**
diff --git a/boards/stm32f0discovery/include/periph_conf.h b/boards/stm32f0discovery/include/periph_conf.h
index 41a86b772a..d382678891 100644
--- a/boards/stm32f0discovery/include/periph_conf.h
+++ b/boards/stm32f0discovery/include/periph_conf.h
@@ -26,10 +26,10 @@ extern "C" {
#endif
/**
- * @name Clock settings
+ * @name Clock settings
*
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
diff --git a/boards/stm32f3discovery/include/periph_conf.h b/boards/stm32f3discovery/include/periph_conf.h
index 8036a92e84..c4842774e4 100644
--- a/boards/stm32f3discovery/include/periph_conf.h
+++ b/boards/stm32f3discovery/include/periph_conf.h
@@ -26,23 +26,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
--
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