From a8b980abfbbaf0d8416f14e8b3de2bcbaf656fa6 Mon Sep 17 00:00:00 2001
From: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Date: Wed, 15 Aug 2018 10:52:17 +0200
Subject: [PATCH] board/nucleo-f030r8: Added SPI config
---
boards/nucleo-f030r8/include/periph_conf.h | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/boards/nucleo-f030r8/include/periph_conf.h b/boards/nucleo-f030r8/include/periph_conf.h
index 5042dbca8d..e054b3fa81 100644
--- a/boards/nucleo-f030r8/include/periph_conf.h
+++ b/boards/nucleo-f030r8/include/periph_conf.h
@@ -139,6 +139,56 @@ static const pwm_conf_t pwm_config[] = {
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
+/**
+ * @name SPI configuration
+ *
+ * @note The spi_divtable is auto-generated from
+ * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+ { /* for APB1 @ 48000000Hz */
+ 7, /* -> 187500Hz */
+ 6, /* -> 375000Hz */
+ 5, /* -> 750000Hz */
+ 2, /* -> 6000000Hz */
+ 1 /* -> 12000000Hz */
+ },
+ { /* for APB2 @ 48000000Hz */
+ 7, /* -> 187500Hz */
+ 6, /* -> 375000Hz */
+ 5, /* -> 750000Hz */
+ 2, /* -> 6000000Hz */
+ 1 /* -> 12000000Hz */
+ }
+};
+
+static const spi_conf_t spi_config[] = {
+ {
+ .dev = SPI1,
+ .mosi_pin = GPIO_PIN(PORT_A, 7),
+ .miso_pin = GPIO_PIN(PORT_A, 6),
+ .sclk_pin = GPIO_PIN(PORT_A, 5),
+ .cs_pin = GPIO_PIN(PORT_A, 4),
+ .af = GPIO_AF0,
+ .rccmask = RCC_APB2ENR_SPI1EN,
+ .apbbus = APB2
+ },
+ {
+ .dev = SPI2,
+ .mosi_pin = GPIO_PIN(PORT_B, 15),
+ .miso_pin = GPIO_PIN(PORT_B, 14),
+ .sclk_pin = GPIO_PIN(PORT_B, 13),
+ .cs_pin = GPIO_PIN(PORT_B, 12),
+ .af = GPIO_AF0,
+ .rccmask = RCC_APB1ENR_SPI2EN,
+ .apbbus = APB1
+ },
+};
+
+#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
/**
* @name ADC configuration
* @{
--
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