From b81094cf7aa06e46d90a29ad5761f96873454bc0 Mon Sep 17 00:00:00 2001
From: Vincent Dupont <vincent@otakeys.com>
Date: Wed, 23 Aug 2017 11:55:48 +0200
Subject: [PATCH] boards/nucleo-f091/103: adapt clock config
---
boards/nucleo-f091/include/periph_conf.h | 34 ++++++++++-----
boards/nucleo-f103/include/periph_conf.h | 53 +++++++++++-------------
2 files changed, 47 insertions(+), 40 deletions(-)
diff --git a/boards/nucleo-f091/include/periph_conf.h b/boards/nucleo-f091/include/periph_conf.h
index 0a32cdfa12..7387e5f7d6 100644
--- a/boards/nucleo-f091/include/periph_conf.h
+++ b/boards/nucleo-f091/include/periph_conf.h
@@ -26,19 +26,31 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
-#define CLOCK_HSE (8000000U) /* external oscillator */
-#define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
-
-/* the actual PLL values are automatically generated */
-#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
-
-/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 48MHz */
+#define CLOCK_CORECLOCK (48000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB2 (CLOCK_APB1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (6)
/** @} */
/**
diff --git a/boards/nucleo-f103/include/periph_conf.h b/boards/nucleo-f103/include/periph_conf.h
index 1b8c2d17a9..88e8251501 100644
--- a/boards/nucleo-f103/include/periph_conf.h
+++ b/boards/nucleo-f103/include/periph_conf.h
@@ -26,37 +26,32 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
- **/
-/* high speed clock configuration:
- * 0 := use internal HSI oscillator (always 8MHz)
- * HSE frequency value := use external HSE oscillator with given freq [in Hz]
- * must be 4000000 <= value <= 16000000 */
-#define CLOCK_HSE (8000000U)
-/* low speed clock configuration:
- * 0 := use internal LSI oscillator (~40kHz)
- * 1 := use extern LSE oscillator, always 32.768kHz */
-#define CLOCK_LSE (1)
-/* targeted system clock speed [in Hz], must be <= 72MHz */
-#define CLOCK_CORECLOCK (72000000U)
-/* PLL configuration, set both values to zero to disable PLL usage. The values
- * must be set to satisfy the following equation:
- * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
- * with
- * 1 <= CLOCK_PLL_DIV <= 2
- * 2 <= CLOCK_PLL_MUL <= 17 */
-#define CLOCK_PLL_DIV (1)
-#define CLOCK_PLL_MUL (9)
-/* AHB and APBx bus clock configuration, keep in mind the following constraints:
- * ABP1 <= 36MHz
*/
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 72MHz */
+#define CLOCK_CORECLOCK (72000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* PLL factors */
+#define CLOCK_PLL_PREDIV (1)
+#define CLOCK_PLL_MUL (9)
/** @} */
/**
--
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