diff --git a/boards/nucleo-f401re/include/periph_conf.h b/boards/nucleo-f401re/include/periph_conf.h
index d697b2ecee33e6ddf0b1fda3856c466a3b4cd4ac..37bb66b36c9b6e9d8a606ce0f907dc37cee8202c 100644
--- a/boards/nucleo-f401re/include/periph_conf.h
+++ b/boards/nucleo-f401re/include/periph_conf.h
@@ -22,42 +22,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
+#include "f4/cfg_clock_84_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * @name Clock settings
- *
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 84MHz */
-#define CLOCK_CORECLOCK (84000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (168)
-#define CLOCK_PLL_P (4)
-#define CLOCK_PLL_Q (7)
-/** @} */
-
/**
* @name Timer configuration
* @{
@@ -249,31 +220,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
*
diff --git a/boards/nucleo-f410rb/include/periph_conf.h b/boards/nucleo-f410rb/include/periph_conf.h
index 0f61d4393f6729c2df586bc157ef0605baa25da1..17e45243695146d34727c041a2d9db16ab415a51 100644
--- a/boards/nucleo-f410rb/include/periph_conf.h
+++ b/boards/nucleo-f410rb/include/periph_conf.h
@@ -22,42 +22,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
+#include "f4/cfg_clock_96_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * @name Clock settings
- *
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (96000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (192)
-#define CLOCK_PLL_P (4)
-#define CLOCK_PLL_Q (8)
-/** @} */
-
/**
* @name Timer configuration
* @{
@@ -178,30 +149,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
*
diff --git a/boards/nucleo-f411re/include/periph_conf.h b/boards/nucleo-f411re/include/periph_conf.h
index 49c0283071bf80de8f034b689cd21e19e4b2f814..558ecd2fb662f4b4798a08c63c5f948b0a9f42be 100644
--- a/boards/nucleo-f411re/include/periph_conf.h
+++ b/boards/nucleo-f411re/include/periph_conf.h
@@ -22,42 +22,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
+#include "f4/cfg_clock_96_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * @name Clock settings
- *
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (96000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (192)
-#define CLOCK_PLL_P (4)
-#define CLOCK_PLL_Q (8)
-/** @} */
-
/**
* @name Timer configuration
* @{
@@ -208,30 +179,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
*
diff --git a/boards/nucleo-f412zg/include/periph_conf.h b/boards/nucleo-f412zg/include/periph_conf.h
index 968d472b5d4e00a87697aa499a156130bd51faa0..5536df2a25420026543da1ed1b033e5e3fa4b149 100644
--- a/boards/nucleo-f412zg/include/periph_conf.h
+++ b/boards/nucleo-f412zg/include/periph_conf.h
@@ -24,53 +24,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
+#include "f4/cfg_clock_100_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * @name Clock settings
- *
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (100000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (200)
-#define CLOCK_PLL_P (4)
-#define CLOCK_PLL_Q (0)
-
-/* PLL I2S configuration */
-#define CLOCK_ENABLE_PLL_I2S (1)
-#define CLOCK_PLL_I2S_SRC (0)
-#define CLOCK_PLL_I2S_M (4)
-#define CLOCK_PLL_I2S_N (216)
-#define CLOCK_PLL_I2S_P (0)
-#define CLOCK_PLL_I2S_Q (9)
-
-/* Use alternative source for 48MHz clock */
-#define CLOCK_USE_ALT_48MHZ (1)
-/** @} */
-
/**
* @name Timer configuration
* @{
@@ -219,30 +179,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
*
diff --git a/boards/nucleo-f413zh/include/periph_conf.h b/boards/nucleo-f413zh/include/periph_conf.h
index 5a88440574f2a30931fef72b70f7c25d13450b69..4b3fd2adf3414828f640572d2034033b8287b5a8 100644
--- a/boards/nucleo-f413zh/include/periph_conf.h
+++ b/boards/nucleo-f413zh/include/periph_conf.h
@@ -24,53 +24,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
+#include "f4/cfg_clock_100_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * @name Clock settings
- *
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (100000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (200)
-#define CLOCK_PLL_P (4)
-#define CLOCK_PLL_Q (0)
-
-/* PLL I2S configuration */
-#define CLOCK_ENABLE_PLL_I2S (1)
-#define CLOCK_PLL_I2S_SRC (0)
-#define CLOCK_PLL_I2S_M (4)
-#define CLOCK_PLL_I2S_N (216)
-#define CLOCK_PLL_I2S_P (0)
-#define CLOCK_PLL_I2S_Q (9)
-
-/* Use alternative source for 48MHz clock */
-#define CLOCK_USE_ALT_48MHZ (1)
-/** @} */
-
/**
* @name DMA streams configuration
* @{
@@ -248,30 +208,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
*
diff --git a/boards/nucleo-f429zi/include/periph_conf.h b/boards/nucleo-f429zi/include/periph_conf.h
index 9c5387b5155c881f07d2493e3890e2e0544eafdf..acccd0d258a2b5f366f87905e7022ea3ae207828 100644
--- a/boards/nucleo-f429zi/include/periph_conf.h
+++ b/boards/nucleo-f429zi/include/periph_conf.h
@@ -23,6 +23,7 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus
@@ -157,30 +158,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
*
diff --git a/boards/nucleo-f446re/include/periph_conf.h b/boards/nucleo-f446re/include/periph_conf.h
index cc69f628e5a235203b4783d8b020137f9cb0e8c0..25ca136d84cd746c52f1980fccc64a9deb316895 100644
--- a/boards/nucleo-f446re/include/periph_conf.h
+++ b/boards/nucleo-f446re/include/periph_conf.h
@@ -23,6 +23,7 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus
@@ -213,31 +214,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
*
diff --git a/boards/nucleo-f446ze/include/periph_conf.h b/boards/nucleo-f446ze/include/periph_conf.h
index ff88e4573df5cbb9931073dda839f64b4285b4fc..fccd35c1286d32950b9ecbc7c6dc1283c97daeb2 100644
--- a/boards/nucleo-f446ze/include/periph_conf.h
+++ b/boards/nucleo-f446ze/include/periph_conf.h
@@ -23,6 +23,7 @@
#include "periph_cpu.h"
#include "f4/cfg_clock_180_8_1.h"
+#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus
@@ -157,30 +158,6 @@ static const spi_conf_t spi_config[] = {
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
-/**
- * @name I2C configuration
- * @{
- */
-static const i2c_conf_t i2c_config[] = {
- {
- .dev = I2C1,
- .speed = I2C_SPEED_NORMAL,
- .scl_pin = GPIO_PIN(PORT_B, 8),
- .sda_pin = GPIO_PIN(PORT_B, 9),
- .scl_af = GPIO_AF4,
- .sda_af = GPIO_AF4,
- .bus = APB1,
- .rcc_mask = RCC_APB1ENR_I2C1EN,
- .clk = CLOCK_APB1,
- .irqn = I2C1_EV_IRQn
- }
-};
-
-#define I2C_0_ISR isr_i2c1_ev
-
-#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
-/** @} */
-
/**
* @name ADC configuration
* @{