From bda86cfcd3d00c882537ec44f85e9770f6d8d286 Mon Sep 17 00:00:00 2001
From: Katja Kirstein <katja.kirstein@haw-hamburg.de>
Date: Tue, 28 Jul 2015 19:08:32 +0200
Subject: [PATCH] boards: limifrog-v1 initial commit
---
boards/limifrog-v1/Makefile | 3 +
boards/limifrog-v1/Makefile.features | 7 +
boards/limifrog-v1/Makefile.include | 16 ++
boards/limifrog-v1/board.c | 58 +++++++
boards/limifrog-v1/dist/openocd.cfg | 5 +
boards/limifrog-v1/include/board.h | 87 +++++++++++
boards/limifrog-v1/include/periph_conf.h | 189 +++++++++++++++++++++++
cpu/stm32l1/ldscripts/stm32l151rc.ld | 27 ++++
cpu/stm32l1/periph/i2c.c | 17 ++
9 files changed, 409 insertions(+)
create mode 100644 boards/limifrog-v1/Makefile
create mode 100644 boards/limifrog-v1/Makefile.features
create mode 100644 boards/limifrog-v1/Makefile.include
create mode 100644 boards/limifrog-v1/board.c
create mode 100644 boards/limifrog-v1/dist/openocd.cfg
create mode 100644 boards/limifrog-v1/include/board.h
create mode 100644 boards/limifrog-v1/include/periph_conf.h
create mode 100644 cpu/stm32l1/ldscripts/stm32l151rc.ld
diff --git a/boards/limifrog-v1/Makefile b/boards/limifrog-v1/Makefile
new file mode 100644
index 0000000000..ff5489888b
--- /dev/null
+++ b/boards/limifrog-v1/Makefile
@@ -0,0 +1,3 @@
+MODULE =$(BOARD)_base
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/limifrog-v1/Makefile.features b/boards/limifrog-v1/Makefile.features
new file mode 100644
index 0000000000..ea61c034ba
--- /dev/null
+++ b/boards/limifrog-v1/Makefile.features
@@ -0,0 +1,7 @@
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_uart
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += cpp
+FEATURES_MCU_GROUP = cortex_m3_2
diff --git a/boards/limifrog-v1/Makefile.include b/boards/limifrog-v1/Makefile.include
new file mode 100644
index 0000000000..40ab526401
--- /dev/null
+++ b/boards/limifrog-v1/Makefile.include
@@ -0,0 +1,16 @@
+## the cpu to build for
+export CPU = stm32l1
+export CPU_MODEL = stm32l151rc
+
+# define the default port depending on the host OS
+PORT_LINUX ?= /dev/ttyUSB0
+PORT_DARWIN ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1)
+
+# setup serial terminal
+include $(RIOTBOARD)/Makefile.include.serial
+
+# this board uses openocd
+include $(RIOTBOARD)/Makefile.include.openocd
+
+# include cortex defaults
+include $(RIOTBOARD)/Makefile.include.cortexm_common
diff --git a/boards/limifrog-v1/board.c b/boards/limifrog-v1/board.c
new file mode 100644
index 0000000000..fda9fb19fd
--- /dev/null
+++ b/boards/limifrog-v1/board.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2015 Hamburg University of Applied Sciences
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup boards_limifrog-v1
+ * @{
+ *
+ * @file
+ * @brief Board specific implementations for the limifrog-v1 board
+ *
+ * @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "cpu.h"
+
+static void leds_init(void);
+
+void board_init(void)
+{
+ /* initialize the boards LEDs */
+ leds_init();
+ /* initialize the CPU */
+ cpu_init();
+}
+
+/**
+ * @brief Initialize the boards on-board LEDs
+ *
+ * The LED initialization is hard-coded in this function.
+ * As the LED is soldered onto the board it is fixed to
+ * its CPU pins.
+ *
+ * The red LED is connected to pin PC3
+ */
+static void leds_init(void)
+{
+ /* enable clock for port GPIOC */
+ RCC->AHBENR |= RCC_AHBENR_GPIOCEN;
+ /* set output speed to 50MHz */
+ LED_RED_PORT->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3;
+ /* set output type to push-pull */
+ LED_RED_PORT->OTYPER &= ~(GPIO_OTYPER_OT_3);
+ /* configure pin as general output */
+ LED_RED_PORT->MODER &= ~(GPIO_MODER_MODER3);
+ LED_RED_PORT->MODER |= GPIO_MODER_MODER3_0;
+ /* disable pull resistors */
+ LED_RED_PORT->PUPDR &= ~(GPIO_PUPDR_PUPDR3);
+ /* turn all LEDs off */
+ LED_RED_PORT->BRR = (1 << 3);
+}
diff --git a/boards/limifrog-v1/dist/openocd.cfg b/boards/limifrog-v1/dist/openocd.cfg
new file mode 100644
index 0000000000..2bf52e0664
--- /dev/null
+++ b/boards/limifrog-v1/dist/openocd.cfg
@@ -0,0 +1,5 @@
+source [find interface/stlink-v2.cfg]
+transport select hla_swd
+
+set WORKAREASIZE 0x2800
+source [find target/stm32l1.cfg]
diff --git a/boards/limifrog-v1/include/board.h b/boards/limifrog-v1/include/board.h
new file mode 100644
index 0000000000..3122e1b7e6
--- /dev/null
+++ b/boards/limifrog-v1/include/board.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2015 Hamburg University of Applied Sciences
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @defgroup boards_limifrog-v1 LimiFrog Version 1
+ * @ingroup boards
+ * @brief Board specific files for the limifrog-v1 board.
+ * @{
+ *
+ * @file
+ * @brief Board specific definitions for the limifrog-v1 board.
+ *
+ * @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include <stdint.h>
+
+#include "cpu.h"
+#include "periph_conf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Define the nominal CPU core clock in this board
+ */
+#define F_CPU CLOCK_CORECLOCK
+/** @} */
+
+/**
+ * @name Define the UART to be used as stdio and its baudrate
+ * @{
+ */
+#define STDIO UART_0
+#define STDIO_BAUDRATE (115200U)
+#define STDIO_RX_BUFSIZE (64U)
+/** @} */
+
+/**
+ * @name Assign the hardware timer
+ */
+#define HW_TIMER TIMER_0
+
+/**
+ * @name LED pin definitions
+ * @{
+ */
+#define LED_RED_PORT (GPIOC)
+#define LED_RED_PIN (3)
+#define LED_RED_GPIO GPIO(PORT_C,3)
+/** @} */
+
+/**
+ * @name Macros for controlling the on-board LEDs.
+ * @{
+ */
+#define LED_GREEN_ON
+#define LED_GREEN_OFF
+#define LED_GREEN_TOGGLE
+#define LED_ORANGE_ON
+#define LED_ORANGE_OFF
+#define LED_ORANGE_TOGGLE
+#define LED_RED_ON (LED_RED_PORT->BSRRL = (1 << LED_RED_PIN))
+#define LED_RED_OFF (LED_RED_PORT->BSRRH = (1 << LED_RED_PIN))
+#define LED_RED_TOGGLE (LED_RED_PORT->ODR ^= (1 << LED_RED_PIN))
+ /** @} */
+
+/**
+ * @brief Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
+/** @} */
diff --git a/boards/limifrog-v1/include/periph_conf.h b/boards/limifrog-v1/include/periph_conf.h
new file mode 100644
index 0000000000..7144c9fda9
--- /dev/null
+++ b/boards/limifrog-v1/include/periph_conf.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2015 Hamburg University of Applied Sciences
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup boards_limifrog-v1
+ * @{
+ *
+ * @file
+ * @brief Peripheral MCU configuration for the limifrog-v1 board
+ *
+ * @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
+ */
+
+#ifndef PERIPH_CONF_H_
+#define PERIPH_CONF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ **/
+#define CLOCK_HSE (16000000U) /* external oscillator */
+#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
+
+/* configuration of PLL prescaler and multiply values */
+/* CORECLOCK := HSI / PLL_HSI_DIV * PLL_HSI_MUL */
+#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLDIV2
+#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMUL4
+/* configuration of peripheral bus clock prescalers */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
+/* configuration of flash access cycles */
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
+/** @} */
+
+/**
+ * @brief Timer configuration
+ * @{
+ */
+#define TIMER_NUMOF (1U)
+#define TIMER_0_EN 1
+#define TIMER_IRQ_PRIO 1
+
+/* Timer 0 configuration */
+#define TIMER_0_DEV_0 TIM2
+#define TIMER_0_DEV_1 TIM3
+#define TIMER_0_CHANNELS 4
+#define TIMER_0_PRESCALER (32U)
+#define TIMER_0_MAX_VALUE (0xffff)
+#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
+#define TIMER_0_ISR_0 isr_tim2
+#define TIMER_0_ISR_1 isr_tim3
+#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
+#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
+#define TIMER_0_IRQ_PRIO 1
+#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
+/** @} */
+
+/**
+ * @brief UART configuration
+ * @{
+ */
+#define UART_NUMOF (2U)
+#define UART_0_EN 1
+#define UART_1_EN 1
+#define UART_IRQ_PRIO 1
+
+/* UART 0 device configuration */
+#define UART_0_DEV USART3
+#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
+#define UART_0_CLK (CLOCK_CORECLOCK)
+#define UART_0_IRQ USART3_IRQn
+#define UART_0_ISR isr_usart3
+/* UART 0 pin configuration */
+#define UART_0_PORT GPIOC
+#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define UART_0_RX_PIN 11
+#define UART_0_TX_PIN 10
+#define UART_0_AF 7
+
+/* UART 1 device configuration */
+#define UART_1_DEV USART3 /* Panasonic PAN1740 BLE module */
+#define UART_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
+#define UART_1_CLK (CLOCK_CORECLOCK)
+#define UART_1_IRQ USART1_IRQn
+#define UART_1_ISR isr_usart1
+/* UART 1 pin configuration */
+#define UART_1_PORT GPIOA
+#define UART_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define UART_1_RX_PIN 10
+#define UART_1_TX_PIN 9
+#define UART_1_AF 7
+/** @} */
+
+/**
+ * @brief SPI configuration
+ * @{
+ */
+#define SPI_NUMOF (2U)
+#define SPI_0_EN 1
+#define SPI_1_EN 1
+
+/* SPI 0 device configuration */
+#define SPI_0_DEV SPI1 /* Densitron DD-160128FC-1a OLED display; external pins */
+#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
+#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define SPI_0_IRQ SPI1_IRQn
+#define SPI_0_ISR isr_spi1
+/* SPI 0 pin configuration */
+#define SPI_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define SPI_0_PORT GPIOA
+#define SPI_0_PIN_SCK 5
+#define SPI_0_PIN_MOSI 7
+#define SPI_0_PIN_MISO 6
+#define SPI_0_PIN_AF 5
+
+/* SPI 1 device configuration */
+#define SPI_1_DEV SPI3 /* Adesto AT45DB641E data flash */
+#define SPI_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_SPI3EN)
+#define SPI_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define SPI_1_IRQ SPI3_IRQn
+#define SPI_1_ISR isr_spi3
+/* SPI 1 pin configuration */
+#define SPI_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
+#define SPI_1_PORT GPIOB
+#define SPI_1_PIN_SCK 3
+#define SPI_1_PIN_MOSI 5
+#define SPI_1_PIN_MISO 4
+#define SPI_1_PIN_AF 6
+/** @} */
+
+/**
+ * @name I2C configuration
+ * @{
+ */
+#define I2C_NUMOF (2U)
+#define I2C_0_EN 1
+#define I2C_1_EN 1
+#define I2C_IRQ_PRIO 1
+#define I2C_APBCLK (36000000U)
+
+/* I2C 0 device configuration */
+#define I2C_0_DEV I2C1
+#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
+#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define I2C_0_EVT_IRQ I2C1_EV_IRQn
+#define I2C_0_EVT_ISR isr_i2c1_ev
+#define I2C_0_ERR_IRQ I2C1_ER_IRQn
+#define I2C_0_ERR_ISR isr_i2c1_er
+/* I2C 0 pin configuration */
+#define I2C_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
+#define I2C_0_PORT GPIOB
+#define I2C_0_SCL_PIN 8
+#define I2C_0_SCL_AF 4
+#define I2C_0_SDA_PIN 9
+#define I2C_0_SDA_AF 4
+
+/* I2C 1 device configuration */
+#define I2C_1_DEV I2C2 /* ST VL6180X, ST LSM6DS3, ST LIS3MDL, ST SLPS25H */
+#define I2C_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C2EN)
+#define I2C_1_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define I2C_1_EVT_IRQ I2C2_EV_IRQn
+#define I2C_1_EVT_ISR isr_i2c2_ev
+#define I2C_1_ERR_IRQ I2C2_ER_IRQn
+#define I2C_1_ERR_ISR isr_i2c2_er
+/* I2C 1 pin configuration */
+#define I2C_1_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
+#define I2C_1_PORT GPIOB
+#define I2C_1_SCL_PIN 10
+#define I2C_1_SCL_AF 4
+#define I2C_1_SDA_PIN 11
+#define I2C_1_SDA_AF 4
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PERIPH_CONF_H */
+/** @} */
diff --git a/cpu/stm32l1/ldscripts/stm32l151rc.ld b/cpu/stm32l1/ldscripts/stm32l151rc.ld
new file mode 100644
index 0000000000..6344f1fc98
--- /dev/null
+++ b/cpu/stm32l1/ldscripts/stm32l151rc.ld
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 Hamburg University of Applied Sciences
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @addtogroup cpu_stm32l1
+ * @{
+ *
+ * @file
+ * @brief Memory definitions for the STM32L151RC
+ *
+ * @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
+ *
+ * @}
+ */
+
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+ ram (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+INCLUDE cortexm_base.ld
diff --git a/cpu/stm32l1/periph/i2c.c b/cpu/stm32l1/periph/i2c.c
index 3bdcc7c814..d8e9deca85 100644
--- a/cpu/stm32l1/periph/i2c.c
+++ b/cpu/stm32l1/periph/i2c.c
@@ -414,6 +414,11 @@ int i2c_write_bytes(i2c_t dev, uint8_t address, char *data, int length)
i2c = I2C_0_DEV;
break;
#endif
+#if I2C_1_EN
+ case I2C_1:
+ i2c = I2C_1_DEV;
+ break;
+#endif
default:
return -1;
@@ -472,6 +477,11 @@ void i2c_poweron(i2c_t dev)
case I2C_0:
I2C_0_CLKEN();
break;
+#endif
+#if I2C_1_EN
+ case I2C_1:
+ I2C_1_CLKEN();
+ break;
#endif
}
}
@@ -486,6 +496,13 @@ void i2c_poweroff(i2c_t dev)
I2C_0_CLKDIS();
break;
#endif
+#if I2C_1_EN
+ case I2C_1:
+ while (I2C_0_DEV->SR2 & I2C_SR2_BUSY);
+
+ I2C_0_CLKDIS();
+ break;
+#endif
}
}
--
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