diff --git a/cpu/stm32_common/dist/clk_conf/clk_conf.c b/cpu/stm32_common/dist/clk_conf/clk_conf.c
index 6d51b487a1be41b048a02316af54d2835913077e..12b4f24cceb96849d17fa259636ef44813a69e01 100644
--- a/cpu/stm32_common/dist/clk_conf/clk_conf.c
+++ b/cpu/stm32_common/dist/clk_conf/clk_conf.c
@@ -300,6 +300,10 @@ int main(int argc, char **argv)
bool use_alt_48MHz = false;
unsigned clock_48MHz = cfg->need_48MHz ? 48000000U : 0;
+ if ((cfg->family == 0 || cfg->family == 1) && pll_src == HSI) {
+ /* HSI / 2 is used as source */
+ m = 2;
+ }
/* main PLL */
/* try to match coreclock with P output and 48MHz for Q output (USB) */
@@ -402,9 +406,11 @@ int main(int argc, char **argv)
break;
}
}
- for (apb2_pre = 1; apb2_pre <= 16; apb2_pre <<= 1) {
- if (coreclock / apb2_pre <= cfg->max_apb2) {
- break;
+ if (cfg->family == STM32F0) {
+ for (apb2_pre = 1; apb2_pre <= 16; apb2_pre <<= 1) {
+ if (coreclock / apb2_pre <= cfg->max_apb2) {
+ break;
+ }
}
}
@@ -432,18 +438,32 @@ int main(int argc, char **argv)
printf("/* peripheral clock setup */\n");
printf("#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1\n"
"#define CLOCK_AHB (CLOCK_CORECLOCK / 1)\n");
- printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV%u /* max %uMHz */\n"
- "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
- apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
- printf("#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV%u /* max %uMHz */\n"
- "#define CLOCK_APB2 (CLOCK_CORECLOCK / %u)\n",
- apb2_pre, cfg->max_apb2 / 1000000U, apb2_pre);
- printf("\n/* Main PLL factors */\n");
- printf("#define CLOCK_PLL_M (%u)\n", m);
- printf("#define CLOCK_PLL_N (%u)\n", n);
- printf("#define CLOCK_PLL_P (%u)\n", p);
- printf("#define CLOCK_PLL_Q (%u)\n", q);
-
+ if (cfg->family == STM32F0) {
+ printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV%u /* max %uMHz */\n"
+ "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
+ apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
+ printf("#define CLOCK_APB2 (CLOCK_APB1)\n");
+ }
+ else {
+ printf("#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV%u /* max %uMHz */\n"
+ "#define CLOCK_APB1 (CLOCK_CORECLOCK / %u)\n",
+ apb1_pre, cfg->max_apb1 / 1000000U, apb1_pre);
+ printf("#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV%u /* max %uMHz */\n"
+ "#define CLOCK_APB2 (CLOCK_CORECLOCK / %u)\n",
+ apb2_pre, cfg->max_apb2 / 1000000U, apb2_pre);
+ }
+ if (cfg->family == STM32F0 || cfg->family == STM32F1 || cfg->family == STM32F3) {
+ printf("\n/* PLL factors */\n");
+ printf("#define CLOCK_PLL_PREDIV (%u)\n", m);
+ printf("#define CLOCK_PLL_MUL (%u)\n", n);
+ }
+ else {
+ printf("\n/* Main PLL factors */\n");
+ printf("#define CLOCK_PLL_M (%u)\n", m);
+ printf("#define CLOCK_PLL_N (%u)\n", n);
+ printf("#define CLOCK_PLL_P (%u)\n", p);
+ printf("#define CLOCK_PLL_Q (%u)\n", q);
+ }
if (pll_i2s_p_out || pll_i2s_q_out) {
printf("\n/* PLL I2S configuration */\n");
diff --git a/cpu/stm32_common/dist/clk_conf/clk_conf.h b/cpu/stm32_common/dist/clk_conf/clk_conf.h
index d335fb3420a7b88b4289d0bc2867b6edd704d356..aad61f6778a7b0043286870ecb994f28797ceac8 100644
--- a/cpu/stm32_common/dist/clk_conf/clk_conf.h
+++ b/cpu/stm32_common/dist/clk_conf/clk_conf.h
@@ -44,6 +44,25 @@ enum fam {
* @{
*/
enum {
+ STM32F030,
+ STM32F070,
+ STM32F031,
+ STM32F051,
+ STM32F071,
+ STM32F091,
+ STM32F042,
+ STM32F072,
+ STM32F038,
+ STM32F048,
+ STM32F058,
+ STM32F078,
+ STM32F098,
+
+ STM32F100,
+ STM32F101,
+ STM32F102,
+ STM32F103,
+
STM32F205,
STM32F207,
STM32F215,
@@ -165,9 +184,29 @@ typedef struct {
/** @} */
#define STM32F(x) [STM32F##x] = x
+#define STM32F0(x) [STM32F0##x] = x
/** List of supported models */
static const unsigned stm32_model[] = {
+ STM32F0(30),
+ STM32F0(70),
+ STM32F0(31),
+ STM32F0(51),
+ STM32F0(71),
+ STM32F0(91),
+ STM32F0(42),
+ STM32F0(72),
+ STM32F0(38),
+ STM32F0(48),
+ STM32F0(58),
+ STM32F0(78),
+ STM32F0(98),
+
+ STM32F(100),
+ STM32F(101),
+ STM32F(102),
+ STM32F(103),
+
STM32F(205),
STM32F(207),
STM32F(215),
@@ -245,6 +284,87 @@ static const unsigned stm32_model[] = {
* @brief Clock config for supported cpu
*/
static const clk_cfg_t stm32_clk_cfg[] = {
+ [STM32F030 ... STM32F098] = {
+ .family = STM32F0,
+ .max_coreclock = 48000000U,
+ .max_apb1 = 48000000U,
+ .max_apb2 = 0,
+ .hsi = 8000000U,
+ .pll = {
+ .min_vco_input = 1000000U,
+ .max_vco_input = 24000000U,
+ .min_vco_output = 16000000U,
+ .max_vco_output = 48000000U,
+ .min_m = 1,
+ .max_m = 16,
+ .inc_m = 1,
+ .min_n = 2,
+ .max_n = 16,
+ .inc_n = 1,
+ .min_p = 1,
+ .max_p = 1,
+ .inc_p = 1,
+ },
+ .has_pll_i2s = false,
+ .has_pll_sai = false,
+ .has_pll_i2s_alt_input = false,
+ .has_alt_48MHz = 0,
+ .need_48MHz = false,
+ },
+ [STM32F100] = {
+ .family = STM32F1,
+ .max_coreclock = 24000000U,
+ .max_apb1 = 24000000U,
+ .max_apb2 = 24000000U,
+ .hsi = 8000000U,
+ .pll = {
+ .min_vco_input = 1000000U,
+ .max_vco_input = 24000000U,
+ .min_vco_output = 16000000U,
+ .max_vco_output = 24000000U,
+ .min_m = 1,
+ .max_m = 16,
+ .inc_m = 1,
+ .min_n = 2,
+ .max_n = 16,
+ .inc_n = 1,
+ .min_p = 1,
+ .max_p = 1,
+ .inc_p = 1,
+ },
+ .has_pll_i2s = false,
+ .has_pll_sai = false,
+ .has_pll_i2s_alt_input = false,
+ .has_alt_48MHz = 0,
+ .need_48MHz = false,
+ },
+ [STM32F101 ... STM32F103] = {
+ .family = STM32F1,
+ .max_coreclock = 72000000U,
+ .max_apb1 = 36000000U,
+ .max_apb2 = 72000000U,
+ .hsi = 8000000U,
+ .pll = {
+ .min_vco_input = 1000000U,
+ .max_vco_input = 25000000U,
+ .min_vco_output = 1000000U,
+ .max_vco_output = 72000000U,
+ .min_m = 1,
+ .max_m = 16,
+ .inc_m = 1,
+ .min_n = 2,
+ .max_n = 16,
+ .inc_n = 1,
+ .min_p = 1,
+ .max_p = 1,
+ .inc_p = 1,
+ },
+ .has_pll_i2s = false,
+ .has_pll_sai = false,
+ .has_pll_i2s_alt_input = false,
+ .has_alt_48MHz = 0,
+ .need_48MHz = false,
+ },
[STM32F205 ... STM32F217] = {
.family = STM32F2,
.max_coreclock = 120000000U,