From c7807517dab52769630c7427c7b5c2fbf317094b Mon Sep 17 00:00:00 2001
From: Hauke Petersen <mail@haukepetersen.de>
Date: Mon, 29 Sep 2014 14:53:59 +0200
Subject: [PATCH] cpu/stm32f1: added clock config to cpu.c
---
cpu/cortex-m3_common/include/cmsis_system.h | 44 ---------------
cpu/stm32f1/cpu.c | 59 +++++++++++++++++++++
2 files changed, 59 insertions(+), 44 deletions(-)
delete mode 100644 cpu/cortex-m3_common/include/cmsis_system.h
diff --git a/cpu/cortex-m3_common/include/cmsis_system.h b/cpu/cortex-m3_common/include/cmsis_system.h
deleted file mode 100644
index c1e0abd592..0000000000
--- a/cpu/cortex-m3_common/include/cmsis_system.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2014 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup cpu_cortexm3_common
- * @{
- *
- * @file
- * @brief CMSIS system header definitions for the Cortex-M3
- *
- * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
- */
-
-#ifndef __CMSIS_SYSTEM_H
-#define __CMSIS_SYSTEM_H
-
-#include <stdint.h>
-
-/**
- * @brief This variable holds the current CPU core clock frequency in Hz
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Initialize the system's clock system
- *
- * This function sets up the system's clock tree, concerning all options
- * regarding PLL setup, external clock source configuration and prescaler
- * setup for peripheral buses.
- */
-void SystemInit(void);
-
-/**
- * @brief Update the `SystemCoreClock` variable with the current core clock value
- */
-void SystemCoreClockUpdate(void);
-
-
-#endif /* __CMSIS_SYSTEM_H */
diff --git a/cpu/stm32f1/cpu.c b/cpu/stm32f1/cpu.c
index 7db00cd3c7..e1e32912db 100644
--- a/cpu/stm32f1/cpu.c
+++ b/cpu/stm32f1/cpu.c
@@ -17,14 +17,73 @@
* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
+#include "periph_conf.h"
+
+static void clk_init(void);
void cpu_init(void)
{
/* set PendSV priority to the lowest possible priority */
NVIC_SetPriority(PendSV_IRQn, 0xff);
+ /* configure the vector table location to internal flash */
+ SCB->VTOR = FLASH_BASE;
+ /* initialize system clocks */
+ clk_init();
+}
+
+/**
+ * @brief Configure the clock system of the stm32f1
+ *
+ */
+static void clk_init(void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = (uint32_t)0x009F0000;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ /* Wait till HSE is ready,
+ * NOTE: the MCU will stay here forever if no HSE clock is connected */
+ while ((RCC->CR & RCC_CR_HSERDY) == 0);
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+ /* Flash 2 wait state */
+ FLASH->ACR &= ~((uint32_t)FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)CLOCK_FLASH_LATENCY;
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
+ /* PLL configuration: PLLCLK = HSE / HSE_DIV * HSE_MUL */
+ RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL);
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+ /* Wait till PLL is ready */
+ while ((RCC->CR & RCC_CR_PLLRDY) == 0);
+ /* Select PLL as system clock source */
+ RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
}
--
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