diff --git a/boards/common/nucleo/Makefile.include b/boards/common/nucleo/Makefile.include
index c8839f7c518dee1c556c5b052620f1697ce859ed..4b6e3db7133a7a7b4b347052800fe97913fdaa5c 100644
--- a/boards/common/nucleo/Makefile.include
+++ b/boards/common/nucleo/Makefile.include
@@ -2,6 +2,9 @@
USEMODULE += boards_common_nucleo
INCLUDES += -I$(RIOTBOARD)/common/nucleo/include
+# we use shared STM32 configuration snippets
+INCLUDES += -I$(RIOTBOARD)/common/stm32/include
+
# configure the serial terminal
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
diff --git a/boards/common/stm32/include/f4/cfg_clock_180_8_1.h b/boards/common/stm32/include/f4/cfg_clock_180_8_1.h
new file mode 100644
index 0000000000000000000000000000000000000000..0e756abbf98426a949d24c2ab2841ff07bddfc08
--- /dev/null
+++ b/boards/common/stm32/include/f4/cfg_clock_180_8_1.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2018 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_common_stm32
+ * @{
+ *
+ * @file
+ * @brief Configure STM32F4 clock to 180MHz using PLL
+ *
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef F4_CFG_CLOCK_180_8_1_H
+#define F4_CFG_CLOCK_180_8_1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
+ * @{
+ */
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 180MHz */
+#define CLOCK_CORECLOCK (180000000U)
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (8000000U)
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (1)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (180)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (0)
+
+/* PLL SAI configuration */
+#define CLOCK_ENABLE_PLL_SAI (1)
+#define CLOCK_PLL_SAI_M (4)
+#define CLOCK_PLL_SAI_N (192)
+#define CLOCK_PLL_SAI_P (8)
+#define CLOCK_PLL_SAI_Q (0)
+
+/* Use alternative source for 48MHz clock */
+#define CLOCK_USE_ALT_48MHZ (1)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* F4_CFG_CLOCK_180_8_1_H */
+/** @} */
diff --git a/boards/nucleo-f446re/include/periph_conf.h b/boards/nucleo-f446re/include/periph_conf.h
index 64e6bf9cd32d2f2055b6c3d72450ed38013c3369..4bd67dc00924a437932dac74ed3e3a80042e7fd4 100644
--- a/boards/nucleo-f446re/include/periph_conf.h
+++ b/boards/nucleo-f446re/include/periph_conf.h
@@ -22,52 +22,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
+#include "f4/cfg_clock_180_8_1.h"
+#include "cfg_spi_divtable.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * @name Clock settings
- *
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 180MHz */
-#define CLOCK_CORECLOCK (180000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (180)
-#define CLOCK_PLL_P (2)
-#define CLOCK_PLL_Q (0)
-
-/* PLL SAI configuration */
-#define CLOCK_ENABLE_PLL_SAI (1)
-#define CLOCK_PLL_SAI_M (4)
-#define CLOCK_PLL_SAI_N (192)
-#define CLOCK_PLL_SAI_P (8)
-#define CLOCK_PLL_SAI_Q (0)
-
-/* Use alternative source for 48MHz clock */
-#define CLOCK_USE_ALT_48MHZ (1)
-/** @} */
-
/**
* @name Timer configuration
* @{
@@ -216,23 +177,6 @@ static const qdec_conf_t qdec_config[] = {
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
-static const uint8_t spi_divtable[2][5] = {
- { /* for APB1 @ 90000000Hz */
- 7, /* -> 351562Hz */
- 7, /* -> 351562Hz */
- 6, /* -> 703125Hz */
- 3, /* -> 5625000Hz */
- 2 /* -> 11250000Hz */
- },
- { /* for APB2 @ 180000000Hz */
- 7, /* -> 703125Hz */
- 7, /* -> 703125Hz */
- 7, /* -> 703125Hz */
- 4, /* -> 5625000Hz */
- 3 /* -> 11250000Hz */
- }
-};
-
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
diff --git a/boards/nucleo-f446ze/include/periph_conf.h b/boards/nucleo-f446ze/include/periph_conf.h
index 3316ae1b62a20eee32ebc339fef01e6c15107159..9735453e8aaa3dde270cd0d1662cda5507eea179 100644
--- a/boards/nucleo-f446ze/include/periph_conf.h
+++ b/boards/nucleo-f446ze/include/periph_conf.h
@@ -22,52 +22,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
+#include "f4/cfg_clock_180_8_1.h"
+#include "cfg_spi_divtable.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * @name Clock settings
- *
- * @note This is auto-generated from
- * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
- * @{
- */
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 180MHz */
-#define CLOCK_CORECLOCK (180000000U)
-/* 0: no external high speed crystal available
- * else: actual crystal frequency [in Hz] */
-#define CLOCK_HSE (8000000U)
-/* 0: no external low speed crystal available,
- * 1: external crystal available (always 32.768kHz) */
-#define CLOCK_LSE (1)
-/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
-#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
-#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
-#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
-#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
-#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
-
-/* Main PLL factors */
-#define CLOCK_PLL_M (4)
-#define CLOCK_PLL_N (180)
-#define CLOCK_PLL_P (2)
-#define CLOCK_PLL_Q (0)
-
-/* PLL SAI configuration */
-#define CLOCK_ENABLE_PLL_SAI (1)
-#define CLOCK_PLL_SAI_M (4)
-#define CLOCK_PLL_SAI_N (192)
-#define CLOCK_PLL_SAI_P (8)
-#define CLOCK_PLL_SAI_Q (0)
-
-/* Use alternative source for 48MHz clock */
-#define CLOCK_USE_ALT_48MHZ (1)
-/** @} */
-
/**
* @name Timer configuration
* @{
@@ -178,28 +139,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
- *
- * @note The spi_divtable is auto-generated from
- * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
-static const uint8_t spi_divtable[2][5] = {
- { /* for APB1 @ 90000000Hz */
- 7, /* -> 351562Hz */
- 7, /* -> 351562Hz */
- 6, /* -> 703125Hz */
- 3, /* -> 5625000Hz */
- 2 /* -> 11250000Hz */
- },
- { /* for APB2 @ 180000000Hz */
- 7, /* -> 703125Hz */
- 7, /* -> 703125Hz */
- 7, /* -> 703125Hz */
- 4, /* -> 5625000Hz */
- 3 /* -> 11250000Hz */
- }
-};
-
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,