From d43dc9182f237e4e214a96311d3fecb7196653ac Mon Sep 17 00:00:00 2001
From: Hauke Petersen <hauke.petersen@fu-berlin.de>
Date: Tue, 15 Sep 2015 11:45:56 +0200
Subject: [PATCH] cpu: s/GPIO(x,y)/GPIO_PIN(x,y)/

---
 cpu/atmega2560/include/periph_cpu.h | 2 +-
 cpu/lpc2387/include/periph_cpu.h    | 2 +-
 cpu/msp430fxyz/include/periph_cpu.h | 2 +-
 cpu/nrf51/include/periph_cpu.h      | 2 +-
 cpu/samd21/include/periph_cpu.h     | 2 +-
 cpu/saml21/include/periph_cpu.h     | 2 +-
 cpu/saml21/periph/spi.c             | 2 +-
 cpu/stm32f1/include/periph_cpu.h    | 2 +-
 cpu/stm32f3/include/periph_cpu.h    | 2 +-
 cpu/stm32f4/include/periph_cpu.h    | 2 +-
 cpu/stm32l1/include/periph_cpu.h    | 2 +-
 11 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/cpu/atmega2560/include/periph_cpu.h b/cpu/atmega2560/include/periph_cpu.h
index 7d38894e90..5d6cd4746f 100644
--- a/cpu/atmega2560/include/periph_cpu.h
+++ b/cpu/atmega2560/include/periph_cpu.h
@@ -29,7 +29,7 @@ extern "C" {
 /**
  * @brief   Define a CPU specific GPIO pin generator macro
  */
-#define GPIO(x, y)          ((x << 4) | y)
+#define GPIO_PIN(x, y)          ((x << 4) | y)
 
 /**
  * @brief   Available ports on the ATmega2560 family
diff --git a/cpu/lpc2387/include/periph_cpu.h b/cpu/lpc2387/include/periph_cpu.h
index 8fccc27687..b80cf392e4 100644
--- a/cpu/lpc2387/include/periph_cpu.h
+++ b/cpu/lpc2387/include/periph_cpu.h
@@ -54,7 +54,7 @@ typedef struct {
 int gpio_init_mux(unsigned pin, unsigned mux);
 void gpio_init_states(void);
 
-#define GPIO(port, pin) (port*32 + pin)
+#define GPIO_PIN(port, pin) (port*32 + pin)
 
 #define HAVE_GPIO_PP_T
 typedef enum {
diff --git a/cpu/msp430fxyz/include/periph_cpu.h b/cpu/msp430fxyz/include/periph_cpu.h
index ca9fc04032..c7050ca2d7 100644
--- a/cpu/msp430fxyz/include/periph_cpu.h
+++ b/cpu/msp430fxyz/include/periph_cpu.h
@@ -43,7 +43,7 @@ typedef uint16_t gpio_t;
  * @brief   Mandatory function for defining a GPIO pins
  * @{
  */
-#define GPIO(x, y)          ((gpio_t)(((x & 0xff) << 8) | (1 << (y & 0xff))))
+#define GPIO_PIN(x, y)      ((gpio_t)(((x & 0xff) << 8) | (1 << (y & 0xff))))
 
 /**
  * @brief   Override direction values
diff --git a/cpu/nrf51/include/periph_cpu.h b/cpu/nrf51/include/periph_cpu.h
index 9bf7ebc31b..2b3fffe910 100644
--- a/cpu/nrf51/include/periph_cpu.h
+++ b/cpu/nrf51/include/periph_cpu.h
@@ -54,7 +54,7 @@ typedef enum {
  *
  * The port definition is used (and zeroed) to suppress compiler warnings
  */
-#define GPIO(x,y)           ((x & 0) | y)
+#define GPIO_PIN(x,y)       ((x & 0) | y)
 
 #ifdef __cplusplus
 }
diff --git a/cpu/samd21/include/periph_cpu.h b/cpu/samd21/include/periph_cpu.h
index e357d1d0bb..09b6cf6adc 100644
--- a/cpu/samd21/include/periph_cpu.h
+++ b/cpu/samd21/include/periph_cpu.h
@@ -42,7 +42,7 @@ typedef uint32_t gpio_t;
  * @brief   Mandatory function for defining a GPIO pins
  * @{
  */
-#define GPIO(x, y)          (((gpio_t)(&PORT->Group[x])) | y)
+#define GPIO_PIN(x, y)      (((gpio_t)(&PORT->Group[x])) | y)
 
 /**
  * @brief   Available ports on the SAMD21
diff --git a/cpu/saml21/include/periph_cpu.h b/cpu/saml21/include/periph_cpu.h
index 1c6dc5eae2..d6384ca654 100644
--- a/cpu/saml21/include/periph_cpu.h
+++ b/cpu/saml21/include/periph_cpu.h
@@ -43,7 +43,7 @@ typedef uint32_t gpio_t;
  * @brief   Mandatory function for defining a GPIO pins
  * @{
  */
-#define GPIO(x, y)          (((gpio_t)(&PORT->Group[x])) | y)
+#define GPIO_PIN(x, y)      (((gpio_t)(&PORT->Group[x])) | y)
 
 /**
  * @brief   Available ports on the SAML21 for convenient access
diff --git a/cpu/saml21/periph/spi.c b/cpu/saml21/periph/spi.c
index c32e2f3129..b2dbafbbfb 100644
--- a/cpu/saml21/periph/spi.c
+++ b/cpu/saml21/periph/spi.c
@@ -72,7 +72,7 @@ typedef struct spi_saml21 {
 static const spi_saml21_t spi[] = {
 #if SPI_0_EN
     /* SPI device */   /* MCLK flag */        /* GLCK id */         /* SCLK */  /* MISO */  /* MOSI */ /* dipo+dopo */
-    { &(SERCOM0->SPI), MCLK_APBCMASK_SERCOM0, SERCOM0_GCLK_ID_CORE, { GPIO(PA,7), 3 }, { GPIO(PA,4), 3 }, { GPIO(PA,6), 3 }, 0, 1 }
+    { &(SERCOM0->SPI), MCLK_APBCMASK_SERCOM0, SERCOM0_GCLK_ID_CORE, { GPIO_PIN(PA,7), 3 }, { GPIO_PIN(PA,4), 3 }, { GPIO_PIN(PA,6), 3 }, 0, 1 }
 #endif
 };
 
diff --git a/cpu/stm32f1/include/periph_cpu.h b/cpu/stm32f1/include/periph_cpu.h
index f883b03b69..1a8e7e6151 100644
--- a/cpu/stm32f1/include/periph_cpu.h
+++ b/cpu/stm32f1/include/periph_cpu.h
@@ -42,7 +42,7 @@ typedef uint32_t gpio_t;
 /**
  * @brief   Define a CPU specific GPIO pin generator macro
  */
-#define GPIO(x, y)          ((GPIOA_BASE + (x << 10)) | y)
+#define GPIO_PIN(x, y)      ((GPIOA_BASE + (x << 10)) | y)
 
 /**
  * @brief   Override values for pull register configuration
diff --git a/cpu/stm32f3/include/periph_cpu.h b/cpu/stm32f3/include/periph_cpu.h
index 8e86ebac7c..0060c1f0e7 100644
--- a/cpu/stm32f3/include/periph_cpu.h
+++ b/cpu/stm32f3/include/periph_cpu.h
@@ -42,7 +42,7 @@ typedef uint32_t gpio_t;
 /**
  * @brief   Define a CPU specific GPIO pin generator macro
  */
-#define GPIO(x, y)          ((GPIOA_BASE + (x << 10)) | y)
+#define GPIO_PIN(x, y)      ((GPIOA_BASE + (x << 10)) | y)
 
 /**
  * @brief   Available ports on the STM32F3 family
diff --git a/cpu/stm32f4/include/periph_cpu.h b/cpu/stm32f4/include/periph_cpu.h
index aead4e9a08..4131cef10a 100644
--- a/cpu/stm32f4/include/periph_cpu.h
+++ b/cpu/stm32f4/include/periph_cpu.h
@@ -42,7 +42,7 @@ typedef uint32_t gpio_t;
 /**
  * @brief   Define a CPU specific GPIO pin generator macro
  */
-#define GPIO(x, y)          ((GPIOA_BASE + (x << 10)) | y)
+#define GPIO_PIN(x, y)      ((GPIOA_BASE + (x << 10)) | y)
 
 /**
  * @brief   Available ports on the STM32F4 family
diff --git a/cpu/stm32l1/include/periph_cpu.h b/cpu/stm32l1/include/periph_cpu.h
index a5507a76e1..a20ef4586e 100644
--- a/cpu/stm32l1/include/periph_cpu.h
+++ b/cpu/stm32l1/include/periph_cpu.h
@@ -43,7 +43,7 @@ typedef uint32_t gpio_t;
 /**
  * @brief   Define a CPU specific GPIO pin generator macro
  */
-#define GPIO(x, y)          ((GPIOA_BASE + (x << 10)) | y)
+#define GPIO_PIN(x, y)      ((GPIOA_BASE + (x << 10)) | y)
 
 /**
  * @brief   Available ports on the STM32L1 family
-- 
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