diff --git a/boards/nucleo-f446/Makefile b/boards/nucleo-f446/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f8fcbb53a06595771dae356338a7bf2c0673734d
--- /dev/null
+++ b/boards/nucleo-f446/Makefile
@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/nucleo-f446/Makefile.features b/boards/nucleo-f446/Makefile.features
new file mode 100644
index 0000000000000000000000000000000000000000..8ea0eba7e3293bba0e988c902d73a608bc481f55
--- /dev/null
+++ b/boards/nucleo-f446/Makefile.features
@@ -0,0 +1,13 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Various other features (if any)
+FEATURES_PROVIDED += cpp
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m4_3
diff --git a/boards/nucleo-f446/Makefile.include b/boards/nucleo-f446/Makefile.include
new file mode 100644
index 0000000000000000000000000000000000000000..00919b161654cac781f8d5dd8ea3fe840aa7ad83
--- /dev/null
+++ b/boards/nucleo-f446/Makefile.include
@@ -0,0 +1,6 @@
+# define the cpu used by the nucleo-f446 board
+export CPU = stm32f4
+export CPU_MODEL = stm32f446re
+
+# load the common Makefile.include for Nucleo boards
+include $(RIOTBOARD)/nucleo-common/Makefile.include
diff --git a/boards/nucleo-f446/board.c b/boards/nucleo-f446/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..60cb20a4ef586cd32ca7101f87df8fdaac5195bc
--- /dev/null
+++ b/boards/nucleo-f446/board.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo-f446
+ * @{
+ *
+ * @file
+ * @brief Board specific implementations for the nucleo-f446 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+
+void board_init(void)
+{
+ /* initialize the CPU */
+ cpu_init();
+
+ /* initialize the boards LEDs */
+ gpio_init(LED0_PIN, GPIO_OUT);
+}
diff --git a/boards/nucleo-f446/dist/openocd.cfg b/boards/nucleo-f446/dist/openocd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..9a3061f0bf823cd3d3ada251afee536c369bd14a
--- /dev/null
+++ b/boards/nucleo-f446/dist/openocd.cfg
@@ -0,0 +1 @@
+source [find board/st_nucleo_f4.cfg]
diff --git a/boards/nucleo-f446/include/board.h b/boards/nucleo-f446/include/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..ebe8b92a08951f842a6c8021141abc6d4c8d403e
--- /dev/null
+++ b/boards/nucleo-f446/include/board.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @defgroup boards_nucleo-f446 Nucleo-F446
+ * @ingroup boards
+ * @brief Board specific files for the nucleo-f446 board
+ * @{
+ *
+ * @file
+ * @brief Board specific definitions for the nucleo-f446 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "board_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name xtimer configuration
+ * @{
+ */
+#define XTIMER_DEV TIMER_0
+#define XTIMER_CHAN (0)
+#define XTIMER_OVERHEAD (6)
+#define XTIMER_BACKOFF (5)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
+/** @} */
diff --git a/boards/nucleo-f446/include/periph_conf.h b/boards/nucleo-f446/include/periph_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..d4a2d093bec93ebbe329ff7197a4c7a2165e818b
--- /dev/null
+++ b/boards/nucleo-f446/include/periph_conf.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo-f446
+ * @{
+ *
+ * @file
+ * @name Peripheral MCU configuration for the nucleo-f446 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef PERIPH_CONF_H_
+#define PERIPH_CONF_H_
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+#define CLOCK_HSE (8000000U) /* external oscillator */
+#define CLOCK_CORECLOCK (180000000U) /* desired core clock frequency */
+
+/* the actual PLL values are automatically generated */
+#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
+#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
+#define CLOCK_PLL_P (2U)
+#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+/** @} */
+
+/**
+ * @name Timer configuration
+ * @{
+ */
+#define TIMER_NUMOF (2U)
+#define TIMER_0_EN 1
+#define TIMER_1_EN 1
+#define TIMER_IRQ_PRIO 1
+
+/* Timer 0 configuration */
+#define TIMER_0_DEV TIM2
+#define TIMER_0_CHANNELS 4
+#define TIMER_0_FREQ (CLOCK_CORECLOCK)
+#define TIMER_0_MAX_VALUE (0xffffffff)
+#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
+#define TIMER_0_ISR isr_tim2
+#define TIMER_0_IRQ_CHAN TIM2_IRQn
+
+/* Timer 1 configuration */
+#define TIMER_1_DEV TIM5
+#define TIMER_1_CHANNELS 4
+#define TIMER_1_FREQ (CLOCK_CORECLOCK)
+#define TIMER_1_MAX_VALUE (0xffffffff)
+#define TIMER_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
+#define TIMER_1_ISR isr_tim5
+#define TIMER_1_IRQ_CHAN TIM5_IRQn
+/** @} */
+
+/**
+ * @brief UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+ {
+ .dev = USART2,
+ .rcc_mask = RCC_APB1ENR_USART2EN,
+ .rx_pin = GPIO_PIN(PORT_A,3),
+ .tx_pin = GPIO_PIN(PORT_A,2),
+ .af = GPIO_AF7,
+ .bus = APB1,
+ .irqn = USART2_IRQn,
+ .dma_stream = 6,
+ .dma_chan = 4
+ }
+};
+
+/* assign ISR vector names */
+#define UART_0_ISR isr_usart2
+#define UART_0_DMA_ISR isr_dma1_stream6
+
+/* deduct number of defined UART interfaces */
+#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @name SPI configuration
+ * @{
+ */
+#define SPI_NUMOF (1U)
+#define SPI_0_EN 1
+#define SPI_IRQ_PRIO 1
+
+/* SPI 0 device config */
+#define SPI_0_DEV SPI1
+#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
+#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
+#define SPI_0_BUS_DIV 1 /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
+#define SPI_0_IRQ SPI1_IRQn
+#define SPI_0_IRQ_HANDLER isr_spi1
+/* SPI 0 pin configuration */
+#define SPI_0_SCK_PORT GPIOA /* A5 pin is shared with the green LED. */
+#define SPI_0_SCK_PIN 5
+#define SPI_0_SCK_AF 5
+#define SPI_0_SCK_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+#define SPI_0_MISO_PORT GPIOA
+#define SPI_0_MISO_PIN 6
+#define SPI_0_MISO_AF 5
+#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+#define SPI_0_MOSI_PORT GPIOA
+#define SPI_0_MOSI_PIN 7
+#define SPI_0_MOSI_AF 5
+#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+/** @} */
+
+
+/**
+ * @name I2C configuration
+ * @{
+ */
+#define I2C_NUMOF (1U)
+#define I2C_0_EN 1
+#define I2C_IRQ_PRIO 1
+#define I2C_APBCLK (42000000U)
+
+/* I2C 0 device configuration */
+#define I2C_0_DEV I2C1
+#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
+#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define I2C_0_EVT_IRQ I2C1_EV_IRQn
+#define I2C_0_EVT_ISR isr_i2c1_ev
+#define I2C_0_ERR_IRQ I2C1_ER_IRQn
+#define I2C_0_ERR_ISR isr_i2c1_er
+/* I2C 0 pin configuration */
+#define I2C_0_SCL_PORT GPIOB
+#define I2C_0_SCL_PIN 8
+#define I2C_0_SCL_AF 4
+#define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
+#define I2C_0_SDA_PORT GPIOB
+#define I2C_0_SDA_PIN 9
+#define I2C_0_SDA_AF 4
+#define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
+/** @} */
+
+/**
+ * @brief ADC configuration
+ * @{
+ */
+#define ADC_NUMOF (0)
+/** @} */
+
+/**
+ * @brief DAC configuration
+ * @{
+ */
+#define DAC_NUMOF (0)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H_ */
+/** @} */