diff --git a/boards/nucleo-l452re/Makefile b/boards/nucleo-l452re/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..4dd17b1d0c90298fe20e7657c9e7aaf3e0c1f656
--- /dev/null
+++ b/boards/nucleo-l452re/Makefile
@@ -0,0 +1,4 @@
+MODULE = board
+DIRS = $(RIOTBOARD)/common/nucleo
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/nucleo-l452re/Makefile.dep b/boards/nucleo-l452re/Makefile.dep
new file mode 100644
index 0000000000000000000000000000000000000000..729485827299c1a63e12514b30d4943aeea41c0d
--- /dev/null
+++ b/boards/nucleo-l452re/Makefile.dep
@@ -0,0 +1 @@
+include $(RIOTBOARD)/common/nucleo/Makefile.dep
diff --git a/boards/nucleo-l452re/Makefile.features b/boards/nucleo-l452re/Makefile.features
new file mode 100644
index 0000000000000000000000000000000000000000..e2b7533200b7706724f3e477fa8ae6ef75657cfb
--- /dev/null
+++ b/boards/nucleo-l452re/Makefile.features
@@ -0,0 +1,16 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_pwm
+FEATURES_PROVIDED += periph_rtc
+FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# load the common Makefile.features for Nucleo boards
+include $(RIOTBOARD)/common/nucleo64/Makefile.features
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m4_2
+
+-include $(RIOTCPU)/stm32l4/Makefile.features
diff --git a/boards/nucleo-l452re/Makefile.include b/boards/nucleo-l452re/Makefile.include
new file mode 100644
index 0000000000000000000000000000000000000000..b820a2b80f0e388fbed7f760af616f969f1a7b3d
--- /dev/null
+++ b/boards/nucleo-l452re/Makefile.include
@@ -0,0 +1,6 @@
+## the cpu to build for
+export CPU = stm32l4
+export CPU_MODEL = stm32l452re
+
+# load the common Makefile.include for Nucleo boards
+include $(RIOTBOARD)/common/nucleo64/Makefile.include
diff --git a/boards/nucleo-l452re/include/periph_conf.h b/boards/nucleo-l452re/include/periph_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..efd5211278a82aaedc39e09353fb01c46919b36b
--- /dev/null
+++ b/boards/nucleo-l452re/include/periph_conf.h
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2017 Freie Universität Berlin
+ * 2017 Inria
+ * 2017 HAW-Hamburg
+ * 2018 Fundacion Inria Chile
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup boards_nucleo-l452re STM32 Nucleo-L452RE
+ * @ingroup boards_common_nucleo64
+ * @brief Support for the STM32 Nucleo-L452RE
+ * @{
+ *
+ * @file
+ * @brief Peripheral MCU configuration for the nucleo-l452re board
+ *
+ * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
+ * @author Francisco Molina <francisco.molina@inria.cl>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+/* 0: no external high speed crystal available
+ * else: actual crystal frequency [in Hz] */
+#define CLOCK_HSE (0)
+
+#ifndef CLOCK_LSE
+/* 0: no external low speed crystal available,
+ * 1: external crystal available (always 32.768kHz) */
+#define CLOCK_LSE (0)
+#endif
+
+/* 0: enable MSI only if HSE isn't available
+ * 1: always enable MSI (e.g. if USB or RNG is used)*/
+#define CLOCK_MSI_ENABLE (1)
+
+#ifndef CLOCK_MSI_LSE_PLL
+/* 0: disable Hardware auto calibration with LSE
+ * 1: enable Hardware auto calibration with LSE (PLL-mode)
+ * Same as with CLOCK_LSE above this defaults to 0 because LSE is
+ * mandatory for MSI/LSE-trimming to work */
+#define CLOCK_MSI_LSE_PLL (0)
+#endif
+
+/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
+#define CLOCK_CORECLOCK (80000000U)
+/* PLL configuration: make sure your values are legit!
+ *
+ * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
+ * with:
+ * PLL_IN: input clock, HSE or MSI @ 48MHz
+ * M: pre-divider, allowed range: [1:8]
+ * N: multiplier, allowed range: [8:86]
+ * R: post-divider, allowed range: [2,4,6,8]
+ *
+ * Also the following constraints need to be met:
+ * (PLL_IN / M) -> [4MHz:16MHz]
+ * (PLL_IN / M) * N -> [64MHz:344MHz]
+ * CORECLOCK -> 80MHz MAX!
+ */
+#define CLOCK_PLL_M (6)
+#define CLOCK_PLL_N (20)
+#define CLOCK_PLL_R (2)
+/* peripheral clock setup */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+/** @} */
+
+/**
+ * @name Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+ {
+ .dev = TIM2,
+ .max = 0xffffffff,
+ .rcc_mask = RCC_APB1ENR1_TIM2EN,
+ .bus = APB1,
+ .irqn = TIM2_IRQn
+ }
+};
+
+#define TIMER_0_ISR isr_tim2
+
+#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @name UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+ {
+ .dev = USART2,
+ .rcc_mask = RCC_APB1ENR1_USART2EN,
+ .rx_pin = GPIO_PIN(PORT_A, 3),
+ .tx_pin = GPIO_PIN(PORT_A, 2),
+ .rx_af = GPIO_AF7,
+ .tx_af = GPIO_AF7,
+ .bus = APB1,
+ .irqn = USART2_IRQn,
+ },
+ {
+ .dev = USART3,
+ .rcc_mask = RCC_APB1ENR1_USART3EN,
+ .rx_pin = GPIO_PIN(PORT_C, 11),
+ .tx_pin = GPIO_PIN(PORT_C, 10),
+ .rx_af = GPIO_AF7,
+ .tx_af = GPIO_AF7,
+ .bus = APB1,
+ .irqn = USART3_IRQn,
+ }
+};
+
+#define UART_0_ISR (isr_usart2)
+#define UART_1_ISR (isr_usart3)
+
+#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @name PWM configuration
+ * @{
+ */
+static const pwm_conf_t pwm_config[] = {
+ {
+ .dev = TIM3,
+ .rcc_mask = RCC_APB1ENR1_TIM3EN,
+ .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
+ { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
+ { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
+ { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
+ .af = GPIO_AF2,
+ .bus = APB1
+ },
+};
+
+#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
+/** @} */
+
+/**
+ * @name SPI configuration
+ *
+ * @note The spi_divtable is auto-generated from
+ * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+ { /* for APB1 @ 20000000Hz */
+ 7, /* -> 78125Hz */
+ 5, /* -> 312500Hz */
+ 3, /* -> 1250000Hz */
+ 1, /* -> 5000000Hz */
+ 0 /* -> 10000000Hz */
+ },
+ { /* for APB2 @ 40000000Hz */
+ 7, /* -> 156250Hz */
+ 6, /* -> 312500Hz */
+ 4, /* -> 1250000Hz */
+ 2, /* -> 5000000Hz */
+ 1 /* -> 10000000Hz */
+ }
+};
+
+static const spi_conf_t spi_config[] = {
+ {
+ .dev = SPI1,
+ .mosi_pin = GPIO_PIN(PORT_A, 7),
+ .miso_pin = GPIO_PIN(PORT_A, 6),
+ .sclk_pin = GPIO_PIN(PORT_A, 5),
+ .cs_pin = GPIO_UNDEF,
+ .af = GPIO_AF5,
+ .rccmask = RCC_APB2ENR_SPI1EN,
+ .apbbus = APB2
+ },
+};
+
+#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+/**
+ * @name ADC configuration
+ * @{
+ */
+#define ADC_NUMOF (0)
+/** @} */
+
+/**
+ * @name RTT configuration
+ *
+ * On the STM32Lx platforms, we always utilize the LPTIM1.
+ * @{
+ */
+#define RTT_NUMOF (1)
+#define RTT_FREQUENCY (1024U) /* 32768 / 2^n */
+#define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
+/** @} */
+
+/**
+ * @name RTC configuration
+ * @{
+ */
+#define RTC_NUMOF (1)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */