diff --git a/cpu/k22f/Makefile b/cpu/k22f/Makefile
index 1f7c73333ce5f291c09ab49a25040655ac548709..4e53b72929a07013e564b710b65e06d318086ea6 100644
--- a/cpu/k22f/Makefile
+++ b/cpu/k22f/Makefile
@@ -4,7 +4,4 @@ MODULE = cpu
# add a list of subdirectories that should also be built
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
-# (file triggers compiler bug. see #5775)
-SRC_NOLTO += vectors.c
-
include $(RIOTBASE)/Makefile.base
diff --git a/cpu/k22f/Makefile.include b/cpu/k22f/Makefile.include
index e12cb2e555a95f2cb770afd604ea4ab12c0cc8fa..6d518675004cefaf6175ed0091a4be66d4d73a50 100644
--- a/cpu/k22f/Makefile.include
+++ b/cpu/k22f/Makefile.include
@@ -19,7 +19,4 @@ include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
-# add the CPU specific system calls implementations for the linker
-export UNDEF += $(BINDIR)/cpu/vectors.o
-
include $(RIOTMAKE)/arch/cortexm.inc.mk
diff --git a/cpu/k22f/vectors.c b/cpu/k22f/vectors.c
deleted file mode 100644
index 8383e8daa30f01c5c2f7c1dbf9645e907ef1560f..0000000000000000000000000000000000000000
--- a/cpu/k22f/vectors.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Copyright (C) 2017 Eistec AB
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup cpu_k22f
- * @{
- *
- * @file
- * @brief Interrupt vector definition for K22F MCUs
- *
- * @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
- *
- * @}
- */
-
-#include "vectors_kinetis.h"
-
-/* CPU specific interrupt vector table */
-ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
- isr_dma0, /* DMA channel 0 transfer complete */
- isr_dma1, /* DMA channel 1 transfer complete */
- isr_dma2, /* DMA channel 2 transfer complete */
- isr_dma3, /* DMA channel 3 transfer complete */
- isr_dma4, /* DMA channel 4 transfer complete */
- isr_dma5, /* DMA channel 5 transfer complete */
- isr_dma6, /* DMA channel 6 transfer complete */
- isr_dma7, /* DMA channel 7 transfer complete */
- isr_dma8, /* DMA channel 8 transfer complete */
- isr_dma9, /* DMA channel 9 transfer complete */
- isr_dma10, /* DMA channel 10 transfer complete */
- isr_dma11, /* DMA channel 11 transfer complete */
- isr_dma12, /* DMA channel 12 transfer complete */
- isr_dma13, /* DMA channel 13 transfer complete */
- isr_dma14, /* DMA channel 14 transfer complete */
- isr_dma15, /* DMA channel 15 transfer complete */
- isr_dma_error, /* DMA channel 0 - 15 error */
- isr_mcm, /* MCM normal interrupt */
- isr_ftfl, /* FTFL command complete */
- isr_ftfl_collision, /* FTFL read collision */
- isr_pmc, /* PMC controller low-voltage detect low-voltage warning */
- isr_llwu, /* Low leakage wakeup */
- isr_wdog_ewm, /* Single interrupt vector for WDOG and EWM */
- isr_rng, /* Randon number generator */
- isr_i2c0, /* Inter-integrated circuit 0 */
- isr_i2c1, /* Inter-integrated circuit 1 */
- isr_spi0, /* Serial peripheral Interface 0 */
- isr_spi1, /* Serial peripheral Interface 1 */
- isr_i2s0_tx, /* Integrated interchip sound 0 transmit interrupt */
- isr_i2s0_rx, /* Integrated interchip sound 0 receive interrupt */
- isr_lpuart0, /* LPUART0 interrupt */
- isr_uart0_rx_tx, /* UART0 receive/transmit interrupt */
- isr_uart0_error, /* UART0 error interrupt */
- isr_uart1_rx_tx, /* UART1 receive/transmit interrupt */
- isr_uart1_error, /* UART1 error interrupt */
- isr_uart2_rx_tx, /* UART2 receive/transmit interrupt */
- isr_uart2_error, /* UART2 error interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- isr_adc0, /* Analog-to-digital converter 0 */
- isr_cmp0, /* Comparator 0 */
- isr_cmp1, /* Comparator 1 */
- isr_ftm0, /* FlexTimer module 0 fault overflow and channels interrupt */
- isr_ftm1, /* FlexTimer module 1 fault overflow and channels interrupt */
- isr_ftm2, /* FlexTimer module 2 fault overflow and channels interrupt */
- dummy_handler, /* Reserved interrupt */
- isr_rtc, /* Real time clock */
- isr_rtc_seconds, /* Real time clock seconds */
- isr_pit0, /* Periodic interrupt timer channel 0 */
- isr_pit1, /* Periodic interrupt timer channel 1 */
- isr_pit2, /* Periodic interrupt timer channel 2 */
- isr_pit3, /* Periodic interrupt timer channel 3 */
- isr_pdb0, /* Programmable delay block */
- isr_usb0, /* USB OTG interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- isr_dac0, /* Digital-to-analog converter 0 */
- isr_mcg, /* Multipurpose clock generator */
- isr_lptmr0, /* Low power timer interrupt */
- isr_porta, /* Port A pin detect interrupt */
- isr_portb, /* Port B pin detect interrupt */
- isr_portc, /* Port C pin detect interrupt */
- isr_portd, /* Port D pin detect interrupt */
- isr_porte, /* Port E pin detect interrupt */
- isr_swi, /* Software interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- isr_ftm3, /* FlexTimer module 3 fault overflow and channels interrupt */
- isr_dac1, /* Digital-to-analog converter 1 */
- isr_adc1, /* Analog-to-digital converter 1 */
- dummy_handler, /* reserved 90 */
- dummy_handler, /* reserved 91 */
- dummy_handler, /* reserved 92 */
- dummy_handler, /* reserved 93 */
- dummy_handler, /* reserved 94 */
- dummy_handler, /* reserved 95 */
- dummy_handler, /* reserved 96 */
- dummy_handler, /* reserved 97 */
- dummy_handler, /* reserved 98 */
- dummy_handler, /* reserved 99 */
- dummy_handler, /* reserved 100 */
- dummy_handler, /* reserved 101 */
- dummy_handler, /* reserved 102 */
- dummy_handler, /* reserved 103 */
- dummy_handler, /* reserved 104 */
- dummy_handler, /* reserved 105 */
- dummy_handler, /* reserved 106 */
- dummy_handler, /* reserved 107 */
- dummy_handler, /* reserved 108 */
- dummy_handler, /* reserved 109 */
- dummy_handler, /* reserved 110 */
- dummy_handler, /* reserved 111 */
- dummy_handler, /* reserved 112 */
- dummy_handler, /* reserved 113 */
- dummy_handler, /* reserved 114 */
- dummy_handler, /* reserved 115 */
- dummy_handler, /* reserved 116 */
- dummy_handler, /* reserved 117 */
- dummy_handler, /* reserved 118 */
- dummy_handler, /* reserved 119 */
- dummy_handler, /* reserved 120 */
- dummy_handler, /* reserved 121 */
- dummy_handler, /* reserved 122 */
- dummy_handler, /* reserved 123 */
- dummy_handler, /* reserved 124 */
- dummy_handler, /* reserved 125 */
- dummy_handler, /* reserved 126 */
- dummy_handler, /* reserved 127 */
- dummy_handler, /* reserved 128 */
- dummy_handler, /* reserved 129 */
- dummy_handler, /* reserved 130 */
- dummy_handler, /* reserved 131 */
- dummy_handler, /* reserved 132 */
- dummy_handler, /* reserved 133 */
- dummy_handler, /* reserved 134 */
- dummy_handler, /* reserved 135 */
- dummy_handler, /* reserved 136 */
- dummy_handler, /* reserved 137 */
- dummy_handler, /* reserved 138 */
- dummy_handler, /* reserved 139 */
- dummy_handler, /* reserved 140 */
- dummy_handler, /* reserved 141 */
- dummy_handler, /* reserved 142 */
- dummy_handler, /* reserved 143 */
- dummy_handler, /* reserved 144 */
- dummy_handler, /* reserved 145 */
- dummy_handler, /* reserved 146 */
- dummy_handler, /* reserved 147 */
- dummy_handler, /* reserved 148 */
- dummy_handler, /* reserved 149 */
- dummy_handler, /* reserved 150 */
- dummy_handler, /* reserved 151 */
- dummy_handler, /* reserved 152 */
- dummy_handler, /* reserved 153 */
- dummy_handler, /* reserved 154 */
- dummy_handler, /* reserved 155 */
- dummy_handler, /* reserved 156 */
- dummy_handler, /* reserved 157 */
- dummy_handler, /* reserved 158 */
- dummy_handler, /* reserved 159 */
- dummy_handler, /* reserved 160 */
- dummy_handler, /* reserved 161 */
- dummy_handler, /* reserved 162 */
- dummy_handler, /* reserved 163 */
- dummy_handler, /* reserved 164 */
- dummy_handler, /* reserved 165 */
- dummy_handler, /* reserved 166 */
- dummy_handler, /* reserved 167 */
- dummy_handler, /* reserved 168 */
- dummy_handler, /* reserved 169 */
- dummy_handler, /* reserved 170 */
- dummy_handler, /* reserved 171 */
- dummy_handler, /* reserved 172 */
- dummy_handler, /* reserved 173 */
- dummy_handler, /* reserved 174 */
- dummy_handler, /* reserved 175 */
- dummy_handler, /* reserved 176 */
- dummy_handler, /* reserved 177 */
- dummy_handler, /* reserved 178 */
- dummy_handler, /* reserved 179 */
- dummy_handler, /* reserved 180 */
- dummy_handler, /* reserved 181 */
- dummy_handler, /* reserved 182 */
- dummy_handler, /* reserved 183 */
- dummy_handler, /* reserved 184 */
- dummy_handler, /* reserved 185 */
- dummy_handler, /* reserved 186 */
- dummy_handler, /* reserved 187 */
- dummy_handler, /* reserved 188 */
- dummy_handler, /* reserved 189 */
- dummy_handler, /* reserved 190 */
- dummy_handler, /* reserved 191 */
- dummy_handler, /* reserved 192 */
- dummy_handler, /* reserved 193 */
- dummy_handler, /* reserved 194 */
- dummy_handler, /* reserved 195 */
- dummy_handler, /* reserved 196 */
- dummy_handler, /* reserved 197 */
- dummy_handler, /* reserved 198 */
- dummy_handler, /* reserved 199 */
- dummy_handler, /* reserved 200 */
- dummy_handler, /* reserved 201 */
- dummy_handler, /* reserved 202 */
- dummy_handler, /* reserved 203 */
- dummy_handler, /* reserved 204 */
- dummy_handler, /* reserved 205 */
- dummy_handler, /* reserved 206 */
- dummy_handler, /* reserved 207 */
- dummy_handler, /* reserved 208 */
- dummy_handler, /* reserved 209 */
- dummy_handler, /* reserved 210 */
- dummy_handler, /* reserved 211 */
- dummy_handler, /* reserved 212 */
- dummy_handler, /* reserved 213 */
- dummy_handler, /* reserved 214 */
- dummy_handler, /* reserved 215 */
- dummy_handler, /* reserved 216 */
- dummy_handler, /* reserved 217 */
- dummy_handler, /* reserved 218 */
- dummy_handler, /* reserved 219 */
- dummy_handler, /* reserved 220 */
- dummy_handler, /* reserved 221 */
- dummy_handler, /* reserved 222 */
- dummy_handler, /* reserved 223 */
- dummy_handler, /* reserved 224 */
- dummy_handler, /* reserved 225 */
- dummy_handler, /* reserved 226 */
- dummy_handler, /* reserved 227 */
- dummy_handler, /* reserved 228 */
- dummy_handler, /* reserved 229 */
- dummy_handler, /* reserved 230 */
- dummy_handler, /* reserved 231 */
- dummy_handler, /* reserved 232 */
- dummy_handler, /* reserved 233 */
- dummy_handler, /* reserved 234 */
- dummy_handler, /* reserved 235 */
- dummy_handler, /* reserved 236 */
- dummy_handler, /* reserved 237 */
- dummy_handler, /* reserved 238 */
- dummy_handler, /* reserved 239 */
- dummy_handler, /* reserved 240 */
- dummy_handler, /* reserved 241 */
- dummy_handler, /* reserved 242 */
- dummy_handler, /* reserved 243 */
- dummy_handler, /* reserved 244 */
- dummy_handler, /* reserved 245 */
- dummy_handler, /* reserved 246 */
- dummy_handler, /* reserved 247 */
- dummy_handler, /* reserved 248 */
- dummy_handler, /* reserved 249 */
- dummy_handler, /* reserved 250 */
- dummy_handler, /* reserved 251 */
- dummy_handler, /* reserved 252 */
- dummy_handler, /* reserved 253 */
- dummy_handler, /* reserved 254 */
- dummy_handler, /* reserved 255 */
-};
diff --git a/cpu/k60/Makefile b/cpu/k60/Makefile
index 68605a469b55f3f54b540cce34fbedeeec39d472..12ba41f9cf16d9b3e8b1e8fcf75cc0bcfa85f04c 100644
--- a/cpu/k60/Makefile
+++ b/cpu/k60/Makefile
@@ -4,7 +4,4 @@ MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
-# (file triggers compiler bug. see #5775)
-SRC_NOLTO += vectors.c
-
include $(RIOTBASE)/Makefile.base
diff --git a/cpu/k60/Makefile.include b/cpu/k60/Makefile.include
index 78c861da5e779c98b6e000fe3d6774a5784e42b4..f5fb57871633b47f455356b8926381e68e4fe075 100644
--- a/cpu/k60/Makefile.include
+++ b/cpu/k60/Makefile.include
@@ -16,7 +16,4 @@ include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
-# add the CPU specific system calls implementations for the linker
-export UNDEF += $(BINDIR)/cpu/vectors.o
-
include $(RIOTMAKE)/arch/cortexm.inc.mk
diff --git a/cpu/k60/vectors.c b/cpu/k60/vectors.c
deleted file mode 100644
index 780272d2ed1924eb33e581464a3e21df695eed95..0000000000000000000000000000000000000000
--- a/cpu/k60/vectors.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * Copyright (C) 2015 Eistec AB
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup cpu_k60
- * @{
- *
- * @file
- *
- * @brief Interrupt vector for K60 MCU.
- *
- * @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
- *
- * @note It is not necessary to modify this file to define custom interrupt
- * service routines. All symbols are defined weak, it is only necessary to
- * define a function with the same name in another file to override the default
- * interrupt handlers.
- */
-
-/**
- * @name Interrupt vector definition
- * @{
- */
-
-#include "vectors_kinetis.h"
-
-/* CPU specific interrupt vector table */
-ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
- isr_dma0,
- isr_dma1,
- isr_dma2,
- isr_dma3,
- isr_dma4,
- isr_dma5,
- isr_dma6,
- isr_dma7,
- isr_dma8,
- isr_dma9,
- isr_dma10,
- isr_dma11,
- isr_dma12,
- isr_dma13,
- isr_dma14,
- isr_dma15,
- isr_dma_error,
- isr_mcm,
- isr_ftfl,
- isr_ftfl_collision,
- isr_pmc,
- isr_llwu,
- isr_wdog_ewm,
- isr_rng,
- isr_i2c0,
- isr_i2c1,
- isr_spi0,
- isr_spi1,
- isr_spi2,
- isr_can0_mb,
- isr_can0_bus_off,
- isr_can0_error,
- isr_can0_tx_warn,
- isr_can0_rx_warn,
- isr_can0_wake_up,
- isr_i2s0_tx,
- isr_i2s0_rx,
- isr_can1_mb,
- isr_can1_bus_off,
- isr_can1_error,
- isr_can1_tx_warn,
- isr_can1_rx_warn,
- isr_can1_wake_up,
- dummy_handler,
- isr_uart0_lon,
- isr_uart0_rx_tx,
- isr_uart0_error,
- isr_uart1_rx_tx,
- isr_uart1_error,
- isr_uart2_rx_tx,
- isr_uart2_error,
- isr_uart3_rx_tx,
- isr_uart3_error,
- isr_uart4_rx_tx,
- isr_uart4_error,
- dummy_handler,
- dummy_handler,
- isr_adc0,
- isr_adc1,
- isr_cmp0,
- isr_cmp1,
- isr_cmp2,
- isr_ftm0,
- isr_ftm1,
- isr_ftm2,
- isr_cmt,
- isr_rtc,
- isr_rtc_seconds,
- isr_pit0,
- isr_pit1,
- isr_pit2,
- isr_pit3,
- isr_pdb0,
- isr_usb0,
- isr_usbdcd,
- isr_enet_1588_timer,
- isr_enet_tx,
- isr_enet_rx,
- isr_enet_error,
- dummy_handler,
- isr_sdhc,
- isr_dac0,
- dummy_handler,
- isr_tsi,
- isr_mcg,
- isr_lptmr0,
- dummy_handler,
- isr_porta,
- isr_portb,
- isr_portc,
- isr_portd,
- isr_porte,
- dummy_handler,
- dummy_handler,
- isr_swi, /* Vector 110 */
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler,
- dummy_handler /* vector 255 */
-};
-
-/** @} */
diff --git a/cpu/k64f/Makefile b/cpu/k64f/Makefile
index 68605a469b55f3f54b540cce34fbedeeec39d472..12ba41f9cf16d9b3e8b1e8fcf75cc0bcfa85f04c 100644
--- a/cpu/k64f/Makefile
+++ b/cpu/k64f/Makefile
@@ -4,7 +4,4 @@ MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
-# (file triggers compiler bug. see #5775)
-SRC_NOLTO += vectors.c
-
include $(RIOTBASE)/Makefile.base
diff --git a/cpu/k64f/Makefile.include b/cpu/k64f/Makefile.include
index e958d7669c5d0506b3dbcc3e62337caba9723d2a..3d0eb9a1cd8e6abb3bf476b844c0c03721d12ec7 100644
--- a/cpu/k64f/Makefile.include
+++ b/cpu/k64f/Makefile.include
@@ -16,7 +16,4 @@ include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
-# add the CPU specific system calls implementations for the linker
-export UNDEF += $(BINDIR)/cpu/vectors.o
-
include $(RIOTMAKE)/arch/cortexm.inc.mk
diff --git a/cpu/k64f/vectors.c b/cpu/k64f/vectors.c
deleted file mode 100644
index 2b084f817e8b80666c12f7234419a2f15e28d33d..0000000000000000000000000000000000000000
--- a/cpu/k64f/vectors.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * Copyright (C) 2014 Freie Universität Berlin
- * Copyright (C) 2015 PHYTEC Messtechnik GmbH
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup cpu_k64f
- * @{
- *
- * @file
- * @brief Interrupt vector definition for K64F MCUs
- *
- * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
- * @author Johann Fischer <j.fischer@phytec.de>
- *
- * @}
- */
-
-#include "vectors_kinetis.h"
-
-/* CPU specific interrupt vector table */
-ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
- isr_dma0, /* DMA channel 0 transfer complete */
- isr_dma1, /* DMA channel 1 transfer complete */
- isr_dma2, /* DMA channel 2 transfer complete */
- isr_dma3, /* DMA channel 3 transfer complete */
- isr_dma4, /* DMA channel 4 transfer complete */
- isr_dma5, /* DMA channel 5 transfer complete */
- isr_dma6, /* DMA channel 6 transfer complete */
- isr_dma7, /* DMA channel 7 transfer complete */
- isr_dma8, /* DMA channel 8 transfer complete */
- isr_dma9, /* DMA channel 9 transfer complete */
- isr_dma10, /* DMA channel 10 transfer complete */
- isr_dma11, /* DMA channel 11 transfer complete */
- isr_dma12, /* DMA channel 12 transfer complete */
- isr_dma13, /* DMA channel 13 transfer complete */
- isr_dma14, /* DMA channel 14 transfer complete */
- isr_dma15, /* DMA channel 15 transfer complete */
- isr_dma_error, /* DMA channel 0 - 15 error */
- isr_mcm, /* MCM normal interrupt */
- isr_ftfl, /* FTFL command complete */
- isr_ftfl_collision, /* FTFL read collision */
- isr_pmc, /* PMC controller low-voltage detect low-voltage warning */
- isr_llwu, /* Low leakage wakeup */
- isr_wdog_ewm, /* Single interrupt vector for WDOG and EWM */
- isr_rng, /* Randon number generator */
- isr_i2c0, /* Inter-integrated circuit 0 */
- isr_i2c1, /* Inter-integrated circuit 1 */
- isr_spi0, /* Serial peripheral Interface 0 */
- isr_spi1, /* Serial peripheral Interface 1 */
- isr_i2s0_tx, /* Integrated interchip sound 0 transmit interrupt */
- isr_i2s0_rx, /* Integrated interchip sound 0 receive interrupt */
- isr_uart0_lon, /* UART0 LON interrupt */
- isr_uart0_rx_tx, /* UART0 receive/transmit interrupt */
- isr_uart0_error, /* UART0 error interrupt */
- isr_uart1_rx_tx, /* UART1 receive/transmit interrupt */
- isr_uart1_error, /* UART1 error interrupt */
- isr_uart2_rx_tx, /* UART2 receive/transmit interrupt */
- isr_uart2_error, /* UART2 error interrupt */
- isr_uart3_rx_tx, /* UART3 receive/transmit interrupt */
- isr_uart3_error, /* UART3 error interrupt */
- isr_adc0, /* Analog-to-digital converter 0 */
- isr_cmp0, /* Comparator 0 */
- isr_cmp1, /* Comparator 1 */
- isr_ftm0, /* FlexTimer module 0 fault overflow and channels interrupt */
- isr_ftm1, /* FlexTimer module 1 fault overflow and channels interrupt */
- isr_ftm2, /* FlexTimer module 2 fault overflow and channels interrupt */
- isr_cmt, /* Carrier modulator transmitter */
- isr_rtc, /* Real time clock */
- isr_rtc_seconds, /* Real time clock seconds */
- isr_pit0, /* Periodic interrupt timer channel 0 */
- isr_pit1, /* Periodic interrupt timer channel 1 */
- isr_pit2, /* Periodic interrupt timer channel 2 */
- isr_pit3, /* Periodic interrupt timer channel 3 */
- isr_pdb0, /* Programmable delay block */
- isr_usb0, /* USB OTG interrupt */
- isr_usbdcd, /* USB charger detect */
- dummy_handler, /* Reserved interrupt */
- isr_dac0, /* Digital-to-analog converter 0 */
- isr_mcg, /* Multipurpose clock generator */
- isr_lptmr0, /* Low power timer interrupt */
- isr_porta, /* Port A pin detect interrupt */
- isr_portb, /* Port B pin detect interrupt */
- isr_portc, /* Port C pin detect interrupt */
- isr_portd, /* Port D pin detect interrupt */
- isr_porte, /* Port E pin detect interrupt */
- isr_swi, /* Software interrupt */
- isr_spi2, /* Serial peripheral Interface 2 */
- isr_uart4_rx_tx, /* UART4 receive/transmit interrupt */
- isr_uart4_error, /* UART4 error interrupt */
- isr_uart5_rx_tx, /* UART5 receive/transmit interrupt */
- isr_uart5_error, /* UART5 error interrupt */
- isr_cmp2, /* Comparator 2 */
- isr_ftm3, /* FlexTimer module 3 fault overflow and channels interrupt */
- isr_dac1, /* Digital-to-analog converter 1 */
- isr_adc1, /* Analog-to-digital converter 1 */
- isr_i2c2, /* Inter-integrated circuit 2 */
- isr_can0_mb, /* CAN0 OR'd message buffers interrupt */
- isr_can0_bus_off, /* CAN0 bus off interrupt */
- isr_can0_error, /* CAN0 error interrupt */
- isr_can0_tx_warn, /* CAN0 tx warning interrupt */
- isr_can0_rx_warn, /* CAN0 rx warning interrupt */
- isr_can0_wake_up, /* CAN0 wake up interrupt */
- isr_sdhc, /* SDHC interrupt */
- isr_enet_1588_timer, /* Ethernet MAC IEEE 1588 Timer interrupt */
- isr_enet_tx, /* Ethernet MAC transmit interrupt */
- isr_enet_rx, /* Ethernet MAC receive interrupt */
- isr_enet_error, /* Ethernet MAC error interrupt */
- dummy_handler, /* reserved 102 */
- dummy_handler, /* reserved 103 */
- dummy_handler, /* reserved 104 */
- dummy_handler, /* reserved 105 */
- dummy_handler, /* reserved 106 */
- dummy_handler, /* reserved 107 */
- dummy_handler, /* reserved 108 */
- dummy_handler, /* reserved 109 */
- dummy_handler, /* reserved 110 */
- dummy_handler, /* reserved 111 */
- dummy_handler, /* reserved 112 */
- dummy_handler, /* reserved 113 */
- dummy_handler, /* reserved 114 */
- dummy_handler, /* reserved 115 */
- dummy_handler, /* reserved 116 */
- dummy_handler, /* reserved 117 */
- dummy_handler, /* reserved 118 */
- dummy_handler, /* reserved 119 */
- dummy_handler, /* reserved 120 */
- dummy_handler, /* reserved 121 */
- dummy_handler, /* reserved 122 */
- dummy_handler, /* reserved 123 */
- dummy_handler, /* reserved 124 */
- dummy_handler, /* reserved 125 */
- dummy_handler, /* reserved 126 */
- dummy_handler, /* reserved 127 */
- dummy_handler, /* reserved 128 */
- dummy_handler, /* reserved 129 */
- dummy_handler, /* reserved 130 */
- dummy_handler, /* reserved 131 */
- dummy_handler, /* reserved 132 */
- dummy_handler, /* reserved 133 */
- dummy_handler, /* reserved 134 */
- dummy_handler, /* reserved 135 */
- dummy_handler, /* reserved 136 */
- dummy_handler, /* reserved 137 */
- dummy_handler, /* reserved 138 */
- dummy_handler, /* reserved 139 */
- dummy_handler, /* reserved 140 */
- dummy_handler, /* reserved 141 */
- dummy_handler, /* reserved 142 */
- dummy_handler, /* reserved 143 */
- dummy_handler, /* reserved 144 */
- dummy_handler, /* reserved 145 */
- dummy_handler, /* reserved 146 */
- dummy_handler, /* reserved 147 */
- dummy_handler, /* reserved 148 */
- dummy_handler, /* reserved 149 */
- dummy_handler, /* reserved 150 */
- dummy_handler, /* reserved 151 */
- dummy_handler, /* reserved 152 */
- dummy_handler, /* reserved 153 */
- dummy_handler, /* reserved 154 */
- dummy_handler, /* reserved 155 */
- dummy_handler, /* reserved 156 */
- dummy_handler, /* reserved 157 */
- dummy_handler, /* reserved 158 */
- dummy_handler, /* reserved 159 */
- dummy_handler, /* reserved 160 */
- dummy_handler, /* reserved 161 */
- dummy_handler, /* reserved 162 */
- dummy_handler, /* reserved 163 */
- dummy_handler, /* reserved 164 */
- dummy_handler, /* reserved 165 */
- dummy_handler, /* reserved 166 */
- dummy_handler, /* reserved 167 */
- dummy_handler, /* reserved 168 */
- dummy_handler, /* reserved 169 */
- dummy_handler, /* reserved 170 */
- dummy_handler, /* reserved 171 */
- dummy_handler, /* reserved 172 */
- dummy_handler, /* reserved 173 */
- dummy_handler, /* reserved 174 */
- dummy_handler, /* reserved 175 */
- dummy_handler, /* reserved 176 */
- dummy_handler, /* reserved 177 */
- dummy_handler, /* reserved 178 */
- dummy_handler, /* reserved 179 */
- dummy_handler, /* reserved 180 */
- dummy_handler, /* reserved 181 */
- dummy_handler, /* reserved 182 */
- dummy_handler, /* reserved 183 */
- dummy_handler, /* reserved 184 */
- dummy_handler, /* reserved 185 */
- dummy_handler, /* reserved 186 */
- dummy_handler, /* reserved 187 */
- dummy_handler, /* reserved 188 */
- dummy_handler, /* reserved 189 */
- dummy_handler, /* reserved 190 */
- dummy_handler, /* reserved 191 */
- dummy_handler, /* reserved 192 */
- dummy_handler, /* reserved 193 */
- dummy_handler, /* reserved 194 */
- dummy_handler, /* reserved 195 */
- dummy_handler, /* reserved 196 */
- dummy_handler, /* reserved 197 */
- dummy_handler, /* reserved 198 */
- dummy_handler, /* reserved 199 */
- dummy_handler, /* reserved 200 */
- dummy_handler, /* reserved 201 */
- dummy_handler, /* reserved 202 */
- dummy_handler, /* reserved 203 */
- dummy_handler, /* reserved 204 */
- dummy_handler, /* reserved 205 */
- dummy_handler, /* reserved 206 */
- dummy_handler, /* reserved 207 */
- dummy_handler, /* reserved 208 */
- dummy_handler, /* reserved 209 */
- dummy_handler, /* reserved 210 */
- dummy_handler, /* reserved 211 */
- dummy_handler, /* reserved 212 */
- dummy_handler, /* reserved 213 */
- dummy_handler, /* reserved 214 */
- dummy_handler, /* reserved 215 */
- dummy_handler, /* reserved 216 */
- dummy_handler, /* reserved 217 */
- dummy_handler, /* reserved 218 */
- dummy_handler, /* reserved 219 */
- dummy_handler, /* reserved 220 */
- dummy_handler, /* reserved 221 */
- dummy_handler, /* reserved 222 */
- dummy_handler, /* reserved 223 */
- dummy_handler, /* reserved 224 */
- dummy_handler, /* reserved 225 */
- dummy_handler, /* reserved 226 */
- dummy_handler, /* reserved 227 */
- dummy_handler, /* reserved 228 */
- dummy_handler, /* reserved 229 */
- dummy_handler, /* reserved 230 */
- dummy_handler, /* reserved 231 */
- dummy_handler, /* reserved 232 */
- dummy_handler, /* reserved 233 */
- dummy_handler, /* reserved 234 */
- dummy_handler, /* reserved 235 */
- dummy_handler, /* reserved 236 */
- dummy_handler, /* reserved 237 */
- dummy_handler, /* reserved 238 */
- dummy_handler, /* reserved 239 */
- dummy_handler, /* reserved 240 */
- dummy_handler, /* reserved 241 */
- dummy_handler, /* reserved 242 */
- dummy_handler, /* reserved 243 */
- dummy_handler, /* reserved 244 */
- dummy_handler, /* reserved 245 */
- dummy_handler, /* reserved 246 */
- dummy_handler, /* reserved 247 */
- dummy_handler, /* reserved 248 */
- dummy_handler, /* reserved 249 */
- dummy_handler, /* reserved 250 */
- dummy_handler, /* reserved 251 */
- dummy_handler, /* reserved 252 */
- dummy_handler, /* reserved 253 */
- dummy_handler, /* reserved 254 */
- dummy_handler, /* reserved 255 */
-};
diff --git a/cpu/kinetis_common/Makefile b/cpu/kinetis_common/Makefile
index 503d148876c4dc73cd6b1d571081bef6a51251b9..8b1b43dea4d66b3da111da96f7e80c3c0615fcb5 100644
--- a/cpu/kinetis_common/Makefile
+++ b/cpu/kinetis_common/Makefile
@@ -3,4 +3,7 @@ MODULE = kinetis_common
DIRS += periph
+# (file triggers compiler bug. see #5775)
+SRC_NOLTO += vectors.c
+
include $(RIOTBASE)/Makefile.base
diff --git a/cpu/kinetis_common/Makefile.include b/cpu/kinetis_common/Makefile.include
index bda15252441829a3bb6922f006c2d739762e6881..bce1c7bf9667d1e78e23a34fbcec0955b1ab842f 100644
--- a/cpu/kinetis_common/Makefile.include
+++ b/cpu/kinetis_common/Makefile.include
@@ -10,6 +10,9 @@ export LINKER_SCRIPT ?= $(LD_$(shell echo $(CPU_MODEL) | tr a-z A-Z))
# add the CPU specific code for the linker
export UNDEF += $(BINDIR)/kinetis_common/fcfield.o
+# add the CPU specific interrupt vector table definition for the linker
+export UNDEF += $(BINDIR)/kinetis_common/vectors.o
+
# include kinetis common periph drivers
export USEMODULE += kinetis_common_periph
export USEMODULE += periph_common
diff --git a/cpu/kinetis_common/include/vectors_kinetis.h b/cpu/kinetis_common/include/vectors_kinetis.h
index 3285c0e6b9b8cb22d1fadffe916cb86682d2f0c3..26068d600bd7e0aae6e8a331c4848bed045f0a22 100644
--- a/cpu/kinetis_common/include/vectors_kinetis.h
+++ b/cpu/kinetis_common/include/vectors_kinetis.h
@@ -38,104 +38,131 @@ extern uint32_t _estack;
*/
void dummy_handler(void);
-/* Cortex-M specific interrupt vectors */
-void isr_svc(void); /**< Supervisor call */
-void isr_pendsv(void); /**< Pending SVC */
-void isr_systick(void); /**< System tick interrupt */
/* Kinetis specific interrupt vectors */
void isr_adc0(void); /**< ADC0 interrupt handler */
void isr_adc1(void); /**< ADC1 interrupt handler */
+void isr_adc2(void); /**< ADC2 interrupt handler */
void isr_can0_bus_off(void); /**< CAN0 bus off interrupt handler */
void isr_can0_error(void); /**< CAN0 error interrupt handler */
-void isr_can0_mb(void); /**< CAN0 message buffer interrupt handler */
-void isr_can0_rx_warn(void); /**< CAN0 receive warning interrupt handler */
-void isr_can0_tx_warn(void); /**< CAN0 transmit warning interrupt handler */
+void isr_can0_ored_message_buffer(void); /**< CAN0 OR'd message buffers interrupt handler */
+void isr_can0_rx_warning(void); /**< CAN0 Rx warning interrupt handler */
+void isr_can0_tx_warning(void); /**< CAN0 Tx warning interrupt handler */
void isr_can0_wake_up(void); /**< CAN0 wake up interrupt handler */
void isr_can1_bus_off(void); /**< CAN1 bus off interrupt handler */
void isr_can1_error(void); /**< CAN1 error interrupt handler */
-void isr_can1_mb(void); /**< CAN1 message buffer interrupt handler */
-void isr_can1_rx_warn(void); /**< CAN1 receive warning interrupt handler */
-void isr_can1_tx_warn(void); /**< CAN1 transmit warning interrupt handler */
+void isr_can1_ored_message_buffer(void); /**< CAN1 OR'd message buffers interrupt handler */
+void isr_can1_rx_warning(void); /**< CAN1 Rx warning interrupt handler */
+void isr_can1_tx_warning(void); /**< CAN1 Tx warning interrupt handler */
void isr_can1_wake_up(void); /**< CAN1 wake up interrupt handler */
void isr_cmp0(void); /**< CMP0 interrupt handler */
void isr_cmp1(void); /**< CMP1 interrupt handler */
void isr_cmp2(void); /**< CMP2 interrupt handler */
+void isr_cmp3(void); /**< CMP3 interrupt handler */
void isr_cmt(void); /**< CMT interrupt handler */
void isr_dac0(void); /**< DAC0 interrupt handler */
void isr_dac1(void); /**< DAC1 interrupt handler */
-void isr_dma0(void); /**< DMA channel 0 interrupt handler */
-void isr_dma1(void); /**< DMA channel 1 interrupt handler */
-void isr_dma2(void); /**< DMA channel 2 interrupt handler */
-void isr_dma3(void); /**< DMA channel 3 interrupt handler */
-void isr_dma4(void); /**< DMA channel 4 interrupt handler */
-void isr_dma5(void); /**< DMA channel 5 interrupt handler */
-void isr_dma6(void); /**< DMA channel 6 interrupt handler */
-void isr_dma7(void); /**< DMA channel 7 interrupt handler */
-void isr_dma8(void); /**< DMA channel 8 interrupt handler */
-void isr_dma9(void); /**< DMA channel 9 interrupt handler */
-void isr_dma10(void); /**< DMA channel 10 interrupt handler */
-void isr_dma11(void); /**< DMA channel 11 interrupt handler */
-void isr_dma12(void); /**< DMA channel 12 interrupt handler */
-void isr_dma13(void); /**< DMA channel 13 interrupt handler */
-void isr_dma14(void); /**< DMA channel 14 interrupt handler */
-void isr_dma15(void); /**< DMA channel 15 interrupt handler */
-void isr_dma_error(void); /**< DMA error interrupt handler */
-void isr_enet_1588_timer(void); /**< ENET 1588 timer interrupt handler */
-void isr_enet_error(void); /**< ENET error interrupt handler */
-void isr_enet_rx(void); /**< ENET receive interrupt handler */
-void isr_enet_tx(void); /**< ENET transmit interrupt handler */
+void isr_dma0(void); /**< DMA channel 0 transfer complete interrupt handler */
+void isr_dma1(void); /**< DMA channel 1 transfer complete interrupt handler */
+void isr_dma2(void); /**< DMA channel 2 transfer complete interrupt handler */
+void isr_dma3(void); /**< DMA channel 3 transfer complete interrupt handler */
+void isr_dma4(void); /**< DMA channel 4 transfer complete interrupt handler */
+void isr_dma5(void); /**< DMA channel 5 transfer complete interrupt handler */
+void isr_dma6(void); /**< DMA channel 6 transfer complete interrupt handler */
+void isr_dma7(void); /**< DMA channel 7 transfer complete interrupt handler */
+void isr_dma8(void); /**< DMA channel 8 transfer complete interrupt handler */
+void isr_dma9(void); /**< DMA channel 9 transfer complete interrupt handler */
+void isr_dma10(void); /**< DMA channel 10 transfer complete interrupt handler */
+void isr_dma11(void); /**< DMA channel 11 transfer complete interrupt handler */
+void isr_dma12(void); /**< DMA channel 12 transfer complete interrupt handler */
+void isr_dma13(void); /**< DMA channel 13 transfer complete interrupt handler */
+void isr_dma14(void); /**< DMA channel 14 transfer complete interrupt handler */
+void isr_dma15(void); /**< DMA channel 15 transfer complete interrupt handler */
+void isr_dma0_dma16(void); /**< DMA channel 0, 16 transfer complete interrupt handler */
+void isr_dma1_dma17(void); /**< DMA channel 1, 17 transfer complete interrupt handler */
+void isr_dma2_dma18(void); /**< DMA channel 2, 18 transfer complete interrupt handler */
+void isr_dma3_dma19(void); /**< DMA channel 3, 19 transfer complete interrupt handler */
+void isr_dma4_dma20(void); /**< DMA channel 4, 20 transfer complete interrupt handler */
+void isr_dma5_dma21(void); /**< DMA channel 5, 21 transfer complete interrupt handler */
+void isr_dma6_dma22(void); /**< DMA channel 6, 22 transfer complete interrupt handler */
+void isr_dma7_dma23(void); /**< DMA channel 7, 23 transfer complete interrupt handler */
+void isr_dma8_dma24(void); /**< DMA channel 8, 24 transfer complete interrupt handler */
+void isr_dma9_dma25(void); /**< DMA channel 9, 25 transfer complete interrupt handler */
+void isr_dma10_dma26(void); /**< DMA channel 10, 26 transfer complete interrupt handler */
+void isr_dma11_dma27(void); /**< DMA channel 11, 27 transfer complete interrupt handler */
+void isr_dma12_dma28(void); /**< DMA channel 12, 28 transfer complete interrupt handler */
+void isr_dma13_dma29(void); /**< DMA channel 13, 29 transfer complete interrupt handler */
+void isr_dma14_dma30(void); /**< DMA channel 14, 30 transfer complete interrupt handler */
+void isr_dma15_dma31(void); /**< DMA channel 15, 31 transfer complete interrupt handler */
+void isr_dma_error(void); /**< DMA Error interrupt handler */
+void isr_enet_1588_timer(void); /**< Ethernet MAC IEEE 1588 timer interrupt handler */
+void isr_enet_error(void); /**< Ethernet MAC error and miscelaneous interrupt handler */
+void isr_enet_receive(void); /**< Ethernet MAC receive interrupt handler */
+void isr_enet_transmit(void); /**< Ethernet MAC transmit interrupt handler */
+void isr_ftfa(void); /**< FTFA Command complete interrupt handler */
+void isr_ftfa_collision(void); /**< FTFA read collision interrupt handler */
+void isr_ftfe(void); /**< FTFE Command complete interrupt handler */
+void isr_ftfe_collision(void); /**< FTFA read collision interrupt handler */
void isr_ftfl(void); /**< FTFL command complete interrupt handler */
-void isr_ftfl_collision(void); /**< FTFL collision interrupt handler */
-void isr_ftm0(void); /**< FTM0 interrupt handler */
-void isr_ftm1(void); /**< FTM1 interrupt handler */
-void isr_ftm2(void); /**< FTM2 interrupt handler */
-void isr_ftm3(void); /**< FTM3 interrupt handler */
+void isr_ftfl_collision(void); /**< FTFL read collision interrupt handler */
+void isr_ftm0(void); /**< FTM0 fault, overflow and channels interrupt handler */
+void isr_ftm1(void); /**< FTM1 fault, overflow and channels interrupt handler */
+void isr_ftm2(void); /**< FTM2 fault, overflow and channels interrupt handler */
+void isr_ftm3(void); /**< FTM3 fault, overflow and channels interrupt handler */
void isr_i2c0(void); /**< I2C0 interrupt handler */
void isr_i2c1(void); /**< I2C1 interrupt handler */
void isr_i2c2(void); /**< I2C2 interrupt handler */
+void isr_i2c3(void); /**< I2C3 interrupt handler */
void isr_i2s0_rx(void); /**< I2S0 receive interrupt handler */
void isr_i2s0_tx(void); /**< I2S0 transmit interrupt handler */
-void isr_llwu(void); /**< LLWU interrupt handler */
-void isr_lpuart0(void); /**< LPUART0 interrupt handler */
-void isr_lptmr0(void); /**< LPTMR0 interrupt handler */
+void isr_llwu(void); /**< Low leakage wakeup interrupt handler */
+void isr_lptmr0(void); /**< Low power timer interrupt handler */
+void isr_lpuart0(void); /**< LPUART0 status/error interrupt handler */
+void isr_lpuart1(void); /**< LPUART1 status/error interrupt handler */
+void isr_lpuart2(void); /**< LPUART2 status/error interrupt handler */
+void isr_lpuart3(void); /**< LPUART3 status/error interrupt handler */
+void isr_lpuart4(void); /**< LPUART4 status/error interrupt handler */
+void isr_lpuart5(void); /**< LPUART5 status/error interrupt handler */
+void isr_lvd_lvw(void); /**< PMC controller low-voltage detect, low-voltage warning interrupt handler */
void isr_mcg(void); /**< MCG interrupt handler */
-void isr_mcm(void); /**< MCM interrupt handler */
+void isr_mcm(void); /**< MCM normal interrupt handler */
void isr_pdb0(void); /**< PDB0 interrupt handler */
-void isr_pit0(void); /**< PIT channel 0 interrupt handler */
-void isr_pit1(void); /**< PIT channel 1 interrupt handler */
-void isr_pit2(void); /**< PIT channel 2 interrupt handler */
-void isr_pit3(void); /**< PIT channel 3 interrupt handler */
-void isr_pmc(void); /**< PMC interrupt handler */
-void isr_porta(void); /**< PORTA interrupt handler */
-void isr_portb(void); /**< PORTB interrupt handler */
-void isr_portc(void); /**< PORTC interrupt handler */
-void isr_portd(void); /**< PORTD interrupt handler */
-void isr_porte(void); /**< PORTE interrupt handler */
-void isr_rng(void); /**< Random number generator interrupt handler */
-void isr_rtc(void); /**< RTC alarm interrupt handler */
+void isr_pit0(void); /**< PIT timer channel 0 interrupt handler */
+void isr_pit1(void); /**< PIT timer channel 1 interrupt handler */
+void isr_pit2(void); /**< PIT timer channel 2 interrupt handler */
+void isr_pit3(void); /**< PIT timer channel 3 interrupt handler */
+void isr_porta(void); /**< Port A pin detect interrupt handler */
+void isr_portb(void); /**< Port B pin detect interrupt handler */
+void isr_portc(void); /**< Port C pin detect interrupt handler */
+void isr_portd(void); /**< Port D pin detect interrupt handler */
+void isr_porte(void); /**< Port E pin detect interrupt handler */
+void isr_rng(void); /**< RNG interrupt handler */
+void isr_rtc(void); /**< RTC interrupt handler */
void isr_rtc_seconds(void); /**< RTC seconds interrupt handler */
void isr_sdhc(void); /**< SDHC interrupt handler */
void isr_spi0(void); /**< SPI0 interrupt handler */
void isr_spi1(void); /**< SPI1 interrupt handler */
void isr_spi2(void); /**< SPI2 interrupt handler */
void isr_swi(void); /**< Software interrupt handler */
-void isr_tsi(void); /**< TSI interrupt handler */
-void isr_uart0_lon(void); /**< UART0 LON sources interrupt handler */
-void isr_uart0_error(void); /**< UART0 error interrupt handler */
+void isr_tpm0(void); /**< TPM0 interrupt handler */
+void isr_tpm1(void); /**< TPM1 interrupt handler */
+void isr_tpm2(void); /**< TPM2 interrupt handler */
+void isr_tsi0(void); /**< TSI0 interrupt handler */
+void isr_uart0_err(void); /**< UART0 error interrupt handler */
+void isr_uart0_lon(void); /**< UART0 LON interrupt handler */
void isr_uart0_rx_tx(void); /**< UART0 receive/transmit interrupt handler */
-void isr_uart1_error(void); /**< UART1 error interrupt handler */
+void isr_uart1_err(void); /**< UART1 error interrupt handler */
void isr_uart1_rx_tx(void); /**< UART1 receive/transmit interrupt handler */
-void isr_uart2_error(void); /**< UART2 error interrupt handler */
+void isr_uart2_err(void); /**< UART2 error interrupt handler */
void isr_uart2_rx_tx(void); /**< UART2 receive/transmit interrupt handler */
-void isr_uart3_error(void); /**< UART3 error interrupt handler */
+void isr_uart3_err(void); /**< UART3 error interrupt handler */
void isr_uart3_rx_tx(void); /**< UART3 receive/transmit interrupt handler */
-void isr_uart4_error(void); /**< UART4 error interrupt handler */
+void isr_uart4_err(void); /**< UART4 error interrupt handler */
void isr_uart4_rx_tx(void); /**< UART4 receive/transmit interrupt handler */
-void isr_uart5_error(void); /**< UART5 error interrupt handler */
+void isr_uart5_err(void); /**< UART5 error interrupt handler */
void isr_uart5_rx_tx(void); /**< UART5 receive/transmit interrupt handler */
-void isr_usb0(void); /**< USB OTG interrupt handler */
-void isr_usbdcd(void); /**< USB charger detection interrupt handler */
-void isr_wdog_ewm(void); /**< WDOG and EWM interrupt handler */
+void isr_usb0(void); /**< USB0 interrupt handler */
+void isr_usbdcd(void); /**< USB charger detect interrupt handler */
+void isr_wdog_ewm(void); /**< WDOG interrupt handler */
#ifdef __cplusplus
} /* extern "C" */
diff --git a/cpu/kinetis_common/isr_kinetis.c b/cpu/kinetis_common/isr_kinetis.c
index b73621b7db761dad5010313e82ded4778b1b7bed..0ce5c0fbafee68f851ebc063ea76e5f53385d4cb 100644
--- a/cpu/kinetis_common/isr_kinetis.c
+++ b/cpu/kinetis_common/isr_kinetis.c
@@ -46,28 +46,26 @@ void dummy_handler(void)
dummy_handler_default();
}
-/* Cortex-M specific interrupt vectors */
-WEAK_DEFAULT void isr_svc(void);
-WEAK_DEFAULT void isr_pendsv(void);
-WEAK_DEFAULT void isr_systick(void);
-/* Kinetis specific interrupt vector */
+/* Kinetis specific interrupt service routines */
WEAK_DEFAULT void isr_adc0(void);
WEAK_DEFAULT void isr_adc1(void);
+WEAK_DEFAULT void isr_adc2(void);
WEAK_DEFAULT void isr_can0_bus_off(void);
WEAK_DEFAULT void isr_can0_error(void);
-WEAK_DEFAULT void isr_can0_mb(void);
-WEAK_DEFAULT void isr_can0_rx_warn(void);
-WEAK_DEFAULT void isr_can0_tx_warn(void);
+WEAK_DEFAULT void isr_can0_ored_message_buffer(void);
+WEAK_DEFAULT void isr_can0_rx_warning(void);
+WEAK_DEFAULT void isr_can0_tx_warning(void);
WEAK_DEFAULT void isr_can0_wake_up(void);
WEAK_DEFAULT void isr_can1_bus_off(void);
WEAK_DEFAULT void isr_can1_error(void);
-WEAK_DEFAULT void isr_can1_mb(void);
-WEAK_DEFAULT void isr_can1_rx_warn(void);
-WEAK_DEFAULT void isr_can1_tx_warn(void);
+WEAK_DEFAULT void isr_can1_ored_message_buffer(void);
+WEAK_DEFAULT void isr_can1_rx_warning(void);
+WEAK_DEFAULT void isr_can1_tx_warning(void);
WEAK_DEFAULT void isr_can1_wake_up(void);
WEAK_DEFAULT void isr_cmp0(void);
WEAK_DEFAULT void isr_cmp1(void);
WEAK_DEFAULT void isr_cmp2(void);
+WEAK_DEFAULT void isr_cmp3(void);
WEAK_DEFAULT void isr_cmt(void);
WEAK_DEFAULT void isr_dac0(void);
WEAK_DEFAULT void isr_dac1(void);
@@ -87,11 +85,31 @@ WEAK_DEFAULT void isr_dma12(void);
WEAK_DEFAULT void isr_dma13(void);
WEAK_DEFAULT void isr_dma14(void);
WEAK_DEFAULT void isr_dma15(void);
+WEAK_DEFAULT void isr_dma0_dma16(void);
+WEAK_DEFAULT void isr_dma1_dma17(void);
+WEAK_DEFAULT void isr_dma2_dma18(void);
+WEAK_DEFAULT void isr_dma3_dma19(void);
+WEAK_DEFAULT void isr_dma4_dma20(void);
+WEAK_DEFAULT void isr_dma5_dma21(void);
+WEAK_DEFAULT void isr_dma6_dma22(void);
+WEAK_DEFAULT void isr_dma7_dma23(void);
+WEAK_DEFAULT void isr_dma8_dma24(void);
+WEAK_DEFAULT void isr_dma9_dma25(void);
+WEAK_DEFAULT void isr_dma10_dma26(void);
+WEAK_DEFAULT void isr_dma11_dma27(void);
+WEAK_DEFAULT void isr_dma12_dma28(void);
+WEAK_DEFAULT void isr_dma13_dma29(void);
+WEAK_DEFAULT void isr_dma14_dma30(void);
+WEAK_DEFAULT void isr_dma15_dma31(void);
WEAK_DEFAULT void isr_dma_error(void);
WEAK_DEFAULT void isr_enet_1588_timer(void);
WEAK_DEFAULT void isr_enet_error(void);
-WEAK_DEFAULT void isr_enet_rx(void);
-WEAK_DEFAULT void isr_enet_tx(void);
+WEAK_DEFAULT void isr_enet_receive(void);
+WEAK_DEFAULT void isr_enet_transmit(void);
+WEAK_DEFAULT void isr_ftfa(void);
+WEAK_DEFAULT void isr_ftfa_collision(void);
+WEAK_DEFAULT void isr_ftfe(void);
+WEAK_DEFAULT void isr_ftfe_collision(void);
WEAK_DEFAULT void isr_ftfl(void);
WEAK_DEFAULT void isr_ftfl_collision(void);
WEAK_DEFAULT void isr_ftm0(void);
@@ -101,11 +119,18 @@ WEAK_DEFAULT void isr_ftm3(void);
WEAK_DEFAULT void isr_i2c0(void);
WEAK_DEFAULT void isr_i2c1(void);
WEAK_DEFAULT void isr_i2c2(void);
+WEAK_DEFAULT void isr_i2c3(void);
WEAK_DEFAULT void isr_i2s0_rx(void);
WEAK_DEFAULT void isr_i2s0_tx(void);
WEAK_DEFAULT void isr_llwu(void);
WEAK_DEFAULT void isr_lptmr0(void);
WEAK_DEFAULT void isr_lpuart0(void);
+WEAK_DEFAULT void isr_lpuart1(void);
+WEAK_DEFAULT void isr_lpuart2(void);
+WEAK_DEFAULT void isr_lpuart3(void);
+WEAK_DEFAULT void isr_lpuart4(void);
+WEAK_DEFAULT void isr_lpuart5(void);
+WEAK_DEFAULT void isr_lvd_lvw(void);
WEAK_DEFAULT void isr_mcg(void);
WEAK_DEFAULT void isr_mcm(void);
WEAK_DEFAULT void isr_pdb0(void);
@@ -113,36 +138,40 @@ WEAK_DEFAULT void isr_pit0(void);
WEAK_DEFAULT void isr_pit1(void);
WEAK_DEFAULT void isr_pit2(void);
WEAK_DEFAULT void isr_pit3(void);
-WEAK_DEFAULT void isr_pmc(void);
WEAK_DEFAULT void isr_porta(void);
WEAK_DEFAULT void isr_portb(void);
WEAK_DEFAULT void isr_portc(void);
WEAK_DEFAULT void isr_portd(void);
WEAK_DEFAULT void isr_porte(void);
WEAK_DEFAULT void isr_rng(void);
-WEAK_DEFAULT void isr_rtc_seconds(void);
WEAK_DEFAULT void isr_rtc(void);
+WEAK_DEFAULT void isr_rtc_seconds(void);
WEAK_DEFAULT void isr_sdhc(void);
WEAK_DEFAULT void isr_spi0(void);
WEAK_DEFAULT void isr_spi1(void);
WEAK_DEFAULT void isr_spi2(void);
WEAK_DEFAULT void isr_swi(void);
-WEAK_DEFAULT void isr_tsi(void);
-WEAK_DEFAULT void isr_uart0_error(void);
+WEAK_DEFAULT void isr_tpm0(void);
+WEAK_DEFAULT void isr_tpm1(void);
+WEAK_DEFAULT void isr_tpm2(void);
+WEAK_DEFAULT void isr_tsi0(void);
+WEAK_DEFAULT void isr_uart0_err(void);
WEAK_DEFAULT void isr_uart0_lon(void);
WEAK_DEFAULT void isr_uart0_rx_tx(void);
-WEAK_DEFAULT void isr_uart1_error(void);
+WEAK_DEFAULT void isr_uart1_err(void);
WEAK_DEFAULT void isr_uart1_rx_tx(void);
-WEAK_DEFAULT void isr_uart2_error(void);
+WEAK_DEFAULT void isr_uart2_err(void);
WEAK_DEFAULT void isr_uart2_rx_tx(void);
-WEAK_DEFAULT void isr_uart3_error(void);
+WEAK_DEFAULT void isr_uart3_err(void);
WEAK_DEFAULT void isr_uart3_rx_tx(void);
-WEAK_DEFAULT void isr_uart4_error(void);
+WEAK_DEFAULT void isr_uart4_err(void);
WEAK_DEFAULT void isr_uart4_rx_tx(void);
-WEAK_DEFAULT void isr_uart5_error(void);
+WEAK_DEFAULT void isr_uart5_err(void);
WEAK_DEFAULT void isr_uart5_rx_tx(void);
WEAK_DEFAULT void isr_usb0(void);
WEAK_DEFAULT void isr_usbdcd(void);
+WEAK_DEFAULT void isr_usbhs(void);
+WEAK_DEFAULT void isr_usbhsdcd(void);
WEAK_DEFAULT void isr_wdog_ewm(void);
/* Empty interrupt vector padding to ensure that all sanity checks in the
diff --git a/cpu/kinetis_common/vectors.c b/cpu/kinetis_common/vectors.c
new file mode 100644
index 0000000000000000000000000000000000000000..6ef29428521f4c8dc0d124636c463e681a149388
--- /dev/null
+++ b/cpu/kinetis_common/vectors.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2017 Eistec AB
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup cpu_kinetis
+ * @{
+ *
+ * @file
+ *
+ * @brief Interrupt vector for Kinetis MCUs
+ *
+ * @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
+ *
+ * @note It is not necessary to modify this file to define custom interrupt
+ * service routines. All symbols are defined weak, it is only necessary to
+ * define a function with the same name in another file to override the default
+ * interrupt handlers.
+ */
+
+/**
+ * @name Interrupt vector definition
+ * @{
+ */
+
+/* This is needed to homogenize the symbolic IRQ names across different versions
+ * of the vendor headers. These must be defined before any vendor headers are
+ * included */
+#define FTFA_IRQn FTF_IRQn
+#define FTFA_Collision_IRQn Read_Collision_IRQn
+#define FTFE_IRQn FTF_IRQn
+#define FTFE_Collision_IRQn Read_Collision_IRQn
+#define FTFL_IRQn FTF_IRQn
+#define FTFL_Collision_IRQn Read_Collision_IRQn
+#define PMC_IRQn LVD_LVW_IRQn
+#define Watchdog_IRQn WDOG_EWM_IRQn
+
+#include "vectors_kinetis.h"
+
+/* CPU specific interrupt vector table */
+ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
+#ifdef DMA0
+/* Devices with >16 DMA channels combine two channels per IRQ number */
+#if defined(DMA_INT_INT16_MASK)
+ [DMA0_DMA16_IRQn ] = isr_dma0_dma16, /* DMA Channel 0, 16 Transfer Complete */
+#elif defined(DMA_INT_INT0_MASK)
+ [DMA0_IRQn ] = isr_dma0, /* DMA Channel 0 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT17_MASK)
+ [DMA1_DMA17_IRQn ] = isr_dma1_dma17, /* DMA Channel 1, 17 Transfer Complete */
+#elif defined(DMA_INT_INT1_MASK)
+ [DMA1_IRQn ] = isr_dma1, /* DMA Channel 1 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT18_MASK)
+ [DMA2_DMA18_IRQn ] = isr_dma2_dma18, /* DMA Channel 2, 18 Transfer Complete */
+#elif defined(DMA_INT_INT2_MASK)
+ [DMA2_IRQn ] = isr_dma2, /* DMA Channel 2 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT19_MASK)
+ [DMA3_DMA19_IRQn ] = isr_dma3_dma19, /* DMA Channel 3, 19 Transfer Complete */
+#elif defined(DMA_INT_INT3_MASK)
+ [DMA3_IRQn ] = isr_dma3, /* DMA Channel 3 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT20_MASK)
+ [DMA4_DMA20_IRQn ] = isr_dma4_dma20, /* DMA Channel 4, 20 Transfer Complete */
+#elif defined(DMA_INT_INT4_MASK)
+ [DMA4_IRQn ] = isr_dma4, /* DMA Channel 4 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT21_MASK)
+ [DMA5_DMA21_IRQn ] = isr_dma5_dma21, /* DMA Channel 5, 21 Transfer Complete */
+#elif defined(DMA_INT_INT5_MASK)
+ [DMA5_IRQn ] = isr_dma5, /* DMA Channel 5 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT22_MASK)
+ [DMA6_DMA22_IRQn ] = isr_dma6_dma22, /* DMA Channel 6, 22 Transfer Complete */
+#elif defined(DMA_INT_INT6_MASK)
+ [DMA6_IRQn ] = isr_dma6, /* DMA Channel 6 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT23_MASK)
+ [DMA7_DMA23_IRQn ] = isr_dma7_dma23, /* DMA Channel 7, 23 Transfer Complete */
+#elif defined(DMA_INT_INT7_MASK)
+ [DMA7_IRQn ] = isr_dma7, /* DMA Channel 7 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT24_MASK)
+ [DMA8_DMA24_IRQn ] = isr_dma8_dma24, /* DMA Channel 8, 24 Transfer Complete */
+#elif defined(DMA_INT_INT8_MASK)
+ [DMA8_IRQn ] = isr_dma8, /* DMA Channel 8 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT25_MASK)
+ [DMA9_DMA25_IRQn ] = isr_dma9_dma25, /* DMA Channel 9, 25 Transfer Complete */
+#elif defined(DMA_INT_INT9_MASK)
+ [DMA9_IRQn ] = isr_dma9, /* DMA Channel 9 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT26_MASK)
+ [DMA10_DMA26_IRQn] = isr_dma10_dma26, /* DMA Channel 10, 26 Transfer Complete */
+#elif defined(DMA_INT_INT10_MASK)
+ [DMA10_IRQn ] = isr_dma10, /* DMA Channel 10 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT27_MASK)
+ [DMA11_DMA27_IRQn] = isr_dma11_dma27, /* DMA Channel 11, 27 Transfer Complete */
+#elif defined(DMA_INT_INT11_MASK)
+ [DMA11_IRQn ] = isr_dma11, /* DMA Channel 11 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT28_MASK)
+ [DMA12_DMA28_IRQn] = isr_dma12_dma28, /* DMA Channel 12, 28 Transfer Complete */
+#elif defined(DMA_INT_INT12_MASK)
+ [DMA12_IRQn ] = isr_dma12, /* DMA Channel 12 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT29_MASK)
+ [DMA13_DMA29_IRQn] = isr_dma13_dma29, /* DMA Channel 13, 29 Transfer Complete */
+#elif defined(DMA_INT_INT13_MASK)
+ [DMA13_IRQn ] = isr_dma13, /* DMA Channel 13 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT30_MASK)
+ [DMA14_DMA30_IRQn] = isr_dma14_dma30, /* DMA Channel 14, 30 Transfer Complete */
+#elif defined(DMA_INT_INT14_MASK)
+ [DMA14_IRQn ] = isr_dma14, /* DMA Channel 14 Transfer Complete */
+#endif
+#if defined(DMA_INT_INT31_MASK)
+ [DMA15_DMA31_IRQn] = isr_dma15_dma31, /* DMA Channel 15, 31 Transfer Complete */
+#elif defined(DMA_INT_INT15_MASK)
+ [DMA15_IRQn ] = isr_dma15, /* DMA Channel 15 Transfer Complete */
+#endif
+ [DMA_Error_IRQn ] = isr_dma_error, /* DMA Error Interrupt */
+#endif /* defined(DMA0) */
+#ifdef MCM
+ [MCM_IRQn ] = isr_mcm, /* Normal Interrupt */
+#endif
+#if defined(FTFA)
+ [FTFA_IRQn ] = isr_ftfa, /* FTFA command complete */
+ [FTFA_Collision_IRQn] = isr_ftfa_collision, /* FTFA read collision */
+#elif defined(FTFE)
+ [FTFE_IRQn ] = isr_ftfe, /* FTFE command complete */
+ [FTFE_Collision_IRQn] = isr_ftfe_collision, /* FTFE read collision */
+#elif defined(FTFL)
+ [FTFL_IRQn ] = isr_ftfl, /* FTFL command complete */
+ [FTFL_Collision_IRQn] = isr_ftfl_collision, /* FTFL read collision */
+#endif
+#ifdef PMC
+ [LVD_LVW_IRQn ] = isr_lvd_lvw, /* Low Voltage Detect, Low Voltage Warning */
+#endif
+#ifdef LLWU
+ [LLWU_IRQn ] = isr_llwu, /* Low Leakage Wakeup Unit */
+#endif
+#ifdef WDOG
+ [WDOG_EWM_IRQn ] = isr_wdog_ewm, /* WDOG/EWM Interrupt */
+#endif
+#ifdef RNG
+ [RNG_IRQn ] = isr_rng, /* RNG Interrupt */
+#endif
+#ifdef I2C0
+ [I2C0_IRQn ] = isr_i2c0, /* I2C0 interrupt */
+#endif
+#ifdef I2C1
+ [I2C1_IRQn ] = isr_i2c1, /* I2C1 interrupt */
+#endif
+#ifdef I2C2
+ [I2C2_IRQn ] = isr_i2c2, /* I2C2 interrupt */
+#endif
+#ifdef I2C3
+ [I2C3_IRQn ] = isr_i2c3, /* I2C3 interrupt */
+#endif
+#ifdef SPI0
+ [SPI0_IRQn ] = isr_spi0, /* SPI0 Interrupt */
+#endif
+#ifdef SPI1
+ [SPI1_IRQn ] = isr_spi1, /* SPI1 Interrupt */
+#endif
+#ifdef SPI2
+ [SPI2_IRQn ] = isr_spi2, /* SPI2 Interrupt */
+#endif
+#ifdef I2S0
+ [I2S0_Tx_IRQn ] = isr_i2s0_tx, /* I2S0 transmit interrupt */
+ [I2S0_Rx_IRQn ] = isr_i2s0_rx, /* I2S0 receive interrupt */
+#endif
+#ifdef UART0
+#ifdef UART_RPL_RPL_MASK
+ [UART0_LON_IRQn ] = isr_uart0_lon, /* UART0 LON interrupt */
+#endif
+ [UART0_RX_TX_IRQn] = isr_uart0_rx_tx, /* UART0 Receive/Transmit interrupt */
+ [UART0_ERR_IRQn ] = isr_uart0_err, /* UART0 Error interrupt */
+#endif
+#ifdef UART1
+ [UART1_RX_TX_IRQn] = isr_uart1_rx_tx, /* UART1 Receive/Transmit interrupt */
+ [UART1_ERR_IRQn ] = isr_uart1_err, /* UART1 Error interrupt */
+#endif
+#ifdef UART2
+ [UART2_RX_TX_IRQn] = isr_uart2_rx_tx, /* UART2 Receive/Transmit interrupt */
+ [UART2_ERR_IRQn ] = isr_uart2_err, /* UART2 Error interrupt */
+#endif
+#ifdef UART3
+ [UART3_RX_TX_IRQn] = isr_uart3_rx_tx, /* UART3 Receive/Transmit interrupt */
+ [UART3_ERR_IRQn ] = isr_uart3_err, /* UART3 Error interrupt */
+#endif
+#ifdef UART4
+ [UART4_RX_TX_IRQn] = isr_uart4_rx_tx, /* UART4 Receive/Transmit interrupt */
+ [UART4_ERR_IRQn ] = isr_uart4_err, /* UART4 Error interrupt */
+#endif
+#ifdef UART5
+ [UART5_RX_TX_IRQn] = isr_uart5_rx_tx, /* UART5 Receive/Transmit interrupt */
+ [UART5_ERR_IRQn ] = isr_uart5_err, /* UART5 Error interrupt */
+#endif
+#ifdef ADC0
+ [ADC0_IRQn ] = isr_adc0, /* ADC0 interrupt */
+#endif
+#ifdef ADC1
+ [ADC1_IRQn ] = isr_adc1, /* ADC1 interrupt */
+#endif
+#ifdef ADC2
+ [ADC2_IRQn ] = isr_adc2, /* ADC2 interrupt */
+#endif
+#ifdef CMP0
+ [CMP0_IRQn ] = isr_cmp0, /* CMP0 interrupt */
+#endif
+#ifdef CMP1
+ [CMP1_IRQn ] = isr_cmp1, /* CMP1 interrupt */
+#endif
+#ifdef CMP2
+ [CMP2_IRQn ] = isr_cmp2, /* CMP2 interrupt */
+#endif
+#ifdef CMP3
+ [CMP3_IRQn ] = isr_cmp3, /* CMP3 interrupt */
+#endif
+#ifdef FTM0
+ [FTM0_IRQn ] = isr_ftm0, /* FTM0 fault, overflow and channels interrupt */
+#endif
+#ifdef FTM1
+ [FTM1_IRQn ] = isr_ftm1, /* FTM1 fault, overflow and channels interrupt */
+#endif
+#ifdef FTM2
+ [FTM2_IRQn ] = isr_ftm2, /* FTM2 fault, overflow and channels interrupt */
+#endif
+#ifdef FTM3
+ [FTM3_IRQn ] = isr_ftm3, /* FTM3 fault, overflow and channels interrupt */
+#endif
+#ifdef CMT
+ [CMT_IRQn ] = isr_cmt, /* CMT interrupt */
+#endif
+#ifdef RTC
+ [RTC_IRQn ] = isr_rtc, /* RTC interrupt */
+ [RTC_Seconds_IRQn] = isr_rtc_seconds, /* RTC seconds interrupt */
+#endif
+#ifdef PIT
+ [PIT0_IRQn ] = isr_pit0, /* PIT timer channel 0 interrupt */
+ [PIT1_IRQn ] = isr_pit1, /* PIT timer channel 1 interrupt */
+ [PIT2_IRQn ] = isr_pit2, /* PIT timer channel 2 interrupt */
+ [PIT3_IRQn ] = isr_pit3, /* PIT timer channel 3 interrupt */
+#endif
+#ifdef PDB0
+ [PDB0_IRQn ] = isr_pdb0, /* PDB0 Interrupt */
+#endif
+#ifdef USB0
+ [USB0_IRQn ] = isr_usb0, /* USB0 interrupt */
+#endif
+#ifdef USBDCD
+ [USBDCD_IRQn ] = isr_usbdcd, /* USBDCD Interrupt */
+#endif
+#if DAC0_BASE /* Not #ifdef because of error in MKW2xD.h files */
+ [DAC0_IRQn ] = isr_dac0, /* DAC0 interrupt */
+#endif
+#ifdef DAC1
+ [DAC1_IRQn ] = isr_dac1, /* DAC1 interrupt */
+#endif
+#ifdef MCG
+ [MCG_IRQn ] = isr_mcg, /* MCG Interrupt */
+#endif
+#ifdef LPTMR0
+ [LPTMR0_IRQn ] = isr_lptmr0, /* LPTimer interrupt */
+#endif
+#ifdef PORTA
+ [PORTA_IRQn ] = isr_porta, /* Port A interrupt */
+#endif
+#ifdef PORTB
+ [PORTB_IRQn ] = isr_portb, /* Port B interrupt */
+#endif
+#ifdef PORTC
+ [PORTC_IRQn ] = isr_portc, /* Port C interrupt */
+#endif
+#ifdef PORTD
+ [PORTD_IRQn ] = isr_portd, /* Port D interrupt */
+#endif
+#ifdef PORTE
+ [PORTE_IRQn ] = isr_porte, /* Port E interrupt */
+#endif
+#if __CORTEX_M >= 3
+ [SWI_IRQn ] = isr_swi, /* Software interrupt */
+#endif
+#ifdef CAN0
+ [CAN0_ORed_Message_buffer_IRQn] = isr_can0_ored_message_buffer, /* CAN0 OR'd message buffers interrupt */
+ [CAN0_Bus_Off_IRQn] = isr_can0_bus_off, /* CAN0 bus off interrupt */
+ [CAN0_Error_IRQn ] = isr_can0_error, /* CAN0 error interrupt */
+ [CAN0_Tx_Warning_IRQn] = isr_can0_tx_warning, /* CAN0 Tx warning interrupt */
+ [CAN0_Rx_Warning_IRQn] = isr_can0_rx_warning, /* CAN0 Rx warning interrupt */
+ [CAN0_Wake_Up_IRQn] = isr_can0_wake_up, /* CAN0 wake up interrupt */
+#endif
+#ifdef CAN1
+ [CAN1_ORed_Message_buffer_IRQn] = isr_can1_ored_message_buffer, /* CAN1 OR'd message buffers interrupt */
+ [CAN1_Bus_Off_IRQn] = isr_can1_bus_off, /* CAN1 bus off interrupt */
+ [CAN1_Error_IRQn ] = isr_can1_error, /* CAN1 error interrupt */
+ [CAN1_Tx_Warning_IRQn] = isr_can1_tx_warning, /* CAN1 Tx warning interrupt */
+ [CAN1_Rx_Warning_IRQn] = isr_can1_rx_warning, /* CAN1 Rx warning interrupt */
+ [CAN1_Wake_Up_IRQn] = isr_can1_wake_up, /* CAN1 wake up interrupt */
+#endif
+#ifdef SDHC
+ [SDHC_IRQn ] = isr_sdhc, /* SDHC interrupt */
+#endif
+#ifdef ENET
+ [ENET_1588_Timer_IRQn] = isr_enet_1588_timer, /* Ethernet MAC IEEE 1588 Timer Interrupt */
+ [ENET_Transmit_IRQn] = isr_enet_transmit, /* Ethernet MAC Transmit Interrupt */
+ [ENET_Receive_IRQn] = isr_enet_receive, /* Ethernet MAC Receive Interrupt */
+ [ENET_Error_IRQn ] = isr_enet_error, /* Ethernet MAC Error and miscelaneous Interrupt */
+#endif
+#ifdef LPUART0
+ [LPUART0_IRQn ] = isr_lpuart0, /* LPUART0 status/error interrupt */
+#endif
+#ifdef LPUART1
+ [LPUART1_IRQn ] = isr_lpuart1, /* LPUART1 status/error interrupt */
+#endif
+#ifdef LPUART2
+ [LPUART2_IRQn ] = isr_lpuart2, /* LPUART2 status/error interrupt */
+#endif
+#ifdef LPUART3
+ [LPUART3_IRQn ] = isr_lpuart3, /* LPUART3 status/error interrupt */
+#endif
+#ifdef LPUART4
+ [LPUART4_IRQn ] = isr_lpuart4, /* LPUART4 status/error interrupt */
+#endif
+#ifdef LPUART5
+ [LPUART5_IRQn ] = isr_lpuart5, /* LPUART5 status/error interrupt */
+#endif
+#ifdef TSI0
+ [TSI0_IRQn ] = isr_tsi0, /* TSI0 interrupt */
+#endif
+#ifdef TPM0
+ [TPM0_IRQn ] = isr_tpm0, /* TPM1 fault, overflow and channels interrupt */
+#endif
+#ifdef TPM1
+ [TPM1_IRQn ] = isr_tpm1, /* TPM1 fault, overflow and channels interrupt */
+#endif
+#ifdef TPM2
+ [TPM2_IRQn ] = isr_tpm2, /* TPM2 fault, overflow and channels interrupt */
+#endif
+#ifdef USBHSDCD
+ [USBHSDCD_IRQn ] = isr_usbhsdcd, /* USBHSDCD, USBHS Phy Interrupt */
+#endif
+#ifdef USBHS
+ [USBHS_IRQn ] = isr_usbhs, /* USB high speed OTG interrupt */
+#endif
+};
+
+/** @} */
diff --git a/cpu/kw2xd/Makefile b/cpu/kw2xd/Makefile
index 68605a469b55f3f54b540cce34fbedeeec39d472..12ba41f9cf16d9b3e8b1e8fcf75cc0bcfa85f04c 100644
--- a/cpu/kw2xd/Makefile
+++ b/cpu/kw2xd/Makefile
@@ -4,7 +4,4 @@ MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(RIOTCPU)/cortexm_common $(KINETIS_COMMON)
-# (file triggers compiler bug. see #5775)
-SRC_NOLTO += vectors.c
-
include $(RIOTBASE)/Makefile.base
diff --git a/cpu/kw2xd/Makefile.include b/cpu/kw2xd/Makefile.include
index 945e071da437cc85a1ad8ac5dda257e6c7096b87..7d634d17e54f385cda6a98bdc940f4940d5dd037 100644
--- a/cpu/kw2xd/Makefile.include
+++ b/cpu/kw2xd/Makefile.include
@@ -17,7 +17,4 @@ include $(KINETIS_COMMON)Makefile.include
# this CPU implementation is using kinetis common startup
export COMMON_STARTUP = $(KINETIS_COMMON)
-# add the CPU specific system calls implementations for the linker
-export UNDEF += $(BINDIR)/cpu/vectors.o
-
include $(RIOTMAKE)/arch/cortexm.inc.mk
diff --git a/cpu/kw2xd/vectors.c b/cpu/kw2xd/vectors.c
deleted file mode 100644
index d77ce14de666e80192d0b6e93f17ccdfb01c983f..0000000000000000000000000000000000000000
--- a/cpu/kw2xd/vectors.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * Copyright (C) 2014 Freie Universität Berlin
- * Copyright (C) 2015 PHYTEC Messtechnik GmbH
- *
- * This file is subject to the terms and conditions of the GNU Lesser General
- * Public License v2.1. See the file LICENSE in the top level directory for more
- * details.
- */
-
-/**
- * @ingroup cpu_kw2xd
- * @{
- *
- * @file
- * @brief Interrupt vector definition for MKW2XDXXX MCUs
- *
- * @author Hauke Petersen <hauke.petersen@fu-berlin.de>
- * @author Johann Fischer <j.fischer@phytec.de>
- *
- * @}
- */
-
-#include "vectors_kinetis.h"
-
-/* CPU specific interrupt vector table */
-ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
- isr_dma0, /* DMA channel 0 transfer complete */
- isr_dma1, /* DMA channel 1 transfer complete */
- isr_dma2, /* DMA channel 2 transfer complete */
- isr_dma3, /* DMA channel 3 transfer complete */
- isr_dma4, /* DMA channel 4 transfer complete */
- isr_dma5, /* DMA channel 5 transfer complete */
- isr_dma6, /* DMA channel 6 transfer complete */
- isr_dma7, /* DMA channel 7 transfer complete */
- isr_dma8, /* DMA channel 8 transfer complete */
- isr_dma9, /* DMA channel 9 transfer complete */
- isr_dma10, /* DMA channel 10 transfer complete */
- isr_dma11, /* DMA channel 11 transfer complete */
- isr_dma12, /* DMA channel 12 transfer complete */
- isr_dma13, /* DMA channel 13 transfer complete */
- isr_dma14, /* DMA channel 14 transfer complete */
- isr_dma15, /* DMA channel 15 transfer complete */
- isr_dma_error, /* DMA channel 0 - 15 error */
- isr_mcm, /* MCM normal interrupt */
- isr_ftfl, /* FTFL command complete */
- isr_ftfl_collision, /* FTFL read collision */
- isr_pmc, /* PMC controller low-voltage detect low-voltage warning */
- isr_llwu, /* Low leakage wakeup */
- isr_wdog_ewm, /* Single interrupt vector for WDOG and EWM */
- isr_rng, /* Randon number generator */
- isr_i2c0, /* Inter-integrated circuit 0 */
- isr_i2c1, /* Inter-integrated circuit 1 */
- isr_spi0, /* Serial peripheral Interface 0 */
- isr_spi1, /* Serial peripheral Interface 1 */
- isr_i2s0_tx, /* Integrated interchip sound 0 transmit interrupt */
- isr_i2s0_rx, /* Integrated interchip sound 0 receive interrupt */
- dummy_handler, /* Reserved interrupt */
- isr_uart0_rx_tx, /* UART0 receive/transmit interrupt */
- isr_uart0_error, /* UART0 error interrupt */
- isr_uart1_rx_tx, /* UART1 receive/transmit interrupt */
- isr_uart1_error, /* UART1 error interrupt */
- isr_uart2_rx_tx, /* UART2 receive/transmit interrupt */
- isr_uart2_error, /* UART2 error interrupt */
- dummy_handler, /* Reserved interrupt */
- dummy_handler, /* Reserved interrupt */
- isr_adc0, /* Analog-to-digital converter 0 */
- isr_cmp0, /* Comparator 0 */
- isr_cmp1, /* Comparator 1 */
- isr_ftm0, /* FlexTimer module 0 fault overflow and channels interrupt */
- isr_ftm1, /* FlexTimer module 1 fault overflow and channels interrupt */
- isr_ftm2, /* FlexTimer module 2 fault overflow and channels interrupt */
- isr_cmt, /* Carrier modulator transmitter */
- isr_rtc, /* Real time clock */
- isr_rtc_seconds, /* Real time clock seconds */
- isr_pit0, /* Periodic interrupt timer channel 0 */
- isr_pit1, /* Periodic interrupt timer channel 1 */
- isr_pit2, /* Periodic interrupt timer channel 2 */
- isr_pit3, /* Periodic interrupt timer channel 3 */
- isr_pdb0, /* Programmable delay block */
- isr_usb0, /* USB OTG interrupt */
- isr_usbdcd, /* USB charger detect */
- dummy_handler, /* Reserved interrupt */
- isr_dac0, /* Digital-to-analog converter 0 */
- isr_mcg, /* Multipurpose clock generator */
- isr_lptmr0, /* Low power timer interrupt */
- isr_porta, /* Port A pin detect interrupt */
- isr_portb, /* Port B pin detect interrupt */
- isr_portc, /* Port C pin detect interrupt */
- isr_portd, /* Port D pin detect interrupt */
- isr_porte, /* Port E pin detect interrupt */
- isr_swi, /* Software interrupt */
- dummy_handler, /* reserved 81 */
- dummy_handler, /* reserved 82 */
- dummy_handler, /* reserved 83 */
- dummy_handler, /* reserved 84 */
- dummy_handler, /* reserved 85 */
- dummy_handler, /* reserved 86 */
- dummy_handler, /* reserved 87 */
- dummy_handler, /* reserved 88 */
- dummy_handler, /* reserved 89 */
- dummy_handler, /* reserved 90 */
- dummy_handler, /* reserved 91 */
- dummy_handler, /* reserved 92 */
- dummy_handler, /* reserved 93 */
- dummy_handler, /* reserved 94 */
- dummy_handler, /* reserved 95 */
- dummy_handler, /* reserved 96 */
- dummy_handler, /* reserved 97 */
- dummy_handler, /* reserved 98 */
- dummy_handler, /* reserved 99 */
- dummy_handler, /* reserved 100 */
- dummy_handler, /* reserved 101 */
- dummy_handler, /* reserved 102 */
- dummy_handler, /* reserved 103 */
- dummy_handler, /* reserved 104 */
- dummy_handler, /* reserved 105 */
- dummy_handler, /* reserved 106 */
- dummy_handler, /* reserved 107 */
- dummy_handler, /* reserved 108 */
- dummy_handler, /* reserved 109 */
- dummy_handler, /* reserved 110 */
- dummy_handler, /* reserved 111 */
- dummy_handler, /* reserved 112 */
- dummy_handler, /* reserved 113 */
- dummy_handler, /* reserved 114 */
- dummy_handler, /* reserved 115 */
- dummy_handler, /* reserved 116 */
- dummy_handler, /* reserved 117 */
- dummy_handler, /* reserved 118 */
- dummy_handler, /* reserved 119 */
- dummy_handler, /* reserved 120 */
- dummy_handler, /* reserved 121 */
- dummy_handler, /* reserved 122 */
- dummy_handler, /* reserved 123 */
- dummy_handler, /* reserved 124 */
- dummy_handler, /* reserved 125 */
- dummy_handler, /* reserved 126 */
- dummy_handler, /* reserved 127 */
- dummy_handler, /* reserved 128 */
- dummy_handler, /* reserved 129 */
- dummy_handler, /* reserved 130 */
- dummy_handler, /* reserved 131 */
- dummy_handler, /* reserved 132 */
- dummy_handler, /* reserved 133 */
- dummy_handler, /* reserved 134 */
- dummy_handler, /* reserved 135 */
- dummy_handler, /* reserved 136 */
- dummy_handler, /* reserved 137 */
- dummy_handler, /* reserved 138 */
- dummy_handler, /* reserved 139 */
- dummy_handler, /* reserved 140 */
- dummy_handler, /* reserved 141 */
- dummy_handler, /* reserved 142 */
- dummy_handler, /* reserved 143 */
- dummy_handler, /* reserved 144 */
- dummy_handler, /* reserved 145 */
- dummy_handler, /* reserved 146 */
- dummy_handler, /* reserved 147 */
- dummy_handler, /* reserved 148 */
- dummy_handler, /* reserved 149 */
- dummy_handler, /* reserved 150 */
- dummy_handler, /* reserved 151 */
- dummy_handler, /* reserved 152 */
- dummy_handler, /* reserved 153 */
- dummy_handler, /* reserved 154 */
- dummy_handler, /* reserved 155 */
- dummy_handler, /* reserved 156 */
- dummy_handler, /* reserved 157 */
- dummy_handler, /* reserved 158 */
- dummy_handler, /* reserved 159 */
- dummy_handler, /* reserved 160 */
- dummy_handler, /* reserved 161 */
- dummy_handler, /* reserved 162 */
- dummy_handler, /* reserved 163 */
- dummy_handler, /* reserved 164 */
- dummy_handler, /* reserved 165 */
- dummy_handler, /* reserved 166 */
- dummy_handler, /* reserved 167 */
- dummy_handler, /* reserved 168 */
- dummy_handler, /* reserved 169 */
- dummy_handler, /* reserved 170 */
- dummy_handler, /* reserved 171 */
- dummy_handler, /* reserved 172 */
- dummy_handler, /* reserved 173 */
- dummy_handler, /* reserved 174 */
- dummy_handler, /* reserved 175 */
- dummy_handler, /* reserved 176 */
- dummy_handler, /* reserved 177 */
- dummy_handler, /* reserved 178 */
- dummy_handler, /* reserved 179 */
- dummy_handler, /* reserved 180 */
- dummy_handler, /* reserved 181 */
- dummy_handler, /* reserved 182 */
- dummy_handler, /* reserved 183 */
- dummy_handler, /* reserved 184 */
- dummy_handler, /* reserved 185 */
- dummy_handler, /* reserved 186 */
- dummy_handler, /* reserved 187 */
- dummy_handler, /* reserved 188 */
- dummy_handler, /* reserved 189 */
- dummy_handler, /* reserved 190 */
- dummy_handler, /* reserved 191 */
- dummy_handler, /* reserved 192 */
- dummy_handler, /* reserved 193 */
- dummy_handler, /* reserved 194 */
- dummy_handler, /* reserved 195 */
- dummy_handler, /* reserved 196 */
- dummy_handler, /* reserved 197 */
- dummy_handler, /* reserved 198 */
- dummy_handler, /* reserved 199 */
- dummy_handler, /* reserved 200 */
- dummy_handler, /* reserved 201 */
- dummy_handler, /* reserved 202 */
- dummy_handler, /* reserved 203 */
- dummy_handler, /* reserved 204 */
- dummy_handler, /* reserved 205 */
- dummy_handler, /* reserved 206 */
- dummy_handler, /* reserved 207 */
- dummy_handler, /* reserved 208 */
- dummy_handler, /* reserved 209 */
- dummy_handler, /* reserved 210 */
- dummy_handler, /* reserved 211 */
- dummy_handler, /* reserved 212 */
- dummy_handler, /* reserved 213 */
- dummy_handler, /* reserved 214 */
- dummy_handler, /* reserved 215 */
- dummy_handler, /* reserved 216 */
- dummy_handler, /* reserved 217 */
- dummy_handler, /* reserved 218 */
- dummy_handler, /* reserved 219 */
- dummy_handler, /* reserved 220 */
- dummy_handler, /* reserved 221 */
- dummy_handler, /* reserved 222 */
- dummy_handler, /* reserved 223 */
- dummy_handler, /* reserved 224 */
- dummy_handler, /* reserved 225 */
- dummy_handler, /* reserved 226 */
- dummy_handler, /* reserved 227 */
- dummy_handler, /* reserved 228 */
- dummy_handler, /* reserved 229 */
- dummy_handler, /* reserved 230 */
- dummy_handler, /* reserved 231 */
- dummy_handler, /* reserved 232 */
- dummy_handler, /* reserved 233 */
- dummy_handler, /* reserved 234 */
- dummy_handler, /* reserved 235 */
- dummy_handler, /* reserved 236 */
- dummy_handler, /* reserved 237 */
- dummy_handler, /* reserved 238 */
- dummy_handler, /* reserved 239 */
- dummy_handler, /* reserved 240 */
- dummy_handler, /* reserved 241 */
- dummy_handler, /* reserved 242 */
- dummy_handler, /* reserved 243 */
- dummy_handler, /* reserved 244 */
- dummy_handler, /* reserved 245 */
- dummy_handler, /* reserved 246 */
- dummy_handler, /* reserved 247 */
- dummy_handler, /* reserved 248 */
- dummy_handler, /* reserved 249 */
- dummy_handler, /* reserved 250 */
- dummy_handler, /* reserved 251 */
- dummy_handler, /* reserved 252 */
- dummy_handler, /* reserved 253 */
- dummy_handler, /* reserved 254 */
- dummy_handler, /* reserved 255 */
-};