diff --git a/boards/nucleo-f334/Makefile.features b/boards/nucleo-f334/Makefile.features
index 53e45310683f633f1d7e4a9079e178ca34a722d3..a283c65cbe8326fd022f263c7eebfcb500651edb 100644
--- a/boards/nucleo-f334/Makefile.features
+++ b/boards/nucleo-f334/Makefile.features
@@ -1,4 +1,6 @@
FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += cpp
FEATURES_MCU_GROUP = cortex_m4
diff --git a/boards/nucleo-f334/include/periph_conf.h b/boards/nucleo-f334/include/periph_conf.h
index 8d668f627d7a560b4e012e018824ce4449fd9957..9168aaf099117d16256e9b769ba56e874ffcd386 100644
--- a/boards/nucleo-f334/include/periph_conf.h
+++ b/boards/nucleo-f334/include/periph_conf.h
@@ -14,6 +14,7 @@
* @brief Peripheral MCU configuration for the nucleo-f334 board
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author Kaspar Schleiser <kaspar.schleiser@fu-berlin.de>
*/
#ifndef __PERIPH_CONF_H
@@ -78,6 +79,89 @@ extern "C" {
#define UART_0_AF 7
/** @} */
+/**
+ * @name SPI configuration
+ * @{
+ */
+#define SPI_NUMOF (1U)
+#define SPI_0_EN 1
+#define SPI_IRQ_PRIO 1
+
+/* SPI 0 device config */
+#define SPI_0_DEV SPI1
+#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
+#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
+#define SPI_0_IRQ SPI1_IRQn
+#define SPI_0_IRQ_HANDLER isr_spi1
+/* SPI 0 pin configuration */
+#define SPI_0_SCK_PORT GPIOA
+#define SPI_0_SCK_PIN 5
+#define SPI_0_SCK_AF 5
+#define SPI_0_SCK_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define SPI_0_MISO_PORT GPIOA
+#define SPI_0_MISO_PIN 6
+#define SPI_0_MISO_AF 5
+#define SPI_0_MISO_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+#define SPI_0_MOSI_PORT GPIOA
+#define SPI_0_MOSI_PIN 7
+#define SPI_0_MOSI_AF 5
+#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
+/** @} */
+
+/**
+ * @brief GPIO configuration
+ * @{
+ */
+#define GPIO_NUMOF 3
+#define GPIO_0_EN 1
+#define GPIO_1_EN 1
+#define GPIO_2_EN 1
+#define GPIO_IRQ_PRIO 1
+
+/* IRQ config */
+#define GPIO_IRQ_0 (-1) /* not configured */
+#define GPIO_IRQ_1 (-1) /* not configured */
+#define GPIO_IRQ_2 GPIO_2
+#define GPIO_IRQ_3 (-1) /* not configured */
+#define GPIO_IRQ_4 (-1) /* not configured */
+#define GPIO_IRQ_5 (-1) /* not configured */
+#define GPIO_IRQ_6 (-1) /* not configured */
+#define GPIO_IRQ_7 (-1) /* not configured */
+#define GPIO_IRQ_8 (-1) /* not configured */
+#define GPIO_IRQ_9 (-1) /* not configured */
+#define GPIO_IRQ_10 GPIO_1
+#define GPIO_IRQ_11 (-1) /* not configured */
+#define GPIO_IRQ_12 (-1) /* not configured */
+#define GPIO_IRQ_13 GPIO_0
+#define GPIO_IRQ_14 (-1) /* not configured */
+#define GPIO_IRQ_15 (-1) /* not configured */
+
+/* GPIO channel 0 config */
+#define GPIO_0_PORT GPIOC /* Used for user button 1 */
+#define GPIO_0_PIN 13
+#define GPIO_0_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define GPIO_0_EXTI_CFG1() (SYSCFG->EXTICR[3] &= ~(SYSCFG_EXTICR4_EXTI13))
+#define GPIO_0_EXTI_CFG2() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PC)
+#define GPIO_0_IRQ EXTI15_10_IRQn
+
+/* GPIO channel 1 config */
+#define GPIO_1_PORT GPIOC
+#define GPIO_1_PIN 10
+#define GPIO_1_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
+#define GPIO_1_EXTI_CFG1() (SYSCFG->EXTICR[2] &= ~(SYSCFG_EXTICR3_EXTI10))
+#define GPIO_1_EXTI_CFG2() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PC)
+#define GPIO_1_IRQ EXTI15_10_IRQn
+
+/* GPIO channel 2 config */
+#define GPIO_2_PORT GPIOD
+#define GPIO_2_PIN 2
+#define GPIO_2_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIODEN)
+#define GPIO_2_EXTI_CFG1() (SYSCFG->EXTICR[0] &= ~(SYSCFG_EXTICR1_EXTI2))
+#define GPIO_2_EXTI_CFG2() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PD)
+#define GPIO_2_IRQ EXTI2_TSC_IRQn
+
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/cpu/stm32f3/periph/gpio.c b/cpu/stm32f3/periph/gpio.c
index 820aa1bab1134ad634ef6150d2def3bcfb62601d..65614884597eeda9a6f9a26eb693b9d2dcea9283 100644
--- a/cpu/stm32f3/periph/gpio.c
+++ b/cpu/stm32f3/periph/gpio.c
@@ -126,6 +126,8 @@ int gpio_init_out(gpio_t dev, gpio_pp_t pushpull)
pin = GPIO_11_PIN;
break;
#endif
+ default:
+ return -1;
}
port->MODER &= ~(2 << (2 * pin)); /* set pin to output mode */
@@ -229,6 +231,8 @@ int gpio_init_in(gpio_t dev, gpio_pp_t pushpull)
pin = GPIO_11_PIN;
break;
#endif
+ default:
+ return -1;
}
port->MODER &= ~(3 << (2 * pin)); /* configure pin as input */
@@ -597,6 +601,8 @@ int gpio_read(gpio_t dev)
pin = GPIO_11_PIN;
break;
#endif
+ default:
+ return -1;
}
if (port->MODER & (3 << (pin * 2))) { /* if configured as output */
@@ -783,7 +789,7 @@ void isr_exti1(void)
}
}
-void isr_exti2(void)
+void isr_exti2_tsc(void)
{
if (EXTI->PR & EXTI_PR_PR2) {
EXTI->PR |= EXTI_PR_PR2; /* clear status bit by writing a 1 to it */
diff --git a/cpu/stm32f3/periph/spi.c b/cpu/stm32f3/periph/spi.c
index 2b401e6468a2ad427b0bfcf7884db97610407e3c..1631998a13348e17c21b16b740325baa5c539efe 100644
--- a/cpu/stm32f3/periph/spi.c
+++ b/cpu/stm32f3/periph/spi.c
@@ -1,6 +1,7 @@
/*
* Copyright (C) 2014 Hamburg University of Applied Sciences
* Copyright (C) 2014 Freie Universität Berlin
+ * Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
@@ -18,6 +19,7 @@
* @author Fabian Nack <nack@inf.fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Joakim Gebart <joakim.gebart@eistec.se>
+ * @author Kaspar Schleiser <kaspar@schleiser.de>
*
* @}
*/
@@ -134,7 +136,9 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
spi_conf_pins(dev);
/**************** SPI-Init *****************/
+#ifdef CPU_MODEL_STM32F303VC
spi[dev]->I2SCFGR &= ~(SPI_I2SCFGR_I2SMOD);/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+#endif
spi[dev]->CR1 = 0;
spi[dev]->CR2 = 0;
/* the NSS (chip select) is managed purely by software */
@@ -142,8 +146,12 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
spi[dev]->CR1 |= (speed_divider << 3); /* Define serial clock baud rate. 001 leads to f_PCLK/4 */
spi[dev]->CR1 |= (SPI_CR1_MSTR); /* 1: master configuration */
spi[dev]->CR1 |= (conf);
+
+ spi[dev]->CR2 |= SPI_CR2_FRXTH; /* set FIFO reception threshold to 8bit (default: 16bit) */
+
/* enable SPI */
spi[dev]->CR1 |= (SPI_CR1_SPE);
+
return 0;
}
@@ -194,7 +202,9 @@ int spi_init_slave(spi_t dev, spi_conf_t conf, char(*cb)(char data))
spi_conf_pins(dev);
/***************** SPI-Init *****************/
+#ifdef CPU_MODEL_STM32F303VC
spi[dev]->I2SCFGR &= ~(SPI_I2SCFGR_I2SMOD);
+#endif
spi[dev]->CR1 = 0;
spi[dev]->CR2 = 0;
/* enable RXNEIE flag to enable rx buffer not empty interrupt */
@@ -299,20 +309,26 @@ int spi_release(spi_t dev)
int spi_transfer_byte(spi_t dev, char out, char *in)
{
- if (dev >= SPI_NUMOF) {
- return -1;
- }
+ char tmp;
- while (!(spi[dev]->SR & SPI_SR_TXE));
- spi[dev]->DR = out;
+ /* recast to uint_8 to force 8bit access */
+ volatile uint8_t *DR = (volatile uint8_t*) &spi[dev]->DR;
- while (!(spi[dev]->SR & SPI_SR_RXNE));
+ /* wait for an eventually previous byte to be readily transferred */
+ while(!(spi[dev]->SR & SPI_SR_TXE));
- if (in != NULL) {
- *in = spi[dev]->DR;
- }
- else {
- spi[dev]->DR;
+ /* put next byte into the output register */
+ *DR = out;
+
+ /* wait until the current byte was successfully transferred */
+ while(!(spi[dev]->SR & SPI_SR_RXNE) );
+
+ /* read response byte to reset flags */
+ tmp = *DR;
+
+ /* 'return' response byte if wished for */
+ if (in) {
+ *in = tmp;
}
return 1;
@@ -320,7 +336,6 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
{
-
int i, trans_ret, trans_bytes = 0;
char in_temp;