From f5e419b4cb4d4023533af8de77261afe8866bffb Mon Sep 17 00:00:00 2001
From: Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
Date: Wed, 7 Aug 2013 12:25:03 +0200
Subject: [PATCH] updated board common initialization
---
msba2-common/board_common_init.c | 41 +++-----------------
msba2/board_init.c | 65 ++++++++++++++++++++++++++++++++
msba2/include/board.h | 2 +
3 files changed, 72 insertions(+), 36 deletions(-)
diff --git a/msba2-common/board_common_init.c b/msba2-common/board_common_init.c
index a437cce2b7..5db84af7ab 100644
--- a/msba2-common/board_common_init.c
+++ b/msba2-common/board_common_init.c
@@ -37,9 +37,10 @@ and the mailinglist (subscription via web site)
* @author Heiko Will
* @author Kaspar Schleiser
* @author Michael Baar <baar@inf.fu-berlin.de>
- *
+ * @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
* @note $Id$
*/
+#include <board.h>
#include <lpc23xx.h>
#include <VIC.h>
#include <cpu.h>
@@ -69,44 +70,11 @@ pllfeed(void)
PLLFEED = 0xAA;
PLLFEED = 0x55;
}
-/*---------------------------------------------------------------------------*/
-void init_clks1(void)
-{
- // Disconnect PLL
- PLLCON &= ~0x0002;
- pllfeed();
- // Disable PLL
- PLLCON &= ~0x0001;
- pllfeed();
- SCS |= 0x20; // Enable main OSC
-
- while (!(SCS & 0x40)); // Wait until main OSC is usable
-
- /* select main OSC, 16MHz, as the PLL clock source */
- CLKSRCSEL = 0x0001;
-
- // Setting Multiplier and Divider values
- PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
- pllfeed();
-
- // Enabling the PLL */
- PLLCON = 0x0001;
- pllfeed();
-
- /* Set clock divider to 4 (value+1) */
- CCLKCFG = CL_CPU_DIV - 1; // Fcpu = 72 MHz
-
-#if USE_USB
- USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
-#endif
-}
-
-void init_clks2(void)
-{
+void init_clks2(void){
// Wait for the PLL to lock to set frequency
- while (!(PLLSTAT & BIT26));
+ while(!(PLLSTAT & BIT26));
// Connect the PLL as the clock source
PLLCON = 0x0003;
@@ -124,3 +92,4 @@ void bl_init_clks(void)
init_mam();
}
+/*---------------------------------------------------------------------------*/
diff --git a/msba2/board_init.c b/msba2/board_init.c
index 729854e433..a600de19d1 100644
--- a/msba2/board_init.c
+++ b/msba2/board_init.c
@@ -1,3 +1,30 @@
+/*
+ * main.c - Main function of the SRF02 ultrasonic sensor project.
+ * Copyright (C) 2013 Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
+ *
+ * The source code is licensed under the LGPLv2 license,
+ * See the file LICENSE for more details.
+ */
+
+/**
+ * @ingroup msba2
+ * @{
+ */
+
+/**
+ * @file
+ * @brief MSB-A2 board initialization
+ *
+ * @author Freie Universität Berlin, Computer Systems & Telematics, FeuerWhere project
+ * @author Heiko Will
+ * @author Kaspar Schleiser
+ * @author Michael Baar <baar@inf.fu-berlin.de>
+ * @author Zakaria Kasmi <zkasmi@inf.fu-berlin.de>
+ *
+ * @note $Id$
+ */
+
+
#include <board.h>
#include <cpu.h>
@@ -41,3 +68,41 @@ void bl_init_ports(void)
bl_blink();
}
+static inline void
+pllfeed(void)
+{
+ PLLFEED = 0xAA;
+ PLLFEED = 0x55;
+}
+
+void init_clks1(void)
+{
+ // Disconnect PLL
+ PLLCON &= ~0x0002;
+ pllfeed();
+
+ // Disable PLL
+ PLLCON &= ~0x0001;
+ pllfeed();
+
+ SCS |= 0x20; // Enable main OSC
+ while( !(SCS & 0x40) ); // Wait until main OSC is usable
+
+ /* select main OSC, 16MHz, as the PLL clock source */
+ CLKSRCSEL = 0x0001;
+
+ // Setting Multiplier and Divider values
+ PLLCFG = 0x0008; // M=9 N=1 Fcco = 288 MHz
+ pllfeed();
+
+ // Enabling the PLL */
+ PLLCON = 0x0001;
+ pllfeed();
+
+ /* Set clock divider to 4 (value+1) */
+ CCLKCFG = CL_CPU_DIV - 1; // Fcpu = 72 MHz
+
+#if USE_USB
+ USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
+#endif
+}
\ No newline at end of file
diff --git a/msba2/include/board.h b/msba2/include/board.h
index 398255ab4d..fb64f0095e 100644
--- a/msba2/include/board.h
+++ b/msba2/include/board.h
@@ -15,4 +15,6 @@
#define LED_RED_ON (FIO3CLR = LED_RED_PIN)
#define LED_RED_TOGGLE (FIO3PIN ^= LED_RED_PIN)
+void init_clks1(void);
+
#endif /* __BOARD_H */
--
GitLab