diff --git a/cpu/cortexm_common/cortexm_init.c b/cpu/cortexm_common/cortexm_init.c
index 73bd40c4d7670b14ab7c5fdecb13fe4ce70b9a82..664c55b05048894723744fbd49455516a3e70999 100644
--- a/cpu/cortexm_common/cortexm_init.c
+++ b/cpu/cortexm_common/cortexm_init.c
@@ -26,6 +26,11 @@
  */
 #define FULL_FPU_ACCESS         (0x00f00000)
 
+/**
+ * Interrupt vector base address, defined by the linker
+ */
+extern const void *_isr_vectors;
+
 void cortexm_init(void)
 {
     /* initialize the FPU on Cortex-M4F CPUs */
@@ -37,7 +42,7 @@ void cortexm_init(void)
     /* configure the vector table location to internal flash */
 #if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
     defined(CPU_ARCH_CORTEX_M4F)
-    SCB->VTOR = CPU_FLASH_BASE;
+    SCB->VTOR = (uint32_t)&_isr_vectors;
 #endif
 
     /* initialize the interrupt priorities */
diff --git a/cpu/cortexm_common/ldscripts/cortexm_base.ld b/cpu/cortexm_common/ldscripts/cortexm_base.ld
index 68c19e7d3ecfd312fda0950f6ad744b03f161555..2e95c8ffc616d4c2fc21ec5262a5a1f976e0dcee 100644
--- a/cpu/cortexm_common/ldscripts/cortexm_base.ld
+++ b/cpu/cortexm_common/ldscripts/cortexm_base.ld
@@ -41,6 +41,7 @@ SECTIONS
     {
         . = ALIGN(4);
         _sfixed = .;
+        _isr_vectors = DEFINED(_isr_vectors) ? _isr_vectors : . ;
         KEEP(*(.vectors .vectors.*))
         *(.text .text.* .gnu.linkonce.t.*)
         *(.glue_7t) *(.glue_7)
diff --git a/cpu/kinetis_common/ldscripts/kinetis.ld b/cpu/kinetis_common/ldscripts/kinetis.ld
index d4be65b5d55a6881121696f6e776135a01960ddc..084b1150332a43d67541bd0c7b8a1492ab938205 100644
--- a/cpu/kinetis_common/ldscripts/kinetis.ld
+++ b/cpu/kinetis_common/ldscripts/kinetis.ld
@@ -25,7 +25,7 @@ SECTIONS
     /* Interrupt vectors 0x00-0x3ff. */
     .vector_table :
     {
-        _vector_rom = .;
+        _isr_vectors = .;
         KEEP(*(.vector_table))
     } > vectors
     ASSERT (SIZEOF(.vector_table) == 0x400, "Interrupt vector table of invalid size.")