diff --git a/chronos/Makefile.include b/chronos/Makefile.include
index 47ba1a079f8cbe1a28487516ff4d404f056ee7d7..04b77c5d4c70caebea91b8da797c8a4199b44dec 100644
--- a/chronos/Makefile.include
+++ b/chronos/Makefile.include
@@ -19,3 +19,4 @@ ifeq ($(strip $(PORT)),)
 endif
 export HEXFILE = bin/$(PROJECT).hex
 export FFLAGS = -d $(PORT) -j uif "prog $(HEXFILE)"
+export OFLAGS = -O ihex
diff --git a/msb-430-common/Makefile.include b/msb-430-common/Makefile.include
index 33ce3d11eba8f2bf6c72e5ec0bac39f826856e1c..b7dd9ef3d9821a702ef072baba7095b286d2f940 100644
--- a/msb-430-common/Makefile.include
+++ b/msb-430-common/Makefile.include
@@ -24,3 +24,4 @@ export FFLAGS = -j olimex "prog $(HEXFILE)"
 
 export USEMODULE += msp430_common 
 export INCLUDES += -I $(RIOTCPU)/msp430-common/include/
+export OFLAGS = -O ihex
diff --git a/msba2-common/Makefile.include b/msba2-common/Makefile.include
index c2832ca47d10a8265a073add4e6b3a0b55405a1d..5d3ba0fb0ddc9791fae6aec8f35e82006ab7150b 100644
--- a/msba2-common/Makefile.include
+++ b/msba2-common/Makefile.include
@@ -24,3 +24,4 @@ export FFLAGS = $(PORT) $(PROJBINDIR)/$(PROJECT).hex
 include $(RIOTBOARD)/msba2-common/Makefile.dep
 
 export INCLUDES += -I$(RIOTCPU)/lpc2387/include
+export OFLAGS = -O ihex
diff --git a/redbee-econotag/Makefile.include b/redbee-econotag/Makefile.include
index 26738a93fc0615dcceb3ee3874b702091de913d3..53a4eec2029e589aaf93242004db2dee59ab6cc8 100644
--- a/redbee-econotag/Makefile.include
+++ b/redbee-econotag/Makefile.include
@@ -19,7 +19,7 @@ export AS = $(PREFIX)as
 export LINK = $(PREFIX)gcc
 export SIZE = $(PREFIX)size
 export OBJCOPY = $(PREFIX)objcopy
-FLASHER = lpc2k_pgm
+FLASHER = mc1322x-load.pl
 TERM = pyterm.py
 LINKFLAGS = -mcpu=arm7tdmi-s -static -lgcc -nostartfiles -T$(RIOTBASE)/cpu/$(CPU)/mc1322x.lds
 
@@ -27,4 +27,5 @@ ifeq ($(strip $(PORT)),)
 	export PORT = /dev/ttyUSB0
 endif
 export HEXFILE = bin/$(PROJECT).hex
-export FFLAGS = -d $(PORT) -j uif "prog $(HEXFILE)"
+export FFLAGS = -t $(PORT) -f $(HEXFILE) -c 'bbmc -l redbee-econotag reset'
+export OFLAGS = -O binary --gap-fill=0xff
diff --git a/wsn430-common/Makefile.include b/wsn430-common/Makefile.include
index 63cee9a3aff788d0adbbaa149e83f2f4548a77b8..f1cde0aab9e7fc61be38cf8dd6b9571e228680b1 100644
--- a/wsn430-common/Makefile.include
+++ b/wsn430-common/Makefile.include
@@ -20,4 +20,6 @@ endif
 export HEXFILE = bin/$(PROJECT).hex
 export FFLAGS = -d $(PORT) -j uif "prog $(HEXFILE)"
 
-export INCLUDES += -I $(RIOTCPU)/msp430-common/include/
\ No newline at end of file
+export INCLUDES += -I $(RIOTCPU)/msp430-common/include/
+export OFLAGS = -O ihex
+