diff --git a/boards/nucleo144-f413/Makefile b/boards/nucleo144-f413/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..f8fcbb53a06595771dae356338a7bf2c0673734d
--- /dev/null
+++ b/boards/nucleo144-f413/Makefile
@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base
diff --git a/boards/nucleo144-f413/Makefile.dep b/boards/nucleo144-f413/Makefile.dep
new file mode 100644
index 0000000000000000000000000000000000000000..76e2dc17b45c22bfb5b499e63647610ca247b349
--- /dev/null
+++ b/boards/nucleo144-f413/Makefile.dep
@@ -0,0 +1 @@
+include $(RIOTBOARD)/nucleo-common/Makefile.dep
diff --git a/boards/nucleo144-f413/Makefile.features b/boards/nucleo144-f413/Makefile.features
new file mode 100644
index 0000000000000000000000000000000000000000..e0517ca85376d4f2d44a7827e02a5de2a7e33fb3
--- /dev/null
+++ b/boards/nucleo144-f413/Makefile.features
@@ -0,0 +1,15 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_rtc
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+FEATURES_PROVIDED += periph_pwm
+
+# load the common Makefile.features for Nucleo boards
+include $(RIOTBOARD)/nucleo-common/Makefile.features
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m4_3
diff --git a/boards/nucleo144-f413/Makefile.include b/boards/nucleo144-f413/Makefile.include
new file mode 100644
index 0000000000000000000000000000000000000000..835cd773aab48e553a2a096ac17c20b9ead0e0f9
--- /dev/null
+++ b/boards/nucleo144-f413/Makefile.include
@@ -0,0 +1,6 @@
+# define the cpu used by the nucleo-f446 board
+export CPU = stm32f4
+export CPU_MODEL = stm32f413zh
+
+# load the common Makefile.include for Nucleo boards
+include $(RIOTBOARD)/nucleo-common/Makefile.include
diff --git a/boards/nucleo144-f413/board.c b/boards/nucleo144-f413/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..29eb82af14122618556b09c6336888dde66546f2
--- /dev/null
+++ b/boards/nucleo144-f413/board.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Inria
+ * 2017 OTA keys S.A.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo144-f413
+ * @{
+ *
+ * @file
+ * @brief Board specific implementations for the nucleo144-f413 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Vincent Dupont <vincent@otakeys.com>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+
+void board_init(void)
+{
+ /* initialize the CPU */
+ cpu_init();
+
+ /* initialize the boards LEDs */
+ gpio_init(LED0_PIN, GPIO_OUT);
+ gpio_init(LED1_PIN, GPIO_OUT);
+ gpio_init(LED2_PIN, GPIO_OUT);
+}
diff --git a/boards/nucleo144-f413/dist/openocd.cfg b/boards/nucleo144-f413/dist/openocd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..9a3061f0bf823cd3d3ada251afee536c369bd14a
--- /dev/null
+++ b/boards/nucleo144-f413/dist/openocd.cfg
@@ -0,0 +1 @@
+source [find board/st_nucleo_f4.cfg]
diff --git a/boards/nucleo144-f413/include/board.h b/boards/nucleo144-f413/include/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..3ac39aa25d586a043fa9755be3b9c4734e564ebb
--- /dev/null
+++ b/boards/nucleo144-f413/include/board.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2016 Inria
+ * 2017 OTA keys S.A.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @defgroup boards_nucleo144-f413 Nucleo-F413
+ * @ingroup boards
+ * @brief Board specific files for the nucleo144-f413 board
+ * @{
+ *
+ * @file
+ * @brief Board specific definitions for the nucleo144-f413 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Vincent Dupont <vincent@otakeys.com>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name xtimer configuration
+ * @{
+ */
+#define XTIMER_DEV TIMER_DEV(0)
+#define XTIMER_CHAN (0)
+#define XTIMER_OVERHEAD (6)
+#define XTIMER_BACKOFF (5)
+/** @} */
+
+/**
+ * @brief LED pin definitions and handlers
+ * @{
+ */
+#define LED_CREG BSRRH
+#define LED_SREG BSRRL
+
+#define LED0_PIN GPIO_PIN(PORT_B, 0)
+#define LED0_MASK (1 << 0)
+#define LED0_ON (GPIOA->LED_SREG = LED0_MASK)
+#define LED0_OFF (GPIOA->LED_CREG = LED0_MASK)
+#define LED0_TOGGLE (GPIOA->ODR ^= LED0_MASK)
+
+#define LED1_PIN GPIO_PIN(PORT_B, 7)
+#define LED1_MASK (1 << 7)
+#define LED1_OFF (GPIOA->LED_CREG = LED1_MASK)
+#define LED1_ON (GPIOA->LED_SREG = LED1_MASK)
+#define LED1_TOGGLE (GPIOA->ODR ^= LED1_MASK)
+
+#define LED2_PIN GPIO_PIN(PORT_B, 14)
+#define LED2_MASK (1 << 14)
+#define LED2_ON (GPIOA->LED_SREG = LED2_MASK)
+#define LED2_OFF (GPIOA->LED_CREG = LED2_MASK)
+#define LED2_TOGGLE (GPIOA->ODR ^= LED2_MASK)
+/** @} */
+
+/**
+ * @brief User button
+ */
+#define BTN_B1_PIN GPIO_PIN(PORT_C, 13)
+
+/**
+ * @brief Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */
diff --git a/boards/nucleo144-f413/include/periph_conf.h b/boards/nucleo144-f413/include/periph_conf.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a475031e442a9ef78ed81c9c4ce023f9da19f64
--- /dev/null
+++ b/boards/nucleo144-f413/include/periph_conf.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2016 Inria
+ * Copyright (C) 2017 OTA keys S.A.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup boards_nucleo144-f413
+ * @{
+ *
+ * @file
+ * @name Peripheral MCU configuration for the nucleo144-f413 board
+ *
+ * @author Alexandre Abadie <alexandre.abadie@inria.fr>
+ * @author Vincent Dupont <vincent@otakeys.com>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+#define CLOCK_HSE (8000000U) /* external oscillator */
+#define CLOCK_CORECLOCK (100000000U) /* desired core clock frequency */
+
+/* the actual PLL values are automatically generated */
+#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
+#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
+#define CLOCK_PLL_P (2U)
+#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
+#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
+#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+/** @} */
+
+/**
+ * @brief Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+ {
+ .dev = TIM5,
+ .max = 0xffffffff,
+ .rcc_mask = RCC_APB1ENR_TIM5EN,
+ .bus = APB1,
+ .irqn = TIM5_IRQn
+ }
+};
+
+#define TIMER_0_ISR isr_tim5
+
+#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @name UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+ {
+ .dev = USART3,
+ .rcc_mask = RCC_APB1ENR_USART3EN,
+ .rx_pin = GPIO_PIN(PORT_D, 9),
+ .tx_pin = GPIO_PIN(PORT_D, 8),
+ .rx_af = GPIO_AF7,
+ .tx_af = GPIO_AF7,
+ .bus = APB1,
+ .irqn = USART3_IRQn,
+#ifdef UART_USE_DMA
+ .dma_stream = 6,
+ .dma_chan = 4
+#endif
+ },
+ {
+ .dev = USART2,
+ .rcc_mask = RCC_APB1ENR_USART2EN,
+ .rx_pin = GPIO_PIN(PORT_A, 3),
+ .tx_pin = GPIO_PIN(PORT_A, 2),
+ .rx_af = GPIO_AF7,
+ .tx_af = GPIO_AF7,
+ .bus = APB1,
+ .irqn = USART2_IRQn,
+#ifdef UART_USE_DMA
+ .dma_stream = 5,
+ .dma_chan = 4
+#endif
+ },
+ {
+ .dev = USART1,
+ .rcc_mask = RCC_APB2ENR_USART1EN,
+ .rx_pin = GPIO_PIN(PORT_A, 10),
+ .tx_pin = GPIO_PIN(PORT_A, 9),
+ .rx_af = GPIO_AF7,
+ .tx_af = GPIO_AF7,
+ .bus = APB2,
+ .irqn = USART1_IRQn,
+#ifdef UART_USE_DMA
+ .dma_stream = 4,
+ .dma_chan = 4
+#endif
+ },
+};
+
+#define UART_0_ISR (isr_usart3)
+#define UART_0_DMA_ISR (isr_dma1_stream6)
+#define UART_1_ISR (isr_usart2)
+#define UART_1_DMA_ISR (isr_dma1_stream5)
+#define UART_2_ISR (isr_usart1)
+#define UART_2_DMA_ISR (isr_dma1_stream4)
+
+#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @brief PWM configuration
+ * @{
+ */
+static const pwm_conf_t pwm_config[] = {
+ {
+ .dev = TIM2,
+ .rcc_mask = RCC_APB1ENR_TIM2EN,
+ .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
+ { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
+ { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
+ { .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} },
+ .af = GPIO_AF1,
+ .bus = APB1
+ },
+ {
+ .dev = TIM3,
+ .rcc_mask = RCC_APB1ENR_TIM3EN,
+ .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 },
+ { .pin = GPIO_UNDEF, .cc_chan = 0 } },
+ .af = GPIO_AF2,
+ .bus = APB1
+ },
+ {
+ .dev = TIM8,
+ .rcc_mask = RCC_APB2ENR_TIM8EN,
+ .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
+ { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
+ { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
+ { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
+ .af = GPIO_AF3,
+ .bus = APB2
+ },
+};
+
+#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
+/** @} */
+
+/**
+ * @name SPI configuration
+ *
+ * @note The spi_divtable is auto-generated from
+ * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+ { /* for APB1 @ 50000000Hz */
+ 7, /* -> 195312Hz */
+ 6, /* -> 390625Hz */
+ 5, /* -> 781250Hz */
+ 2, /* -> 6250000Hz */
+ 1 /* -> 12500000Hz */
+ },
+ { /* for APB2 @ 100000000Hz */
+ 7, /* -> 390625Hz */
+ 7, /* -> 390625Hz */
+ 6, /* -> 781250Hz */
+ 3, /* -> 6250000Hz */
+ 2 /* -> 12500000Hz */
+ }
+};
+
+
+
+static const spi_conf_t spi_config[] = {
+ {
+ .dev = SPI1,
+ .mosi_pin = GPIO_PIN(PORT_A, 7),
+ .miso_pin = GPIO_PIN(PORT_A, 6),
+ .sclk_pin = GPIO_PIN(PORT_A, 5),
+ .cs_pin = GPIO_PIN(PORT_A, 4),
+ .af = GPIO_AF5,
+ .rccmask = RCC_APB2ENR_SPI1EN,
+ .apbbus = APB2
+ }
+};
+
+#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+
+/**
+ * @name I2C configuration
+ * @{
+ */
+#define I2C_NUMOF (1U)
+#define I2C_0_EN 1
+#define I2C_IRQ_PRIO 1
+#define I2C_APBCLK (42000000U)
+
+/* I2C 0 device configuration */
+#define I2C_0_DEV I2C1
+#define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
+#define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
+#define I2C_0_EVT_IRQ I2C1_EV_IRQn
+#define I2C_0_EVT_ISR isr_i2c1_ev
+#define I2C_0_ERR_IRQ I2C1_ER_IRQn
+#define I2C_0_ERR_ISR isr_i2c1_er
+/* I2C 0 pin configuration */
+#define I2C_0_SCL_PORT GPIOB
+#define I2C_0_SCL_PIN 8
+#define I2C_0_SCL_AF 4
+#define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
+#define I2C_0_SDA_PORT GPIOB
+#define I2C_0_SDA_PIN 9
+#define I2C_0_SDA_AF 4
+#define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
+/** @} */
+
+/**
+ * @name ADC configuration
+ * @{
+ */
+#define ADC_NUMOF (0)
+/** @} */
+
+/**
+ * @name DAC configuration
+ * @{
+ */
+#define DAC_NUMOF (0)
+/** @} */
+
+/**
+ * @name RTC configuration
+ * @{
+ */
+#define RTC_NUMOF (1)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */