From fc9a853c20212e8ca18e6bf9969b79d9f0a1c99c Mon Sep 17 00:00:00 2001
From: Alexandre Abadie <alexandre.abadie@inria.fr>
Date: Sun, 1 Apr 2018 17:41:34 +0200
Subject: [PATCH] cpu/stm32l0: add definitions for internal eeprom
---
cpu/stm32l0/Makefile.features | 1 +
cpu/stm32l0/include/cpu_conf.h | 14 ++++++++++++++
2 files changed, 15 insertions(+)
diff --git a/cpu/stm32l0/Makefile.features b/cpu/stm32l0/Makefile.features
index d24cf4c8db..79346e3fde 100644
--- a/cpu/stm32l0/Makefile.features
+++ b/cpu/stm32l0/Makefile.features
@@ -1,6 +1,7 @@
FEATURES_PROVIDED += periph_flash_common
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
+FEATURES_PROVIDED += periph_eeprom
FEATURES_PROVIDED += periph_hwrng
BOARDS_WITHOUT_HWRNG += nucleo-l031k6
diff --git a/cpu/stm32l0/include/cpu_conf.h b/cpu/stm32l0/include/cpu_conf.h
index d8cb2b5ed4..bae780aef6 100644
--- a/cpu/stm32l0/include/cpu_conf.h
+++ b/cpu/stm32l0/include/cpu_conf.h
@@ -79,6 +79,20 @@ extern "C" {
#define FLASHPAGE_RAW_ALIGNMENT (4U)
/** @} */
+/**
+ * @name EEPROM configuration
+ * @{
+ */
+#define EEPROM_START_ADDR (0x08080000)
+#if defined(CPU_MODEL_STM32L073RZ) || defined(CPU_MODEL_STM32L072CZ)
+#define EEPROM_SIZE (6144U) /* 6kB */
+#elif defined(CPU_MODEL_STM32L053R8)
+#define EEPROM_SIZE (2048U) /* 2kB */
+#elif defined(CPU_MODEL_STM32L031K6)
+#define EEPROM_SIZE (1024U) /* 1kB */
+#endif
+/** @} */
+
#ifdef __cplusplus
}
#endif
--
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