diff --git a/boards/f4vi1/include/periph_conf.h b/boards/f4vi1/include/periph_conf.h
index ccf2dbb455e19bab305584fd905357d9ae91a8fa..1722444c1d5de12b4fc41b576a158e46de5837d1 100644
--- a/boards/f4vi1/include/periph_conf.h
+++ b/boards/f4vi1/include/periph_conf.h
@@ -28,25 +28,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 168MHz */
+#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 168MHz */
-#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (8)
+#define CLOCK_PLL_N (168)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (7)
/** @} */
/**
diff --git a/boards/msbiot/include/periph_conf.h b/boards/msbiot/include/periph_conf.h
index e3045332e6391e7f726c1e092937d9c77fadc132..52629ab8d4a915f10d9e882027a1de25fa3bc162 100644
--- a/boards/msbiot/include/periph_conf.h
+++ b/boards/msbiot/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 168MHz */
+#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 168MHz */
-#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (8)
+#define CLOCK_PLL_N (168)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (7)
/** @} */
/**
diff --git a/boards/nucleo-f401/include/periph_conf.h b/boards/nucleo-f401/include/periph_conf.h
index ae5ce5ccfbfea82d5b2b6b5f589393265353cf32..6bcfe0c61076a9b9fb398bdee8a6703575cda8b1 100644
--- a/boards/nucleo-f401/include/periph_conf.h
+++ b/boards/nucleo-f401/include/periph_conf.h
@@ -26,27 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 84MHz */
+#define CLOCK_CORECLOCK (84000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 84MHz */
-#define CLOCK_CORECLOCK (84000000U)
-/* PLL Output divisor */
-#define P (4U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (168)
+#define CLOCK_PLL_P (4)
+#define CLOCK_PLL_Q (7)
/** @} */
/**
diff --git a/boards/nucleo-f410/include/periph_conf.h b/boards/nucleo-f410/include/periph_conf.h
index 1f2f29edb86e7a8f31dcdd4fcd7069675748535c..0c8fb5a590c5b8d558bcaef586e59be154660a3c 100644
--- a/boards/nucleo-f410/include/periph_conf.h
+++ b/boards/nucleo-f410/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 100MHz */
+#define CLOCK_CORECLOCK (96000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (192)
+#define CLOCK_PLL_P (4)
+#define CLOCK_PLL_Q (8)
/** @} */
/**
@@ -119,19 +128,19 @@ static const uart_conf_t uart_config[] = {
* @{
*/
static const uint8_t spi_divtable[2][5] = {
- { /* for APB1 @ 50000000Hz */
- 7, /* -> 195312Hz */
- 6, /* -> 390625Hz */
- 5, /* -> 781250Hz */
- 2, /* -> 6250000Hz */
- 1 /* -> 12500000Hz */
+ { /* for APB1 @ 48000000Hz */
+ 7, /* -> 187500Hz */
+ 6, /* -> 375000Hz */
+ 5, /* -> 750000Hz */
+ 2, /* -> 6000000Hz */
+ 1 /* -> 12000000Hz */
},
- { /* for APB2 @ 100000000Hz */
- 7, /* -> 390625Hz */
- 7, /* -> 390625Hz */
- 6, /* -> 781250Hz */
- 3, /* -> 6250000Hz */
- 2 /* -> 12500000Hz */
+ { /* for APB2 @ 96000000Hz */
+ 7, /* -> 375000Hz */
+ 7, /* -> 375000Hz */
+ 6, /* -> 750000Hz */
+ 3, /* -> 6000000Hz */
+ 2 /* -> 12000000Hz */
}
};
diff --git a/boards/nucleo-f411/include/periph_conf.h b/boards/nucleo-f411/include/periph_conf.h
index 4ce6b7fb125152187e35a4a9e62be4c4dccee0fb..05077cc2c862bc4df168ce087e2a6973909cbc57 100644
--- a/boards/nucleo-f411/include/periph_conf.h
+++ b/boards/nucleo-f411/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 100MHz */
+#define CLOCK_CORECLOCK (96000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (192)
+#define CLOCK_PLL_P (4)
+#define CLOCK_PLL_Q (8)
/** @} */
/**
@@ -165,19 +174,19 @@ static const pwm_conf_t pwm_config[] = {
* @{
*/
static const uint8_t spi_divtable[2][5] = {
- { /* for APB1 @ 50000000Hz */
- 7, /* -> 195312Hz */
- 6, /* -> 390625Hz */
- 5, /* -> 781250Hz */
- 2, /* -> 6250000Hz */
- 1 /* -> 12500000Hz */
+ { /* for APB1 @ 48000000Hz */
+ 7, /* -> 187500Hz */
+ 6, /* -> 375000Hz */
+ 5, /* -> 750000Hz */
+ 2, /* -> 6000000Hz */
+ 1 /* -> 12000000Hz */
},
- { /* for APB2 @ 100000000Hz */
- 7, /* -> 390625Hz */
- 7, /* -> 390625Hz */
- 6, /* -> 781250Hz */
- 3, /* -> 6250000Hz */
- 2 /* -> 12500000Hz */
+ { /* for APB2 @ 96000000Hz */
+ 7, /* -> 375000Hz */
+ 7, /* -> 375000Hz */
+ 6, /* -> 750000Hz */
+ 3, /* -> 6000000Hz */
+ 2 /* -> 12000000Hz */
}
};
diff --git a/boards/nucleo-f446/include/periph_conf.h b/boards/nucleo-f446/include/periph_conf.h
index 62ba179169ec741a02ea3f6c7ee306a6c044c9e5..2ce1f9526ad5eb0ef99bfb73dd20e62e1773ad86 100644
--- a/boards/nucleo-f446/include/periph_conf.h
+++ b/boards/nucleo-f446/include/periph_conf.h
@@ -26,25 +26,44 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 180MHz */
+#define CLOCK_CORECLOCK (180000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 180MHz */
-#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (180)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (0)
+
+/* PLL SAI configuration */
+#define CLOCK_ENABLE_PLL_SAI (1)
+#define CLOCK_PLL_SAI_M (4)
+#define CLOCK_PLL_SAI_N (192)
+#define CLOCK_PLL_SAI_P (8)
+#define CLOCK_PLL_SAI_Q (0)
+
+/* Use alternative source for 48MHz clock */
+#define CLOCK_USE_ALT_48MHZ (1)
/** @} */
/**
diff --git a/boards/nucleo144-f207/include/periph_conf.h b/boards/nucleo144-f207/include/periph_conf.h
index 47b12acd23ceccfc7145cb623625ab30e2db1488..9735c5d2cbd363a48208f5dab7996026102819d5 100644
--- a/boards/nucleo144-f207/include/periph_conf.h
+++ b/boards/nucleo144-f207/include/periph_conf.h
@@ -28,25 +28,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 120MHz */
+#define CLOCK_CORECLOCK (120000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 120MHz */
-#define CLOCK_CORECLOCK (120000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (120)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (5)
/** @} */
/**
diff --git a/boards/nucleo144-f412/include/periph_conf.h b/boards/nucleo144-f412/include/periph_conf.h
index 842baa7fb2ad440e7e27b3408c83c7df0507d893..980ebd06299322984baa6e7b2877d488ff92d5ae 100644
--- a/boards/nucleo144-f412/include/periph_conf.h
+++ b/boards/nucleo144-f412/include/periph_conf.h
@@ -28,25 +28,45 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 100MHz */
+#define CLOCK_CORECLOCK (100000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (200)
+#define CLOCK_PLL_P (4)
+#define CLOCK_PLL_Q (0)
+
+/* PLL I2S configuration */
+#define CLOCK_ENABLE_PLL_I2S (1)
+#define CLOCK_PLL_I2S_SRC (0)
+#define CLOCK_PLL_I2S_M (4)
+#define CLOCK_PLL_I2S_N (216)
+#define CLOCK_PLL_I2S_P (0)
+#define CLOCK_PLL_I2S_Q (9)
+
+/* Use alternative source for 48MHz clock */
+#define CLOCK_USE_ALT_48MHZ (1)
/** @} */
/**
diff --git a/boards/nucleo144-f413/include/periph_conf.h b/boards/nucleo144-f413/include/periph_conf.h
index c47822189064f2bdff2e0304bdb2e8b5af11b166..69d4aed14da0823ff91b7594423bec60918f6dcf 100644
--- a/boards/nucleo144-f413/include/periph_conf.h
+++ b/boards/nucleo144-f413/include/periph_conf.h
@@ -28,25 +28,45 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 100MHz */
+#define CLOCK_CORECLOCK (100000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (96000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (200)
+#define CLOCK_PLL_P (4)
+#define CLOCK_PLL_Q (0)
+
+/* PLL I2S configuration */
+#define CLOCK_ENABLE_PLL_I2S (1)
+#define CLOCK_PLL_I2S_SRC (0)
+#define CLOCK_PLL_I2S_M (4)
+#define CLOCK_PLL_I2S_N (216)
+#define CLOCK_PLL_I2S_P (0)
+#define CLOCK_PLL_I2S_Q (9)
+
+/* Use alternative source for 48MHz clock */
+#define CLOCK_USE_ALT_48MHZ (1)
/** @} */
/**
diff --git a/boards/nucleo144-f429/include/periph_conf.h b/boards/nucleo144-f429/include/periph_conf.h
index 3679d69232bfb73378dbf86c576d33f8a32db88b..230793cbc20c72e308dd86b610aa62f53adf61ad 100644
--- a/boards/nucleo144-f429/include/periph_conf.h
+++ b/boards/nucleo144-f429/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 180MHz */
+#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 180MHz */
-#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (168)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (7)
/** @} */
/**
diff --git a/boards/nucleo144-f446/include/periph_conf.h b/boards/nucleo144-f446/include/periph_conf.h
index 70905380ed220bd9230fee6087193d5825c8c83d..56d42da52d548714417e061a690a6a056bec9c96 100644
--- a/boards/nucleo144-f446/include/periph_conf.h
+++ b/boards/nucleo144-f446/include/periph_conf.h
@@ -26,25 +26,44 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 180MHz */
+#define CLOCK_CORECLOCK (180000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 100MHz */
-#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (180)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (0)
+
+/* PLL SAI configuration */
+#define CLOCK_ENABLE_PLL_SAI (1)
+#define CLOCK_PLL_SAI_M (4)
+#define CLOCK_PLL_SAI_N (192)
+#define CLOCK_PLL_SAI_P (8)
+#define CLOCK_PLL_SAI_Q (0)
+
+/* Use alternative source for 48MHz clock */
+#define CLOCK_USE_ALT_48MHZ (1)
/** @} */
/**
diff --git a/boards/nucleo144-f722/include/periph_conf.h b/boards/nucleo144-f722/include/periph_conf.h
index e93c86811aae5c1e6ab790f8b21ba2c140d3b344..67f6b9cc816480bddbc68e201f36cd52d3fbb1dc 100644
--- a/boards/nucleo144-f722/include/periph_conf.h
+++ b/boards/nucleo144-f722/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 216MHz */
+#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
-#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (216)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (9)
/** @} */
/**
diff --git a/boards/nucleo144-f746/include/periph_conf.h b/boards/nucleo144-f746/include/periph_conf.h
index 46cc3540c6af1332cc309ad7bc995335450bd83c..b74fc078067b715c5431f498968254390b8c6c4b 100644
--- a/boards/nucleo144-f746/include/periph_conf.h
+++ b/boards/nucleo144-f746/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 216MHz */
+#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
-#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (216)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (9)
/** @} */
/**
diff --git a/boards/nucleo144-f767/include/periph_conf.h b/boards/nucleo144-f767/include/periph_conf.h
index 0242bc2c45a206471b8d991700e527e193290205..ec67f3c8a820f054b3be2c518e5f7013960bdb24 100644
--- a/boards/nucleo144-f767/include/periph_conf.h
+++ b/boards/nucleo144-f767/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 216MHz */
+#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
-#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (216)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (9)
/** @} */
/**
diff --git a/boards/stm32f4discovery/include/periph_conf.h b/boards/stm32f4discovery/include/periph_conf.h
index c1ab8c8afb8e66bf5ebdfb209c75b80bfd8ca2ab..9bc1f93e2d2b2f1b682b358d5cdb7539d8033694 100644
--- a/boards/stm32f4discovery/include/periph_conf.h
+++ b/boards/stm32f4discovery/include/periph_conf.h
@@ -27,25 +27,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 168MHz */
+#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 168MHz */
-#define CLOCK_CORECLOCK (168000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (4)
+#define CLOCK_PLL_N (168)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (7)
/** @} */
/**
diff --git a/boards/stm32f7discovery/include/periph_conf.h b/boards/stm32f7discovery/include/periph_conf.h
index 95eaaf5f986dec11500681fe35eb3582a23b10f5..759d56acedc99891ade0c4ece6467280c0122e18 100644
--- a/boards/stm32f7discovery/include/periph_conf.h
+++ b/boards/stm32f7discovery/include/periph_conf.h
@@ -26,25 +26,34 @@ extern "C" {
#endif
/**
- * @name Clock system configuration
+ * @name Clock settings
+ *
+ * @note This is auto-generated from
+ * `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
+/* give the target core clock (HCLK) frequency [in Hz],
+ * maximum: 216MHz */
+#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (25000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
-/* give the target core clock (HCLK) frequency [in Hz],
- * maximum: 216MHz, min: 96MHz, must be multiple of 48MHz */
-#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */
-#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
+#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
+
+/* Main PLL factors */
+#define CLOCK_PLL_M (25)
+#define CLOCK_PLL_N (432)
+#define CLOCK_PLL_P (2)
+#define CLOCK_PLL_Q (9)
/** @} */
/**