dw1000: Reworked driver regarding to the offical one from decawave, working...

dw1000: Reworked driver regarding to the offical one from decawave, working only with the first trace_printf in ISR

Inc/dw1000.h

-
 #ifndef __dw1000_H
 #define __dw1000_H
-
+#include "FreeRTOS.h"
 #include <stdint.h>
+//DECA:DW1000 SLEEP and WAKEUP configuration parameters
+#define DWT_LOADLDO              0x1000                                          // ONW_LLDO - on wakeup load the LDO tune value
+#define DWT_LOADUCODE    0x0800                      // ONW_LLDE - on wakeup load the LDE ucode
+#define DWT_PRESRV_SLEEP 0x0100                      // PRES_SLEEP - on wakeup preserve sleep bit
+#define DWT_LOADOPSET    0x0080                                          // ONW_L64P - on wakeup load operating parameter set for 64 PSR
+#define DWT_CONFIG       0x0040                                          // ONW_LDC - on wakeup restore (load) the saved configurations (from AON array into HIF)
+#define DWT_TANDV        0x0001                      // ONW_RADC - on wakeup run ADC to sample temperature and voltage sensor values
+
+#define DWT_XTAL_EN              0x10                                           // keep XTAL running during sleep
+#define DWT_WAKE_SLPCNT  0x8                                            // wake up after sleep count
+#define DWT_WAKE_CS      0x4                                            // wake up on chip select
+#define DWT_WAKE_WK      0x2                                            // wake up on WAKEUP PIN
+#define DWT_SLP_EN       0x1                                            // enable sleep/deep sleep functionality
+
+//DECA:DW1000 INIT configuration parameters
+#define DWT_LOADLDOTUNE   0x8
+#define DWT_LOADTXCONFIG  0x4
+#define DWT_LOADANTDLY    0x2
+#define DWT_LOADXTALTRIM  0x1
+#define DWT_LOADNONE      0x0
+
+//DECA:DW1000 OTP operating parameter set selection
+#define DWT_OPSET_64LEN   0x0
+#define DWT_OPSET_TIGHT   0x1
+#define DWT_OPSET_DEFLT   0x2
+
+#define DWT_SFDTOC_DEF				0x1041	// default SFD timeout value
+
+#define DWT_PHRMODE_STD				0x0		// standard PHR mode 
+#define DWT_PHRMODE_EXT				0x3		// DW proprietary extended frames PHR mode
+
+//! constants for selecting the bit rate for data TX (and RX)
+//! These are defined for write (with just a shift) the TX_FCTRL register
+#define DWT_BR_110K		0	//!< UWB bit rate 110 kbits/s
+#define DWT_BR_850K		1	//!< UWB bit rate 850 kbits/s
+#define DWT_BR_6M8		2	//!< UWB bit rate 6.8 Mbits/s
+
+//! constants for specifying the (Nominal) mean Pulse Repetition Frequency
+//! These are defined for direct write (with a shift if necessary) to CHAN_CTRL and TX_FCTRL regs
+#define DWT_PRF_16M		1	//!< UWB PRF 16 MHz
+#define DWT_PRF_64M		2	//!< UWB PRF 64 MHz
+
+//! constants for specifying Preamble Acquisition Chunk (PAC) Size in symbols
+#define DWT_PAC8		0	//!< PAC  8 (recommended for RX of preamble length  128 and below
+#define DWT_PAC16		1	//!< PAC 16 (recommended for RX of preamble length  256
+#define DWT_PAC32		2	//!< PAC 32 (recommended for RX of preamble length  512
+#define DWT_PAC64		3	//!< PAC 64 (recommended for RX of preamble length 1024 and up
+
+
+//! constants for specifying TX Preamble length in symbols
+//! These are defined to allow them be directly written into byte 2 of the TX_FCTRL register
+//! (i.e. a four bit value destined for bits 20..18 but shifted left by 2 for byte alignment)
+#define DWT_PLEN_4096	0x0C	//! Standard preamble length 4096 symbols
+#define DWT_PLEN_2048	0x28	//! Non-standard preamble length 2048 symbols
+#define DWT_PLEN_1536	0x18	//! Non-standard preamble length 1536 symbols
+#define DWT_PLEN_1024	0x08	//! Standard preamble length 1024 symbols
+#define DWT_PLEN_512	0x34	//! Non-standard preamble length 512 symbols
+#define DWT_PLEN_256	0x24	//! Non-standard preamble length 256 symbols
+#define DWT_PLEN_128	0x14	//! Non-standard preamble length 128 symbols
+#define DWT_PLEN_64		0x04	//! Standard preamble length 64 symbols
+typedef struct {
+	uint8_t chan;          //!< channel number {1, 2, 3, 4, 5, 7 }
+	uint8_t prf;      //!< Pulse Repetition Frequency {DWT_PRF_16M or DWT_PRF_64M}
+
+	uint8_t txPreambLength;   //!< DWT_PLEN_64..DWT_PLEN_4096
+	uint8_t rxPAC;     //!< Acquisition Chunk Size (Relates to RX preamble length)
+
+	uint8_t txCode;        //!< TX preamble code
+	uint8_t rxCode;        //!< RX preamble code
+
+	uint8_t nsSFD; //!< Boolean should we use non-standard SFD for better performance
+	uint8_t dataRate;      //!< Data Rate {DWT_BR_110K, DWT_BR_850K or DWT_BR_6M8}
+
+	uint8_t phrMode; //!< PHR mode {0x0 - standard DWT_PHRMODE_STD, 0x3 - extended frames DWT_PHRMODE_EXT}
+
+	uint8_t smartPowerEn;  //!< Smart Power enable / disable
+
+	uint16_t sfdTO;                  //!< SFD timeout value (in symbols)
+
+}dwt_config_t;
 
+int dw1000_init(uint16_t config, BaseType_t (*sendCallback)(),
+		BaseType_t (*receiveCallback)(uint32_t bufferLength));
+int dw1000_configure(dwt_config_t *config, uint8_t use_otpconfigvalues);
 int dw1000_sendFrame(uint8_t *payload, uint16_t len);
+int dw_1000_receiveFrameFromIsr(uint8_t * buffer, uint32_t length);
+void dw1000_extiCallback(void);
 
 #endif /*__ dw1000_H */

Inc/dw1000_hal.h

@@ -3,7 +3,6 @@
 #define __dw1000_hal_H
 #include "FreeRTOS.h"
 #include "task.h"
-extern TaskHandle_t xHandleDW1000HAL;
 
 #define DW1000HAL_SPI_TIMEOUT 10
 
@@ -11,14 +10,13 @@ extern TaskHandle_t xHandleDW1000HAL;
 #define DW1000HAL_SS_GPIO GPIOB
 
 #include <stdint.h>
-
+void dw1000Hal_init(void);
 int dw1000Hal_readSubRegister(uint8_t regID, uint16_t offset, uint8_t *dest, uint16_t len);
 int dw1000Hal_writeSubRegister(uint8_t regID, uint16_t offset, uint8_t *src, uint16_t len);
 int dw1000Hal_readRegister(uint8_t regID, uint8_t *dest, uint16_t len);
 int dw1000Hal_writeRegister(uint8_t regID, uint8_t *src, uint16_t len);
+int dw1000Hal_readRegisterFromIsr(uint8_t regID, uint8_t *dest, uint16_t len);
+int dw1000Hal_writeRegisterFromIsr(uint8_t regID, uint8_t *dest, uint16_t len);
 int dw1000Hal_readDmaRegister(uint8_t regID, uint8_t *dest, uint16_t len, void (*callback)(int state, void *data, uint16_t len));
 int dw1000Hal_writeDmaRegister(uint8_t regID, uint8_t *src, uint16_t len, void (*callback)(int state, void *data, uint16_t len));
-
-void vTaskDW1000HAL(void *pvParameters);
-void dw1000Hal_extiCallback(void);
 #endif /*__ dw1000_hal_H */

Inc/dw1000_isr.h

+#ifndef __dw1000_isr_H
+#define __dw1000_isr_H
+#include "FreeRTOS.h"
+#include <stdint.h>
+
+
+void dw1000Isr_handleInterrupt(void);
+#endif /*__ dw1000_isr_H */

Inc/dw1000_util.h

+#ifndef __dw1000_util_H
+#define __dw1000_util_H
+#include "FreeRTOS.h"
+#include <stdint.h>
+#include "deca_regs.h"
+
+
+//DECA:Defines for enable_clocks function
+#define FORCE_SYS_XTI  0
+#define ENABLE_ALL_SEQ 1
+#define FORCE_SYS_PLL  2
+#define READ_ACC_ON    7
+#define READ_ACC_OFF   8
+#define FORCE_OTP_ON   11
+#define FORCE_OTP_OFF  12
+#define FORCE_TX_PLL   13
+
+#define PEAK_MULTPLIER (0x60)	//3 -> (0x3 * 32) & 0x00E0 
+#define N_STD_FACTOR (13)
+#define LDE_PARAM1		(PEAK_MULTPLIER | N_STD_FACTOR)
+
+#define LDE_PARAM3_16 (0x1607)
+#define LDE_PARAM3_64 (0x0607)
+
+#define NUM_BR 3
+#define NUM_PRF 2
+#define NUM_PACS 4
+#define NUM_BW 2 //2 bandwidths are supported
+#define NUM_SFD 2	//supported number of SFDs - standard = 0, non-standard = 1
+#define NUM_CH 6 //supported channels are 1, 2, 3, 4, 5, 7
+#define NUM_CH_SUPPORTED 8 //supported channels are '0', 1, 2, 3, 4, 5, '6', 7
+#define PCODES 25 //supported preamble codes
+
+typedef struct {//DECA
+	uint32_t 	txFCTRL;           	// keep TX_FCTRL register config
+	uint16_t 	rfrxDly; 			// rf delay (delay though the RF blocks before the signal comes out of the antenna i.e. "antenna delay")
+	uint16_t 	rftxDly; 			// rf delay (delay though the RF blocks before the signal comes out of the antenna i.e. "antenna delay")
+	uint32_t 	antennaDly; 		// antenna delay read from OTP 64 PRF value is in high 16 bits and 16M PRF in low 16 bits
+	uint8_t 	xtrim;              // xtrim value read from OTP
+	uint8_t 	dblbuffon;          // double rx buffer mode flag
+	uint32_t 	sysCFGreg;         	// local copy of system config register
+	uint32_t 	txPowCfg[12]; 		// stores the Tx power configuration read from OTP (6 channels consecutively with PRF16 then 64, e.g. Ch 1 PRF16 is index 0 and 64 index 1)
+	BaseType_t (*sendCB)();
+	BaseType_t (*receiveCB)(uint32_t bufferLength);
+	int 		prfIndex;
+    uint8_t       longFrames ;        // flag in non-standard long frame mode
+	uint32_t 	ldoTune;			//low 32 bits of LDO tune value
+    uint8_t       chan;               // added chan here - used in the reading of acc
+
+} dw1000_local_data_t;
+extern dw1000_local_data_t dw1000local; // Static local device data
+
+
+extern const uint8_t pll2calcfg;
+
+// SFD Threshold
+extern const uint16_t sftsh[NUM_BR][NUM_SFD];
+
+extern const uint16_t dtune1[NUM_PRF];
+//-----------------------------------------
+// map the channel number to the index in the configuration arrays below
+// 0th element is chan 1, 1st is chan 2, 2nd is chan 3, 3rd is chan 4, 4th is chan 5, 5th is chan 7
+extern const uint8_t chan_idx[NUM_CH_SUPPORTED];
+
+extern const uint32_t tx_config[NUM_CH] ;
+
+extern const uint8_t pll2_config[NUM_CH][5];
+
+//bandwidth configuration
+extern const uint8_t rx_config[NUM_BW];
+
+extern const uint8_t dwnsSFDlen[NUM_BR]; //DW non-standard SFD length for 110k, 850k and 6.81M
+
+extern const uint32_t digital_bb_config[NUM_PRF][NUM_PACS];
+
+extern const uint16_t lde_replicaCoeff[PCODES];
+
+
+#define DEBUG
+
+
+
+void dw1000Util_enableclocks(int clocks);
+void dw1000Util_enableRX();
+uint32_t dw1000Util_otpread(uint32_t address);
+void dw1000Util_forceTrxOff(void);
+void dw1000Util_reset(void);
+void dw1000Util_resetRxOnly(void);
+
+
+#ifdef DEBUG
+void hexdump(uint8_t * buffer, uint8_t len);
+#endif
+
+#endif /*__ dw1000_util_H */