Merge pull request #6025 from aabadie/nucleo_f410

boards/nucleo-f410: initial support

boards/nucleo-f410/Makefile

+MODULE = board
+
+include $(RIOTBASE)/Makefile.base

boards/nucleo-f410/Makefile.dep

+include $(RIOTBOARD)/nucleo-common/Makefile.dep

boards/nucleo-f410/Makefile.features

+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_hwrng
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Various other features (if any)
+FEATURES_PROVIDED += cpp
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = cortex_m4_3

boards/nucleo-f410/Makefile.include

+# define the cpu used by the nucleo-f401 board
+export CPU = stm32f4
+export CPU_MODEL = stm32f410rb
+
+# load the common Makefile.include for Nucleo boards
+include $(RIOTBOARD)/nucleo-common/Makefile.include

boards/nucleo-f410/board.c

+/*
+ * Copyright (C) 2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nucleo-f410
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations for the nucleo-f410 board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ *
+ * @}
+ */
+
+#include "board.h"
+#include "periph/gpio.h"
+
+void board_init(void)
+{
+    /* initialize the CPU */
+    cpu_init();
+
+    /* initialize the boards LEDs */
+    gpio_init(LED0_PIN, GPIO_OUT);
+}

boards/nucleo-f410/dist/openocd.cfg

+source [find board/st_nucleo_f4.cfg]

boards/nucleo-f410/include/board.h

+/*
+ * Copyright (C) 2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @defgroup    boards_nucleo-f410 Nucleo-F410
+ * @ingroup     boards
+ * @brief       Board specific files for the nucleo-f410 board
+ * @{
+ *
+ * @file
+ * @brief       Board specific definitions for the nucleo-f410 board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include "board_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name xtimer configuration
+ * @{
+ */
+#define XTIMER_DEV          TIMER_DEV(0)
+#define XTIMER_CHAN         (0)
+#define XTIMER_OVERHEAD     (6)
+#define XTIMER_BACKOFF      (5)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */

boards/nucleo-f410/include/periph_conf.h

+/*
+ * Copyright (C) 2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nucleo-f410
+ * @{
+ *
+ * @file
+ * @name        Peripheral MCU configuration for the nucleo-f410 board
+ *
+ * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+#define CLOCK_HSE           (8000000U)           /* external oscillator */
+#define CLOCK_CORECLOCK     (100000000U)         /* desired core clock frequency */
+
+/* the actual PLL values are automatically generated */
+#define CLOCK_PLL_M         (CLOCK_HSE / 1000000)
+#define CLOCK_PLL_N         ((CLOCK_CORECLOCK / 1000000) * 2)
+#define CLOCK_PLL_P         (2U)
+#define CLOCK_PLL_Q         (CLOCK_PLL_N / 48)
+#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
+#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2
+#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
+
+/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
+#define CLOCK_AHB           (CLOCK_CORECLOCK / 1)
+#define CLOCK_APB1          (CLOCK_CORECLOCK / 2)
+#define CLOCK_APB2          (CLOCK_CORECLOCK / 1)
+/** @} */
+
+/**
+ * @name Timer configuration
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIM5,
+        .max      = 0xffffffff,
+        .rcc_mask = RCC_APB1ENR_TIM5EN,
+        .bus      = APB1,
+        .irqn     = TIM5_IRQn
+    }
+};
+
+#define TIMER_0_ISR         isr_tim5
+
+#define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
+/** @} */
+
+/**
+ * @name   UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {
+        .dev        = USART2,
+        .rcc_mask   = RCC_APB1ENR_USART2EN,
+        .rx_pin     = GPIO_PIN(PORT_A, 3),
+        .tx_pin     = GPIO_PIN(PORT_A, 2),
+        .rx_af      = GPIO_AF7,
+        .tx_af      = GPIO_AF7,
+        .bus        = APB1,
+        .irqn       = USART2_IRQn,
+#ifdef UART_USE_DMA
+        .dma_stream = 6,
+        .dma_chan   = 4
+#endif
+    },
+    {
+        .dev        = USART1,
+        .rcc_mask   = RCC_APB2ENR_USART1EN,
+        .rx_pin     = GPIO_PIN(PORT_A, 10),
+        .tx_pin     = GPIO_PIN(PORT_A, 9),
+        .rx_af      = GPIO_AF7,
+        .tx_af      = GPIO_AF7,
+        .bus        = APB2,
+        .irqn       = USART1_IRQn,
+#ifdef UART_USE_DMA
+        .dma_stream = 5,
+        .dma_chan   = 4
+#endif
+    }
+};
+
+/* assign ISR vector names */
+#define UART_0_ISR          (isr_usart2)
+#define UART_0_DMA_ISR      (isr_dma1_stream6)
+#define UART_1_ISR          (isr_usart1)
+#define UART_1_DMA_ISR      (isr_dma1_stream5)
+
+/* deduct number of defined UART interfaces */
+#define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
+/** @} */
+
+/**
+ * @name   SPI configuration
+ *
+ * @note    The spi_divtable is auto-generated from
+ *          `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
+ * @{
+ */
+static const uint8_t spi_divtable[2][5] = {
+    {       /* for APB1 @ 50000000Hz */
+        7,  /* -> 195312Hz */
+        6,  /* -> 390625Hz */
+        5,  /* -> 781250Hz */
+        2,  /* -> 6250000Hz */
+        1   /* -> 12500000Hz */
+    },
+    {       /* for APB2 @ 100000000Hz */
+        7,  /* -> 390625Hz */
+        7,  /* -> 390625Hz */
+        6,  /* -> 781250Hz */
+        3,  /* -> 6250000Hz */
+        2   /* -> 12500000Hz */
+    }
+};
+
+static const spi_conf_t spi_config[] = {
+    {
+        .dev      = SPI1,
+        .mosi_pin = GPIO_PIN(PORT_A, 7),
+        .miso_pin = GPIO_PIN(PORT_A, 6),
+        .sclk_pin = GPIO_PIN(PORT_A, 5),
+        .cs_pin   = GPIO_PIN(PORT_A, 4),
+        .af       = GPIO_AF5,
+        .rccmask  = RCC_APB2ENR_SPI1EN,
+        .apbbus   = APB2
+    }
+};
+
+#define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
+/** @} */
+
+/**
+ * @name I2C configuration
+ * @{
+ */
+#define I2C_NUMOF           (1U)
+#define I2C_0_EN            1
+#define I2C_IRQ_PRIO        1
+#define I2C_APBCLK          (42000000U)
+
+/* I2C 0 device configuration */
+#define I2C_0_DEV           I2C1
+#define I2C_0_CLKEN()       (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
+#define I2C_0_CLKDIS()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define I2C_0_EVT_IRQ       I2C1_EV_IRQn
+#define I2C_0_EVT_ISR       isr_i2c1_ev
+#define I2C_0_ERR_IRQ       I2C1_ER_IRQn
+#define I2C_0_ERR_ISR       isr_i2c1_er
+/* I2C 0 pin configuration */
+#define I2C_0_SCL_PORT      GPIOB
+#define I2C_0_SCL_PIN       8
+#define I2C_0_SCL_AF        4
+#define I2C_0_SCL_CLKEN()   (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
+#define I2C_0_SDA_PORT      GPIOB
+#define I2C_0_SDA_PIN       9
+#define I2C_0_SDA_AF        4
+#define I2C_0_SDA_CLKEN()   (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
+/** @} */
+
+/**
+ * @name   ADC configuration
+ * @{
+ */
+#define ADC_NUMOF          (0)
+/** @} */
+
+/**
+ * @brief   DAC configuration
+ * @{
+ */
+#define DAC_NUMOF           (0)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */

cpu/stm32_common/cpu_common.c

@@ -59,12 +59,15 @@ void periph_clk_en(bus_t bus, uint32_t mask)
         case AHB1:
             RCC->AHB1ENR |= mask;
             break;
+/* STM32F410 RCC doesn't provide AHB2 and AHB3 */
+#if !defined(CPU_MODEL_STM32F410RB)
         case AHB2:
             RCC->AHB2ENR |= mask;
             break;
         case AHB3:
             RCC->AHB3ENR |= mask;
             break;
+#endif
 #endif
         default:
             DEBUG("unsupported bus %d\n", (int)bus);
@@ -99,12 +102,15 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
         case AHB1:
             RCC->AHB1ENR &= ~(mask);
             break;
+/* STM32F410 RCC doesn't provide AHB2 and AHB3 */
+#if !defined(CPU_MODEL_STM32F410RB)
         case AHB2:
             RCC->AHB2ENR &= ~(mask);
             break;
         case AHB3:
             RCC->AHB3ENR &= ~(mask);
             break;
+#endif
 #endif
         default:
             DEBUG("unsupported bus %d\n", (int)bus);

cpu/stm32f4/include/cpu_conf.h

@@ -27,6 +27,8 @@
 #include "vendor/stm32f401xe.h"
 #elif defined(CPU_MODEL_STM32F407VG)
 #include "vendor/stm32f407xx.h"
+#elif defined(CPU_MODEL_STM32F410RB)
+#include "vendor/stm32f410rx.h"
 #elif defined(CPU_MODEL_STM32F411RE)
 #include "vendor/stm32f411xe.h"
 #elif defined(CPU_MODEL_STM32F413ZH)

cpu/stm32f4/include/periph_cpu.h

@@ -43,7 +43,7 @@ enum {
 /**
  * @brief   Available number of ADC devices
  */
-#if defined(CPU_MODEL_STM32F401RE) || defined(CPU_MODEL_STM32F411RE)|| defined(CPU_MODEL_STM32F413ZH)
+#if defined(CPU_MODEL_STM32F401RE) || defined(CPU_MODEL_STM32F410RB) || defined(CPU_MODEL_STM32F411RE)|| defined(CPU_MODEL_STM32F413ZH)
 #define ADC_DEVS            (1U)
 #elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG) || defined(CPU_MODEL_STM32F446RE)
 #define ADC_DEVS            (3U)

cpu/stm32f4/ldscripts/stm32f410rb.ld

+/*
+ * Copyright (C) 2016 Freie Universität Berlin
+ *               2016 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @addtogroup      cpu_stm32f4
+ * @{
+ *
+ * @file
+ * @brief           Memory definitions for the STM32F410RB
+ *
+ * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
+ * @author          Alexandre Abadie <alexandre.abadie@inria.fr>
+ *
+ * @}
+ */
+
+MEMORY
+{
+    rom (rx)    : ORIGIN = 0x08000000, LENGTH = 128K
+    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 32K
+    cpuid (r)   : ORIGIN = 0x1fff7a10, LENGTH = 12
+}
+
+_cpuid_address = ORIGIN(cpuid);
+
+INCLUDE cortexm_base.ld

cpu/stm32f4/periph/hwrng.c

@@ -36,7 +36,11 @@ void hwrng_read(void *buf, unsigned int num)
     uint8_t *b = (uint8_t *)buf;
 
     /* power on and enable the device */
+#if defined(CPU_MODEL_STM32F410RB)
+    periph_clk_en(AHB1, RCC_AHB1ENR_RNGEN);
+#else
     periph_clk_en(AHB2, RCC_AHB2ENR_RNGEN);
+#endif
     RNG->CR = RNG_CR_RNGEN;
 
     /* get random data */
@@ -54,7 +58,11 @@ void hwrng_read(void *buf, unsigned int num)
 
     /* finally disable the device again */
     RNG->CR = 0;
+#if defined(CPU_MODEL_STM32F410RB)
+    periph_clk_dis(AHB1, RCC_AHB1ENR_RNGEN);
+#else
     periph_clk_dis(AHB2, RCC_AHB2ENR_RNGEN);
+#endif
 }
 
 #endif /* RNG */

tests/unittests/Makefile

@@ -7,10 +7,10 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon arduino-duemilanove arduino-mega2560 \
                              msb-430 msb-430h nrf51dongle nrf6310 nucleo32-f031 \
                              nucleo32-f042 nucleo32-f303 nucleo-f030 nucleo-f070 \
                              nucleo-f072 nucleo-f091 nucleo-f103 nucleo-f334 \
-                             nucleo-l053 nucleo-l073 opencm904 pba-d-01-kw2x \
-                             pca10000 pca10005 remote-pa remote-reva remote-revb \
-                             saml21-xpro samr21-xpro seeeduino_arch-pro slwstk6220a \
-                             sodaq-autonomo spark-core stm32f0discovery \
+                             nucleo-f410 nucleo-l053 nucleo-l073 opencm904 \
+                             pba-d-01-kw2x pca10000 pca10005 remote-pa remote-reva \
+                             remote-revb saml21-xpro samr21-xpro seeeduino_arch-pro \
+                             slwstk6220a sodaq-autonomo spark-core stm32f0discovery \
                              stm32f3discovery telosb waspmote-pro weio wsn430-v1_3b \
                              wsn430-v1_4 yunjia-nrf51822 z1
 
@@ -29,9 +29,9 @@ ARM_CORTEX_M_BOARDS := airfy-beacon arduino-due arduino-zero cc2538dk ek-lm4f120
                        f4vi1 fox frdm-k64f iotlab-m3 limifrog-v1 mbed_lpc1768 msbiot \
                        mulle nrf51dongle nrf6310 nucleo32-f031 nucleo32-f303 \
                        nucleo-f030 nucleo-f070 nucleo-f091 nucleo-f303 nucleo-f334 \
-                       nucleo-f401 nucleo-f411 nucleo-l053 nucleo-l073 nucleo-l1 \
-                       opencm904 openmote-cc2538 pba-d-01-kw2x pca10000 pca10005 \
-                       remote saml21-xpro samr21-xpro slwstk6220a sodaq-autonomo \
+                       nucleo-f401 nucleo-f410 nucleo-f411 nucleo-l053 nucleo-l073 \
+                       nucleo-l1 opencm904 openmote-cc2538 pba-d-01-kw2x pca10000 \
+                       pca10005 remote saml21-xpro samr21-xpro slwstk6220a sodaq-autonomo \
                        spark-core stm32f0discovery stm32f3discovery stm32f4discovery \
                        udoo weio yunjia-nrf51822
 

tests/unittests/tests-relic/Makefile

@@ -4,6 +4,6 @@ MODULE = tests-relic
 BOARD_BLACKLIST := arduino-mega2560 chronos f4vi1 msb-430 msb-430h msbiot \
                    qemu-i386 redbee-econotag stm32f0discovery \
                    stm32f3discovery telosb wsn430-v1_3b wsn430-v1_4 z1 \
-                   waspmote-pro
+                   waspmote-pro nucleo-f410
 
 include $(RIOTBASE)/Makefile.base