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Commit 1e3fdce1 authored by Bas Stottelaar's avatar Bas Stottelaar
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cpu/efm32: efm32lg: add vendor headers

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/**************************************************************************//**
* @file efm32lg990f256.h
* @brief CMSIS Cortex-M Peripheral Access Layer Header File
* for EFM32LG990F256
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
#ifndef EFM32LG990F256_H
#define EFM32LG990F256_H
#ifdef __cplusplus
extern "C" {
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup EFM32LG990F256 EFM32LG990F256
* @{
*****************************************************************************/
/** Interrupt Number Definition */
typedef enum IRQn{
/****** Cortex-M3 Processor Exceptions Numbers ********************************************/
NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
/****** EFM32LG Peripheral Interrupt Numbers **********************************************/
DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
} IRQn_Type;
/**************************************************************************//**
* @defgroup EFM32LG990F256_Core EFM32LG990F256 Core
* @{
* @brief Processor and Core Peripheral Section
*****************************************************************************/
#define __MPU_PRESENT 1 /**< Presence of MPU */
#define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
/** @} End of group EFM32LG990F256_Core */
/**************************************************************************//**
* @defgroup EFM32LG990F256_Part EFM32LG990F256 Part
* @{
******************************************************************************/
/** Part family */
#define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
#define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
#define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
#define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
#define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /**< Silicon Labs internal use only, may change any time */
#define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
#define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
/* If part number is not defined as compiler option, define it */
#if !defined(EFM32LG990F256)
#define EFM32LG990F256 1 /**< Giant/Leopard Gecko Part */
#endif
/** Configure part number */
#define PART_NUMBER "EFM32LG990F256" /**< Part Number */
/** Memory Base addresses and limits */
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
/** Bit banding area */
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
/** Flash and SRAM limits for EFM32LG990F256 */
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
#define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
#define FLASH_PAGE_SIZE 2048U /**< Flash Memory page size */
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
#define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
#define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
#define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
#define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */
/** AF channels connect the different on-chip peripherals with the af-mux */
#define AFCHAN_MAX 163
#define AFCHANLOC_MAX 7
/** Analog AF channels */
#define AFACHAN_MAX 53
/* Part number capabilities */
#define USART_PRESENT /**< USART is available in this part */
#define USART_COUNT 3 /**< 3 USARTs available */
#define UART_PRESENT /**< UART is available in this part */
#define UART_COUNT 2 /**< 2 UARTs available */
#define TIMER_PRESENT /**< TIMER is available in this part */
#define TIMER_COUNT 4 /**< 4 TIMERs available */
#define ACMP_PRESENT /**< ACMP is available in this part */
#define ACMP_COUNT 2 /**< 2 ACMPs available */
#define LEUART_PRESENT /**< LEUART is available in this part */
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
#define LETIMER_PRESENT /**< LETIMER is available in this part */
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
#define PCNT_PRESENT /**< PCNT is available in this part */
#define PCNT_COUNT 3 /**< 3 PCNTs available */
#define I2C_PRESENT /**< I2C is available in this part */
#define I2C_COUNT 2 /**< 2 I2Cs available */
#define ADC_PRESENT /**< ADC is available in this part */
#define ADC_COUNT 1 /**< 1 ADCs available */
#define DAC_PRESENT /**< DAC is available in this part */
#define DAC_COUNT 1 /**< 1 DACs available */
#define DMA_PRESENT /**< DMA is available in this part */
#define DMA_COUNT 1 /**< 1 DMA available */
#define AES_PRESENT /**< AES is available in this part */
#define AES_COUNT 1 /**< 1 AES available */
#define USBC_PRESENT /**< USBC is available in this part */
#define USBC_COUNT 1 /**< 1 USBC available */
#define USB_PRESENT /**< USB is available in this part */
#define USB_COUNT 1 /**< 1 USB available */
#define LE_PRESENT /**< LE is available in this part */
#define LE_COUNT 1 /**< 1 LE available */
#define MSC_PRESENT /**< MSC is available in this part */
#define MSC_COUNT 1 /**< 1 MSC available */
#define EMU_PRESENT /**< EMU is available in this part */
#define EMU_COUNT 1 /**< 1 EMU available */
#define RMU_PRESENT /**< RMU is available in this part */
#define RMU_COUNT 1 /**< 1 RMU available */
#define CMU_PRESENT /**< CMU is available in this part */
#define CMU_COUNT 1 /**< 1 CMU available */
#define LESENSE_PRESENT /**< LESENSE is available in this part */
#define LESENSE_COUNT 1 /**< 1 LESENSE available */
#define EBI_PRESENT /**< EBI is available in this part */
#define EBI_COUNT 1 /**< 1 EBI available */
#define RTC_PRESENT /**< RTC is available in this part */
#define RTC_COUNT 1 /**< 1 RTC available */
#define GPIO_PRESENT /**< GPIO is available in this part */
#define GPIO_COUNT 1 /**< 1 GPIO available */
#define VCMP_PRESENT /**< VCMP is available in this part */
#define VCMP_COUNT 1 /**< 1 VCMP available */
#define PRS_PRESENT /**< PRS is available in this part */
#define PRS_COUNT 1 /**< 1 PRS available */
#define OPAMP_PRESENT /**< OPAMP is available in this part */
#define OPAMP_COUNT 1 /**< 1 OPAMP available */
#define BU_PRESENT /**< BU is available in this part */
#define BU_COUNT 1 /**< 1 BU available */
#define LCD_PRESENT /**< LCD is available in this part */
#define LCD_COUNT 1 /**< 1 LCD available */
#define BURTC_PRESENT /**< BURTC is available in this part */
#define BURTC_COUNT 1 /**< 1 BURTC available */
#define HFXTAL_PRESENT /**< HFXTAL is available in this part */
#define HFXTAL_COUNT 1 /**< 1 HFXTAL available */
#define LFXTAL_PRESENT /**< LFXTAL is available in this part */
#define LFXTAL_COUNT 1 /**< 1 LFXTAL available */
#define WDOG_PRESENT /**< WDOG is available in this part */
#define WDOG_COUNT 1 /**< 1 WDOG available */
#define DBG_PRESENT /**< DBG is available in this part */
#define DBG_COUNT 1 /**< 1 DBG available */
#define ETM_PRESENT /**< ETM is available in this part */
#define ETM_COUNT 1 /**< 1 ETM available */
#define BOOTLOADER_PRESENT /**< BOOTLOADER is available in this part */
#define BOOTLOADER_COUNT 1 /**< 1 BOOTLOADER available */
#define ANALOG_PRESENT /**< ANALOG is available in this part */
#define ANALOG_COUNT 1 /**< 1 ANALOG available */
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
#include "system_efm32lg.h" /* System Header */
/** @} End of group EFM32LG990F256_Part */
/**************************************************************************//**
* @defgroup EFM32LG990F256_Peripheral_TypeDefs EFM32LG990F256 Peripheral TypeDefs
* @{
* @brief Device Specific Peripheral Register Structures
*****************************************************************************/
#include "efm32lg_dma_ch.h"
#include "efm32lg_dma.h"
#include "efm32lg_aes.h"
#include "efm32lg_usb_hc.h"
#include "efm32lg_usb_diep.h"
#include "efm32lg_usb_doep.h"
#include "efm32lg_usb.h"
#include "efm32lg_msc.h"
#include "efm32lg_emu.h"
#include "efm32lg_rmu.h"
#include "efm32lg_cmu.h"
#include "efm32lg_lesense_st.h"
#include "efm32lg_lesense_buf.h"
#include "efm32lg_lesense_ch.h"
#include "efm32lg_lesense.h"
#include "efm32lg_ebi.h"
#include "efm32lg_usart.h"
#include "efm32lg_timer_cc.h"
#include "efm32lg_timer.h"
#include "efm32lg_acmp.h"
#include "efm32lg_leuart.h"
#include "efm32lg_rtc.h"
#include "efm32lg_letimer.h"
#include "efm32lg_pcnt.h"
#include "efm32lg_i2c.h"
#include "efm32lg_gpio_p.h"
#include "efm32lg_gpio.h"
#include "efm32lg_vcmp.h"
#include "efm32lg_prs_ch.h"
#include "efm32lg_prs.h"
#include "efm32lg_adc.h"
#include "efm32lg_dac.h"
#include "efm32lg_lcd.h"
#include "efm32lg_burtc_ret.h"
#include "efm32lg_burtc.h"
#include "efm32lg_wdog.h"
#include "efm32lg_etm.h"
#include "efm32lg_dma_descriptor.h"
#include "efm32lg_devinfo.h"
#include "efm32lg_romtable.h"
#include "efm32lg_calibrate.h"
/** @} End of group EFM32LG990F256_Peripheral_TypeDefs */
/**************************************************************************//**
* @defgroup EFM32LG990F256_Peripheral_Base EFM32LG990F256 Peripheral Memory Map
* @{
*****************************************************************************/
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
#define AES_BASE (0x400E0000UL) /**< AES base address */
#define USB_BASE (0x400C4000UL) /**< USB base address */
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
#define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
#define EBI_BASE (0x40008000UL) /**< EBI base address */
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
#define UART1_BASE (0x4000E400UL) /**< UART1 base address */
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
#define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
#define RTC_BASE (0x40080000UL) /**< RTC base address */
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
#define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
#define BURTC_BASE (0x40081000UL) /**< BURTC base address */
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
#define ETM_BASE (0xE0041000UL) /**< ETM base address */
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
#define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
#define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
/** @} End of group EFM32LG990F256_Peripheral_Base */
/**************************************************************************//**
* @defgroup EFM32LG990F256_Peripheral_Declaration EFM32LG990F256 Peripheral Declarations
* @{
*****************************************************************************/
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
#define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
#define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
#define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
/** @} End of group EFM32LG990F256_Peripheral_Declaration */
/**************************************************************************//**
* @defgroup EFM32LG990F256_BitFields EFM32LG990F256 Bit Fields
* @{
*****************************************************************************/
#include "efm32lg_prs_signals.h"
#include "efm32lg_dmareq.h"
#include "efm32lg_dmactrl.h"
#include "efm32lg_uart.h"
/**************************************************************************//**
* @defgroup EFM32LG990F256_UNLOCK EFM32LG990F256 Unlock Codes
* @{
*****************************************************************************/
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
#define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
/** @} End of group EFM32LG990F256_UNLOCK */
/** @} End of group EFM32LG990F256_BitFields */
/**************************************************************************//**
* @defgroup EFM32LG990F256_Alternate_Function EFM32LG990F256 Alternate Function
* @{
*****************************************************************************/
#include "efm32lg_af_ports.h"
#include "efm32lg_af_pins.h"
/** @} End of group EFM32LG990F256_Alternate_Function */
/**************************************************************************//**
* @brief Set the value of a bit field within a register.
*
* @param REG
* The register to update
* @param MASK
* The mask for the bit field to update
* @param VALUE
* The value to write to the bit field
* @param OFFSET
* The number of bits that the field is offset within the register.
* 0 (zero) means LSB.
*****************************************************************************/
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
/** @} End of group EFM32LG990F256 */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
#endif /* EFM32LG990F256_H */
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/**************************************************************************//**
* @file efm32lg_aes.h
* @brief EFM32LG_AES register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32LG_AES
* @{
* @brief EFM32LG_AES Register Declaration
*****************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Control Register */
__IOM uint32_t CMD; /**< Command Register */
__IM uint32_t STATUS; /**< Status Register */
__IOM uint32_t IEN; /**< Interrupt Enable Register */
__IM uint32_t IF; /**< Interrupt Flag Register */
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
__IOM uint32_t DATA; /**< DATA Register */
__IOM uint32_t XORDATA; /**< XORDATA Register */
uint32_t RESERVED0[3]; /**< Reserved for future use **/
__IOM uint32_t KEYLA; /**< KEY Low Register */
__IOM uint32_t KEYLB; /**< KEY Low Register */
__IOM uint32_t KEYLC; /**< KEY Low Register */
__IOM uint32_t KEYLD; /**< KEY Low Register */
__IOM uint32_t KEYHA; /**< KEY High Register */
__IOM uint32_t KEYHB; /**< KEY High Register */
__IOM uint32_t KEYHC; /**< KEY High Register */
__IOM uint32_t KEYHD; /**< KEY High Register */
} AES_TypeDef; /**< AES Register Declaration *//** @} */
/**************************************************************************//**
* @defgroup EFM32LG_AES_BitFields
* @{
*****************************************************************************/
/* Bit fields for AES CTRL */
#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
#define _AES_CTRL_MASK 0x00000077UL /**< Mask for AES_CTRL */
#define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */
#define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */
#define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */
#define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */
#define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */
#define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */
#define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */
#define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */
#define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */
#define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */
#define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */
#define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */
#define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */
#define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */
#define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */
#define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_BYTEORDER (0x1UL << 6) /**< Configure byte order in data and key registers */
#define _AES_CTRL_BYTEORDER_SHIFT 6 /**< Shift value for AES_BYTEORDER */
#define _AES_CTRL_BYTEORDER_MASK 0x40UL /**< Bit mask for AES_BYTEORDER */
#define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
#define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */
/* Bit fields for AES CMD */
#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
#define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */
#define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */
#define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */
#define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
#define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
#define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */
#define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */
#define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */
#define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
#define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
/* Bit fields for AES STATUS */
#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
#define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */
#define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */
#define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */
#define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */
#define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
#define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
/* Bit fields for AES IEN */
#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
#define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */
#define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */
#define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
#define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
/* Bit fields for AES IF */
#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
#define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */
#define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */
#define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
#define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
/* Bit fields for AES IFS */
#define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */
#define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */
#define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */
#define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */
#define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
/* Bit fields for AES IFC */
#define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */
#define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */
#define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */
#define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */
#define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
#define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */
#define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
/* Bit fields for AES DATA */
#define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */
#define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */
#define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */
#define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */
#define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */
#define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
/* Bit fields for AES XORDATA */
#define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */
#define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */
#define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */
#define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */
#define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */
#define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
/* Bit fields for AES KEYLA */
#define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */
#define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */
#define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */
#define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */
#define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */
#define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
/* Bit fields for AES KEYLB */
#define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */
#define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */
#define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */
#define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */
#define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */
#define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
/* Bit fields for AES KEYLC */
#define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */
#define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */
#define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */
#define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */
#define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */
#define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
/* Bit fields for AES KEYLD */
#define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */
#define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */
#define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */
#define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */
#define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */
#define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
/* Bit fields for AES KEYHA */
#define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */
#define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */
#define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */
#define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */
#define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */
#define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */
/* Bit fields for AES KEYHB */
#define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */
#define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */
#define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */
#define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */
#define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */
#define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */
/* Bit fields for AES KEYHC */
#define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */
#define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */
#define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */
#define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */
#define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */
#define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */
/* Bit fields for AES KEYHD */
#define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */
#define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */
#define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */
#define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */
#define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */
#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
/** @} End of group EFM32LG_AES */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
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/**************************************************************************//**
* @file efm32lg_burtc_ret.h
* @brief EFM32LG_BURTC_RET register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief BURTC_RET EFM32LG BURTC RET
*****************************************************************************/
typedef struct {
__IOM uint32_t REG; /**< Retention Register */
} BURTC_RET_TypeDef;
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
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/**************************************************************************//**
* @file efm32lg_calibrate.h
* @brief EFM32LG_CALIBRATE register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32LG_CALIBRATE
* @{
*****************************************************************************/
#define CALIBRATE_MAX_REGISTERS 50 /**< Max number of address/value pairs for calibration */
typedef struct {
__IM uint32_t ADDRESS; /**< Address of calibration register */
__IM uint32_t VALUE; /**< Default value for calibration register */
} CALIBRATE_TypeDef; /** @} */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
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/**************************************************************************//**
* @file efm32lg_devinfo.h
* @brief EFM32LG_DEVINFO register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32LG_DEVINFO
* @{
*****************************************************************************/
typedef struct {
__IM uint32_t CAL; /**< Calibration temperature and checksum */
__IM uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
__IM uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
__IM uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
uint32_t RESERVED0[2]; /**< Reserved */
__IM uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
__IM uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
__IM uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
__IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO calibration register 0 */
__IM uint32_t AUXHFRCOCAL1; /**< AUXHFRCO calibration register 1 */
__IM uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
__IM uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
__IM uint32_t MEMINFO; /**< Memory information */
uint32_t RESERVED2[2]; /**< Reserved */
__IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
__IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
__IM uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
__IM uint32_t PART; /**< Part description */
} DEVINFO_TypeDef; /** @} */
/**************************************************************************//**
* @defgroup EFM32LG_DEVINFO_BitFields
* @{
*****************************************************************************/
/* Bit fields for EFM32LG_DEVINFO */
#define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
#define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
#define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /**< Gain for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /**< Gain for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /**< Gain for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /**< Gain for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /**< Gain for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /**< Gain for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for VDD reference, shift*/
#define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for HFRCO, mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Flash page size (refer to ref.man for encoding) mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Flash page size shift */
#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
#define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
#define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
#define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
/* Legacy family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_HG 77 /**< Happy Gecko Device Family */
/* New style family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 71 /**< Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 72 /**< Giant Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 73 /**< Tiny Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 74 /**< Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 75 /**< Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 76 /**< Zero Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 77 /**< Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 120 /**< EZR Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 121 /**< EZR Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 122 /**< EZR Happy Gecko Device Family */
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
/** @} End of group EFM32LG_DEVINFO */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h 0 → 100644
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− 0
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cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h 0 → 100644
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− 0
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/**************************************************************************//**
* @file efm32lg_dma_ch.h
* @brief EFM32LG_DMA_CH register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @brief DMA_CH EFM32LG DMA CH
*****************************************************************************/
typedef struct {
__IOM uint32_t CTRL; /**< Channel Control Register */
} DMA_CH_TypeDef;
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h 0 → 100644
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− 0
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/**************************************************************************//**
* @file efm32lg_dma_descriptor.h
* @brief EFM32LG_DMA_DESCRIPTOR register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32LG_DMA_DESCRIPTOR
* @{
*****************************************************************************/
typedef struct {
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
/* pointer and referenced memory are declared volatile. */
__IOM void * __IOM SRCEND; /**< DMA source address end */
__IOM void * __IOM DSTEND; /**< DMA destination address end */
__IOM uint32_t CTRL; /**< DMA control register */
__IOM uint32_t USER; /**< DMA padding register, available for user */
} DMA_DESCRIPTOR_TypeDef; /** @} */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h 0 → 100644
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− 0
View file @ 1e3fdce1
/**************************************************************************//**
* @file efm32lg_dmactrl.h
* @brief EFM32LG_DMACTRL register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32LG_DMACTRL_BitFields
* @{
*****************************************************************************/
#define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
#define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
#define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
#define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
#define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
#define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
#define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
#define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
#define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
#define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
#define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
#define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
#define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
#define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
#define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
#define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
#define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
#define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
#define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
#define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
#define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
#define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
#define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
#define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
#define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
#define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
#define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
#define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
#define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
#define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
#define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
#define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
#define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
#define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
#define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
#define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
#define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
#define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
#define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
#define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
#define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
#define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
#define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
#define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
#define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
#define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
#define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
#define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
#define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
#define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
#define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
#define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
#define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
#define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
#define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
#define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
#define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
#define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
#define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
#define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
#define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
#define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
#define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
#define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
#define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
#define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
#define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
#define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
#define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
#define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
#define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
#define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
#define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
#define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
#define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
#define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
#define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
#define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
#define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
#define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
#define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
#define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
#define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
#define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
#define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
#define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
/** @} End of group EFM32LG_DMA */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h 0 → 100644
+ 118
− 0
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/**************************************************************************//**
* @file efm32lg_dmareq.h
* @brief EFM32LG_DMAREQ register and bit field definitions
* @version 5.3.3
******************************************************************************
* # License
* <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include /* Treat file as system include file. */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* Treat file as system include file. */
#endif
/**************************************************************************//**
* @addtogroup Parts
* @{
******************************************************************************/
/**************************************************************************//**
* @defgroup EFM32LG_DMAREQ_BitFields
* @{
*****************************************************************************/
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
#define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */
#define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
#define DMAREQ_USART2_RXDATAVRIGHT ((14 << 16) + 3) /**< DMA channel select for USART2_RXDATAVRIGHT */
#define DMAREQ_USART2_TXBLRIGHT ((14 << 16) + 4) /**< DMA channel select for USART2_TXBLRIGHT */
#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
#define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
#define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
#define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
#define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
#define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
#define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
#define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
#define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
#define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
#define DMAREQ_TIMER3_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
#define DMAREQ_TIMER3_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
#define DMAREQ_TIMER3_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
#define DMAREQ_TIMER3_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
#define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
#define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */
#define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
#define DMAREQ_UART1_RXDATAV ((45 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
#define DMAREQ_UART1_TXBL ((45 << 16) + 1) /**< DMA channel select for UART1_TXBL */
#define DMAREQ_UART1_TXEMPTY ((45 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
#define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
#define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
#define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
#define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
#define DMAREQ_LESENSE_BUFDATAV ((50 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
#define DMAREQ_EBI_PXL0EMPTY ((51 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
#define DMAREQ_EBI_PXL1EMPTY ((51 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
#define DMAREQ_EBI_PXLFULL ((51 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
#define DMAREQ_EBI_DDEMPTY ((51 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
/** @} End of group EFM32LG_DMAREQ */
/** @} End of group Parts */
#ifdef __cplusplus
}
#endif
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