Merge pull request #4119 from latsku/nucleo-f401

boards: Add support for Nucleo-f401

boards/nucleo-f401/Makefile

+MODULE = $(BOARD)_base
+
+include $(RIOTBASE)/Makefile.base

boards/nucleo-f401/Makefile.features

+FEATURES_PROVIDED += cpp
+FEATURES_PROVIDED += periph_uart
+FEATURES_PROVIDED += periph_gpio
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_cpuid
+FEATURES_PROVIDED += periph_timer
+FEATURES_MCU_GROUP = cortex_m4

boards/nucleo-f401/Makefile.include

+# define the cpu used by the nucleo-f401 board
+export CPU = stm32f4
+export CPU_MODEL = stm32f401re
+
+# define the default port depending on the host OS
+PORT_LINUX ?= /dev/ttyACM0
+PORT_DARWIN ?= $(shell ls -1 /dev/tty.usbmodem* | head -n 1)
+
+# setup serial terminal
+include $(RIOTBOARD)/Makefile.include.serial
+
+# this board uses openocd
+include $(RIOTBOARD)/Makefile.include.openocd
+
+# include cortex defaults
+include $(RIOTBOARD)/Makefile.include.cortexm_common

boards/nucleo-f401/board.c

+/*
+ * Copyright (C) 2015 Lari Lehtomäki
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nucleo-f401
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations for the nucleo-f401 board
+ *
+ * @author      Lari Lehtomäki <lari@lehtomaki.fi>
+ *
+ * @}
+ */
+
+#include "board.h"
+
+static void leds_init(void);
+
+void board_init(void)
+{
+    /* initialize the CPU */
+    cpu_init();
+    /* initialize the boards LEDs */
+    leds_init();
+
+}
+
+/**
+ * @brief Initialize the boards on-board LED
+ *
+ * The LED initialization is hard-coded in this function. As the LED is
+ * soldered onto the board it is fixed to its CPU pins.
+ *
+ * The green LED is connected to pin PA5
+ */
+static void leds_init(void)
+{
+    /* enable clock for port GPIOA */
+    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
+    /* set output speed to 50MHz */
+    LED_GREEN_PORT->OSPEEDR |= (0x3 << LED_GREEN_PIN * 2);
+    /* set output type to push-pull */
+    LED_GREEN_PORT->OTYPER &= ~(1 << LED_GREEN_PIN);
+    /* configure pins as general outputs */
+    LED_GREEN_PORT->MODER &= ~(0x3 << LED_GREEN_PIN * 2);
+    LED_GREEN_PORT->MODER |= (0x1 << LED_GREEN_PIN * 2);
+    /* disable pull resistors */
+    LED_GREEN_PORT->PUPDR &= ~(0x3 << LED_GREEN_PIN * 2);
+    /* turn all LEDs off */
+    LED_GREEN_PORT->BSRRL &= (1 << LED_GREEN_PIN);
+
+}

boards/nucleo-f401/dist/openocd.cfg

+source [find board/st_nucleo_f4.cfg]

boards/nucleo-f401/include/board.h

+/*
+ * Copyright (C) 2015 Lari Lehtomäki
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @defgroup    boards_nucleo-f401 Nucleo-F401
+ * @ingroup     boards
+ * @brief       Board specific files for the nucleo-f401 board
+ * @{
+ *
+ * @file
+ * @brief       Board specific definitions for the nucleo-f401 board
+ *
+ * @author      Lari Lehtomäki <lari@lehtomaki.fi>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "cpu.h"
+#include "periph_conf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Define the nominal CPU core clock in this board
+ */
+#define F_CPU               CLOCK_CORECLOCK
+
+/**
+ * @name xtimer configuration
+ * @{
+ */
+#define XTIMER              TIMER_0
+#define XTIMER_CHAN         (0)
+#define XTIMER_OVERHEAD     (6)
+#define XTIMER_BACKOFF      (5)
+/** @} */
+
+/**
+ * @name Define UART device and baudrate for stdio
+ * @{
+ */
+#define STDIO               UART_0
+#define STDIO_BAUDRATE      (115200U)
+#define STDIO_RX_BUFSIZE    (64U)
+/** @} */
+
+/**
+ * @name LED pin definitions
+ * @{
+ */
+#define LED_GREEN_PORT      (GPIOA)
+#define LED_GREEN_PIN       (5)
+#define LED_GREEN_GPIO      GPIO_PIN(PORT_A,5)
+/** @} */
+
+/**
+ * @name Macros for controlling the on-board LEDs.
+ * @{
+ */
+#define LED_RED_ON
+#define LED_RED_OFF
+#define LED_RED_TOGGLE
+
+#define LED_GREEN_ON        (LED_GREEN_PORT->BSRRL = (1<<LED_GREEN_PIN))
+#define LED_GREEN_OFF       (LED_GREEN_PORT->BSRRH = (1<<LED_GREEN_PIN))
+#define LED_GREEN_TOGGLE    (LED_GREEN_PORT->ODR ^= (1<<LED_GREEN_PIN))
+
+#define LED_ORANGE_ON
+#define LED_ORANGE_OFF
+#define LED_ORANGE_TOGGLE
+/** @} */
+
+
+/**
+ * @brief Initialize board specific hardware, including clock, LEDs and std-IO
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
+/** @} */

boards/nucleo-f401/include/periph_conf.h

+/*
+ * Copyright (C) 2015 Lari Lehtomäki
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_nucleo-f401
+ * @{
+ *
+ * @file
+ * @name        Peripheral MCU configuration for the nucleo-f401 board
+ *
+ * @author      Lari Lehtomäki <lari@lehtomaki.fi>
+ */
+
+#ifndef PERIPH_CONF_H_
+#define PERIPH_CONF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name Clock system configuration
+ * @{
+ */
+#define CLOCK_HSE           (8000000U)          /* external oscillator */
+#define CLOCK_CORECLOCK     (84000000U)         /* desired core clock frequency */
+
+/* the actual PLL values are automatically generated */
+#define CLOCK_PLL_M         (CLOCK_HSE / 1000000)
+#define CLOCK_PLL_N         ((CLOCK_CORECLOCK / 1000000) * 2)
+#define CLOCK_PLL_P         (2U)
+#define CLOCK_PLL_Q         (CLOCK_PLL_N / 48)
+#define CLOCK_AHB_DIV       RCC_CFGR_HPRE_DIV1
+#define CLOCK_APB1_DIV      RCC_CFGR_PPRE1_DIV2
+#define CLOCK_APB2_DIV      RCC_CFGR_PPRE2_DIV1
+#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
+/** @} */
+
+/**
+ * @name Timer configuration
+ * @{
+ */
+#define TIMER_NUMOF         (2U)
+#define TIMER_0_EN          1
+#define TIMER_1_EN          1
+#define TIMER_IRQ_PRIO      1
+
+/* Timer 0 configuration */
+#define TIMER_0_DEV         TIM2
+#define TIMER_0_CHANNELS    4
+#define TIMER_0_PRESCALER   (83U)
+#define TIMER_0_MAX_VALUE   (0xffffffff)
+#define TIMER_0_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
+#define TIMER_0_ISR         isr_tim2
+#define TIMER_0_IRQ_CHAN    TIM2_IRQn
+
+/* Timer 1 configuration */
+#define TIMER_1_DEV         TIM5
+#define TIMER_1_CHANNELS    4
+#define TIMER_1_PRESCALER   (83U)
+#define TIMER_1_MAX_VALUE   (0xffffffff)
+#define TIMER_1_CLKEN()     (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
+#define TIMER_1_ISR         isr_tim5
+#define TIMER_1_IRQ_CHAN    TIM5_IRQn
+/** @} */
+
+/**
+ * @name UART configuration
+ * @{
+ */
+#define UART_NUMOF          (1U)
+#define UART_0_EN           1
+#define UART_IRQ_PRIO       1
+#define UART_CLK            (14000000U)         /* UART clock runs with 14MHz */
+
+/* UART 0 device configuration */
+#define UART_0_DEV          USART2
+#define UART_0_CLKEN()      (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
+#define UART_0_CLKDIS()     (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define UART_0_CLK          (CLOCK_CORECLOCK / 2)          /* UART clock runs with 42MHz (F_CPU / 2) */
+#define UART_0_IRQ_CHAN     USART2_IRQn
+#define UART_0_ISR          isr_usart2
+/* UART 0 pin configuration */
+#define UART_0_PORT         GPIOA
+#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+#define UART_0_RX_PIN       3
+#define UART_0_TX_PIN       2
+#define UART_0_AF           7
+/** @} */
+
+/**
+ * @name SPI configuration
+ * @{
+ */
+#define SPI_NUMOF           (1U)
+#define SPI_0_EN            1
+#define SPI_IRQ_PRIO        1
+
+/* SPI 0 device config */
+#define SPI_0_DEV               SPI1
+#define SPI_0_CLKEN()           (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
+#define SPI_0_CLKDIS()          (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
+#define SPI_0_BUS_DIV           1   /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
+#define SPI_0_IRQ               SPI1_IRQn
+#define SPI_0_IRQ_HANDLER       isr_spi1
+/* SPI 0 pin configuration */
+#define SPI_0_SCK_PORT          GPIOA       /* A5 pin is shared with the green LED. */
+#define SPI_0_SCK_PIN           5
+#define SPI_0_SCK_AF            5
+#define SPI_0_SCK_PORT_CLKEN()  (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+#define SPI_0_MISO_PORT         GPIOA
+#define SPI_0_MISO_PIN          6
+#define SPI_0_MISO_AF           5
+#define SPI_0_MISO_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+#define SPI_0_MOSI_PORT         GPIOA
+#define SPI_0_MOSI_PIN          7
+#define SPI_0_MOSI_AF           5
+#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H_ */
+/** @} */

cpu/stm32f4/include/cpu_conf.h

@@ -21,7 +21,9 @@
 #ifndef __CPU_CONF_H
 #define __CPU_CONF_H
 
-#if defined(CPU_MODEL_STM32F407VG)
+#if defined(CPU_MODEL_STM32F401RE)
+#include "stm32f401xe.h"
+#elif defined(CPU_MODEL_STM32F407VG)
 #include "stm32f407xx.h"
 #elif defined(CPU_MODEL_STM32F415RG)
 #include "stm32f415xx.h"

cpu/stm32f4/ldscripts/stm32f401re.ld

+/*
+ * Copyright (C) 2015 Lari Lehtomäki
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @addtogroup      cpu_stm32f4
+ * @{
+ *
+ * @file
+ * @brief           Memory definitions for the STM32F401xE
+ *
+ * @author          Lari Lehtomäki <lari@lehtomaki.fi>
+ *
+ * @}
+ */
+
+MEMORY
+{
+    rom (rx)    : ORIGIN = 0x08000000, LENGTH = 512K
+    ram (rwx)   : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+INCLUDE cortexm_base.ld

tests/pkg_cmsis-dsp/Makefile

@@ -16,6 +16,7 @@ BOARD_WHITELIST := \
   nucleo-f091 \
   nucleo-f303 \
   nucleo-f334 \
+  nucleo-f401 \
   nucleo-l1 \
   openmote \
   pba-d-01-kw2x \