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Commit 3edc40e4 authored by Kaspar Schleiser's avatar Kaspar Schleiser
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drivers: nrf24l01p: use xtimer

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drivers/nrf24l01p/include/nrf24l01p_settings.h
+ 7
− 7
View file @ 3edc40e4
......@@ -31,18 +31,18 @@ extern "C" {
#define INITIAL_RF_CHANNEL 5
#define INITIAL_RX_POWER_0dB 0
#define DELAY_CS_TOGGLE_TICKS 2
#define DELAY_AFTER_FUNC_TICKS 2
#define DELAY_CE_HIGH_US HWTIMER_TICKS(20)
#define DELAY_CHANGE_PWR_MODE_US HWTIMER_TICKS(1500)
#define DELAY_CHANGE_TXRX_US HWTIMER_TICKS(130)
#define DELAY_CE_START_US HWTIMER_TICKS(5)
#define DELAY_CS_TOGGLE_TICKS 2
#define DELAY_AFTER_FUNC_TICKS 2
#define DELAY_CE_HIGH (20)
#define DELAY_CHANGE_PWR_MODE (1500)
#define DELAY_CHANGE_TXRX (130)
#define DELAY_CE_START (5)
/*
* This is the time which is needed to physically transmit the data.
* Compare nrf24l01+ pruduct specification p.42. It is computed just
* for this setup
*/
#define DELAY_DATA_ON_AIR HWTIMER_TICKS(1300)
#define DELAY_DATA_ON_AIR (1300)
#define CMD_R_REGISTER 0x00
......
drivers/nrf24l01p/nrf24l01p.c
+ 48
− 48
View file @ 3edc40e4
......@@ -18,7 +18,7 @@
#include "mutex.h"
#include "periph/gpio.h"
#include "periph/spi.h"
#include "hwtimer.h"
#include "xtimer.h"
#include "thread.h"
#include "msg.h"
......@@ -34,14 +34,14 @@ int nrf24l01p_read_reg(nrf24l01p_t *dev, char reg, char *answer)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_reg(dev->spi, (CMD_R_REGISTER | (REGISTER_MASK & reg)), CMD_NOP, answer);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
......@@ -54,14 +54,14 @@ int nrf24l01p_write_reg(nrf24l01p_t *dev, char reg, char write)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_reg(dev->spi, (CMD_W_REGISTER | (REGISTER_MASK & reg)), write, &reg_content);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
......@@ -100,7 +100,7 @@ int nrf24l01p_init(nrf24l01p_t *dev, spi_t spi, gpio_t ce, gpio_t cs, gpio_t irq
return status;
}
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
/* Flush TX FIFIO */
status = nrf24l01p_flush_tx_fifo(dev);
......@@ -204,7 +204,7 @@ int nrf24l01p_on(nrf24l01p_t *dev)
nrf24l01p_read_reg(dev, REG_CONFIG, &read);
status = nrf24l01p_write_reg(dev, REG_CONFIG, (read | PWR_UP));
hwtimer_wait(DELAY_CHANGE_PWR_MODE_US);
xtimer_usleep(DELAY_CHANGE_PWR_MODE_US);
return status;
}
......@@ -217,7 +217,7 @@ int nrf24l01p_off(nrf24l01p_t *dev)
nrf24l01p_read_reg(dev, REG_CONFIG, &read);
status = nrf24l01p_write_reg(dev, REG_CONFIG, (read & ~PWR_UP));
hwtimer_wait(DELAY_CHANGE_PWR_MODE_US);
xtimer_usleep(DELAY_CHANGE_PWR_MODE_US);
return status;
}
......@@ -225,10 +225,10 @@ int nrf24l01p_off(nrf24l01p_t *dev)
void nrf24l01p_transmit(nrf24l01p_t *dev)
{
gpio_set(dev->ce);
hwtimer_wait(DELAY_CE_HIGH_US); /* at least 10 us high */
xtimer_usleep(DELAY_CE_HIGH_US); /* at least 10 us high */
gpio_clear(dev->ce);
hwtimer_spin(DELAY_CHANGE_TXRX_US);
xtimer_spin(DELAY_CHANGE_TXRX_US);
}
int nrf24l01p_read_payload(nrf24l01p_t *dev, char *answer, unsigned int size)
......@@ -238,11 +238,11 @@ int nrf24l01p_read_payload(nrf24l01p_t *dev, char *answer, unsigned int size)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, CMD_R_RX_PAYLOAD, 0, answer, size);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
/* Release the bus for other threads. */
spi_release(dev->spi);
......@@ -273,12 +273,12 @@ void nrf24l01p_get_id(nrf24l01p_t *dev, unsigned int *pid)
void nrf24l01p_start(nrf24l01p_t *dev)
{
gpio_set(dev->ce);
hwtimer_wait(DELAY_CE_START_US);
xtimer_usleep(DELAY_CE_START_US);
}
void nrf24l01p_stop(nrf24l01p_t *dev)
{
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_clear(dev->ce);
}
......@@ -291,14 +291,14 @@ int nrf24l01p_preload(nrf24l01p_t *dev, char *data, unsigned int size)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, CMD_W_TX_PAYLOAD, data, NULL, size);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
......@@ -318,7 +318,7 @@ int nrf24l01p_set_address_width(nrf24l01p_t *dev, nrf24l01p_aw_t aw)
char aw_setup;
nrf24l01p_read_reg(dev, REG_SETUP_AW, &aw_setup);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
switch (aw) {
case NRF24L01P_AW_3BYTE:
......@@ -396,14 +396,14 @@ int nrf24l01p_set_tx_address(nrf24l01p_t *dev, char *saddr, unsigned int length)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, (CMD_W_REGISTER | (REGISTER_MASK & REG_TX_ADDR)), saddr, NULL, length); /* address width is 5 byte */
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
......@@ -427,14 +427,14 @@ int nrf24l01p_set_tx_address_long(nrf24l01p_t *dev, uint64_t saddr, unsigned int
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, (CMD_W_REGISTER | (REGISTER_MASK & REG_TX_ADDR)), buf, NULL, length); /* address width is 5 byte */
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
......@@ -448,20 +448,20 @@ uint64_t nrf24l01p_get_tx_address_long(nrf24l01p_t *dev)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, (CMD_R_REGISTER | (REGISTER_MASK & REG_TX_ADDR)), 0, addr_array, INITIAL_ADDRESS_WIDTH); /* address width is 5 byte */
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
if (status < 0) {
return -1;
}
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
for (int i = 0; i < INITIAL_ADDRESS_WIDTH; i++) {
saddr_64 |= (((uint64_t) addr_array[i]) << (8 * (INITIAL_ADDRESS_WIDTH - i - 1)));
......@@ -508,14 +508,14 @@ int nrf24l01p_set_rx_address(nrf24l01p_t *dev, nrf24l01p_rx_pipe_t pipe, char *s
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, (CMD_W_REGISTER | (REGISTER_MASK & pipe_addr)), saddr, NULL, length); /* address width is 5 byte */
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
/* Enable this pipe */
nrf24l01p_enable_pipe(dev, pipe);
......@@ -580,9 +580,9 @@ uint64_t nrf24l01p_get_rx_address_long(nrf24l01p_t *dev, nrf24l01p_rx_pipe_t pip
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, (CMD_R_REGISTER | (REGISTER_MASK & pipe_addr)), 0, addr_array, INITIAL_ADDRESS_WIDTH); /* address width is 5 byte */
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
......@@ -591,7 +591,7 @@ uint64_t nrf24l01p_get_rx_address_long(nrf24l01p_t *dev, nrf24l01p_rx_pipe_t pip
return -1;
}
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
for (int i = 0; i < INITIAL_ADDRESS_WIDTH; i++) {
saddr_64 |= (((uint64_t) addr_array[i]) << (8 * (INITIAL_ADDRESS_WIDTH - i - 1)));
......@@ -635,14 +635,14 @@ int nrf24l01p_get_status(nrf24l01p_t *dev)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
spi_transfer_byte(dev->spi, CMD_NOP, &status);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return (int)status;
}
......@@ -717,7 +717,7 @@ int nrf24l01p_set_txmode(nrf24l01p_t *dev)
conf &= ~(PRIM_RX);
status = nrf24l01p_write_reg(dev, REG_CONFIG, conf);
hwtimer_wait(DELAY_CHANGE_TXRX_US);
xtimer_usleep(DELAY_CHANGE_TXRX_US);
return status;
}
......@@ -738,7 +738,7 @@ int nrf24l01p_set_rxmode(nrf24l01p_t *dev)
nrf24l01p_start(dev);
hwtimer_wait(DELAY_CHANGE_TXRX_US);
xtimer_usleep(DELAY_CHANGE_TXRX_US);
return status;
}
......@@ -874,14 +874,14 @@ int nrf24l01p_flush_tx_fifo(nrf24l01p_t *dev)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_byte(dev->spi, CMD_FLUSH_TX, &reg_content);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
......@@ -894,14 +894,14 @@ int nrf24l01p_flush_rx_fifo(nrf24l01p_t *dev)
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_byte(dev->spi, CMD_FLUSH_RX, &reg_content);
hwtimer_spin(DELAY_CS_TOGGLE_TICKS);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
hwtimer_spin(DELAY_AFTER_FUNC_TICKS);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
......
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