cpu: stm32f1/2/4: unify periph/pm support

cpu/stm32_common/include/periph_cpu_common.h

@@ -44,6 +44,13 @@ extern "C" {
 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
 /** @} */
 
+/**
+ * @brief   Number of usable low power modes
+ */
+#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(DOXYGEN)
+#define PM_NUM_MODES    (2U)
+#endif
+
 /**
  * @brief   Available peripheral buses
  */

cpu/stm32f1/periph/pm.c → cpu/stm32_common/periph/pm.c

 /*
  * Copyright (C) 2016 Kaspar Schleiser <kaspar@schleiser.de>
+ *               2015 Freie Universität Berlin
  *               2015 Engineering-Spirit
  *
  * This file is subject to the terms and conditions of the GNU Lesser
@@ -8,7 +9,7 @@
  */
 
 /**
- * @ingroup     cpu_stm32f1
+ * @ingroup     cpu_stm32
  * @{
  *
  * @file
@@ -16,10 +17,12 @@
  *
  * @author      Nick v. IJzendoorn <nijzndoorn@engineering-spirit.nl>
  * @author      Kaspar Schleiser <kaspar@schleiser.de>
+ * @author      Fabian Nack <nack@inf.fu-berlin.de>
  *
  * @}
  */
 
+#include "irq.h"
 #include "periph/pm.h"
 
 #define ENABLE_DEBUG (1)
@@ -27,10 +30,17 @@
 
 void pm_set(unsigned mode)
 {
+/* I just copied it from stm32f1/2/4, but I suppose it would work for the
+ * others... /KS */
+#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
     switch (mode) {
-        case 0:                  /* STM Sleep mode */
-            /* Reset SLEEPDEEP bit of system control block */
-            SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
+        case 0:
+            /* Set PDDS to enter standby mode on deepsleep and clear flags */
+            PWR->CR |= (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF);
+            /* Enable WKUP pin to use for wakeup from standby mode */
+            PWR->CSR |= PWR_CSR_EWUP;
+            /* Set SLEEPDEEP bit of system control block */
+            SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
             break;
         case 1:                 /* STM Stop mode */
             /* Clear PDDS and LPDS bits to enter stop mode on */
@@ -39,9 +49,12 @@ void pm_set(unsigned mode)
             /* Set SLEEPDEEP bit of system control block */
             SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
             break;
-        default:
-            DEBUG("pm: invalid power mode selected.\n");
+        case 2:                  /* STM Sleep mode */
+            /* Reset SLEEPDEEP bit of system control block */
+            SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk);
+            break;
     }
+#endif
 
     /* Executes a device DSB (Data Synchronization Barrier) */
     __DSB();
@@ -49,15 +62,10 @@ void pm_set(unsigned mode)
     __WFI();
 }
 
+#if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
 void pm_off(void)
 {
-    /* Set PDDS to enter standby mode on deepsleep and clear flags */
-    PWR->CR |= (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF);
-    /* Enable WKUP pin to use for wakeup from standby mode */
-    PWR->CSR |= PWR_CSR_EWUP;
-    /* Set SLEEPDEEP bit of system control block */
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-    __DSB();
-    __WFI();
+    irq_disable();
+    pm_set(0);
 }
+#endif

cpu/stm32f1/Makefile.features

-FEATURE_PROVIDED += periph_pm
+FEATURES_PROVIDED += periph_pm

cpu/stm32f1/Makefile.include

 export CPU_ARCH = cortex-m3
 export CPU_FAM  = stm32f1
 
+USEMODULE += pm_layered
+
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTCPU)/Makefile.include.cortexm_common

cpu/stm32f2/Makefile.features

+FEATURES_PROVIDED += periph_pm

cpu/stm32f2/Makefile.include

 export CPU_ARCH = cortex-m3
 export CPU_FAM  = stm32f2
 
+USEMODULE += pm_layered
+
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTCPU)/Makefile.include.cortexm_common

cpu/stm32f4/Makefile.features

+FEATURES_PROVIDED += periph_pm

cpu/stm32f4/Makefile.include

 export CPU_ARCH = cortex-m4f
 export CPU_FAM  = stm32f4
 
+USEMODULE += pm_layered
+
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTCPU)/Makefile.include.cortexm_common