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Commit b4ee555d authored by Oleg Hahm's avatar Oleg Hahm
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coding convention fixes

parent c99539c5
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......@@ -81,7 +81,8 @@ void init_clks1(void)
pllfeed();
SCS |= 0x20; // Enable main OSC
while( !(SCS & 0x40) ); // Wait until main OSC is usable
while (!(SCS & 0x40)); // Wait until main OSC is usable
/* select main OSC, 16MHz, as the PLL clock source */
CLKSRCSEL = 0x0001;
......@@ -102,9 +103,10 @@ void init_clks1(void)
#endif
}
void init_clks2(void){
void init_clks2(void)
{
// Wait for the PLL to lock to set frequency
while(!(PLLSTAT & BIT26));
while (!(PLLSTAT & BIT26));
// Connect the PLL as the clock source
PLLCON = 0x0003;
......
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