cpu/stm32f4: add support for stm32f405rg

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>

cpu/stm32f4/include/cpu_conf.h

@@ -38,7 +38,8 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
 #if defined(CPU_LINE_STM32F401xE)
 #define CPU_IRQ_NUMOF                   (85U)
-#elif defined(CPU_LINE_STM32F407xx) || defined(CPU_LINE_STM32F415xx)
+#elif defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) \
+    || defined(CPU_LINE_STM32F415xx)
 #define CPU_IRQ_NUMOF                   (82U)
 #elif defined(CPU_LINE_STM32F410Rx)
 #define CPU_IRQ_NUMOF                   (98U)

cpu/stm32f4/include/periph_cpu.h

@@ -52,9 +52,9 @@ enum {
     || defined(CPU_LINE_STM32F411xE) || defined(CPU_LINE_STM32F412Zx) \
     || defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
 #define ADC_DEVS            (1U)
-#elif defined(CPU_LINE_STM32F407xx) || defined(CPU_LINE_STM32F415xx) \
-    || defined(CPU_LINE_STM32F429xx) || defined(CPU_LINE_STM32F437xx) \
-    || defined(CPU_LINE_STM32F446xx)
+#elif defined(CPU_LINE_STM32F405xx)  || defined(CPU_LINE_STM32F407xx) \
+    || defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F429xx) \
+    || defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F446xx)
 #define ADC_DEVS            (3U)
 #endif
 

cpu/stm32f4/vectors.c

@@ -199,6 +199,42 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
     [72] = isr_i2c3_ev,              /* [72] I2C3 event interrupt */
     [73] = isr_i2c3_er,              /* [73] I2C3 error interrupt */
     [84] = isr_spi4,                 /* [84] SPI4 global Interrupt */
+#elif defined(CPU_LINE_STM32F405xx)
+    [18] = isr_adc,                  /* [18] ADC1, ADC2 and ADC3 global Interrupts */
+    [19] = isr_can1_tx,              /* [19] CAN1 TX Interrupt */
+    [20] = isr_can1_rx0,             /* [20] CAN1 RX0 Interrupt */
+    [21] = isr_can1_rx1,             /* [21] CAN1 RX1 Interrupt */
+    [22] = isr_can1_sce,             /* [22] CAN1 SCE Interrupt */
+    [25] = isr_tim1_up_tim10,        /* [25] TIM1 Update Interrupt and TIM10 global interrupt */
+    [28] = isr_tim2,                 /* [28] TIM2 global Interrupt */
+    [29] = isr_tim3,                 /* [29] TIM3 global Interrupt */
+    [30] = isr_tim4,                 /* [30] TIM4 global Interrupt */
+    [39] = isr_usart3,               /* [39] USART3 global Interrupt */
+    [42] = isr_otg_fs_wkup,          /* [42] USB OTG FS Wakeup through EXTI line interrupt */
+    [43] = isr_tim8_brk_tim12,       /* [43] TIM8 Break Interrupt and TIM12 global interrupt */
+    [44] = isr_tim8_up_tim13,        /* [44] TIM8 Update Interrupt and TIM13 global interrupt */
+    [45] = isr_tim8_trg_com_tim14,   /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+    [46] = isr_tim8_cc,              /* [46] TIM8 Capture Compare global interrupt */
+    [48] = isr_fsmc,                 /* [48] FSMC global Interrupt */
+    [49] = isr_sdio,                 /* [49] SDIO global Interrupt */
+    [51] = isr_spi3,                 /* [51] SPI3 global Interrupt */
+    [52] = isr_uart4,                /* [52] UART4 global Interrupt */
+    [53] = isr_uart5,                /* [53] UART5 global Interrupt */
+    [54] = isr_tim6_dac,             /* [54] TIM6 global and DAC1&2 underrun error  interrupts */
+    [55] = isr_tim7,                 /* [55] TIM7 global interrupt */
+    [63] = isr_can2_tx,              /* [63] CAN2 TX Interrupt */
+    [64] = isr_can2_rx0,             /* [64] CAN2 RX0 Interrupt */
+    [65] = isr_can2_rx1,             /* [65] CAN2 RX1 Interrupt */
+    [66] = isr_can2_sce,             /* [66] CAN2 SCE Interrupt */
+    [67] = isr_otg_fs,               /* [67] USB OTG FS global Interrupt */
+    [72] = isr_i2c3_ev,              /* [72] I2C3 event interrupt */
+    [73] = isr_i2c3_er,              /* [73] I2C3 error interrupt */
+    [74] = isr_otg_hs_ep1_out,       /* [74] USB OTG HS End Point 1 Out global interrupt */
+    [75] = isr_otg_hs_ep1_in,        /* [75] USB OTG HS End Point 1 In global interrupt */
+    [76] = isr_otg_hs_wkup,          /* [76] USB OTG HS Wakeup through EXTI interrupt */
+    [77] = isr_otg_hs,               /* [77] USB OTG HS global interrupt */
+    [78] = isr_dcmi,                 /* [78] DCMI global interrupt */
+    [80] = isr_rng,                  /* [80] RNG global Interrupt */
 #elif defined(CPU_LINE_STM32F407xx)
     [18] = isr_adc,                  /* [18] ADC1, ADC2 and ADC3 global Interrupts */
     [19] = isr_can1_tx,              /* [19] CAN1 TX Interrupt */