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Commit e5bd44d5 authored by Colin Wulf's avatar Colin Wulf
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dw1000: dtune2 now for prf 64 mhz

parent 1c5f5204
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......@@ -58,6 +58,7 @@ extern dw1000_local_data_t dw1000local; // Static local device data
extern const uint8_t pll2calcfg;
extern const uint16_t sftsh[NUM_BR][NUM_SFD];
extern const uint16_t dtune1[NUM_PRF];
extern const uint32_t digital_bb_config[NUM_PRF][NUM_PACS];
extern const uint8_t chan_idx[NUM_CH_SUPPORTED];
extern const uint32_t tx_config[NUM_CH];
extern const uint8_t pll2_config[NUM_CH][5];
......
......@@ -192,17 +192,20 @@ void dw1000_configure(dw1000_config_t *config) {
(uint8_t *) &temp, 1);
} else {
uint8_t temp = 0x20;
//DECA: dwt_write16bitoffsetreg(DRX_CONF_ID, DRX_TUNE1b_OFFSET, 0x20);
dw1000Hal_writeSubRegister(DRX_CONF_ID, DRX_TUNE1b_OFFSET,
(uint8_t *) &temp, DRX_TUNE1b_LEN);
temp = 0x28;
//DECA: dwt_writetodevice(DRX_CONF_ID, 0x26, 1, &temp);
dw1000Hal_writeSubRegister(DRX_CONF_ID, DRX_DRX_TUNE4HOFFSET,
(uint8_t *) &temp, 1);
}
}
//DTUNE2 magic values for prf 64
if(config->pulse_repetition_frequency == DWT_PRF_64M){
dw1000Hal_writeSubRegister(DRX_CONF_ID, DRX_TUNE2_OFFSET, &digital_bb_config[prfIndex][config->preamble_acquisition_chunk_size], 4);
}
//DTUNE3 set SFD detection timeout count
if (config->sfd_timeout != DWT_SFDTOC_DEF) { //if default value no need to program it
dw1000Hal_writeSubRegister(DRX_CONF_ID, DRX_SFDTOC_OFFSET,
......
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