xen: use bsrq instead of bsrl for event channels

This patch fixes the Amazon crash many CPUs. Funny enough, it is not
actually related to the number of CPUs. In that situation, the port
numbers allocated for the event channels are quite high. I don't
really know the reason for that, maybe the Hypervisor reserves the
small bits for CPU related things...

As we have more and more CPUs and the bits shift more and more rightwards,
they eventually reach the second long word of the event channel quadword.

But we have been operating this with brsl, which will only reach a long word.
If bit 32, for instance, is 1, it  will be interpreted as bit 0 == 1. Bit 0
having no registered handler, that will turn into a nullptr access.

Cheers for Dima for doing most of the debugging and heavy lifting here.
The hang issues are still present.

Fixes #109.

Signed-off-by: Glauber Costa <glommer@cloudius-systems.com>
Signed-off-by: Dmitry Fleytman <dmitry@daynix.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

arch/x64/bitops.h

@@ -15,6 +15,14 @@ bsrl(unsigned int mask)
     return result;
 }
 
+static inline unsigned long
+bsrq(unsigned long mask)
+{
+    unsigned long result;
+    asm volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
+    return result;
+}
+
 static inline int
 fls(int mask)
 {

arch/x64/xen_intr.cc

@@ -66,11 +66,11 @@ void xen_irq::do_irq(void)
         });
 
         while (l1 != 0) {
-            l1i = bsrl(l1);
+            l1i = bsrq(l1);
             l1 &= ~(1 << l1i);
 
             while ((l2 = active_evtchns(l1i, cpu_mask)) != 0) {
-                l2i = bsrl(l2);
+                l2i = bsrq(l2);
                 unsigned long port = (l1i * LONG_BIT) + l2i;
 
                 // FIXME: It should be possible to mask all channels