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cm-projects
RIOT
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6a32f1dd
Commit
6a32f1dd
authored
7 years ago
by
Francisco Acosta
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boards/nucleo-l152: configure LSI by default
parent
368818aa
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boards/nucleo-l152/include/periph_conf.h
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11 additions, 3 deletions
boards/nucleo-l152/include/periph_conf.h
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boards/nucleo-l152/include/periph_conf.h
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6a32f1dd
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@@ -34,9 +34,17 @@ extern "C" {
...
@@ -34,9 +34,17 @@ extern "C" {
**/
**/
#define CLOCK_HSI (16000000U)
/* frequency of internal oscillator */
#define CLOCK_HSI (16000000U)
/* frequency of internal oscillator */
#define CLOCK_CORECLOCK (32000000U)
/* targeted core clock frequency */
#define CLOCK_CORECLOCK (32000000U)
/* targeted core clock frequency */
/* 0: no external low speed crystal available,
/*
* 1: external crystal available (always 32.768kHz) */
* 0: no external low speed crystal available,
#define CLOCK_LSE (1)
* 1: external crystal available (always 32.768kHz)
*
* LSE might not be available by default in early (C-01) Nucleo boards.
* For newer revisions, LSE crystal is present, but currently is not working.
* (issue at https://github.com/RIOT-OS/RIOT/pull/8545).
*/
#ifndef CLOCK_LSE
#define CLOCK_LSE (0)
#endif
/* configuration of PLL prescaler and multiply values */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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