cpu/kinetis/rtt: clear TPR when writing TSR

net/nanocoap: add debug message for server

sys/crypto/aes: avoid UB by explicit unsigned integer promotion

cpu/nrf5x: handle multiple exti pins in gpio driver

Each pin is associated to a given GPIOTE channel

gnrc_sixlowpan: document submodules according to #8511

gnrc_lwmac: enable radio duty-cycle printing.

net/gcoap: make options buf macros configurable

examples/bindist: cleanup and fix formatting in README

gnrc_mac: add timeout module.

dist/tools/compile_and_test_for_board: add compile and test script

cpu/saml1x: add support for SAML10 and SAML11 MCUs (Cortex-M23)

cpu/atmega_common: refactor AVR libc code into module

cpu/esp8266: change of ETS task handling 

tests/posix_semaphore: private sub functions for tests libs

tests/periph_dma: add automatic testing of DMA over UART

cpu/esp32: fix of buffer sizes and length checking in esp_eth and esp_wifi

Disable optimization for this function only with CPU_SAML1X MCUs due to an internal crosscompiler bug

Add SAML10/SAML11 support through SAM0 because hardware IP are the same so reuse to avoid duplication

boards/stm32: revert forced use of dma feature in STM32 boards

During flash write access, the IROM cache cannot be used and is disabled therefore. During that time, ets_post crashes if a functions is called which is not in IRAM. Therefore thread_flags_set must not be called if IROM cache is disabled.

With the new ETS task handling thread, the stack sizes could be down sized.

Changes of ETS task handling require the context switch by software interrupt. The context switch based on interrupt is therefore enabled by default. Furthermore, the number of priority levels are increased due to the new additional thread.

ETS tasks are now handled by a high priority RIOT thread

Co-Authored-By: zhuoshuguo <zhuosgzju@gmail.com>