If a thread which invokes flush_tlb_all() is migrated between the
call to flush_tlb_local() and send_allbutself(), the CPU onto which it
was migrated would not get its TLB flushed.

Spotted during code inspection.

Signed-off-by: Tomasz Grabiec <tgrabiec@cloudius-systems.com>
Signed-off-by: Avi Kivity <avi@cloudius-systems.com>

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Avi Kivity <avi@cloudius-systems.com>

move driver setup and console creation to arch-setup,
and ioapic init for x64 to smp_launch, so that we
can remove ifdefs and increase the amount of common code.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: Nadav Har'El <nyh@cloudius-systems.com>

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>

[claudio: renamed fixup.hh to fault-fixup.hh]
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

implement fixup fault and the backtrace functionality which is
its first simple user.

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>

[claudio: added elf changes to allow lookup and demangling to work]

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

generate exception frame

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

arch::init_on_cpu should initialize the gic cpu interface,
but not for the boot CPU, for which this has already been
done.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

we need to do that because load/store instructions
behave differently with Device-nGnRnE memory.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

fix build for Aarch64 broken by commit 66317807 and b3fa77d3.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

Resolve and demangle symbol name of RIP, show it.

Signed-off-by: Takuya ASADA <syuu@cloudius-systems.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

implement a simple interrupt table with descriptors
which record interrupt IDs, handlers and interrupt type.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

add include <osv/prio.hh>, this time at the beginning of the file.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

remove a spurious include <osv/prio.hh> which seems to be
a merge artifact.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

implement simple GIC class for interacting with
the GIC distributor and CPU interface.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Avi Kivity <avi@cloudius-systems.com>

the class construction of the page_table_root must happen
before priority "mempool", or all the work in arch-setup
will be destroyed by the class constructor.
Problem noticed while working on the page fault handler for AArch64.

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Avi Kivity <avi@cloudius-systems.com>

includes an implementation of arch_early_console for x64
using isa-serial, and an implementation for aarch64
using the (for now write-only) pl011.

This restores output functionality for AArch64 lost in
commit 9bbbe9dc.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Avi Kivity <avi@cloudius-systems.com>

Signed-off-by: Takuya ASADA <syuu@cloudius-systems.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

Signed-off-by: Takuya ASADA <syuu@cloudius-systems.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

Also, move platform dependent fast dispatch to platform arch code tree(s)

The patching code is a bit more complex than would seem immediately (or
even factually) neccesary. However, depending on cpu, there might be
issues with trying to code patch across cache lines (unaligned).
To be safe, we do it with the old 16-bit jmp + write + finish dance.

[avi: fix up build.mk]

Signed-off-by: Calle Wilund <calle@cloudius-systems.com>
Signed-off-by: Avi Kivity <avi@cloudius-systems.com>

Write permission should not be granted to ptes that has no write
permission because they are COW, but currently there is no way to
distinguish between write protection due to vma permission and write
protection due to COW. Use bit reserved for software use in pte as a
marker for COW ptes and check it during permission changes.

Signed-off-by: Gleb Natapov <gleb@cloudius-systems.com>

We are usign %x instead of %lx for x86_64. This has the effect of trimming all
64 bits to 32 bits creating a very, very confusing situation for people
debugging OSv.

Signed-off-by: Glauber Costa <glommer@cloudius-systems.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
[claudio: some fixes]
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

add the APIs to flush a single processor tlb or all
tlbs in the cluster.

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

create the initial page tables for TTBR0 / TTBR1
and set up the registers for the MMU.

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

in order to share most of the fault code in core/mmu.cc,
we add accessors to get the program counter and an error
code whose interpretation is arch-dependent
(error_code for x64, ESR for AArch64).

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

forgot to build the arm-clock stub, which will cause
a NULL pointer dereference when we turn the mmu on.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

The content of .fixup section is sorted during boot. Moreover, since
.fixup contains pointers to locations in .text section it requires
R_X86_64_RELATIVE relocations.

Reviewed-by: Glauber Costa <glommer@cloudius-systems.com>
Signed-off-by: Pawel Dziepak <pdziepak@quarnos.org>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

FPSR and FPCR registers are 32-bit wide.

Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
Signed-off-by: Pekka Enberg <penberg@cloudius-systems.com>

get the command line and elf header start, then try to
stay clear of apparent random limitations during boot
early stage with the model, and set up vectors as soon
as possible, to enable some minimal post-mortem info.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

rename processor::halt_no_interrupts to cli_hlt, which
logically matches existing processor::sti_hlt.

Make use of arch::halt_no_interrupts in core/power.cc,
enclose x64-specific code in ifdefs, as well as putting
code on AArch64.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>

This allows those function to be called on const object.

Signed-off-by: Gleb Natapov <gleb@cloudius-systems.com>